TSC2046E SBAS417B − JUNE 2007 − REVISED JANUARY 2008 Low Voltage I/O TOUCH SCREEN CONTROLLER FEATURES DESCRIPTION (cid:1) Same Pinout as ADS7846 The TSC2046E is the next-generation version of the (cid:1) 2.2V to 5.25V Operation ADS7846 4-wire touch screen controller, supporting a (cid:1) 1.5V to 5.25V Digital I/O low-voltage I/O interface from 1.5V to 5.25V. The (cid:1) Internal 2.5V Reference TSC2046E is 100% pin-compatible with the existing (cid:1) Direct Battery Measurement (0V to 6V) ADS7846, and drops into the same socket. This design (cid:1) On-Chip Temperature Measurement allows for an easy upgrade of current applications to the (cid:1) Touch-Pressure Measurement new version. The TSC2046E also has an on-chip 2.5V (cid:1) QSPI and SPI 3-Wire Interface reference that can be used for the auxiliary input, battery (cid:1) monitor, and temperature measurement modes. The Auto Power-Down (cid:1) reference can also be powered down when not used to Exceeds IEC 61000-4-2 ESD Requirements − (cid:1)15kV Contact Discharge conserve power. The internal reference operates down to a supply voltage of 2.7V, while monitoring the battery − No External Components Needed (cid:1) voltage from 0V to 6V. Available In TSSOP-16, QFN-16, and VFBGA-48 Packages The low-power consumption of < 0.75mW typ at 2.7V (reference off), high-speed (up to 125kHz sample rate), APPLICATIONS and on-chip drivers make the TSC2046E an ideal choice for battery-operated systems such as personal digital (cid:1) Personal Digital Assistants assistants (PDAs) with resistive touch screens, pagers, (cid:1) Portable Instruments cellular phones, and other portable equipment. The (cid:1) Point-of-Sale Terminals TSC2046E is available in TSSOP-16, QFN-16, and (cid:1) Pagers VFBGA-48 packages and is specified over the –40°C to (cid:1) Touch Screen Monitors +85°C temperature range. (cid:1) Cellular Phones US Patent No. 6246394 PenDetect PENIRQ +V CC X+ X− TemSepensraotrure SAR IOVDD Y+ Y− TSC2046E DOUT BUSY Comparator 6−Channel Serial CS MUX CDAC Data In/Out Battery DCLK VBAT Monitor DIN AUX V Internal2.5VReference REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola Inc. Microwire is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:4)(cid:10)(cid:7)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:11)(cid:19) (cid:20)(cid:21)(cid:15)(cid:15)(cid:22)(cid:12)(cid:18) (cid:17)(cid:19) (cid:14)(cid:13) (cid:23)(cid:21)(cid:24)(cid:25)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:26)(cid:17)(cid:18)(cid:22)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:19) Copyright  2007−2008, Texas Instruments Incorporated (cid:20)(cid:14)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16) (cid:18)(cid:14) (cid:19)(cid:23)(cid:22)(cid:20)(cid:11)(cid:13)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12)(cid:19) (cid:23)(cid:22)(cid:15) (cid:18)(cid:28)(cid:22) (cid:18)(cid:22)(cid:15)(cid:16)(cid:19) (cid:14)(cid:13) (cid:7)(cid:22)(cid:29)(cid:17)(cid:19) (cid:8)(cid:12)(cid:19)(cid:18)(cid:15)(cid:21)(cid:16)(cid:22)(cid:12)(cid:18)(cid:19) (cid:19)(cid:18)(cid:17)(cid:12)(cid:26)(cid:17)(cid:15)(cid:26) (cid:30)(cid:17)(cid:15)(cid:15)(cid:17)(cid:12)(cid:18)(cid:31)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:11)(cid:14)(cid:12) (cid:23)(cid:15)(cid:14)(cid:20)(cid:22)(cid:19)(cid:19)(cid:11)(cid:12)! (cid:26)(cid:14)(cid:22)(cid:19) (cid:12)(cid:14)(cid:18) (cid:12)(cid:22)(cid:20)(cid:22)(cid:19)(cid:19)(cid:17)(cid:15)(cid:11)(cid:25)(cid:31) (cid:11)(cid:12)(cid:20)(cid:25)(cid:21)(cid:26)(cid:22) (cid:18)(cid:22)(cid:19)(cid:18)(cid:11)(cid:12)! (cid:14)(cid:13) (cid:17)(cid:25)(cid:25) (cid:23)(cid:17)(cid:15)(cid:17)(cid:16)(cid:22)(cid:18)(cid:22)(cid:15)(cid:19)(cid:27) www.ti.com

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VCC and IOVDD to GND . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V This integrated circuit can be damaged by ESD. Texas Analog Inputs to GND . . . . . . . . . . . . . . . . . −0.3V to +VCC + 0.3V Instruments recommends that all integrated circuits be Digital Inputs to GND . . . . . . . . . . . . . . . . . −0.3V to IOVDD + 0.3V handled with appropriate precautions. Failure to observe Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW proper handling and installation procedures can cause damage. Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +150°C ESD damage can range from subtle performance degradation to Operating Temperature Range . . . . . . . . . . . . . . . . −40°C to +85°C complete device failure. Precision integrated circuits may be more Storage Temperature Range . . . . . . . . . . . . . . . . . −65°C to +150°C susceptible to damage because very small parametric changes could Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C cause the device not to meet its published specifications. IEC Contact Discharge (X+, X−, Y+, Y−)(2) . . . . . . . . . . . . . . . ±15kV (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2)Test method based on IEC standard 61000−4−2. Contact Texas Instruments for test details. PACKAGE/ORDERING INFORMATION(1) NOMINAL MAXIMUM PENIRQ INTEGRAL PULLUP LINEARITY SPECIFIED RESISTOR ERROR PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT VALUES (LSB) LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY TSC2046EIPW Rails, 100 TTSSSSOOPP--1166 PPWW −−4400°°CC ttoo ++8855°°CC TTSSCC22004466EEII TSC2046EIPWR Tape and Reel, 2500 4x4, 0.8mm TSC2046EIRGVT Tape and Reel, 250 TTSSCC22004466EE 5500kkΩΩ ±±22 TThhiinn RRGGVV −−4400°°CC ttoo ++8855°°CC TTSSCC22004466EE QFN-16 TSC2046EIRGVR Tape and Reel, 2500 4x4 ZQC −40°C to +85°C BC2046E TSC2046EIZQCR Tape and Reel, 2500 VFBGA-48 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. 2

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS: V = +2.7V to +5.5V S At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be ≥ IOVDD, unless otherwise noted. TSC2046E PARAMETER CONDITION MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Span Positive Input−Negative Input 0 VREF V Absolute Input Range Positive Input −0.2 +VCC + 0.2 V Negative Input −0.2 +0.2 V Capacitance 25 pF Leakage Current 0.1 µA SYSTEM PERFORMANCE Resolution 12 Bits No Missing Codes 11 Bits Integral Linearity Error ±2 LSB(1) Offset Error ±6 LSB Gain Error External VREF ±4 LSB Noise Including Internal VREF 70 µVrms Power-Supply Rejection 70 dB SAMPLING DYNAMICS Conversion Time 12 CLK Cycles Acquisition Time 3 CLK Cycles Throughput Rate 125 kHz Multiplexer Settling Time 500 ns Aperture Delay 30 ns Aperture Jitter 100 ps Channel-to-Channel Isolation VIN = 2.5VPP at 50kHz 100 dB SWITCH DRIVERS On-Resistance Y+, X+ 5 Ω Y−, X− 6 Ω Drive Current(2) Duration 100ms 50 mA REFERENCE OUTPUT Internal Reference Voltage 2.45 2.50 2.55 V Internal Reference Drift 15 ppm/°C Quiescent Current 500 µA REFERENCE INPUT Range 1.0 +VCC V Input Impedance SER/DFR = 0, PD1 = 0 1 GΩ Internal Reference Off Internal Reference On 250 Ω BATTERY MONITOR Input Voltage Range 0.5 6.0 V Input Impedance Sampling Battery 10 kΩ Battery Monitor Off 1 GΩ Accuracy VBAT = 0.5V to 5.5V, External VREF = 2.5V −2 +2 % VBAT = 0.5V to 5.5V, Internal Reference −3 +3 % TEMPERATURE MEASUREMENT Temperature Range −40 +85 °C Resolution Differential Method(3) 1.6 °C TEMP0(4) 0.3 °C Accuracy Differential Method(3) ±2 °C TEMP0(4) ±3 °C (1) LSB means Least Significant Bit. With VREF = +2.5V, 1 LSB is 610µV. (2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is −2.1mV/°C. (5) TSC2046E operates down to 2.2V. (6) IOVDD must be ≤ (+VCC). (7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. 3

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS: V = +2.7V to +5.5V (continued) S At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be ≥ IOVDD, unless otherwise noted. TSC2046E PARAMETER CONDITION MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Logic Family CMOS Capacitance All Digital Control Input Pins 5 15 pF VIH | IIH | ≤ +5µA IOVDD • 0.7 IOVDD + 0.3 V VIL | IIL | ≤ +5µA −0.3 0.3 •IOVDD V VOH IOH = −250µA IOVDD • 0.8 V VOL IOL = 250µA 0.4 V Straight Data Format Binary POWER-SUPPLY REQUIREMENTS +VCC(5) Specified Performance 2.7 3.6 V Operating Range 2.2 5.25 V IOVDD(6) 1.5 +VCC V Quiescent Current(7) Internal Reference Off 280 650 µA Internal Reference On 780 µA fSAMPLE = 12.5kHz 220 µA Power-Down Mode with 3 µA CS = DCLK = DIN = IOVDD Power Dissipation +VCC = +2.7V 1.8 mW TEMPERATURE RANGE Specified Performance −40 +85 °C (1) LSB means Least Significant Bit. With VREF = +2.5V, 1 LSB is 610µV. (2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is −2.1mV/°C. (5) TSC2046E operates down to 2.2V. (6) IOVDD must be ≤ (+VCC). (7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. 4

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 PIN CONFIGURATION Top View TSSOP Top View VFBGA DCLK CS DIN BUSYDOUT 1 2 3 4 5 6 7 +VCC 1 16 DCLK A NC NC X+ 2 15 CS B NC NC NC NC NC Y+ 3 14 DIN +VCC PENIRQ C NC NC NC NC X− 4 13 BUSY +VCC IOVDD TSC2046E Y− 5 12 DOUT D NC NC NC NC NC X+ V REF GND 6 11 PENIRQ E NC NC NC NC NC Y+ AUX V 7 10 IOVDD BAT F NC NC NC NC NC NC NC AUX 8 9 V REF G NC NC X− Y− GND GND V BAT Top View Q QFN DOUT PENIR IOVDD VREF 6 5 4 3 1 1 1 1 BUSY 1 12 AUX DIN 2 11 V BAT TSC2046E CS 3 10 GND DCLK 4 (Thermal Pad)(1) 9 Y− 5 6 7 8 C + + − VC X Y X + (1)The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. PIN DESCRIPTION TSSOP PIN # VFBGA PIN # QFN PIN # NAME DESCRIPTION 1 B1 and C1 5 +VCC Power Supply 2 D1 6 X+ X+ Position Input 3 E1 7 Y+ Y+ Position Input 4 G2 8 X− X− Position Input 5 G3 9 Y− Y− Position Input 6 G4 and G5 10 GND Ground 7 G6 11 VBAT Battery Monitor Input 8 E7 12 AUX Auxiliary Input to ADC 9 D7 13 VREF Voltage Reference Input/Output 10 C7 14 IOVDD Digital I/O Power Supply 11 B7 15 PENIRQ Pen Interrupt 12 A6 16 DOUT Serial Data Output. Data are shifted on the falling edge of DCLK. This output is high impedance when CS is high. 13 A5 1 BUSY Busy Output. This output is high impedance when CS is high. 14 A4 2 DIN Serial Data Input. If CS is low, data sre latched on the rising edge of DCLK. 15 A3 3 CS Chip Select Input. Controls conversion timing and enables the serial input/output register. CS high = power-down mode (ADC only). 16 A2 4 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. 5

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. +VCCSUPPLYCURRENTvsTEMPERATURE IOVDDSUPPLYCURRENTvsTEMPERATURE 400 30 350 µA) µ(A) 25 SupplyCurrent( 322050000 SupplyCurrent 2105 CC DD +V 150 OV 10 I 100 5 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) POWER−DOWNSUPPLYCURRENTvsTEMPERATURE +VCCSUPPLYCURRENTvs+VCC 140 450 400 120 A) fSAMPLE=125kHz A) µ( 350 n nt Current( 100 plyCurre 320500 upply 80 SupC 200 S 60 +VC fSAMPLE=12.5kHz 150 40 100 −40 −20 0 20 40 60 80 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Temperature (°C) +V (V) CC IOVDDSUPPLYCURRENTvsIOVDD MAXIMUMSAMPLERATEvs+V CC 60 1M +V ≥IOVDD CC 50 A) µ ( nt 40 z) 100k e H yCurr 30 fSAMPLE=125kHz Rate( DSuppl 20 Sample 10k D V O 10 I f =12.5kHz SAMPLE 0 1k 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IOVDD(V) +V (V) CC 6

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. CHANGEINGAINvsTEMPERATURE CHANGEINOFFSETvsTEMPERATURE 0.15 0.6 0.10 0.4 B) B) LS 0.05 LS 0.2 C ( C ( °25 0 °25 0 + + m m a fro −0.05 a fro −0.2 elt elt D −0.10 D −0.4 −0.15 −0.6 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) REFERENCECURRENTvsSAMPLERATE REFERENCECURRENTvsTEMPERATURE 14 18 12 16 µA) 10 µA) ( ( 14 nt nt Curre 8 Curre 12 e 6 e nc nc e e 10 er 4 er ef ef R R 2 8 0 6 0 25 50 75 100 125 −40 −20 0 20 40 60 80 100 SampleRate(kHz) Temperature (°C) SWITCHON−RESISTANCEvs+VCC SWITCHON−RESISTANCEvsTEMPERATURE (X+,Y+:+VCCtoPin;X−,Y−:PintoGND) (X+,Y+:+VCCtoPin;X−,Y−:PintoGND) 8 8 Y− 7 7 Y− 6 Ω ()N 6 Ω ()N 5 X− X+,Y+ O O 4 R 5 X− R 3 X+,Y+ 4 2 3 1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 −40 −20 0 20 40 60 80 100 +VCC(V) Temperature (°C) 7

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. INTERNALV vsTEMPERATURE REF MAXIMUMSAMPLINGRATEvsRIN 2.5080 2.0 INL:R =500Ω 2.5075 m 1.8 INL:RIINN=2kΩ 2.5070 aErrorfroSB) 111...642 DDNNLL::RRIINN==520kΩ0Ω (V)REF 22..55006650 Delt0(L 1.0 alV 3.5055 bsoluteR=IN 00..86 Intern 22..55005405 A 2.5040 ax 0.4 M 2.5035 0.2 2.5030 0 05050505050505050505050505 4332211− 1122334455667788 20 40 60 80 100 120 140 160 180 200 −−−−−−− SamplingRate(kHz) Temperature (°C) INTERNALVREFvs+VCC INTERNALVREFvsTURN−ONTIME 2.510 100 2.505 No Cap 80 (42µs) V) 2.500 %) 12-Bit Settling 1µF Cap V(REF 2.495 V(REF 60 (1122-B4µit sS)ettling Internal 2.490 Internal 40 2.485 20 2.480 0 2.5 3.0 3.5 4.0 4.5 5.0 0 200 400 600 800 1000 1200 1400 +V (V) Turn-On Time (µs) CC TEMPDIODEVOLTAGEvsTEMPERATURE TEMP0DIODEVOLTAGEvs+V CC 850 604 800 mV) 750 90.1mV mV) 602 Voltage( 760500 TEMP1 Voltage( 600 Diode 600 Diode 598 MP 550 TEMP0 135.1mV MP0 TE TE 596 500 450 594 05050505050505050505050505 2.7 3.0 3.3 4332211− 1122334455667788 −−−−−−− +V (V) Temperature (°C) CC 8

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. TEMP1DIODEVOLTAGEvs+V CC 720 V) 718 m ( e g olta 716 V e d o 714 Di 1 P M E 712 T 710 2.7 3.0 3.3 +V (V) CC THEORY OF OPERATION The analog input (X-, Y-, and Z-Position coordinates, auxiliary input, battery voltage, and chip temperature) The TSC2046E is a classic successive approximation to the converter is provided via a multiplexer. A unique register (SAR) analog-to-digital converter (ADC). The configuration of low on-resistance touch panel driver architecture is based on capacitive redistribution, which switches allows an unselected ADC input channel to inherently includes a sample-and-hold function. The provide power and the accompanying pin to provide converter is fabricated on a 0.6µm CMOS process. ground for an external device, such as a touch screen. By maintaining a differential input to the converter and The basic operation of the TSC2046E is shown in a differential reference architecture, it is possible to Figure 1. The device features an internal 2.5V reference and uses an external clock. Operation is maintained from negate the error from each touch panel driver switch a single supply of 2.7V to 5.25V. The internal reference can on-resistance (if this is a source of error for the be overdriven with an external, low-impedance source particular measurement). between 1V and +V . The value of the reference voltage CC directly sets the input range of the converter. +2.7Vto+5V TSC2046E 1µF + 10µtoF 0.1µF B1 +VCC DCLK A2 Serial/ConversionClock (Optional) C1 +V CS A3 ChipSelect CC D1 X+ DIN A4 SerialDataIn E1 Y+ BUSY A5 ConverterStatus Touch G2 X− DOUT A6 SerialDataOut Screen G3 Y− PENIRQ B7 PenInterrupt ToBattery G6 V IOVDD C7 BAT AuxiliaryInput E7 AUX V D7 REF GND G4 G5 GND Voltage Regulator NOTE:VFBGApackageandpinnamesshown. Figure 1. Basic Operation of the TSC2046E 9

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (shown in Figure 2 shows a block diagram of the input multiplexer on Figure 2) is captured on the internal capacitor array. The the TSC2046E, the differential input of the ADC, and the input current into the analog inputs depends on the differential reference of the converter. Table 1 and Table 2 conversion rate of the device. During the sample period, the show the relationship between the A2, A1, A0, and source must charge the internal sampling capacitor (typically SER/DFR control bits and the configuration of the 25pF). After the capacitor is fully charged, there is no further TSC2046E. The control bits are provided serially via the DIN input current. The rate of charge transfer from the analog pin—see the Digital Interface section of this data sheet for source to the converter is a function of conversion rate. more details. PENIRQ IOVDD +VCC VREF Level 50kΩ TEMP1 TEMP0 Shifter or 90kΩ Logic A2− A0 SER/DFR (Shown 001B) (Shown Low) X+ X− Ref On/Off Y+ +REF +IN Y− ADC −IN 2.5V −REF Reference 7.5kΩ VBAT 2.5kΩ Battery On AUX GND Figure 2. Simplified Diagram of Analog Input A2 A1 A0 VBAT AUXIN TEMP Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS Y-DRIVERS 0 0 0 +IN (TEMP0) Off Off 0 0 1 +IN Measure Off On 0 1 0 +IN Off Off 0 1 1 +IN Measure X−, On Y+, On 1 0 0 +IN Measure X−, On Y+, On 1 0 1 +IN Measure On Off 1 1 0 +IN Off Off 1 1 1 +IN (TEMP1) Off Off Table 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high) A2 A1 A0 +REF −REF Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION DRIVERS 0 0 1 Y+ Y− +IN Measure Y+, Y− 0 1 1 Y+ X− +IN Measure Y+, X− 1 0 0 Y+ X− +IN Measure Y+, X− 1 0 1 X+ X− +IN Measure X+, X− Table 2. Input Configuration (DIN), Differential Reference Mode (SER/DFR low) 10

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 INTERNAL REFERENCE There is also a critical item regarding the reference when making measurements while the switch drivers are ON. For The TSC2046E has an internal 2.5V voltage reference that this discussion, it is useful to consider the basic operation of can be turned on or off with the control bit, PD1 (see Table 5 the TSC2046E (see Figure 1). This particular application and Figure 3). Typically, the internal reference voltage is only shows the device being used to digitize a resistive touch used in the single-ended mode for battery monitoring, screen. A measurement of the current Y-Position of the temperature measurement, and for using the auxiliary input. pointing device is made by connecting the X+ input to the Optimal touch screen performance is achieved when using ADC, turning on the Y+ and Y– drivers, and digitizing the the differential mode. The internal reference voltage of the voltage on X+ (Figure 4 shows a block diagram). For this TSC2046E must be commanded to be off to maintain measurement, the resistance in the X+ lead does not affect compatibility with the ADS7843. Therefore, after power-up, the conversion (it does affect the settling time, but the a write of PD1 = 0 is required to ensure the reference is off resistance is usually small enough that this is not a concern). (see the Typical Characteristics for power-up time of the However, because the resistance between Y+ and Y– is reference from power-down). fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it is not possible to achieve a 0V input or a full-scale input regardless Reference of where the pointing device is on the touch screen because Power−Down some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. V Band REF Buffer Gap +V V CC REF To Optional CDAC Y+ Figure 3. Simplified Diagram of the Internal Reference X+ REFERENCE INPUT +IN +REF Converter The voltage difference between +REF and –REF (see Figure 2) sets the analog input range. The TSC2046E −IN −REF operates with a reference in the range of 1V to +V . There Y− CC are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output GND code (referred to as LSB size) is also reduced. The LSB (least significant bit) size is equal to the reference voltage divided by 4096 in 12-bit mode. Any offset or gain error Figure 4. Simplified Diagram of Single-Ended inherent in the ADC appears to increase, in terms of LSB Reference (SER/DFR high, Y switches enabled, X+ is analog input) size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it is typically 5LSBs with a 1V reference. In each This situation can be remedied as shown in Figure 5. By case, the actual offset of the device is the same, 1.22mV. setting the SER/DFR bit low, the +REF and –REF inputs With a lower reference voltage, more care must be taken are connected directly to Y+ and Y–, respectively, making to provide a clean layout including adequate bypassing, a the analog-to-digital conversion ratiometric. The result of clean (low-noise, low-ripple) power supply, a low-noise the conversion is always a percentage of the external reference (if an external reference is used), and a resistance, regardless of how it changes in relation to the low-noise input signal. on-resistance of the internal switches. Note that there is an important consideration regarding power dissipation when The voltage into the V input directly drives the REF using the ratiometric mode of operation (see the Power capacitor digital-to-analog converter (CDAC) portion of the Dissipation section for more details). TSC2046E. Therefore, the input current is very low (typically < 13µA). 11

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 TSC2046E data rate. Once the required number of +V CC conversions have been made, the processor commands the TSC2046E to go into its power-down state on the last measurement. This process is required for X-Position, Y+ Y-Position, and Z-Position measurements. Option 3 is to operate in the 15 Clock-per-Conversion mode, which overlaps the analog-to-digital conversions and maintains the touch screen drivers on until commanded to stop by the X+ +IN +REF processor (see Figure 13). Converter TEMPERATURE MEASUREMENT −IN −REF Y− In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2046E relies on the characteristics of a GND semiconductor junction operating at a fixed current level. The forward diode voltage (V ) has a well-defined Figure 5. Simplified Diagram of Differential BE Reference (SER/DFR low, Y switches enabled, characteristic versus temperature. The ambient X+ is analog input) temperature can be predicted in applications by knowing the +25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The As a final note about the differential reference mode, it TSC2046E offers two modes of operation. The first mode must be used with +VCC as the source of the +REF voltage requires calibration at a known temperature, but only and cannot be used with V . It is possible to use a REF requires a single reading to predict the ambient high-precision reference on VREF and single-ended temperature. A diode is used (turned on) during this reference mode for measurements that do not need to be measurement cycle. The voltage across the diode is ratiometric. In some cases, it is possible to power the connected through the MUX for digitizing the forward bias converter directly from a precision reference. Most voltage by the ADC with an address of A2 = 0, A1 = 0, and references can provide enough power for the TSC2046E, A0 = 0 (see Table 1 and Figure 6 for details). This voltage but might not be able to supply enough current for the is typically 600mV at +25°C with a 20µA current through external load (such as a resistive touch screen). the diode. The absolute value of this diode voltage can vary by a few millivolts. However, the temperature TOUCH SCREEN SETTLING coefficient (T ) of this voltage is very consistent at C In some applications, external capacitors may be required –2.1mV/°C. During the final test of the end product, the across the touch screen for filtering noise picked up by the diode voltage would be stored at a known room touch screen (for example, noise generated by the LCD temperature, in memory, for calibration purposes by the panel or backlight circuitry). These capacitors provide a user. The result is an equivalent temperature low-pass filter to reduce the noise, but cause a settling time measurement resolution of 0.3°C/LSB (in 12-bit mode). requirement when the panel is touched that typically shows up as a gain error. There are several methods for minimizing or eliminating this issue. The problem is that +VCC the input and/or reference has not settled to the final steady-state value prior to the ADC sampling the input(s) and providing the digital output. Additionally, the reference voltage may still be changing during the measurement TEMP0 TEMP1 cycle. Option 1 is to stop or slow down the TSC2046E DCLK for the required touch screen settling time. This MUX ADC option allows the input and reference to have stable values for the Acquire period (3 clock cycles of the TSC2046E; see Figure 9). This option works for both the single-ended and the differential modes. Option 2 is to operate the TSC2046E in the differential mode only for the touch screen measurements and command the TSC2046E to remain on (touch screen drivers ON) and not go into power-down (PD0 = 1). Several conversions are made, Figure 6. Functional Block Diagram of depending on the settling time required and the Temperature Measurement 12

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 The second mode of operation does not require a test BATTERY MEASUREMENT temperature calibration, but uses a two-measurement An added feature of the TSC2046E is the ability to monitor method to eliminate the need for absolute temperature calibration and for achieving 2°C accuracy. This mode the battery voltage on the other side of the voltage regulator (dc/dc converter), as shown in Figure 7. The battery voltage requires a second conversion with an address of A2 = 1, can vary from 0V to 6V, while maintaining the voltage to the A1 = 1, and A0 = 1, with a 91 times larger current. The voltage TSC2046E at 2.7V, 3.3V, etc. The input voltage (V ) is difference between the first and second conversion using 91 BAT divided down by four so that a 5.5V battery voltage is times the bias current is represented by Equation (1): represented as 1.375V to the ADC. This design simplifies the (cid:1)V(cid:1)kT(cid:2)In(N) multiplexer and control logic. In order to minimize the power q (1) consumption, the divider is only on during the sampling period when A2 = 0, A1 = 1, and A0 = 0 (see Table 1 for the where: relationship between the control bits and configuration of the N is the current ratio = 91. TSC2046E). k = Boltzmann’s constant = 1.3807 × 10−23 J/K (joules/kelvins). q = the electron charge = 1.6022 × 10–19 C (coulombs). DC/DC 2.7V Converter T = the temperature in kelvins (K). Battery 0.5V + This method can provide improved absolute temperature to measurement, but at a lower resolution of 1.6°C/LSB. The 5.5V +VCC resulting equation that solves for T is: q(cid:2)(cid:1)V T (cid:1) k(cid:2)In(N) (2) 0.125Vto1.375V VBAT ADC where: 7.5kΩ ∆V = V (TEMP1) – V (TEMP0) (in mV) BE BE ∴ T = 2.573 ⋅ ∆V (in K) 2.5kΩ or T = 2.573 ⋅ ∆V – 273 (in °C) NOTE: The bias current for each diode temperature measurement is only on for three clock cycles (during the acquisition mode) and, therefore, does not add any Figure 7. Battery Measurement Functional Block noticeable increase in power, especially if the temperature Diagram measurement only occurs occasionally. 13

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 PRESSURE MEASUREMENT DIGITAL INTERFACE Measuring touch pressure can also be done with the See Figure 9 for the typical operation of the TSC2046E TSC2046E. To determine pen or finger touch, the pressure digital interface. This diagram assumes that the source of of the touch needs to be determined. Generally, it is not the digital signals is a microcontroller or digital signal necessary to have very high performance for this test; processor with a basic serial interface. Each therefore, the 8-bit resolution mode is recommended communication between the processor and the converter, (however, calculations shown here are in the 12-bit such as SPI, SSI, or Microwire(cid:2) synchronous serial resolution mode). There are several different ways of interface, consists of eight clock cycles. One complete performing this measurement. The TSC2046E supports conversion can be accomplished with three serial two methods. The first method requires knowing the communications for a total of 24 clock cycles on the DCLK X-plate resistance, measurement of the X-Position, and input. two additional cross panel measurements (Z1 and Z2) of The first eight clock cycles are used to provide the control the touch screen, as shown in Figure 8. Using Equation (3) byte via the DIN pin. When the converter has enough calculates the touch resistance: information about the following conversion to set the input (cid:3) (cid:5) multiplexer and reference inputs appropriately, the R (cid:1) R (cid:2)X−Position Z2(cid:4)1 converter enters the acquisition (sample) mode and, if TOUCH X−Plate 4096 Z 1 (3) needed, the touch panel drivers are turned on. After three more clock cycles, the control byte is complete and the The second method requires knowing both the X-plate converter enters the conversion mode. At this point, the and Y-plate resistance, measurement of X-Position and input sample-and-hold goes into the hold mode and the Y-Position, and Z1. Using Equation (4) also calculates touch panel drivers turn off (in single-ended mode). The the touch resistance: next 12 clock cycles accomplish the actual analog- (cid:3) (cid:5) to-digital conversion. If the conversion is ratiometric R (cid:1) RX−Plate(cid:2)X−Position 4096(cid:4)1 (SER/DFR = 0), the drivers are on during the conversion TOUCH 4096 Z and a 13th clock cycle is needed for the last bit of the 1 (cid:3) (cid:5) conversion result. Three more clock cycles are needed to (cid:4)R 1(cid:4)Y−Position complete the last byte (DOUT will be low), which are Y−Plate 4096 (4) ignored by the converter. Measure Measure X−Position Z−Position 1 X+ Y+ X+ Y+ X+ Y+ Touch Touch Touch Z−Position 2 X−Position Z−Position X− Y− X−1 Y− X− Y− Measure Z−Position 2 Figure 8. Pressure Measurement Block Diagrams 14

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 Control Byte mode, the converter reference voltage is always the difference between the V and GND pins (see Table 1 The control byte (on DIN), as shown in Table 3, provides REF and Table 2, and Figure 2 through Figure 5, for further the start conversion, addressing, ADC resolution, information). configuration, and power-down of the TSC2046E. Figure 9, Table 3 and Table 4 give detailed information regarding the order and description of these control bits BIT 7 BIT 0 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB) within the control byte. S A2 A1 A0 MODE SER/DFR PD1 PD0 Initiate START—The first bit, the S bit, must always be Table 3. Order of the Control Bits in the Control high and initiates the start of the control byte. The Byte TSC2046E ignores inputs on the DIN pin until the start bit is detected. Addressing—The next three bits (A2, A1, and A0) select BIT NAME DESCRIPTION the active input channel(s) of the input multiplexer (see 7 S Start bit. Control byte starts with first high bit on DIN. A new control byte can start every 15th clock cycle Table 1, Table 2, and Figure 2), touch screen drivers, and in 12-bit conversion mode or every 11th clock cycle the reference inputs. in 8-bit conversion mode (see Figure 13). MODE—The mode bit sets the resolution of the ADC. With 6-4 A2-A0 Channel Select bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, this bit low, the next conversion has 12-bit resolution, touch driver switches, and reference inputs (see whereas with this bit high, the next conversion has 8-bit Table 1 and Figure 13). resolution. 3 MODE 12-Bit/8-Bit Conversion Select bit. This bit controls the number of bits for the next conversion: 12-bits SER/DFR—The SER/DFR bit controls the reference (low) or 8-bits (high). mode, either single-ended (high) or differential (low). The 2 SER/DFR Single-Ended/Differential Reference Select bit. Along differential mode is also referred to as the ratiometric with bits A2-A0, this bit controls the setting of the conversion mode and is preferred for X-Position, multiplexer input, touch driver switches, and Y-Position, and Pressure-Touch measurements for reference inputs (see Table 1 and Table 2). optimum performance. The reference is derived from the 1-0 PD1-PD0 Power-Down Mode Select bits. Refer to Table 5 for details. voltage at the switch drivers, which is almost the same as the voltage to the touch screen. In this case, a reference Table 4. Descriptions of the Control Bits within voltage is not needed as the reference voltage to the ADC the Control Byte is the voltage across the touch screen. In the single-ended CS t ACQ DCLK 1 8 1 8 1 8 DIN S A2 A1 A0 MODE SDEFRR/ PD1 PD0 (START) Idle Acquire Conversion Idle BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 ZeroFilled... (MSB) (LSB) Drivers1and2(1) (SER/DFRHigh) Off On Off Drivers1and2(1,2) (SER/DFRLow) Off On Off NOTES:(1)ForY−Position,Driver1isonX+isselected,andDriver2isoff.ForX−Position,Driver1isoff,Y+isselected,andDriver2ison.Y−willturnon whenpower−downmodeisenteredandPD0=0. (2)DriverswillremainonifPD0=1(nopowerdown)untilselectedinputchannel,referencemode,orpower−downmodeischanged,orCSishigh. Figure 9. Conversion Timing, 24 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port 15

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 If X-Position, Y-Position, and Pressure-Touch are measured in the single-ended mode, an external reference IOVDD voltage is needed. The TSC2046E must also be powered +V CC Level from the external reference. Caution should be observed PENIRQ Shifter when using the single-ended mode such that the input 50kΩ +V voltage to the ADC does not exceed the internal reference or CC 90kΩ voltage, especially if the supply voltage is greater than Y+ TEMP0 TEMP1 2.7V. Highexcept NOTE: The differential mode can only be used for whenTEMP0, X-Position, Y-Position, and Pressure-Touch TEMP1activated. TEMP DIODE X+ measurements. All other measurements require the single-ended mode. PD0 and PD1—Table 5 describes the power-down and the internal reference voltage configurations. The internal Y− reference voltage can be turned on or off independently of On the ADC. This feature can allow extra time for the internal reference voltage to settle to the final value prior to making Y+orX+driverson, a conversion. Make sure to also allow this extra wake-up orTEMP0,TEMP1 measurementsactivated. time if the internal reference is powered down. The ADC requires no wake-up time and can be instantaneously Figure 10. PENIRQ Functional Block Diagram used. Also note that the status of the internal reference power-down is latched into the part (internally) with BUSY The −90 version of the TSC2046E uses a nominal 90kΩ going high. In order to turn the reference off, an additional pullup resistor that allows the total resistance between the write to the TSC2046E is required after the channel has X+ and Y− terminals to be as high as 30kΩ. Note that the been converted. higher pullup resistance causes a slower response time of the PENIRQ to a screen touch, so user software should PD1 PD0 PENIRQ DESCRIPTION take this into account. 0 0 Enabled Power-Down Between Conversions. When The PENIRQ output goes low due to the current path through each conversion is finished, the converter the touch screen to ground, initiating an interrupt to the enters a low-power mode. At the start of the next conversion, the device instantly powers up processor. During the measurement cycle for X-, Y-, and to full power. There is no need for additional Z-Position, the X+ input is disconnected from the PENIRQ delays to ensure full operation, and the very first internal pull-up resistor. This disconnection is done to conversion is valid. The Y− switch is on when in eliminate any leakage current from the internal pull-up power-down. resistor through the touch screen, thus causing no errors. 0 1 Disabled Reference is off and ADC is on. 1 0 Enabled Reference is on and ADC is off. Furthermore, the PENIRQ output is disabled and low during 1 1 Disabled Device is always powered. Reference is on and the measurement cycle for X-, Y-, and Z-Position. The ADC is on. PENIRQ output is disabled and high during the measurement cycle for battery monitor, auxiliary input, and Table 5. Power-Down and Internal Reference chip temperature. If the last control byte written to the Selection TSC2046E contains PD0 = 1, the pen-interrupt output function is disabled and is not able to detect when the screen PENIRQ OUTPUT is touched. In order to re-enable the pen-interrupt output The pen-interrupt output function is shown in Figure 10. function under these circumstances, a control byte needs to While in power-down mode with PD0 = 0, the Y-driver is on be written to the TSC2046E with PD0 = 0. If the last control and connects the Y-plane of the touch screen to GND. The byte written to the TSC2046E contains PD0 = 0, the PENIRQ output is connected to the X+ input through two pen-interrupt output function is enabled at the end of the transmission gates. When the screen is touched, the X+ conversion. The end of the conversion occurs on the falling input is pulled to ground through the touch screen. edge of DCLK after bit 1 of the converted data is clocked out of the TSC2046E. In most of the TSC2046E models, the internal pullup resistor value is nominally 50kΩ, but this value may vary between It is recommended that the processor mask the interrupt that 36kΩ and 67kΩ given process and temperature variations. PENIRQ is associated with whenever the processor sends In order to assure a logic low of 0.35 (cid:3) (+VCC) is presented a control byte to the TSC2046E. This masking prevents false to the PENIRQ circuitry, the total resistance between the X+ triggering of interrupts when the PENIRQ output is disabled and Y− terminals must be less than 21kΩ. in the cases discussed in this section. 16

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 16 Clocks-per-Conversion Digital Timing The control bits for conversion n + 1 can be overlapped Figure 9, Figure 12, and Table 6 provide detailed timing for with conversion n to allow for a conversion every 16 clock the digital interface of the TSC2046E. cycles, as shown in Figure 11. This figure also shows 15 Clocks-per-Conversion possible serial communication occurring with other serial peripherals between each byte transfer from the processor Figure 13 provides the fastest way to clock the to the converter. (16 clocks cycles are possible, provided TSC2046E. This method does not work with the serial that each conversion completes within 1.6ms of starting. interface of most microcontrollers and digital signal Otherwise, the signal that is captured on the input processors, as they are generally not capable of providing sample-and-hold may droop enough to affect the 15 clock cycles per serial transfer. However, this method conversion result.) Note that the TSC2046E is fully can be used with field-programmable gate arrays (FPGAs) powered while other serial communications are taking or application- specific integrated circuits (ASICs). Note place during a conversion. that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which assume 16 clock cycles per conversion. CS DCLK 1 8 1 8 1 8 1 DIN S S ControlBits ControlBits BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 Figure 11. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port CS t t t CL t t t t CSS CH BD BD DO CSH DCLK t t DH DS DIN PD0 t t BDV BTR BUSY t t DV TR DOUT 11 10 Figure 12. Detailed Timing Diagram 17

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 +VCC (cid:1) 2.7V, +VCC (cid:1) IOVDD (cid:1) 1.5V, CLOAD = 50pF SYMBOL DESCRIPTION MIN TYP MAX UNITS tACQ Acquisition Time 1.5 µs tDS DIN Valid Prior to DCLK Rising 100 ns tDH DIN Hold After DCLK High 50 ns tDO DCLK Falling to DOUT Valid 200 ns tDV CS Falling to DOUT Enabled 200 ns tTR CS Rising to DOUT Disabled 200 ns tCSS CS Falling to First DCLK Rising 100 ns tCSH CS Rising to DCLK Ignored 10 ns tCH DCLK High 200 ns tCL DCLK Low 200 ns tBD DCLK Falling to BUSY Rising/Falling 200 ns tBDV CS Falling to BUSY Enabled 200 ns tBTR CS Rising to BUSY Disabled 200 ns Table 6. Timing Specifications, T = −40(cid:2)C to +85(cid:2)C A CS Power−Down DCLK 1 15 1 15 1 DIN S A2 A1 A0 MODE SDEFRR/ PD1PD0 S A2 A1 A0 MODE SDEFRR/PD1PD0 S A2 A1 A0 BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 Figure 13. Maximum Conversion Rate, 15 Clocks-per-Conversion Data Format FS=Full−ScaleVoltage=V (1) The TSC2046E output data is in Straight Binary format, as REF 1LSB=V (1)/4096 REF shown in Figure 14. This figure shows the ideal output 1LSB code for the given input voltage and does not include the 11...111 effects of offset, gain, or noise. 11...110 8-Bit Conversion 11...101 e d The TSC2046E provides an 8-bit conversion mode that o C can be used when faster throughput is needed and the ut p digital result is not as critical. By switching to the 8-bit Out00...010 mode, a conversion is complete four clock cycles earlier. 00...001 Not only does this shorten each conversion by four bits 00...000 (25% faster throughput), but each conversion can actually occur at a faster clock rate. This faster rate occurs because the internal settling time of the TSC2046E is not as 0V FS−1LSB InputVoltage(2)(V) critical—settling to better than 8 bits is all that is needed. NOTES:(1)Referencevoltageatconverter:+REF− (−REF);seeFigure2. The clock rate can be as much as 50% faster. The faster (2)Inputvoltageatconverter,aftermultiplexer:+IN−(−IN);see clock rate and fewer clock cycles combine to provide a 2x Figure2. increase in conversion rate. Figure 14. Ideal Input Voltages and Output Codes 18

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 POWER DISSIPATION Another important consideration for power dissipation is the reference mode of the converter. In the single-ended There are two major power modes for the TSC2046E: reference mode, the touch panel drivers are ON only when full-power (PD0 = 1) and auto power-down (PD0 = 0). the analog input voltage is being acquired (see Figure 9 When operating at full speed and 16 and Table 1). The external device (for example, a resistive clocks-per-conversion (see Figure 11), the TSC2046E touch screen), therefore, is only powered during the spends most of the time acquiring or converting. There is acquisition period. In the differential reference mode, the little time for auto power-down, assuming that this mode is external device must be powered throughout the active. Therefore, the difference between full-power mode acquisition and conversion periods (see Figure 9). If the and auto power-down is negligible. If the conversion rate conversion rate is high, it could substantially increase is decreased by slowing the frequency of the DCLK input, power dissipation. the two modes remain approximately equal. However, if CS also puts the TSC2046E into power-down mode. the DCLK frequency is kept at the maximum rate during a conversion but conversions are done less often, the When CS goes high, the TSC2046E immediately goes into difference between the two modes is dramatic. power-down mode and does not complete the current conversion. The internal reference, however, does not turn Figure 15 shows the difference between reducing the off with CS going high. To turn the reference off, an DCLK frequency (scaling DCLK to match the conversion additional write is required before CS goes high (PD1 = 0). rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the When the TSC2046E first powers up, the device draws about 20µA of current until a control byte is written to it with latter case, the converter spends an increasing PD0 = 0 to put it into power-down mode. This current draw percentage of time in power-down mode (assuming the can be avoided if the TSC2046E is powered up with CS = auto power-down mode is active). 0 and DCLK = IOVDD. 1000 fCLK = 16 ⋅ fSAMPLE A) µ 100 ( nt e Curr fCLK=2MHz SupplyCurrentfrom y +V andIOVDD ppl 10 CC u S T =25¡C A +V =2.7V CC IOVDD=1.8V 1 1k 10k 100k 1M f (Hz) SAMPLE Figure 15. Supply Current versus Directly Scaling the Frequency of DCLK with Sample Rate or Maintaining DCLK at the Maximum Possible Frequency 19

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 LAYOUT The TSC2046E architecture offers no inherent rejection of noise or voltage variation in regards to using an external The following layout suggestions provide the most reference input. This is of particular concern when the optimum performance from the TSC2046E. Many portable reference input is tied to the power supply. Any noise and applications, however, have conflicting requirements ripple from the supply appears directly in the digital results. concerning power, cost, size, and weight. In general, most Whereas high-frequency noise can be filtered out, voltage portable devices have fairly clean power and grounds variation bacause of line frequency (50Hz or 60Hz) can be because most of the internal components are very low difficult to remove. power. This situation means less bypassing for the The GND pin must be connected to a clean ground point. converter power and less concern regarding grounding. In many cases, this is the analog ground. Avoid Still, each situation is unique and the following connections which are too near the grounding point of a suggestions should be reviewed carefully. microcontroller or digital signal processor. If needed, run For optimum performance, care should be taken with the a ground trace directly from the converter to the physical layout of the TSC2046E circuitry. The basic SAR power-supply entry or battery connection point. The ideal architecture is sensitive to glitches or sudden changes on layout includes an analog ground plane dedicated to the the power supply, reference, ground connections, and converter and associated analog circuitry. digital inputs that occur just prior to latching the output of In the specific case of use with a resistive touch screen, the analog comparator. Therefore, during any single care should be taken with the connection between the conversion for an n-bit SAR converter, there are n windows converter and the touch screen. Although resistive touch in which large external transient voltages can easily affect screens have fairly low resistance, the interconnection the conversion result. Such glitches can originate from should be as short and robust as possible. Longer switching power supplies, nearby digital logic, and connections are a source of error, much like the high-power devices. The degree of error in the digital on-resistance of the internal switches. Likewise, loose output depends on the reference voltage, layout, and the connections can be a source of error when the contact exact timing of the external event. The error can change if resistance changes with flexing or vibrations. the external event changes in time with respect to the As indicated previously, noise can be a major source of DCLK input. error in touch screen applications (such as in applications Because of the SAR architecture sensitvity, power to the that require a backlit LCD panel). This EMI noise can be TSC2046E should be clean and well bypassed. A 0.1µF coupled through the LCD panel to the touch screen and ceramic bypass capacitor should be placed as close to the cause flickering of the converted data. Several things can device as possible. A 1µF to 10µF capacitor may also be be done to reduce this error; for instance, using a touch needed if the impedance of the connection between +VCC screen with a bottom-side metal layer connected to ground or IOVDD and the power supplies is high. Low-leakage to shunt the majority of noise to ground. Additionally, capacitors should be used to minimize power dissipation filtering capacitors from Y+, Y–, X+, and X− pins to ground through the bypass capacitors when the TSC2046E is in can also help. Caution should be observed under these power-down mode. circumstances for settling time of the touch screen, A bypass capacitor is generally not needed on the V especially operating in the single-ended mode and at high REF pin because the internal reference is buffered by an data rates. internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. 20

(cid:7)"(cid:6)#$%&’ www.ti.com SBAS417B − JUNE 2007 − REVISED JANUARY 2008 Revision History DATE REV PAGE SECTION DESCRIPTION 3, 4 Electrical Characteristics Fixed typos in conditions header and in Note (6). 11//0088 BB 13 Temperature Measurement Fixed typos in Equations (1) and (2). 8/07 A 5 Pin Configuration Added note to QFN package. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 21

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TSC2046EIPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TSC & no Sb/Br) 2046EI TSC2046EIPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TSC & no Sb/Br) 2046EI TSC2046EIPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TSC & no Sb/Br) 2046EI TSC2046EIPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TSC & no Sb/Br) 2046EI TSC2046EIRGVR ACTIVE VQFN RGV 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TSC & no Sb/Br) 2046E TSC2046EIRGVT ACTIVE VQFN RGV 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TSC & no Sb/Br) 2046E TSC2046EIZQCR LIFEBUY BGA ZQC 48 2500 Pb-Free SNAGCU Level-3-260C-168 HR -40 to 85 BC2046E MICROSTAR (RoHS) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TSC2046E : •Automotive: TSC2046E-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TSC2046EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TSC2046EIRGVR VQFN RGV 16 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TSC2046EIRGVT VQFN RGV 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TSC2046EIZQCR BGAMI ZQC 48 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q1 CROSTA RJUNI OR PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TSC2046EIPWR TSSOP PW 16 2000 350.0 350.0 43.0 TSC2046EIRGVR VQFN RGV 16 2500 350.0 350.0 43.0 TSC2046EIRGVT VQFN RGV 16 250 210.0 185.0 35.0 TSC2046EIZQCR BGAMICROSTAR ZQC 48 2500 350.0 350.0 43.0 JUNIOR PackMaterials-Page2

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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