Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 TSB81BA3E IEEE 1394b Three-Port Cable Transceiver/Arbiter 1 Features (PHYs)Using1.8-V,3.3-V,and5-VSupplies • FullySupportsProvisionsofIEEEP1394b • LowJitter,ExternalCrystalOscillatorProvides 1 Revision1.33+at1-GigabitSignalingRates TransmitandReceiveDataat100/200/400/800 Mbits/s,andLink-LayerControllerClockat49.152 • FullySupportsProvisionsofIEEE1394a-2000 MHzand98.304MHz and1394-1995StandardforHighPerformance SerialBus • SeparateBias(TPBIAS)forEachPort • FullyInteroperableWithFirewire,i.LINK,and • LowCost,HighPerformance80-PinTQFP(PFP) SB1394™,ImplementationofIEEEStd1394 ThermallyEnhancedPackageand168-PinZAJ (BGA)Package • ProvidesThreeFullyBackwardCompatible, (1394a-2000FullyCompliant)BilingualP1394b • SoftwareDeviceReset(SWR) CablePortsatupto800MegabitsperSecond • Fail-SafeCircuitrySensesSuddenLossofPower (Mbits/s) totheDeviceandDisablesthePortstoEnsure • ProvidesThree1394a-2000FullyCompliant ThattheTSB81BA3EDoesNotLoadtheTPBIAS CablePortsat100/200/400Mbits/s ofAnyConnectedDeviceandBlocksany LeakageFromthePortBacktoPowerPlane • Full1394a-2000SupportIncludes: • TheTSB81BA3EHasa1394a-2000Compliant – ConnectionDebounce Common-ModeNoiseFilterontheIncomingBias – ArbitratedShortReset DetectCircuittoFilterOutCross-TalkNoise – MultispeedConcatenation • TheTSB81BA3EIsPortProgrammabletoForce – ArbitrationAcceleration 1394aModetoAllowUseof1394aConnectors – Fly-ByConcatenation (1394bSignalingMustNotBePutAcross1394a – PortDisable/Suspend/Resume ConnectorsorCables) – ExtendedResumeSignalingforCompatibility • InternalVoltageRegulatorOption WithLegacyDVDevices 2 Description • Power-DownFeaturestoConserveEnergyin The TSB81BA3E provides the digital and analog BatteryPoweredApplications transceiver functions needed to implement a three- • Low-PowerSleepMode port node in a cable-based IEEE 1394 network. Each • FullyCompliantWithOpenHostController cable port incorporates two differential line Interface(HCI)Requirements transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining • CablePowerPresenceMonitoring connectionstatus,forinitializationandarbitration,and • CablePortsMonitorLineConditionsforActive for packet reception and transmission. The ConnectiontoRemoteNode TSB81BA3E is designed to interface with a link-layer • RegisterBitsGiveSoftwareControlofContender controller (LLC), such as the TSB82AA2, Bit,PowerClassBits,LinkActiveControlBit,and TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, 1394a-2000Features TSB42AB4, TSB12LV01B, or TSB12LV01C. It also may be connected cable port to cable port to an • DataInterfacetoLink-LayerControllerPin integrated 1394 Link + PHY layer such as the SelectableFrom1394a-2000Mode(2/4/8Parallel TSB43AB2. Bitsat49.152MHz)or1394bMode (8ParallelBitsat98.304MHz) DeviceInformation(1) • InterfacetoLink-LayerControllerSupportsLow PARTNUMBER PACKAGE BODYSIZE(NOM) CostTIBus-HolderIsolation HTQFP(80) 12.00mmx12.00mm • InteroperableWithLink-LayerControllersUsing TSB81BA3E NFBGA(167) 12.00mmx12.00mm 3.3-VSupplies (1) For all available packages, see the orderable addendum at • InteroperableWithOther1394PhysicalLayers theendofthedatasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.5 Programming...........................................................20 2 Description............................................................. 1 8.6 RegisterMaps.........................................................22 3 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 28 4 DescriptionContinued.......................................... 3 9.1 ApplicationInformation............................................28 9.2 TypicalApplication..................................................28 5 PinConfigurationandFunction........................... 4 10 PowerSupplyRecommendations..................... 30 6 ElectricalSpecfications....................................... 10 11 Layout................................................................... 31 6.1 AbsoluteMaximumRatings ...................................10 6.2 ThermalInformation................................................10 11.1 LayoutGuidelines.................................................31 6.3 RecommendedOperatingConditions.....................11 12 DeviceandDocumentationSupport................. 35 6.4 ElectricalCharacteristics,Driver.............................12 12.1 DeviceSupport......................................................35 6.5 ElectricalCharacteristics,Receiver........................12 12.2 RelatedLinks........................................................35 6.6 ElectricalCharacteristics,Device............................12 12.3 CommunityResources..........................................35 6.7 SwitchingCharacteristics........................................13 12.4 Trademarks...........................................................35 7 ParameterMeasurementInformation................14 12.5 ElectrostaticDischargeCaution............................35 12.6 Glossary................................................................35 8 DetailedDescription............................................ 15 13 Mechanical,Packaging,andOrderable 8.1 Overview.................................................................15 Information........................................................... 36 8.2 FunctionalBlockDiagram.......................................17 13.1 DesigningWithPowerPAD™Devices(PFP 8.3 FeatureDescription.................................................17 PackageOnly).........................................................36 8.4 DeviceFunctionalModes........................................19 3 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(October2015)toRevisionC Page • ChangedtheADDRESScolumnofTable8 ........................................................................................................................ 27 • ChangedtheADDRESScolumnofTable10 ...................................................................................................................... 27 ChangesfromRevisionA(May2010)toRevisionB Page • AddedFeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementationsection,Power SupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,andMechanical, Packaging,andOrderableInformationsection ..................................................................................................................... 1 • ReplacedtheDissipationRatingswiththeThermalInformation.......................................................................................... 10 • ChangedtheAddresscolumnofTable6 ............................................................................................................................ 24 ChangesfromOriginal(May2009)toRevisionA Page • UniversalchangeofthepinnamefromTESTWtoVREG_PD ............................................................................................ 1 • DeletedparagraphformtheTPBIASxpinsinthePinFunctionstable"WhenaportisconfiguredasaBeta-mode port(B1,B2,B4...: ................................................................................................................................................................. 9 2 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 4 Description Continued TheTSB81BA3Ecanbepoweredbyasingle3.3-VsupplywhentheVREG_PDterminal(terminal73onthePFP package and terminal B7 on the ZAJ package) is tied to GND. VREG_PD enables the internal 3.3-V to 1.95-V regulator which provides the 1.95-V to the core. The When VREG_PD is pulled high to VDD through at least a 1- kΩ resistor the TSB81BA3E internal regulator is off and the device can be powered by two separate external regulatedsupplies:3.3-VfortheI/Osand1.95-Vforthecore.ThecorevoltageissuppliedtothePLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions (1.95-V nominal). The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals. The PLLVDD-CORE and the DVDD-CORE terminals must be decoupled with 1 uF capacitors to stabilze the respective supply. Additional 0.10 µF and 0.01 µF high-frequency bypass capacitors may also be used. The separation between DVDD-CORE and PLLVDD-CORE may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply. The TSB81BA3E requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronizationofthereceiveddatawhenoperatingthePHY-linkinterfaceincompliancewiththeIEEE1394a- 2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD)function,whenenabledbyassertingthePDterminalhigh,stopsoperationofthePLL. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 5 Pin Configuration and Function PFP PACKAGE (TOPVIEW) 3 3 3 BIAS2 A2+A2−DD−3.B2+ B2− BIAS1 A1+A1−DD−3.ND B1+ B1− BIAS0 A0+A0−DD−3. NDB0+ B0− P PPVP P P PPVG P P P PPV GP P T TTAT T T TTAA T T T TTA AT T 60 5958 57 56 5554 53 5251 50 49 48 47 4645 44 43 42 41 AGND 61 40 AGND AGND 62 39 AVDD−3.3 AVDD−3.3 63 38 DGND DGND 64 37 DVDD−CORE DVDD−CORE 65 36 SM PC0 66 35 SE PC1 67 34 CPS PC2 68 33 DS0 DVDD−3.3 69 32 DS1 DVDD−3.3 70 TSB81BA3E 31 PLLVDD−3.3 DVDD−CORE 71 30 PLLVDD−CORE DGND 72 29 PLLVDD−CORE VREG_PD 73 28 PLLGND BMODE 74 27 XI RESETz 75 26 RSVD DGND 76 25 PLLGND PD 77 24 AVDD−3.3 TESTM 78 23 R0 CNA 79 22 R1 LPS 80 21 AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16 17 18 19 20 PINTN/DS2 LREQDGND PCLK D−3.3LCLK CORECTL0 CTL1 D0 D1 D2 DGND D3 D4 D5 D−3.3D6 D7 O D − D K V D V L D D D V D 4 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 ZAJ PACKAGE (TOPVIEW) Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com PinFunctions PFP ZAJ NAME TYPE I/O DESCRIPTION NO. NO. AGND(1) Supply 21,40,43,50, SeeDGND – Analogcircuitgroundterminals.Theseterminalsmustbetiedtogethertothelow- 61,62 impedancecircuitboardgroundplane. Analogcircuitpowerterminals.Acombinationofhigh-frequencydecoupling capacitors near eachterminalis suggested,such as paralleled0.1 μFand 0.001 μF. Lower frequency 10-μF filtering capacitors are also 24,39,44,51, M4,F10,H10, recommended. These supply terminals are separated from the PLLVDD- AVDD-3.3 Supply – 57,63 J10,E10 CORE,PLLVDD-3.3,DVDD-CORE,andDVDD-3.3terminalsinternaltothe device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminalsmustbetiedtogetherwithalowdcimpedanceconnectiononthe circuitboard. Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-link interface. When logic-low (deasserted), the PHY-link interface complies with the legacy 1394a-2000 BMODE CMOS 74 B6 I standard. When using an LLC such as the 1394b-2002 TSB82AA2, this terminalmustbepulledhigh.WhenusinganLLCsuchasthe1394a-2000 TSB12LV26,thisterminalmustbetiedlow. NOTE: The PHY-link interface cannot be changed between the different protocolsduringoperation. Cablenotactiveoutput.Thisterminalisassertedhighwhentherearenoports CNA CMOS 79 A2 O receivingincomingbiasvoltage.Whenanyportreceivesbias,thisterminalgoeslow. Cable-power status input. This terminal is normally connected to cable powerthrougha 400-kΩ resistor.Thiscircuitdrives an internalcomparator CPS CMOS 34 N9 I that detects thepresenceofcablepower.Thistransitionfromcablepower sensedtocablepowernotsensedcanbeusedtogenerateaninterruptto theLLC. CTL0 9 F1 ControlI/Os.Thesebidirectionalsignalscontrolcommunicationbetweenthe CMOS I/O CTL1 10 G1 TSB81BA3EandtheLLC.Busholdersarebuiltintotheseterminals. 11,12,13,15, H1,H2,J2,J1, DataI/Os.ThesearebidirectionaldatasignalsbetweentheTSB82BA3and D0-D7 CMOS I/O 16,17,19,20 K2,K1,L1,M1 theLLC.Busholdersarebuiltintotheseterminals. E5,F4,F5,F6, F7,F9,G4,G5, G6,G7,G8, DGND(1) Supply 4,14,38,64, G9,G10,H4, – Digitalcircuitgroundterminals.Theseterminalsmustbetiedtogethertothe 72,76 H5,H6,H7, low-impedancecircuitboardgroundplane. H8,J4,J5,J6, J7,J8,K7,L7 Data-strobe-onlymodeforport0.1394a-onlyport0enableprogrammingterminal.On hardwarereset,thisterminalallowstheusertoselectwhetherport0actslikea1394b bilingualport(terminalatlogic0)orasa1394a-2000-onlyport(terminalatlogic1). DS0 CMOS 33 N8 I Programmingisaccomplishedbytyingtheterminallowthrougha1-kΩorlessresistor (toenable1394bbilingualmode)orhighthrougha1-kΩorlessresistor(toenable 1394a-2000-onlymode).Abusholderisbuiltintothisterminal. Data-strobe-onlymodeforport1.1394a-onlyport1enableprogrammingterminal.On hardwarereset,thisterminalallowstheusertoselectwhetherport1actslikea1394b bilingualport(terminalatlogic0)orasa1394a-2000-onlyport(terminalatlogic1). DS1 CMOS 32 M7 I Programmingisaccomplishedbytyingtheterminallowthrougha1-kΩorlessresistor (toenable1394bbilingualmode)orhighthrougha1-kΩorlessresistor(toenable 1394a-2000-onlymode).Abusholderisbuiltintothisterminal. Digital core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001 μF. An additional 1-μF capacitor is required for voltage DVDD-CORE Supply 8,37,65,71 D9,K9,D8 – regulation. These supply terminals are separated from the DVDD-3.3, PLLVDD-CORE,PLLVDD-3.3,andAVDDterminalsinternaltothedeviceto providenoiseisolation. (1) AllAGNDandDGNDterminalsareinternallytiedtogetherintheZAJpackage. 6 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 PinFunctions(continued) PFP ZAJ NAME TYPE I/O DESCRIPTION NO. NO. Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001 μF. Lower-frequency 10-μF filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a low- DVDD-3.3 Supply 6,18,69,70 E4,K5,K6 – impedancepointonthecircuitboard.Thesesupplyterminalsareseparated fromthePLLVDD-CORE,PLLVDD-3.3,DVDD-CORE,andAVDDterminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connectiononthecircuitboard. Linkclock.Link-provided98.304-MHzclocksignaltosynchronizedatatransfersfrom LCLK CMOS 7 G2 I linktothePHYwhenthePHY-linkinterfaceisinthe1394bmode.Abusholderisbuilt intothisterminal. Link-on output/Data-strobe-only input for port 2. This terminal may be connectedtothelink-oninputterminaloftheLLCthrougha1-kΩresistorif thelink-oninputisavailableonthelinklayer. Data-strobe-only mode for port 2. 1394a-only port 0 enable programming terminal.Onhardwarereset,thisterminalallowstheusertoselectwhether port 2 acts like a 1394b bilingual port (terminal at logic 0) or as a 1394a- 2000-only port (terminalatlogic 1). Programmingis accomplishedby tying the terminal low through a 1-kΩ or less resistor to enable 1394b bilingual mode or high through a 1-kΩ or less resistor to enable 1394a-2000-only mode.Abusholderisbuiltintothisterminal. After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, exceptduringhardwareresetwhenitishighimpedance. Thelink-onoutputisactivatediftheLLCisinactive(theLPSinputinactive LKON/DS2 CMOS 2 D2 I/O ortheLCtrlbitcleared)andwhenone: a. ThePHYreceivesalink-onPHYpacketaddressedtothisnode. b. ThePEI(port-eventinterrupt)registerbitis1. c. Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1 and the RPIE (resuming-portinterruptenable)registerbitisalso1. d. ThePHYispower-cycledandthepowerclassis0through4. Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwiseactivebecauseoneoftheinterruptbitsisset(thatis,thelink-on outputisactiveduesolelytothereceptionofalink-onPHYpacket). In the case of power-cycling the PHY, the LKON signal must stop after 167μsiftheprecedingconditionshavenotbeenmet. NOTE:Ifaninterruptconditionexists,whichotherwisewouldcausethelink- onoutputtobeactivatediftheLLCwereinactive,thenthelink-onoutputis activatedwhentheLLCsubsequentlybecomesinactive. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com PinFunctions(continued) PFP ZAJ NAME TYPE I/O DESCRIPTION NO. NO. Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the V supplying the DD LLC through an approximately 1-kΩ resistor or to a pulsed output that is active when the LLC is powered. A pulsed signal must be used when an isolationbarrierexistsbetweentheLLCandPHY(seeFigure8). The LPS input is considered inactive if it is sampled low by the PHY for more than an LPS_RESET time (~2.6 μs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low timelessthan2.6μs).TheLPSinputmustbehighforatleast22nstobe observedashighbythePHY. LPS CMOS 80 D3 I When the TSB81BA3E detects that the LPS input is inactive, it places the PHY-LLCinterfaceintoalow-powerresetstate.Intheresetstate,theCTL (CTL0andCTL1)andD(D0toD7)outputsareheldinthelogic0stateand theLREQinputisignored;however,thePCLKoutputremainsactive.Ifthe LPSinputremainslowformorethananLPS_DISABLEtime(~26μs),then the PHY-LLC interface is put into a low-power disabled state in which the PCLKoutputisalsoheldinactive. The LLC state that is communicated in the self-ID packet is considered activeonlyifboththeLPSinputisactiveandtheLCtrlregisterbitissetto 1. The LLC state that is communicated in the self-ID packet is considered inactiveifeithertheLPSinputisinactiveortheLCtrlregisterbitiscleared to0. LLC request input. The LLC uses this input to initiate a service request to LREQ CMOS 3 E1 I theTSB81BA3E.Abusholderisbuiltintothisterminal. Power class programming inputs. On hardware reset, these inputs set the PC0 66 C11 default value of the power class indicated during self-ID. Programming is PC1 CMOS 67 A9 I done by tying the terminals high through a 1-kΩ or smaller resistor or by PC2 68 B8 tyingdirectlytogroundthrougha1-kΩorsmallerresistor.Busholdersare builtintotheseterminals. PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers,totheLLCwhenthePHY-linkinterfaceisoperatinginthe1394b PCLK CMOS 5 F2 O mode (BMODE asserted). PCLK output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interfaceisinlegacy1394a-2000(BMODEinputdeasserted). Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output. PD CMOS 77 B3 I Asserting the PD input high also activates an internal pulldown on the RESETterminaltoforcearesetoftheinternalcontrollogic. PHY interrupt. The PHY uses this output to serially transfer status and PINT CMOS 1 E3 O interrupt information to the link when PHY-link interface is in the 1394b mode.Abusholderisbuiltintothisterminal. PLL circuit ground terminals. These terminals must be tied together to the PLLGND Supply 25,28 F8,N4 – low-impedancecircuitboardgroundplane. PLL core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled PLLVDD- 0.1 μF and 0.001 μF. An additional 1-μF capacitor is required for voltage Supply 29,30 N6 – CORE regulation. The PLLVDD-CORE terminals must be separate from the DVDD-CORE terminals. These supply terminals are separated from the DVDD-CORE,DVDD-3. PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 μF and 0.001 μF. Lower frequency 10-μF filtering capacitors are also recommended. This supply terminal is separated from the DVDD-CORE, PLLVDD-3.3 Supply 31 N7 – DVDD-3.3, PLLVDD-CORE,andAVDD-3.3terminalsinternaltothedevice toprovidenoiseisolation.TheDVDD-3.3terminalsmustbetiedtogetherat a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection. 8 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 PinFunctions(continued) PFP ZAJ NAME TYPE I/O DESCRIPTION NO. NO. Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to V is provided so only an external delay DD capacitor is required for proper power-up operation (see power-up reset in RESET CMOS 75 A6 I theApplicationsInformationsection). The RESET terminal also incorporates an internal pulldown, which is activated when the PD input is asserted high. This input is otherwise a standardlogicinput,andcanalsobedrivenbyanopen-drain-typedriver. Thisterminalmustnormallybeleftunconnected.Whenthisterminalisprobed,the terminalshowsa98.304-MHzsignal.IfthisisperceivedasanEMIproblem,thenthe RSVD OscOut 26 M5 O terminalmaybepulledtogroundthrougha10-kΩresistor.However,thiscausesan increaseofupto340μAindevicecurrentconsumption. Current setting resistor terminals. These terminals are connected to a R0 23 N3 precisionexternalresistancetosettheinternaloperatingcurrentsandcable Bias – R1 22 N2 driveroutputcurrents.Aresistanceof6.34kΩ,±1%,isrequiredtomeetthe IEEEStd1394-1995outputvoltagelimits. Testcontrolinput.ThisinputisusedinthemanufacturingtestoftheTSB81BA3E.For SE CMOS 35 M10 I normalusethisterminalmustbepulledloweitherthrougha1-kΩresistortoGNDor directlytoGND. Testcontrolinput.ThisinputisusedinthemanufacturingtestoftheTSB81BA3E.For SM CMOS 36 N10 I normalusethisterminalmustbepulledloweitherthrougha1-kΩresistortoGNDor directlytoGND. Test control input. This input is used in the manufacturing test of the TESTM CMOS 78 A3 I TSB81BA3E.Fornormalusethisterminalmustbepulledhighthrougha1- kΩresistortoV . DD Voltageregulatorpower-downinput.Whenassertedlogichigh,thispinwillpower- downtheinternal3.3-Vto1.95-Vregulator.Forsingle3.3-Vsupplyoperation,thispin VREG_PD CMOS 73 B7 I shouldbetiedtoGND.Ifanexternalregulatorisusedtosupplythe1.95-VPLLVDD- COREandDVDD-COREpowerrailsthisterminalsshouldbepulledtoVccthrougha 1-kΩresistortoVDD. Port-0twisted-pairdifferential-signalterminals.Boardtracesfromeachpair TPA0– 45 K13 of positive and negative differential signal terminals must be kept matched TPA0+ 46 J13 TPB0– Cable 41 M13 I/O and as short as possible to the external load resistors and to the cable TPB0+ 42 L13 connector. Request the S800 1394b layout recommendations document fromyourTexasInstrumentsrepresentative. Port-1twisted-pairdifferential-signalterminals.Boardtracesfromeachpair TPA1– 52 F13 of positive and negative differential signal terminals must be kept matched TPA1+ 53 E13 TPB1– Cable 48 H13 I/O and as short as possible to the external load resistors and to the cable TPB1+ 49 G13 connector. Request the S800 1394b layout recommendations document fromyourTexasInstrumentsrepresentative. Port-2twisted-pairdifferential-signalterminals.Boardtracesfromeachpair TPA2– 58 B13 of positive and negative differential signal terminals must be kept matched TPA2+ 59 A13 TPB2– Cable 55 D13 I/O and as short as possible to the external load resistors and to the cable TPB2+ 56 C13 connector. Request the S800 1394b layout recommendations document fromyourTexasInstrumentsrepresentative. Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable driversandreceivers,andforsignalingtotheremotenodesthatthereisan TPBIAS0 47 J12 active cable connection in 1394a-2000 mode. Each of these terminals, TPBIAS1 Cable 54 E12 I/O TPBIAS2 60 A12 except for an unused port, must be decoupled with a 1-μF capacitor to ground.Fortheunusedport,thisterminalcanbeleftunconnected.Please request the S800 1394b layout recommendation documents from your TI representative. Oscillator input. This terminal connects to a 98.304-MHz low jitter external oscillator. The XI terminal is a 1.8-V CMOS input. Oscillator jitter must be 5 ps RMS or better. If only 3.3-V oscillators can be acquired, then great care must be taken to XI OscIn 27 N5 – notintroducesignificantjitterbythemeansusedtolevelshiftfrom3.3Vto 1.8 V. If a resistor divider is used, then a high current oscillator and low- value resistors must be used to minimize RC time constants. If a level- shifting circuit is used, then it must introduce very little jitter. Please see layoutrecommendationsdocument. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 6 Electrical Specfications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange(2) –0.3 4 V DD V Inputvoltagerange(2) –0.5 V +0.5 V I DD V Outputvoltagerangeatanyoutput –0.5 V +0.5 V O DD Continuoustotalpowerdissipation SeeDissipationRatingsTable TSB81BA3E 0 70 T Operatingfree-airtemperature °C A TSB81BA3EI –40 85 T Storagetemperaturerange 65 150 °C stg Leadtemperature1.6mm(1/16in)fromcasefor10s 260 °C (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkground. 6.2 Thermal Information TSB81BA3E THERMALMETRIC(1) PFP ZJA UNIT (HTQFP) (NFBGA) 80PINS 167PINS R LowKJEDECTestBoard,1s(single θJA Junction-to-ambientthermalresistance 27.2 46.2 °C/W signallayer),noairflow R HighKJEDECTestBoard2s2p(double θJC(top) Junction-to-case(top)thermalresistance 8.9 23.5 °C/W signallayer,doubleburiedpowerplane) R Junction-to-boardthermalresistance CuColdPlateMeasurementProcess 11.1 27.8 °C/W θJB ψ Junction-to-topcharacterizationparameter EIA/JESD51-8 0.3 0.45 °C/W JT ψ Junction-to-boardcharacterization JB EIA/JESD51-2 11.0 27.4 °C/W parameter R Junction-to-case(bottom)thermal θJC(bot) EIA/JESD51-6 0.3 N/A °C/W resistance (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 10 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 6.3 Recommended Operating Conditions MIN TYP(1) MAX UNIT Sourcepowernode 3.0 3.3 3.6 3.3V Supplyvoltage V DD Nonsourcepowernode 3.0(2) 3.3 3.6 Core Supplyvoltage 1.85 1.95 2.05 V V DD LREQ,CTL0,CTL1,D0-D7,LCLK 2.6 0.7× LKON/DS2,PC0,PC1,PC2,PD,BMODE V High-levelinputvoltage V V IH DD 0.6× RESETz V DD LREQ,CTL0,CTL1,D0-D7,LCLK 1.2 V Low-levelinputvoltage LKON/DS2,PC0,PC1,PC2,PD,BMODE 0.2×V V IL DD RESETz 0.3×V DD V 1394bDifferentialoutputvoltage 700 mV OD 1394bCommon-modeoutput V 1.5 V CM voltage Supplycurrentinlow VDD=3.3V 4 mA IDD power/suspend(3) V =3V 3 mA DD CTL0,CTL1,D0-D7,CNA,LKON/DS2,PINT,and I Outputcurrent –4 4 mA OL/OH PCLK I Outputcurrent TPBIASoutputs –5.6 1.3 mA O Operatingambienttemperature T TSB81BA3E 0 70 °C A range T Junctiontemperature(4) TSB81BA3E 0 105 °C J V 1394bDifferentialinputvoltage Cableinputs,duringdatareception 200 800 mV ID Cableinputs,duringdatareception 118 260 V 1394aDifferentialinputvoltage mV ID Cableinputs,duringarbitration 168 265 1394aCommon-modeinput TPBcableinputs,sourcepowernode 0.4706 2.515 V V IC voltage TPBcableinputs,nonsourcepowernode 0.4706 2.015(2) t Power-upresettime RESETzinput 2(5) ms pu TPA,TPBcableinputs,S100operation ±1.08 Receiveinputjitter TPA,TPBcableinputs,S200operation ±0.5 ns TPA,TPBcableinputs,S400operation ±0.315 BetweenTPAandTPBcableinputs,S100 ±0.8 operation BetweenTPAandTPBcableinputs,S200 Receiveinputskew ±0.55 ns operation BetweenTPAandTPBcableinputs,S400 ±0.5 operation (1) AlltypicalvaluesareatV =3.3VandT =25°C. DD A (2) Foranodethatdoesnotsourcepower,seeSection4.2.2.2inIEEE1394a-2000. (3) Thelowpower/suspendmodeassumesthatthedeviceisnotreceivingpacketsanditistoning. (4) Thejunctiontemperaturereflectssimulatedconditions.Thecustomerisresponsibleforverifyingjunctiontemperature. (5) TimeaftervalidclockreceivedatPHYXIinputterminal. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 6.4 Electrical Characteristics, Driver overrecommendedrangesofoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Differentialoutputvoltage 56Ω,SeeFigure1 172 265 mV OD I Driverdifferencecurrent,TPA+,TPA–,TPB+,TPB– Driversenabled,speedsignaling –1.05(1) 1.05(1) mA DIFF off I Common-modespeedsignalingcurrent,TPB+, S200speedsignalingenabled –4.84(2) –2.53(2) mA SP200 TPB– I Common-modespeedsignalingcurrent,TPB+, S400speedsignalingenabled –12.4(2) –8.1(2) mA SP400 TPB– V Off-statedifferentialvoltage Driversdisabled,SeeFigure1 20 mV OFF (1) LimitsdefinedasalgebraicsumofTPA+andTPA–drivercurrents.LimitsalsoapplytoTPB+andTPB–algebraicsumofdriver currents. (2) LimitsdefinedasabsolutelimitofeachofTPB+andTPB–drivercurrents. 6.5 Electrical Characteristics, Receiver PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 4 7 kΩ Z Differentialimpedance Driversdisabled ID 4 pF 20 kΩ Z Common-modeimpedance Driversdisabled IC 24 pF V Receiverinputthresholdvoltage Driversdisabled –30 30 mV TH-R V Cablebiasdetectthreshold,TPBxcableinputs Driversdisabled 0.6 1 V TH-CB Positivearbitrationcomparatorthreshold V Driversdisabled 89 168 mV TH+ voltage Negativearbitrationcomparatorthreshold V Driversdisabled –168 –89 mV TH– voltage VTH-SP200 Speedsignalthreshold TPBIAS-TPAcommon-modevoltage, 49 131 mV V Speedsignalthreshold driversdisabled 314 396 mV TH-SP400 6.6 Electrical Characteristics, Device PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 3.3V 120 150 I Supplycurrent DD (1) mA DD CoreV 79 DD V Powerstatusthreshold,CPSinput(2) 400-kΩresistor(2) 4.7 7.5 V TH High-leveloutputvoltage,CTL0,CTL1,D0-D7,PCLK, V =3to3.6V, V DD 2.8 V OH LKON/DS2outputs I =4mA OH Low-leveloutputvoltage,CTL0,CTL1,D0-D7,PCLK, V I =4mA 0.4 V OL LKON/DS2outputs OL V =3.6V, I Positivepeakbusholdercurrent,D0-D7,CTL0-CTL1,LREQ DD 0.05 1 mA BH+ V =0VtoV I DD Negativepeakbusholdercurrent,D0-D7,CTL0-CTL1, V =3.6V, I DD –1.0 –0.05 mA BH– LREQ V =0VtoV I DD Off-stateoutputcurrent,CTL0,CTL1,D0-D7,LKON/DS2 TSB81BA3E ±5 I V =V or0V μA OZ I/Os O DD TSB81BA3EI ±20 I Pullupcurrent,RESETinput V =1.5Vor0V –90 –20 μA IRST I V TPBIASoutputvoltage AtratedI current 1.665 2.015 V O O (1) Repeatmaxpacket(oneportreceivingmaximumsizeisochronouspacket–8192bytes,sentoneveryisochronousinterval,S800,data valueof0xCCCCCCCCh;twoportsrepeating;allportswithbeta-modeconnection),V =3.3V,V =1.95V,T =25°C. DD3.3 DDCORE A (2) Measuredatcable-powersideofresistor. 12 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 6.7 Switching Characteristics PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TPdifferentialrisetime,transmit 10%to90%, At1394connector 0.5 1.2 ns r t TPdifferentialfalltime,transmit 90%to10%, At1394connector 0.5 1.2 ns f Setuptime, t 1394a-2000 50%to50%, SeeFigure2 2.5 ns su CTL0,CTL1,D1-D7,LREQtoPCLK Holdtime, t 1394a-2000 50%to50%, SeeFigure2 0 ns h CTL0,CTL1,D1-D7,LREQafterPCLK Setuptime, t 1394b 50%to50%, SeeFigure2 2.5 ns su CTL0,CTL1,D1-D7,LREQtoLCLK_PMC Holdtime, t 1394b 50%to50%, SeeFigure2 0 ns h CTL0,CTL1,D1-D7,LREQafterLCLK_PMC Delaytime, 1394a-2000 t 50%to50%, SeeFigure3 0.5 7 ns d PCLKtoCTL0,CTL1,D1-D7,PINT and1394b Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 7 Parameter Measurement Information TPAx+ xCLK TPBx+ tsu th 56 W Dx, CTLx, LREQ TPAx− Figure2.Dx,CTLx,LREQInputSetupandHoldTime Waveforms TPBx− Figure1.TestLoadDiagram xCLK td Dx, CTLx Figure3.DxandCTLxOutputDelayRelativetoxCLKWaveforms 14 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 8 Detailed Description 8.1 Overview Data bits to be transmitted through the cable ports are received from the LLC on two-, four-, or eight-bit parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream. The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard. The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The TSB81BA3Eautomaticallydeterminesthecorrectcableinterfaceconnectionmethodforthebilingualports. NOTE The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is disabled. During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected andactivecableports. During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected andactivecableports. Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twistedpairbias(TPBIAS)voltage. When connected to a 1394a-2000 compliant node, the TSB81BA3E provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection.Thisbiasvoltagesourcemustbestabilizedbyanexternalfiltercapacitorof1 μF. The line drivers in the TSB81BA3E are designed to work with external 112-Ω termination resistor networks to matchthe110-Ω cableimpedance.Oneterminationnetworkisrequiredateachendofatwisted-paircable.Each network is composed of a pair of series-connected ~56-Ω resistors. The midpoint of the pair of resistors that are connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that are directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with otherinternaloperatingcurrents. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Overview (continued) When the power supply of the TSB81BA3E is off while the twisted-pair cables are connected, the TSB81BA3E transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at theotherendofthecable. When the TSB81BA3E is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forcedtothe1394a-onlymode(Data-Strobe-onlymode),thentheTPB+andTPB–terminalscanbetiedtogether and then pulled to ground; or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS terminalcanbeconnectedtoa1-μFcapacitortogroundorleftunconnected. To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2) needs to be pulled to ground through a 1-kΩ resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a 1394a-only port, the force data-strobe-only terminal (DS0, DS1, or DS2) needs to be pulled to 3.3 V V through CC a 1-kΩ resistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6 pin, which is recommended, or 4 pin). This mode is provided to ensure that 1394b Signalingisneversentacrossa1394acable. The TESTM, VREG_PD, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and VREG_PD terminals must be connected to V through a 1-kΩ resistor. The DD SEandSMterminalsmustbetiedtogroundthrougha1-kΩ resistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self- ID packet. They may be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB81BA3E, this bit may only be set by a write to the PHY register set. If a node desires to be a contenderforIRMorBM,thenthenodesoftwaremustsetthisbitinthePHYregisterset. TheLPS(linkpowerstatus)terminalworkswiththeLKON/DS2terminaltomanagethepowerusageinthenode. The LPS signal from the LLC is used with the LCtrl bit (see Table 4 and Table 5 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the stateoftheLCtrlbit). The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3E detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3E continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3E issues a bus reset. This broadcasts the node self-ID packet, whichcontainstheupdatedLbitstate(thePHYLLCnowbeingaccessible). The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists, which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY assertsLKON/DS2forapproximately167μsoruntilboththeLPSisactiveandtheLCTRLbitis1. 16 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 8.2 Functional Block Diagram R0 CPS R1 LPS Bias Voltage CNA DReceocedievre/Rd eDtiamtaer Cuarnrdent TPBIAS0 PINT Generator TPBIAS1 PCLK TPBIAS2 LCLK LREQ CTL0 Link CTL1 Interface TPA0+ I/O D0 TPA0- D1 D2 D3 D4 Bilingual D5 Cable Port 0 D6 TPB0+ D7 TPB0- RESETz Arbitration and Control LKON/DS2 State Machine BMODE Logic PD TPA1+ PC0 TPA1- Bilingual PC1 Cable Port 1 PC2 TPB1+ SE TPB1- SM TPA2+ DS0 TPA2- DS1 Bilingual TESTM Cable Port 2 TPB2+ VREG_PD TPB2- Crystal Oscillator, PLLSystem, XI and Transmit Clock Generator Voltage Transmit Regulator Data Encoder 8.3 Feature Description 8.3.1 TTLInputData The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the TSB81BA3E and can connect directly to low-power, low-voltageapplicationandgraphicprocessors.ThebitmappingislistedinTable1. Table1.PixelBitOrdering RED GREEN BLUE LSB R0 G0 B0 R1 G1 B1 R2 G2 B2 4-bitMSB R3 G3 B3 R4 G4 B4 Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Feature Description (continued) Table1.PixelBitOrdering(continued) RED GREEN BLUE 6-bitMSB R5 G5 B5 R6 G6 B6 8-bitMSB R7 G7 B7 8.3.2 LVDSOutputData ThepixeldataassignmentislistedinTable2for24-bit,18-bit,and12-bitcolorhosts. Table2.PixelDataAssignment 8-BIT 6-BIT 4-BIT SERIAL CHANNEL DATABITS FORMAT-1 FORMAT-2 FORMAT-3 NON-LINEARSTEP LINEARSTEP SIZE SIZE D0 R0D27 R2 R2 R0 R2 VCC D1 R1 R3 R3 R1 R3 GND D2 R2 R4 R4 R2 R0 R0 Y0 D3 R3 R5 R5 R3 R1 R1 D4 R4 R6 R6 R4 R2 R2 D6 R5 R7 R7 R5 R3 R3 D7 G0 G2 G2 G0 G2 VCC D8 G1 G3 G3 G1 G3 GND D9 G2 G4 G4 G2 G0 G0 D12 G3 G5 G5 G3 G1 G1 Y1 D13 G4 G6 G6 G4 G2 G2 D14 G5 G7 G7 G5 G3 G3 D15 B0 B2 B2 B0 B2 VCC D18 B1 B3 B3 B1 B3 GND D19 B2 B4 B4 B2 B0 B0 D20 B3 B5 B5 B3 B1 B1 D21 B4 B6 B6 B4 B2 B2 Y2 D22 B5 B7 B7 B5 B3 B3 D24 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC D25 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC D26 ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE D27 R6 R0 GND GND GND GND D5 R7 R1 GND GND GND GND D10 G6 G0 GND GND GND GND Y3 D11 G7 G1 GND GND GND GND D16 B6 B0 GND GND GND GND D17 B7 B1 GND GND GND GND D23 RSVD RSVD GND GND GND GND CLKOUT CLKIN CLK CLK CLK CLK CLK CLK 18 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 8.4 Device Functional Modes 8.4.1 InputClockEdge The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the CLKIN signal, where the rising or falling edge of the clock may be selected via CLKSEL. The selection of a clock rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pull-up resistor to pull CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to GND. 8.4.2 LowPowerMode The TSB81BA3E can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low- level on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to enable thedevicefornormaloperation. 8.4.3 1394bPortInterfaceConsiderations The TSB81BA3E has three 1394b cable ports that can operate at 100, 200, 400, or 800 Mbps. These ports are compliant with the IEEE Std 1394b-2002, standard. This section describes implementation considerations for the TSB81BA3E’s1394bcableports. • The cable not active (CNA) terminal is an output that reflects the state of the incoming 1394b cable port bias voltage. If no cable bias voltage is detected by the TSB81BA3E, then this output is asserted high. If the CNA terminalisnotused,thenitmustbeconnectedtoGNDthrougha43-kΩresistor. • The cable power status (CPS) terminal is an input that drives an internal comparator for the purpose of detecting the presence of 1394b cable power. Normally, terminal CPS is connected to the 1394b cable power source through a 390-kΩ resistor. However, if this detection feature is not used, then CPS should be connecteddirectlytoGND. • PC2, PC1, and PC0 are the power class programming inputs. These inputs are loaded into the power class field in the 1394b PHY base configuration registers. Since the binary value associated with the power class field is implementation specific, the system designer must reference the 1394b power class description table in the TSB81BA3E Data Manual to determine the appropriate PC2:0 input levels. Each terminal is connected to either GND or VDD_33 to specify the appropriate power class binary value. This connection may either be directorthroughaweakresistor. • Terminals R0 and R1 are provided to set the operating current of the cable driver. A 6.34-kΩ ±1% resistor is required to meet the IEEE Std. output voltage limits. One side of the resistor is connected to the R0 terminal and the other side of the resistor to the R1 terminal. Signal traces must be short to minimize noise coupling intothetwoterminals. • TPAxP, TPAxN, TPBxP, TPBxN, and TPBIASx comprise the five major terminals associated with 1394b PHY port (Where x = Port#). TPAxP and TPAxN are the cable-A differential signals. TPBxP and TPBxN are the cable-B differential signals. TPBIASx provides the 1.86-V nominal bias required for proper 1394a driver/receiver operation and for active cable connection signaling to the remote node. The 1394b TPA and TPBdifferentialpairsmustfollowthesameroutingguidelinesasthePCIExpressTXandRXdifferentialpairs except for the differential impedance requirement of 110 ohms. For an unused port, all five terminals can be left as no connects. See the attached schematics for external circuit recommendations between the TSB81BA3Eand1394bcableconnector. • The TSB81BA3E is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks required fortransmissionandresynchronizationofdataattheS100throughS800mediadatarates. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 8.5 Programming 8.5.1 Power-Class The PC0-PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21−23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 3. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loadedintothePwr_Classfieldinregister4. Table3.Power-ClassDescriptions PC0-PC2 DESCRIPTION 000 Nodedoesnotneedpoweranddoesnotrepeatpower 001 Nodeisself-poweredandprovidesaminimumof15Wtothebus. 010 Nodeisself-poweredandprovidesaminimumof30Wtothebus. 011 Nodeisself-poweredandprovidesaminimumof45Wtothebus. Nodecanbepoweredfromthebusandisusingupto3W;noadditionalpowerisneededtoenablethelink.Thenode 100 canalsoprovidepowertothebus.TheamountofbuspowerthatitprovidescanbefoundintheconfigurationROM. 101 Reservedforfuturestandardization. 110 Nodeispoweredfromthebusandusesupto3W.Anadditional3Wisneededtoenablethelink. 111 Nodeispoweredfromthebusandusesupto3W.Anadditional7Wisneededtoenablethelink. OuterShield Termination TSB81BA3E 400kΩ CPS VP Cable Power 1µF TPBIAS Pair 56Ω 56Ω 270pF TPA+ Cable TPA- Pair A 1MΩ 0.1µF TPA_REFGND CablePort TPB+ Cable TPB- Pair B 56Ω 56Ω TPB_REFGND VG 270pF 5kΩ (seeNoteA) NOTEA: TheIEEEStd1394-1995callsfora250-pFcapacitor,whichisanonstandardcomponentvalue.A270-pFcapacitorisrecommended. Figure4. TypicalTPCableConnections 20 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 Outer Cable Shield 1 MW 0.01 m F 0.001 m F Chassis Ground Figure5. TypicalDC-IsolatedOuterShieldTermination Outer Cable Shield Chassis Ground Figure6. Non-DC-IsolatedOuterShieldTermination 10 kW Link Power LPS Square-Wave Input LPS 10 kW Figure7. NonisolatedConnectionVariationsforLPS PHY VDD 18 kW Square-Wave Signal LPS 0.033 (cid:1)F 13 kW PHY GND Figure8. IsolatedCircuitConnectionforLPS Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 8.6 Register Maps 8.6.1 InternalRegisterConfiguration There are 16 accessible internal registers in the TSB81BA3E. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. Note that while this register set is compatible with 1394a--2000 register sets,somefieldshavebeenredefinedandthisregistersetcontainsadditionalfields. Table 4 shows the configuration of the base registers, and Table 5 gives the corresponding field descriptions. Thebaseregisterfielddefinitionsareunaffectedbytheselectedpagenumber. A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is readas0,butissubjecttofutureusage.Allregistersinaddresspages2through6arereserved. Table4.BaseRegisterConfiguration BITPOSITION ADDRESS 0 1 2 3 4 5 6 7 0000 PhysicalID R CPS 0001 RHB IBR Gap_Count 0010 Extended(111b) Num_Ports(0011b) 0011 PHY_Speed(111b) SREN Delay(1111b) 0100 LCtrl C Jitter(000b) Pwr_Class 0101 WDIE ISBR CTOI CPSI STOI PEI EAA EMC 0110 MaxLegacySPD BLINK Bridge Rsvd 0111 Page_Select Rsvd Port_Select Table5.BaseRegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION ThisfieldcontainsthephysicaladdressIDofthisnodedeterminedduringself-ID.Thephysical-IDis PhysicalID 6 Rd invalidafterabusresetuntiltheself-IDhascompletedasindicatedbyanunsolicitedregister0 statustransferfromthePHYtotheLLC. Root.Thisbitindicatesthatthisnodeistherootnode.TheRbitisresetto0bybusreset,andis R 1 Rd setto1duringtree-IDifthisnodebecomesroot. Cable-powerstatus.ThisbitindicatesthestateoftheCPSinputterminal.TheCPSterminalis CPS 1 Rd normallytiedtoserialbuscablepowerthrougha400-kΩresistor.A0inthisbitindicatesthatthe cable-powervoltagehasdroppedbelowitsthresholdforensuredreliableoperation. Root-holdoffbit.ThisbitinstructsthePHYtoattempttobecomerootafterthenextbusreset.The RHBbitisresetto0byahardwareresetandisunaffectedbyabusreset.Iftwonodesonasingle RHB 1 Rd/Wr bushavetheirrootholdoffbitset,thentheresultisnotdefined.Topreventtwonodesfromhaving theirroot-holdoffbitset,thisbitmustonlybewrittenusingaPHYconfigurationpacket. Initiatebusreset.ThisbitinstructsthePHYtoinitiatealong(166-μs)busresetatthenext opportunity.Anyreceiveortransmitoperationinprogresswhenthisbitissetcompletesbeforethe IBR 1 Rd/Wr busresetisinitiated.TheIBRbitisresetto0afterahardwareresetorabusreset.Caremustbe exercisedwhenwritingtothisbittonotchangetheotherbitsinthisregister.Itisrecommendedthat wheneverpossibleabusresetbeinitiatedusingtheISBRbitandnottheIBRbit. Arbitrationgapcount.Thisvaluesetsthesubaction(fair)gap,arb-resetgap,andarb-delaytimes. Thegapcountcanbeseteitherbyawritetotheregister,orbyreceptionortransmissionofa PHY_CONFIGpacket.Thegapcountisresetto3Fhbyhardwareresetoraftertwoconsecutive Gap_Count 6 Rd/Wr busresetswithoutaninterveningwritetothegapcountregister(eitherbyawritetothePHY registerorbyaPHY_CONFIGpacket).Itisstronglyrecommendedthatthisfieldonlybe changedusingPHYconfigurationpackets. Extendedregisterdefinition.FortheTSB81BA3E,thisfieldis111b,indicatingthattheextended Extended 3 Rd registersetisimplemented. Numberofports.FortheTSB81BA3E,thisfieldindicatesthenumberofportsimplementedinthe Num_Ports 4 Rd PHY.Thisfieldis3. PHYspeedcapability.FortheTSB81BA3E,thisfieldisnolongerused.Thisfieldis111b.Speeds PHY_Speed 3 Rd for1394bPHYsmustbecheckedonaport-by-portbasis. 22 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 Table5.BaseRegisterFieldDescriptions(continued) FIELD SIZE TYPE DESCRIPTION PHYrepeaterdatadelay.Thisfieldindicatestheworst-caserepeaterdatadelayofthePHY, expressedas144+(delay×20)ns.FortheTSB81BA3E,thisfieldis02h. ThisvalueistherepeaterdelayfortheS400Bcase,whichisslowerthantheS800Bor1394a Delay 4 Rd cases.SincetheIEEE1394B−2002StdPhyregistersetonlyhasasinglefieldforthedelay parameter,theslowestvalueisused.IfanetworkusesonlyS800Bor1394aconnections,thena delayvalueof00hmaybeused.TheworstcasePhyrepeaterdelayis197nsforS400Band127 nsforS800Bcablespeeds(trained,rawbitspeed). Link-activestatuscontrol.ThisbitcontrolstheindicatedactivestatusoftheLLCreportedintheself- IDpacket.ThelogicalANDofthisbitandtheLPSactivestatusisreplicatedintheLfield(bit9)of theself-IDpacket.TheLLCbitinthenodeself-IDpacketissetactiveonlyifboththeLPSinputis activeandtheLCtrlbitisset. TheLCtrlbitprovidesasoftware-controllablemeanstoindicatetheLLCself-IDactivestatusinlieu LCtrl 1 Rd/Wr ofusingtheLPSinputterminal. TheLCtrlbitissetto1byhardwareresetandisunaffectedbybusreset. NOTE: The state ofthePHY-LLC interfaceis controlledsolely by theLPSinput,regardlessofthe stateoftheLCtrlbit.IfthePHY-LLCinterfaceisoperationalasdeterminedbytheLPSinputbeing active,thenreceivedpacketsandstatusinformationcontinuetobepresentedontheinterface,and anyrequestsindicatedontheLREQinputareprocessed,eveniftheLCtrlbitisclearedto0. Contenderstatus.Thisbitindicatesthatthisnodeisacontenderforthebusorisochronous resourcemanager.Thisbitisreplicatedinthecfield(bit20)oftheself-IDpacket.Thisbitissetto0 C 1 Rd/Wr onhardwarereset.Afterhardwarereset,thisbitcanonlybesetviaasoftwareregisterwrite.This bitisunaffectedbyabusreset. PHYrepeaterjitter.Thisfieldindicatestheworst-casedifferencebetweenthefastestandslowest Jitter 3 Rd repeaterdatadelay,expressedas(jitter+1)×20ns.FortheTSB81BA3E,thisfieldis0. Nodepowerclass.Thisfieldindicatesthisnodepowerconsumptionandsourcecharacteristicsand isreplicatedinthepwrfield(bits21–23)oftheself-IDpacket.Thisfieldisresettothestate Pwr_Class 3 Rd/Wr specifiedbythePC0-PC2inputterminalsuponahardwarereset,andisunaffectedbyabusreset. SeeTable3. Watchdoginterruptenable.Thisbit,ifsetto1,enablestheporteventinterrupt(PIE)bittobeset whenresumeoperationsbeginonanyport,orwhenanyoftheCTOI,CPSI,orSTOIinterruptbits WDIE 1 Rd/Wr aresetandthelinkinterfaceisnonoperational.Thisbitisresetto0byhardwareresetandis unaffectedbybusreset. Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 μs) arbitratedbusresetatthenextopportunity.Thisbitisresetto0byabusreset.Itisrecommended that short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node ISBR 1 Rd/Wr initiateshortbusresetstominimizeanydisturbancetoanaudiostream. NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device resultsinalongbusresetbeingperformed. Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start and might indicate that the bus is configured in a loop. This bit is reset to 0 by hardwareresetorbywritinga1tothisregisterbit. IftheCTOIandWDIEbitsarebothsetandtheLLCisorbecomesinactive,thenthePHYactivates CTOI 1 Rd/Wr theLKON/DS2outputtonotifytheLLCtoservicetheinterrupt. NOTE: If the network is configured in a loop, then only those nodes that are part of the loop generate a configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/orself-IDprocesstocompleteandthengenerateastatetime-outinterruptandbusreset.This bitisonlysetwhenthebustopologyincludes1394anodes;otherwise,1394bloophealingprevents loopsfrombeingformedinthetopology. Cable power status interrupt. This bit is set to 1 when the CPS input transitions from high to low, indicatingthatcablepowermightbetoolowforreliableoperation.Thisbitisresetto1byhardware CPSI 1 Rd/Wr reset.Itcanbeclearedbywritinga1tothisregisterbit. IftheCPSIandWDIEbitsarebothsetandtheLLCisorbecomesinactive,thenthePHYactivates theLKON/DS2outputtonotifytheLLCtoservicetheinterrupt. State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a busresettooccur).Thisbitisresetto0byhardwareresetorbywritinga1tothisregisterbit. STOI 1 Rd/Wr IftheSTOIandWDIEbitsarebothsetandtheLLCisorbecomesinactive,thenthePHYactivates theLKON/DS2outputtonotifytheLLCtoservicetheinterrupt. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Table5.BaseRegisterFieldDescriptions(continued) FIELD SIZE TYPE DESCRIPTION Porteventinterrupt.Thisbitissetto1onanychangeintheconnected,bias,disabled,orfaultbits foranyportforwhichtheportinterruptenable(PEI)bitisset.Additionally,iftheresumingport PEI 1 Rd/Wr interruptenable(WDIE)bitisset,thenthePEIbitissetto1atthestartofresumeoperationson anyport.Thisbitisresetto0byhardwarereset,orbywritinga1tothisregisterbit. Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration accelerationenhancementsdefinedin1394a-2000 (ACK-acceleratedarbitration, asynchronousfly- by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset andisunaffectedbybusreset.Thisbithasnoeffectwhenthedeviceisoperatingin1394bmode. EAA 1 Rd/Wr NOTE:Theuseofacceleratedarbitrationiscompletelycompatiblewithnetworkscontaininglegacy IEEEStd1394-1995PHYs.TheEAAbitissetonlyiftheattachedLLCis1394a-2000-compliant.If the LLC is not 1394a-2000 or 1394b-2002-compliant, then the use of the arbitration acceleration enhancements can interfere with isochronous traffic by excessively delaying the transmission of cycle-startpackets. Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packetsofdifferingspeedsinaccordancewiththeprotocolsdefinedin1394a-2000.Thisbitisreset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is EMC 1 Rd/Wr operatingin1394bmode. NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attachedLLCbe1394a-2000or1394b-2002-compliant. Maximumlegacy-pathspeed.Thisfieldholdsthemaximumspeedcapabilityofanylegacynode MaxLegacySPD 3 Rd (1394a-2000or1394-1995-compliant)asindicatedintheself-IDpacketsreceivedduringbus initialization.EncodingisthesameasforthePHY_SPEEDfield(butlimitedtoS400maximum). Beta-modelink.ThisbitindicatesthataBeta-mode-capablelinkisattachedtothePHY.Thisbitis BLINK 1 Rd setbytheBMODEinputterminalontheTSB81BA3E. Thisfieldcontrolsthevalueofthebridge(brdg)fieldinself-IDpacket.Thepowerresetvalueis0. Bridge 2 Rd/Wr DetailsforwhentosetthesebitsarespecifiedintheIEEE1394.1bridgingspecification. Page_Select.Thisfieldselectstheregisterpagetousewhenaccessingregisteraddresses8 Page_Select 3 Rd/Wr through15.Thisfieldisresetto0byahardwareresetandisunaffectedbybusreset. Port_Select.Thisfieldselectstheportwhenaccessingper-portstatusorcontrol(forexample,when Port_Select 4 Rd/Wr oneoftheportstatus/controlregistersisaccessedinpage0).Portsarenumberedstartingat0. Thisfieldisresetto0byhardwareresetandisunaffectedbybusreset. The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register7.Table6showstheconfigurationoftheportstatuspageregisters,andTable7 givesthecorresponding fielddescriptions.Iftheselectedportisunimplemented,thenallregistersintheportstatuspagearereadas0. Table6.Page0(PortStatus)RegisterConfiguration BITPOSITION ADDRESS 0 1 2 3 4 5 6 7 1000 Astat Bstat Ch Con RxOK Dis 1001 Negotiated_speed PIE Fault Standby_fault Disscrm B_Only(0) 1010 DC_connected Max_port_speed LPP Cable_speed 1011 Connection_unreliable Reserved Beta_mode Reserved 1100 Port_error 1101 Reserved Loop_disable In_standby Hard_disable 1110 Reserved 1111 Reserved 24 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 Table7.Page0(PortStatus)RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION TPAlinestate.ThisfieldindicatestheinstantaneousTPAlinestateoftheselectedport,encodedas follows: Code ArbValue Astat 2 Rd 11 Z 01 1 10 0 00 invalid TPBlinestate.ThisfieldindicatestheTPBlinestateoftheselectedport.Thisfieldhasthesame Bstat 2 Rd encodingastheAstatfield. Child/parentstatus.A1indicatesthattheselectedportisachildport.A0indicatesthattheselected Ch 1 Rd portistheparentport.Adisconnected,disabled,orsuspendedportisreportedasachildport.The Chbitisinvalidafterabusresetuntiltree-IDhascompleted. Debounced port connection status. This bit indicates that the selected port is connected. The connectionmustbestableforthedebouncetimeofapproximately341msfortheConbittobesetto 1.TheConbitisresetto0byhardwareresetandisunaffectedbybusreset. Con 1 Rd NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but this does not mean that the port is necessarily active. For 1394b-coupled connections, the Con bit is set when a portdetectsconnectiontonesfromthepeerPHYandoperating-speednegotiationiscompleted. Receive OK. In 1394a-2000 mode this bit indicates the reception of a debounced TPBias signal. In RxOK 1 Rd Betamode,thisbitindicatesthereceptionofacontinuouselectricallyvalidsignal. Note:RxOKissettofalseduringthetimethatonlyconnectiontonesaredetectedinBetamode. Portdisabledcontrol.Ifthisbitis1,thentheselectedportisdisabled.TheDisbitisresetto0by hardwarereset(allportsareenabledfornormaloperationfollowinghardwarereset).TheDisbitisnot Dis 1 Rd/Wr affectedbybusreset.Whenthisbitisset,theportcannotbecomeactive;however,theportstill tones,butdoesnotestablishanactiveconnection. IndicatesthemaximumspeednegotiatedbetweenthisPHYportanditsimmediatelyconnectedport. Negotiated_speed 3 Rd TheencodingisasforMax_port_speed.ItissetduringconnectionwheninBetamodeortoavalue establishedduringself-IDwhenin1394a-2000mode. Port-event-interruptenable.Whenthisbitis1,aporteventontheselectedportsetstheport-event- PIE 1 Rd/Wr interrupt(PEI)bitandnotifiesthelink.Thisbitisresetto0byahardwareresetandisunaffectedby busreset. Fault.Thisbitindicatesthataresumefaultorsuspendfaulthasoccurredontheselectedport,and thattheportisinthesuspendedstate.Aresume-faultoccurswhenaresumingportfailstodetect Fault 1 Rd/Wr incomingcablebiasfromitsattachedpeer.Asuspendfaultoccurswhenasuspendingportcontinues todetectincomingcablebiasfromitsattachedpeer.Writing1tothisbitclearstheFaultbitto0.This bitisresetto0byhardwareresetandisunaffectedbybusreset. Thisbitissetto1ifanerrorisdetectedduringastandbyoperationandclearedonexitfromthe Standby_fault 1 Rd/Wr standbystate.Awriteof1tothisbitorreceiptoftheappropriateremotecommandpacketclearsitto 0.Whenthisbitiscleared,standbyerrorsarecleared. Disablescrambler.Ifthisbitissetto1,thenthedatasentduringpackettransmissionisnot Disscrm 1 Rd/Wr scrambled. B_Only 1 Rd Beta-modeoperationonly.FortheTSB81BA3E,thisbitissetto0forallports. Ifthisbitissetto1,theporthasdetectedadcconnectiontothepeerportbymeansofa1394a-style DC_connected 1 Rd connect-detectcircuit. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Table7.Page0(PortStatus)RegisterFieldDescriptions(continued) FIELD SIZE TYPE DESCRIPTION Max_port_speed ThemaximumspeedatwhichaportisallowedtooperateinBetamode.Theencodingis: 000=S100 001=S200 010=S400 011=S800 100=S1600 101=S3200 Max_port_speed 3 Rd/Wr 110=reserved 111=reserved Anattempttowritetotheregisterwithavaluegreaterthanthehardwarecapabilityoftheportresults in the maximum value that the port is capable of being stored in the register. The port uses this registeronlywhenanewconnectionisestablishedintheBetamodeorwhenaportisprogrammed as a Beta-only port. When a port is programmed as a bilingual port, it is fixed at S400 for the Beta speed and is not updated by a write to this register. The power reset value is the maximum speed capable oftheport.Softwarecan modifythisvaluetoforce a port totrainata lower-than-maximum speed(wheninaBeta-onlymode),butnolowerthantheminimumspeed. LPP(Local_plug_ 1 Rd Thisflagissetpermanentlyto1. present) Thisvariableissettothemaximumspeedthattheportiscapableof.Theencodingisthesameasfor Cable_speed 3 Rd Max_port_speed. Connection_ Ifthisbitissetto1,thenaBeta-modespeednegotiationhasfailedorsynchronizationhasfailed.A 1 Rd/Wr unreliable writeof1tothisfieldresetsthevalueto0. OperatinginBetamode.Ifthisbitis1,theportisoperatinginBetamode;itisequalto0otherwise Beta_mode 1 Rd (thatis,whenoperatingin1394a-2000mode,orwhendisconnected).IfConis1,RxOKis1,and Beta_modeis0,thentheportisactiveandoperatinginthe1394a-2000mode. Incrementedwhentheportreceivesaninvalidcodeword,unlessthevalueisalready255.Cleared Port_error 8 Rd/Wr whenread(includingbeingreadbymeansofaremoteaccesspacket).Intendedforusebyasingle bus-widediagnosticprogram. Thisbitissetto1iftheporthasbeenplacedintheloop-disablestateaspartoftheloop-freebuild Loop_disable 1 Rd process(thePHYsateitherendoftheconnectionareactive,butiftheconnectionitselfwere activated,thenaloopwouldexist).Clearedonbusresetandondisconnection. In_standby 1 Rd Thisbitissetto1iftheportisinstandbypower-managementstate. Noeffectunlesstheportisdisabled.Ifthisbitissetto1,theportdoesnotmaintainconnectivity statusonanacconnectionwhendisabled.ThevaluesoftheConandRxOKbitsareforcedto0.This Hard_disable 1 Rd/Wr flagcanbeusedtoforcerenegotiationofthespeedofaconnection.Itcanalsobeusedtoplacethe deviceintoalower-powerstatebecausewhenhard-disabled,aportnolongertonestomaintain 1394bac-connectivitystatus. The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 8 shows the configuration of the vendor identification page,andTable9showsthecorrespondingfielddescriptions. 26 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 Table8.Page1(VendorID)RegisterConfiguration BITPOSITION ADDRESS 0 1 2 3 4 5 6 7 1000 Compliance 1001 Reserved 1010 Vendor_ID0 1011 Vendor_ID1 1100 Vendor_ID2 1101 Product_ID0 1110 Product_ID1 1111 Product_ID2 Table9.Page1(VendorID)RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION Compliancelevel.FortheTSB81BA3E,thisfieldis02h,indicatingcompliancewiththe1394b-2002 Compliance 8 Rd specification. Manufacturer'sorganizationallyuniqueidentifier(OUI).FortheTSB81BA3E,thisfieldis08_00_28h Vendor_ID 24 Rd (TexasInstruments)(theMSBisatregisteraddress1010b). Productidentifier.FortheTSB81BA3E,thisfieldcanbeeither83_13_07h(theMSBisatregister Product_ID 24 Rd address1101b). The vendor-dependent page provides access to the special control features of the TSB81BA3E, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10 shows the configuration of the vendor-dependent page and Table11showsthecorrespondingfielddescriptions. Table10.Page7(Vendor-Dependent)RegisterConfiguration BITPOSITION ADDRESS 0 1 2 3 4 5 6 7 1000 Reserved Reserved 1001 Reservedfortest 1010 Reservedfortest 1011 Reservedfortest 1100 Reservedfortest 1101 Reservedfortest 1110 SWR Reservedfortest 1111 Reservedfortest Table11.Page7(Vendor-Dependent)RegisterFieldDescriptions FIELD SIZE TYPE DESCRIPTION Softwarehardreset.Writinga1tothisbitforcesahardresetofthePHY(sameeffectasmomentarily SWR 1 Rd/Wr assertingtheRESETterminallow).Thisbitisalwaysreadasa0. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The TSB81BA3E provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line Interface (HCI) Requirements transceivers. The transceivers include circuitry to monitor the line conditions as needed for determiningconnectionstatus,forinitializationandarbitration,andforpacketreceptionandtransmission. 9.2 Typical Application A common application of the TSB81BA3E is a three-port 1394 transceiver, it can be configured port-basis for datastrobeonly,betamodeorbilingualmodes. Figure9. 3-Port1394Transceiverin1394bMode 28 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 Typical Application (continued) 9.2.1 DesignRequirements Forthisdesignexample,usetheparametersshowninTable12. Table12.DesignParameters PARAMETER EXAMPLEVALUE PHYPOWER 3.3V LLCController TSB82AA2 Crystal 24.576MHz DownstreamPorts 3-1394Bilingual PowerClass PC[0:2]=100 BusPower 12V 9.2.2 DetailedDesignProcedure 9.2.2.1 PortTerminationfora1394BilingualPort The TPA and TPB lines require termination as illustrated in the following figure, the 1394 node connecting to this externalportshallhavethesameterminationsonitsports. WhenconfiguringtheTSB81BA3Eporttobedata-strobeonlytheTPBIASterminalcanbeleftunconnected. Figure10. PortTermination Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 9.2.2.2 PHY-LINKInterface The PHY-link interface of the TSB81BA3E can follow either the 1394a protocol or the 1394b protocol. When using any 1394-1995 or 1394a links such as the TSB12LV01B or the TSB12LV32, the PHY-link interface has to beinthe1394aprotocol.Inthiscase,theBMODEpinhastobetiedlowtoGND. When using any 1394b link such as the TSB82AA2, the PHY-link interface has to be in the 1394b protocol. In thiscase,theBMODEpinistiedhigh.TheBMODEpinonlysetsthemodeofoperationofthePHY-linkinterface; itdoesnotsetthemodeofoperationofthecableinterface.Noisolationisimplementedinthisschematic. The PHY and link operate off of the same ground plane. To reduce EMI emissions and reduce reflections on the PCLK line, a series-damping resistor is recommended. The schematic shows a 0-Ω resistor, which is essentially a placeholder on the board. To reduce EMI, a 22-Ω resistor on the PCLK line is recommended. This resistor should be placed as close to the PHY as possible. Its value can be adjusted to reduce emissions. By slowing down the edge rates on PCLK, this 22-Ω resistor significantly reduces reflections that may occur when the distancebetweenthePHYandlinkislarge(greaterthan4inchesinthiscase). The Link Request signal (LREQ) is input to the PHY from the link. The link uses this to initiate a service request to the PHY. When the BMODE pin is deasserted, the IEEE 1394b-2002 BOSS arbitration is disabled and the LREQrequeststreamfollowsthe1394aspecification. If a power down option control for PD is not implemented, the PD pin on the PHY (pin 77) should be tied to groundthrougha1-kΩ resistortokeepthePHYenabled. 10 Power Supply Recommendations AnothermeanstominimizeEMIemissionsistoadddecouplingcapacitorswithaferritebeadatPLLVDDpinand DVDD pins of the chip. This array should be as close as possible to the chip in order to minimize the inductance of the line and minimize noise contributions to the system, a suggested example is shown in Figure 11(a) and Figure 11(b). In the case of DVDD pins, it is recommended to tie them up to a single low impedance point in the board and then adding the decoupling capacitors in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and Jitter performance. Both EMI and Jitter should be taken into account before altering the configuration. VDD VDD 60Ohmsat100MHz 60Ohmsat100MHz PLLVDD DVDD PLANE PLANE 10uF 0.001uF 0.01uF 1uF 10uF 0.001uF 0.01uF 1uF (a) (b) Figure11. SuggestedArrayatPLLVDDandDVDDinOrdertoMinimizeEMI 30 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 11 Layout 11.1 Layout Guidelines Put pads in for all components in prototype boards. When testing prototype boards for EMI and ESD, some of thefollowingcomponentsmaynotberequired: • The 1394 connector gasket between chassis GND, 1394 connector shield, and metal bracket on PCB board (forexampleonaPCIadd-incard). • TheferriteonthecableV-groundpin(socketpin2). • TheferriteonthecableV+powerpin(socketpin1). 11.1.1 BoardStackup Because of the high frequencies associated with 1394, a 1394 board with at least four layers is recommended; twosignallayersseparatedbyagroundandpowerlayer(SeeFigure12). SIGNAL1 GROUND POWER SIGNAL2 Figure12. Four-LayerBoardStackup The majority of signal traces should be run on a single layer, preferably SIGNAL1. Immediately next to this layer should be the GND plane which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used (see Section 3.3).MinimizingthenumberofsignalviascouldreduceEMIduetoareductionininductanceathighfrequencies. 11.1.2 DigitalandAnalogPartitioning If separate power planes are used, they must be tied together at one point through a low impedance bridge or preferably through a ferrite bead (See Figure 13). Care must be taken to capacitively de-couple each power rail closetothedevice. The analog ground (AGND), digital ground (DGND), and Phase Locked Loop (PLL) ground (PLLGND) must be tiedtogethertothelowimpedancecircuitboardgroundplane. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Layout Guidelines (continued) ANALOGPOWER FERRITEBEAD SHIELDGND DIGITALPOWER FERRITE BEAD POPWLLER VCCP Figure13. AImagePlanePartition,RouteSignalCarefully 11.1.3 ImagePlanes Animageplaneisalayerofcopper(voltageplaneorgroundplane),physicallyadjacenttoasignalroutingplane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a 1394 board the best image plane is the ground plane, since on most designs a common ground can be used for both analog and digital circuits. Care should be taken not to route traces such that they cross from one plane to the other, as this can cause a broken RF return path resulting in an EMI radiating loop (See Figure 7). This is important for higher frequency or repetitive signals. Therefore it is best to run all clock signals on the signal plane above a solid ground plane (on a multi-layer board). Avoid crossing the image power or ground plane boundaries with high speed clock signal traces immediately above or below the separated planes. This also holds true for the twisted pair signals (TPA, TPB). Special care should be applied to the LPS and LKON signals as these do not alwaysrouteeasilyonasinglelayer. AnyunusedareaofthetopandbottomsignallayersofthePCBcanbefilledwithcopperthatisconnectedtothe groundplanethroughvias. DON'T DO Figure14. DoNotCrossImagePlaneBoundaries 32 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 Layout Guidelines (continued) Care should also be taken not to overlap planes that do not reference each other. For example do not overlap a digital power plane with an analog power plane as this will produce a capacitance between the overlapping area whichcouldpassRFemissionsfromoneplanetotheother.SeeFigure15. UNWANTEDRFPATHCAUSEDBYOVERLAPPINGPLANES Figure15. DoNotOverlapPlanes Avoidimageplaneviolations.TracesthatrouteoveraslotinanimageplaneresultsinapossibleRFreturnloop. SeeFigure16. RFRETURNCURRENT RFRETURNCURRENT SLOTINIMAGEPLANE SLOTIN IMAGE PLANE BAD BETTER Figure16. DoNotViolateImagePlanes 11.1.4 PartsPlacement Components should be placed on the board such that the traces coming from a component will always be above its corresponding image plane. The PHY should also be placed close to the link to reduce the trace length of the PHY/link interface. For less radiated EMI, place the PHY device as far away from the 1394 connector (termination network should be close to the PHY) as is practical. Balance this against keeping the twisted pair trace lengths short (for signal integrity), keeping the PHY-Link interface traces short (for signal integrity and EMI) andkeepingthePHYawayfromanyswitchingpowersupply. 11.1.5 DecouplingCapacitors Properly used decoupling caps keep RF energy from being injected into the power planes from high frequency components. Decoupling capacitors also provides a localized source of pulsed DC power for device or components. This reduces peak current surges from propagating across the board. Use 0.1 µF and 0.001 µF decoupling caps on the PHY and link (For PLLVDD see Power Supply Recommendations. Minimize the trace length between the decoupling capacitor and the corresponding power pins on the device. Also minimize the tracelengthfromthecapacitorpadtothepowerorgroundplane.SeeFigure17. Figure17. DecouplingCapacitors Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com Layout Guidelines (continued) 11.1.6 3WRuleforSCLK When routing the SCLK trace from the PHY to link, try to use the 3W spacing rule. The distance from the center of the SCLK trace to the center of any adjacent signal trace should be at least three times the width of the SCLK trace. SCLK is a 49.152 MHz clock with a fast rise time. Using the 3W rule will cut down on crosstalk between traces.Ingeneral,leavespacebetweeneachofthetracesrunningfromthePHYtolink.Avoidusingrightangles whenroutingtracestominimizetheroutingdistanceandimpedancediscontinuities. For further protection from crosstalk, run guard traces beside the SCLK signal from PHY to Link (GND pin to GND pin if possible). This is to lessen clock signal coupling onto the other PHYLink interface traces near it and thusradiatingtheclocksignalfrommoreantennas.SeeFigure18. 3W 3W TRACE W Figure18. 3WRule 34 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

TSB81BA3E www.ti.com SLLS783C–MAY2009–REVISEDMARCH2016 12 Device and Documentation Support 12.1 Device Support 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2009–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TSB81BA3E

TSB81BA3E SLLS783C–MAY2009–REVISEDMARCH2016 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 13.1 Designing With PowerPAD™ Devices (PFP Package Only) The TSB81BA3E is housed in a high performance, thermally enhanced, 80-terminal PFP PowerPAD™ package. Use of the PowerPAD™ package does not require any special considerations except to note that the PowerPAD™, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD™ PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD™ of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the maximum size required for the keepout area for the 80-terminal PFP PowerPAD™packageis10mm×10mm.TheactualPowerPAD™sizefortheTSB81BA3Eis6mm × 6mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD™ package. The thermal land varies in size, depending on the PowerPAD™ package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may notcontainnumerousthermalviasdependingonPCBconstruction. Other requirements for thermal lands and thermal vias are detailed in the Texas Instruments PowerPAD™ Thermally Enhanced Package application report (SLMA002) available via the Texas Instruments web page at http://www.ti.com. Figure19. ExampleofaThermalLandfortheTSB81BA3EPHY The thermal land must be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size ought to be as large as possible without shorting the device signal terminals. The thermal land can be soldered to the exposed thermalpadusingstandardreflowsolderingtechniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low impedance ground plane for the device. More informationmaybeobtainedfromtheTIapplicationnote PHYLayout(SLLA020). 36 SubmitDocumentationFeedback Copyright©2009–2016,TexasInstrumentsIncorporated ProductFolderLinks:TSB81BA3E

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TSB81BA3EIPFP ACTIVE HTQFP PFP 80 96 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 TSB81BA3EI & no Sb/Br) TSB81BA3EIZAJ ACTIVE NFBGA ZAJ 168 260 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 TSB81BA3EI & no Sb/Br) TSB81BA3EPFP ACTIVE HTQFP PFP 80 96 Green (RoHS NIPDAU Level-3-260C-168 HR 0 to 70 TSB81BA3E & no Sb/Br) TSB81BA3EZAJ ACTIVE NFBGA ZAJ 168 260 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 70 TSB81BA3E & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

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