TS12A4516,, TS12A4517 www.ti.com................................................................................................................................................. SCDS236B–DECEMBER2006–REVISEDAPRIL2009 DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES FEATURES 1 • ±1-Vto±6-VDual-SupplyOperation • SpecifiedLowON-LeakageCurrents: • SpecifiedON-StateResistance: – 5nAat25°C – 25ΩMaxWith±5-VSupply – 10nAat85°C – 35ΩMaxWith±3.3-VSupply • LowChargeInjection:13pC(±5-VSupply) – 47ΩMaxWith±1.8-VSupply • FastSwitchingSpeed: • SpecifiedLowOFF-LeakageCurrents: tON=85ns,tOFF=50ns(±5-VSupply) – 5nAat25°C • Break-Before-MakeOperation(tON>tOFF) – 10nAat85°C • Latch-UpPerformanceExceeds100mAPer JESD78,ClassII • ESDPerformanceTestedPerJESD22 – 2500-VHuman-BodyModel(A114-F) – 1000-VCharged-DeviceModel(C101-C) – 250-VMachineModel(A115-A) DESCRIPTION/ORDERING INFORMATION The TS12A4516/TS12A4517 are single pole/single throw (SPST), low-voltage, dual-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A4516 is normally open (NO). The TS12A4517 is normallyclosed(NC). These CMOS switches can operate continuously with a dual supplies between ±1 V and ±6 V [(2 V < (V – V ) < + – 12V].Eachswitchcanhandlerail-to-railanalogsignals.TheOFF-leakagecurrentmaximumisonly5 nA at 25°C or10nAat85°C. Forpin-compatiblepartsforusewithsinglesupply,seetheTS12A4514/TS12A4515. ORDERINGINFORMATION T PACKAGE(1)(2) ORDERABLEPARTNUMBER TOP-SIDEMARKING A Reelof1500 TS12A4516D SOIC–D YD516 Reelof2500 TS12A4516DR SOP(SOT-23)–DBV Reelof3000 TS12A4516DBVR 9CL_ –40°Cto85°C Reelof1500 TS12A4517D SOIC–D YD517 Reelof2500 TS12A4517DR SOP(SOT-23)–DBV Reelof3000 TS12A4517DBVR 9CM_ (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. (2) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TS12A4516,, TS12A4517 SCDS236B–DECEMBER2006–REVISEDAPRIL2009................................................................................................................................................. www.ti.com PIN CONFIGURATIONS TS12A4516 TS12A4517 TS12A4516 TS12A4517 D PACKAGE D PACKAGE DBV PACKAGE DBV PACKAGE (TOPVIEW) (TOPVIEW) (TOPVIEW) (TOPVIEW) COM 1 8 NO COM 1 8 NC COM 1 5 V+ COM 1 5 V+ N.C. 2 7 V– N.C. 2 7 V– NC 2 NO 2 N.C. 3 6 IN N.C. 3 6 IN V+ 4 5 N.C. V+ 4 5 N.C. V– 3 4 IN V– 3 4 IN SWITCH STATE INPUT TS12A4516 TS12A4517 N.C.= Not internally connected LOW OFF ON NC = Normally closed HIGH ON OFF NO = Normally open Absolute Minimum and Maximum Ratings(1)(2) voltagesreferencedto0V MIN MAX UNIT V Supplyvoltagerange –0.3 13 V + V NC V Analogvoltagerange(3) V –0.3 V +0.3 V NO – + V COM V Logicinputrange V –0.3 V +0.3 V IN – + Continuouscurrentintoanyterminal ±20 mA Peakcurrent,NOorCOM(pulsedat1ms,10%dutycycle) ±30 mA ESDpermethod3015.7 >2000 V 8-pinSOIC(derate5.88mW/°Cabove70°C) 471 Continuouspowerdissipation(T =70°C) mW A 5-pinSOT23-5(derate7.1mW/°Cabove70°C) 571 T Operatingtemperaturerange –40 85 °C A T Storagetemperaturerange –65 150 °C stg Leadtemperature(soldering,10s) 300 °C (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum (3) VoltagesexceedingV orGNDonanysignalterminalareclampedbyinternaldiodes.Limitforward-diodecurrenttomaximumcurrent + rating. 2 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4516TS12A4517

TS12A4516,, TS12A4517 www.ti.com................................................................................................................................................. SCDS236B–DECEMBER2006–REVISEDAPRIL2009 Electrical Characteristics for ±5-V Supply(1) V =4.5Vto5.5V,V =–4.5Vto–5.5V,T =–40°Cto85°C(unlessotherwisenoted) + – A PARAMETER SYMBOL TESTCONDITIONS T MIN TYP(2) MAX UNIT A AnalogSwitch Analogsignalrange V ,V ,V V V V COM NO NC – + V =4.5V,V =–4.5V, 25°C 12 20 + – ON-stateresistance r V =3.5V, Ω on COM I =20mA Full 25 COM V =4.5V,V =–4.5V, 25°C 1.2 2.5 ON-stateresistance + – r V =–3.5V,0V,3.5V, Ω flatness on(flat) I COM=20mA Full 3 COM V =5.5V,V =–5.5V, 25°C 5 NO,NC I , + – OFFleakagecurrent(3) INNOC((OOFFFF)) VVCOMor=V4.5V=,–4.5V Full 10 nA NO NC V =5.5V,V =–5.5V, 25°C 5 COM + – OFFleakagecurrent(3) ICOM(OFF) VVCOMor=V–4.5=V4,.5V Full 10 nA NO NC V =5.5V,V =–5.5V, 25°C 5 COM + – ONleakagecurrent(3) ICOM(ON) VVCOMor=V5.5V=,open Full 10 nA NO NC DigitalControlInput(IN) Inputlogichigh V Full V –1.5 V IH + Inputlogiclow V Full V V –3.5 V IL – + Inputleakagecurrent I ,I V =V ,0V Full 0.010 m A IH IL IN + Dynamic 25°C 58 75 Turn-ontime t SeeFigure2 ns ON Full 85 25°C 28 45 Turn-offtime t SeeFigure2 ns OFF Full 50 Chargeinjection(4) Q CL=1nF,VNO=0V, 25°C –13 pC C R =0Ω,SeeFigure1 S NO,NC C , NO(OFF) f=1MHz,SeeFigure4 25°C 5.5 pF OFFcapacitance C NC(OFF) COM C f=1MHz,SeeFigure4 25°C 5.5 pF OFFcapacitance COM(OFF) COM C f=1MHz,SeeFigure4 25°C 16 pF ONcapacitance COM(ON) Digitalinputcapacitance C V =V ,0V 25°C 1.5 pF I IN + R =50Ω,C =15pF, Bandwidth BW L L 25°C 464 MHz V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, OFFisolation O L L 25°C –83 dB ISO V =1V ,f=1MHz NO RMS R =600Ω,C =15pF, Totalharmonicdistortion THD L L 25°C 0.07 % V =1V ,f=20kHz NO RMS Supply 25°C 70 V supplycurrent I V =0VorV m A + + IN + Full 80 25°C –70 V supplycurrent I V =0VorV m A – – IN + Full –80 (1) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum. (2) TypicalvaluesareatT =25°C. A (3) Leakageparametersare100%testedatmaximum-ratedhotoperatingtemperature,andareensuredbycorrelationat25°C. (4) Specifiedbydesign,notproductiontested Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TS12A4516TS12A4517

TS12A4516,, TS12A4517 SCDS236B–DECEMBER2006–REVISEDAPRIL2009................................................................................................................................................. www.ti.com Electrical Characteristics for ±3.3-V Supply(1) V =3.0Vto3.6V,V =–3.0Vto–3.6,T =–40°Cto85°C(unlessotherwisenoted) + – A PARAMETER SYMBOL TESTCONDITIONS T MIN TYP(2) MAX UNIT A AnalogSwitch Analogsignalrange V ,V ,V V V V COM NO NC – + V =3.0V,V =–3.0V, 25°C 17 25 + – ON-stateresistance r V =3V, Ω on COM I =20mA Full 35 COM ON-stateresistance V =–2V,0V,2V, 25°C 1.5 3 r COM Ω flatness on(flat) ICOM=20mA Full 4 V =3.6V,V =–3.6V, 25°C 5 NO,NC I + – OFFleakagecurrent(3) INNOC((OOFFFF)), VVCOMor=V3V,=–3V Full 10 nA NO NC V =3.6V,V =–3.6V, 25°C 5 COM + – OFFleakagecurrent(3) ICOM(OFF) VVCOMor=V–3V=,3V Full 10 nA NO NC V =3.6V,V =–3.6V, 25°C 5 COM + – ONleakagecurrent(3) ICOM(ON) VVCOMor=V3.6V=,open Full 10 nA NO NC DigitalControlInput(IN) Inputlogichigh V Full V –1.5 V IH + Inputlogiclow V Full V V –3.5 V IL – + Inputleakagecurrent I ,I V =V ,0V Full 0.01 m A IH IL IN + Dynamic 25°C 65 85 Turn-ontime t seeFigure2 ns ON Full 95 25°C 37 60 Turn-offtime t seeFigure2 ns OFF Full 70 Chargeinjection(4) Q CL=1nF,VNO=0V, 25°C –7.5 pC C R =0Ω,SeeFigure1 S NO,NC C NO(OFF) f=1MHz,SeeFigure4 25°C 5.5 pF OFFcapacitance C NC(OFF) COM C f=1MHz,SeeFigure4 25°C 5.5 pF OFFcapacitance COM(OFF) COM C f=1MHz,SeeFigure4 25°C 16 pF ONcapacitance COM(ON) Digitalinputcapacitance C V =V ,0V 25°C 1.5 pF I IN + R =50Ω,C =15pF, Bandwidth BW L L 25°C 464 MHz V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, OFFisolation O L L 25°C –83 dB ISO V =1V ,f=100kHz NO RMS R =600Ω,C =15pF, Totalharmonicdistortion THD L L 25°C 0.10 % V =1V ,f=20kHz NO RMS Supply 25°C 40 V supplycurrent I V =0VorV m A + + IN + Full 45 25°C –40 V supplycurrent I V =0VorV m A – – IN + Full 45 (1) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum. (2) TypicalvaluesareatT =25°C. A (3) Leakageparametersare100%testedatmaximum-ratedhotoperatingtemperature,andareensuredbycorrelationat25°C. (4) Specifiedbydesign,notproductiontested 4 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4516TS12A4517

TS12A4516,, TS12A4517 www.ti.com................................................................................................................................................. SCDS236B–DECEMBER2006–REVISEDAPRIL2009 Electrical Characteristics for ±1.8-V Supply(1) V =1.65Vto1.95V,V =–1.65Vto–1.95V,T =–40°Cto85°C(unlessotherwisenoted) + – A PARAMETER SYMBOL TESTCONDITIONS T MIN TYP(2) MAX UNIT A AnalogSwitch Analogsignalrange V ,V ,V V V V COM NO NC – + V =1.65V,V =–1.65V, 25°C 28 40 + – ON-stateresistance r V =0V, Ω on COM I =20mA Full 47 COM V =1.65V,V =–1.65V, 25°C 9 13 ON-stateresistance + – r V =–1.8V,0V,1.5V, Ω flatness on(flat) I COM=20mA Full 15 COM V =1.95V,V =–1.95V, 25°C 5 NO,NC I + – OFFleakagecurrent(3) INNOC((OOFFFF)), VVCOMor=V1.65=V–,1.65V Full 10 nA NO NC V =1.95V,V =–1.95V, 25°C 5 COM + – OFFleakagecurrent(3) ICOM(OFF) VVCOMor=V–1.6=51V.6,5V Full 10 nA NO NC V =1.95V,V =–1.95V, 25°C 5 COM + – ONleakagecurrent(3) ICOM(ON) VVCOMor=V1.95=Vo,pen Full 10 nA NO NC DigitalControlInput(IN) Inputlogichigh V Full V –1.5 V IH + Inputlogiclow V Full V V –3.5 V IL – + Inputleakagecurrent I ,I V =V ,0V Full 0.01 m A IH IL IN + Dynamic 25°C 90 120 Turn-ontime(4) t SeeFigure2 ns ON Full 150 25°C 95 150 Turn-offtime(4) t SeeFigure2 ns OFF Full 200 Chargeinjection(4) Q C =1nF,SeeFigure1 25°C –3.5 pC C L NO,NC C , NO(OFF) f=1MHz,SeeFigure4 25°C 6 pF OFFcapacitance C NC(OFF) COM C f=1MHz,SeeFigure4 25°C 6 pF OFFcapacitance COM(OFF) COM C f=1MHz,SeeFigure4 25°C 14.5 pF ONcapacitance COM(ON) Digitalinputcapacitance C V =V ,0V 25°C 1.5 pF I IN + R =50Ω,C =15pF, Bandwidth BW L L 25°C 464 MHz V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, OFFisolation O L L 25°C –83 dB ISO V =1V ,f=1MHz NO RMS R =600Ω,C =50pF, Totalharmonicdistortion THD L L 25°C 0.37 % V =1V ,f=20kHz NO RMS Supply 25°C 20 V supplycurrent I V =0VorV m A + + IN + Full 30 25°C –20 V supplycurrent I V =0VorV m A – – IN + Full –30 (1) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum. (2) TypicalvaluesareatT =25°C. A (3) Leakageparametersare100%testedatmaximum-ratedhotoperatingtemperature,andareensuredbycorrelationat25°C. (4) Specifiedbydesign,notproductiontested Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TS12A4516TS12A4517

TS12A4516,, TS12A4517 SCDS236B–DECEMBER2006–REVISEDAPRIL2009................................................................................................................................................. www.ti.com PINDESCRIPTION(1) PINNO. TS12A4516 TS12A4517 NAME DESCRIPTION D,P SOT23-5 D,P SOT23-5 1 1 1 1 COM Common 2,3,5 – 2,3,5 – N.C. Noconnect(notinternallyconnected) 4 5 4 5 V Positivepowersupply + 6 4 6 4 IN DigitalcontroltoconnectCOMtoNOorNC 7 3 7 3 V Negativepowersupply – 8 2 – – NO Normallyopen – – 8 2 NC Normallyclosed (1) NO,NC,andCOMpinsareidenticalandinterchangeable.Anymaybeconsideredasaninputoranoutput;signalspassinboth directions. 6 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4516TS12A4517

TS12A4516,, TS12A4517 www.ti.com................................................................................................................................................. SCDS236B–DECEMBER2006–REVISEDAPRIL2009 APPLICATION INFORMATION Power-Supply Considerations TheTS12A4516andTS12A4517operatewithpower-supplyvoltagesfrom±1Vto±6V[(2V<(V –V )<12V], + – but are tested and specified at ±5V, ±3.3V, and ±1.8V supplies. The pin-compatible TS12A4514 and TS12A4515 arerecommendedforusewhenonlyasinglesupplyisdesirable. The TS12A4516 and TS12A4517 construction is typical of most CMOS analog switches, except that they have only two supply pins: V and V . V and V drive the internal CMOS switches and set their analog voltage limits. + – + – Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V and V . + – OneofthesediodesconductsifanyanalogsignalexceedsV orV . + – Virtually all the analog leakage current comes from the ESD diodes to V or V . Although the ESD diodes on a + – given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is biased by either V or V and the analog signal. This means their leakages will vary as the signal varies. The + – difference in the two diode leakages to the V and V pins constitutes the analog-signal-path leakage current. All + – analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. Thisiswhybothsidesofagivenswitchcanshowleakagecurrentsofthesameoroppositepolarity. V and V also power the internal logic and logic-level translators. The logic-level translators convert the logic + – levelstoswitchedV andV signalstodrivetheanalogsignalgates. + – Logic-Level Thresholds Since these parts have no ground pin, the logic-level threshold is referenced to V . The threshold limits are V + + –1.5 V and V –3.5 V for V levels between 6 V and 3 V. When V = 2 V, the logic threshold is approximately 0.6 + + + V. CAUTION: Do not connect the TS12A4516/TS12A4517 V to 3 V and then connect the + logic-level pins to logic-level signals that operate from 5-V supply. TTL levels can exceed 3 V and violate the absolute maximum ratings, damaging the part and/orexternalcircuits. Test Circuits/Timing Diagrams NO or NC Figure1.ChargeInjection Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TS12A4516TS12A4517

TS12A4516,, TS12A4517 SCDS236B–DECEMBER2006–REVISEDAPRIL2009................................................................................................................................................. www.ti.com V+ V+ V+ VIN 50% NO VNO 0 V TS12A4516 VIN VNOPEAK 90% 90% IN COM VOUT 50 W V– 300 W 35 pF VOUT 0 V tON tOFF V+ V+ V+ VIN 50% NC VNO 0 V VIN TS12A4517 VNOPEAK 90% 90% IN COM VOUT V– 35 pF VOUT 50 W 300 W 0 V tOFF tON Figure2.SwitchingTimes V+ 10 nF V+ NO VIN 50 W 50 W or NC TS12A4516 V+ TS12A4517 VOUT MEAS REF IN COM V– 50 W 50 W Measurements are standardized against short at socket OFF Isolation = 20logVOUT terminals. OFF isolation is measured between COM and OFF VIN taenrdm inOaNls toenrm eiancahls sownit ceha. cOhN s lwositsc his. mSiegansaul reddir ebcetitowne etnh rCouOgMh ON Loss = 20log VOUT switch is reversed; worst values are recorded. VIN Figure3.OFFIsolationandONLoss V+ V+ NO or NC TS12A4516 TS12A4517 As 1-MHz IN COM Capacitance Required Analyzer V– Figure4.NO,NC,andCOMCapacitance 8 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4516TS12A4517

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TS12A4516D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD516 & no Sb/Br) TS12A4516DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (9CLA, 9CLM) & no Sb/Br) TS12A4516DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD516 & no Sb/Br) TS12A4517D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD517 & no Sb/Br) TS12A4517DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 (9CMA, 9CMM) & no Sb/Br) TS12A4517DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD517 & no Sb/Br) TS12A4517DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD517 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TS12A4516DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TS12A4516DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TS12A4517DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TS12A4516DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 TS12A4516DR SOIC D 8 2500 367.0 367.0 35.0 TS12A4517DR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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