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参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC SWITCH SPST 8SOIC模拟开关 IC Lo-Vltg Lo On-St Resist SPST CMOS |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 开关 IC,模拟开关 IC,Texas Instruments TS12A4514DR- |
数据手册 | |
产品型号 | TS12A4514DR |
产品种类 | 模拟开关 IC |
供应商器件封装 | 8-SOIC |
其它名称 | 296-21907-1 |
功能 | |
包装 | 剪切带 (CT) |
单位重量 | 76 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
导通电阻 | 15 欧姆 |
导通电阻—最大值 | 40 Ohms |
封装 | Reel |
封装/外壳 | 8-SOIC(0.154",3.90mm 宽) |
封装/箱体 | SOIC-8 |
工作温度 | -40°C ~ 85°C |
工作电源电压 | 2 V to 12 V |
工厂包装数量 | 2500 |
开关数量 | 1 |
开关配置 | SPST |
最大功率耗散 | 471 mW |
最大工作温度 | + 85 C |
最小工作温度 | - 40 C |
标准包装 | 1 |
电压-电源,单/双 (±) | 2 V ~ 12 V |
电压源 | 单电源 |
电流-电源 | 50nA |
电源电压-最大 | 12 V |
电源电压-最小 | 2 V |
电源电流—最大值 | 0.00005 mA |
电路 | 1 x SPST - NO |
空闲时间—最大值 | 60 ns |
系列 | TS12A4514 |
运行时间—最大值 | 125 ns |
TS12A4514,, TS12A4515 www.ti.com................................................................................................................................................... SCDS193D–AUGUST2006–REVISEDMARCH2009 SPST CMOS ANALOG SWITCHES FEATURES 1 • 2-Vto12-VSingle-SupplyOperation • SpecifiedLowON-LeakageCurrents: • SpecifiedON-StateResistance: – 1nAat25°C – 15ΩMaxWith12-VSupply – 10nAat85°C – 20ΩMaxWith5-VSupply • LowChargeInjection:11.5pC(12-VSupply) – 50ΩMaxWith3.3-VSupply • FastSwitchingSpeed: • SpecifiedLowOFF-LeakageCurrents: tON=80ns,tOFF=50ns(12-VSupply) – 1nAat25°C • Break-Before-MakeOperation(tON>tOFF) – 10nAat85°C • TTL/CMOS-LogicCompatibleWith5-VSupply DESCRIPTION/ORDERING INFORMATION The TS12A4514/TS12A4515 are single pole/single throw (SPST), low-voltage, single-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A4514 is normally open (NO). The TS12A4515 is normallyclosed(NC). These CMOS switches can operate continuously with a single supply between 2 V and 12 V. Each switch can handlerail-to-railanalogsignals.TheOFF-leakagecurrentmaximumisonly1nAat25°Cor10nAat85°C. All digital inputs have 0.8-V to 2.4-V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a 5-V supply. Forpin-compatiblepartsforusewithdualsupplies,seetheTS12A4516/TS12A4517. ORDERINGINFORMATION T PACKAGE(1)(2) ORDERABLEPARTNUMBER TOP-SIDEMARKING(3) A PDIP–P Reelof1000 TS12A4514P TS12A4514P Reelof1500 TS12A4514D SOIC–D YD514 Reelof2500 TS12A4514DR SOP(SOT-23)–DBV Reelof3000 TS12A4514DBVR 9CJ_ –40°Cto85°C PDIP–P Reelof1000 TS12A4515P TS12A4515P Reelof1500 TS12A4515D SOIC–D YD515 Reelof2500 TS12A4515DR SOP(SOT-23)–DBV Reelof3000 TS12A4515DBVR 9CK_ (1) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (2) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (3) DBV:Thelastcharacterdesignatesassembly/testSite 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.
TS12A4514,, TS12A4515 SCDS193D–AUGUST2006–REVISEDMARCH2009................................................................................................................................................... www.ti.com PIN CONFIGURATIONS TS12A4514 TS12A4515 TS12A4514 TS12A4515 D OR P PACKAGE D OR P PACKAGE SOT-23 PACKAGE SOT-23 PACKAGE (TOPVIEW) (TOPVIEW) (TOPVIEW) (TOPVIEW) COM 1 8 NO COM 1 8 NC COM 1 5 V+ COM 1 5 V+ N.C. 2 7 GND N.C. 2 7 GND NO 2 NC 2 N.C. 3 6 IN N.C. 3 6 IN V+ 4 5 N.C. V+ 4 5 N.C. GND 3 4 IN GND 3 4 IN SWITCH STATE MARKNG INFORMATION (SOTs only) INPUT TS12A4514 TS12A4515 LOT SPECIFIC CODE LOW OFF ON XX XX AE =TS12A4514 HIGH ON OFF AF =TS12A4515 N.C.–Not internally connected NO – Normally open NC – Normally closed Absolute Minimum and Maximum Ratings(1)(2) voltagesreferencedtoGND MIN MAX UNIT V Supplyvoltagerange(3) –0.3 13 V + V VNC Analogvoltagerange(4) –0.3 V++0.3 V NO or±20mA V COM Continuouscurrentintoanyterminal ±20 mA Peakcurrent,NOorCOM(pulsedat1ms,10%dutycycle) ±30 mA ESDpermethod3015.7 >2000 V 8-pinplasticDIP(derate9.09mW/°Cabove70°C) 727 Continuouspowerdissipation(T =70°C) 8-pinSOIC(derate5.88mW/°Cabove70°C) 471 mW A 5-pinSOT-23(derate7.1mW/°Cabove70°C) 571 T Operatingtemperaturerange –40 85 °C A T Storagetemperaturerange –65 150 °C stg Leadtemperature(soldering,10s) 300 °C (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum (3) Allvoltagesarewithrespecttoground,unlessotherwisespecified. (4) VoltagesexceedingV orGNDonanysignalterminalareclampedbyinternaldiodes.Limitforward-diodecurrenttomaximumcurrent + rating. 2 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4514TS12A4515
TS12A4514,, TS12A4515 www.ti.com................................................................................................................................................... SCDS193D–AUGUST2006–REVISEDMARCH2009 Electrical Characteristics for 5-V Supply(1) V =4.5Vto5.5V,V =2.4V,V =0.8V,T =–40°Cto85°C(unlessotherwisenoted) + INH INL A PARAMETER SYMBOL TESTCONDITIONS T MIN TYP(2) MAX UNIT A AnalogSwitch Analogsignalrange V ,V ,V 0 V V COM NO NC + V =4.5V,V =3.5V, 25°C 9.5 15 ON-stateresistance r + COM Ω on ICOM=1mA Full 20 ON-stateresistance V =1V,2V,3V, 25°C 1 3 r COM Ω flatness on(flat) ICOM=1mA Full 4 NO,NC I , V =5.5V,V =1V, 25°C 1 OFFleakagecurrent(3) INNOC((OOFFFF)) V+NOorVNC=C4O.M5V Full 10 nA COM V =5.5V,V =1V, 25°C 1 OFFleakagecurrent(3) ICOM(OFF) V+NOorVNC=C4O.M5V Full 10 nA COM V =5.5V,V =4.5V, 25°C 1 ONleakagecurrent(3) ICOM(ON) V+NOorVNC=C4O.M5V Full 10 nA DigitalControlInput(IN) Inputlogichigh V Full 2.4 V V IH + Inputlogiclow V Full 0 0.8 V IL Inputleakagecurrent I ,I V =V ,0V Full 0.01 m A IH IL IN + Dynamic 25°C 32 100 Turn-ontime t seeFigure2 ns ON Full 125 25°C 25 50 Turn-offtime t seeFigure2 ns OFF Full 60 Chargeinjection(4) Q CL=1nF,VNO=0V, 25°C –3 pC C R =0Ω,SeeFigure1 S NO,NC C , NO(OFF) f=1MHz,SeeFigure4 25°C 7.5 pF OFFcapacitance C NC(OFF) COM C f=1MHz,SeeFigure4 25°C 7.5 pF OFFcapacitance COM(OFF) COM C f=1MHz,SeeFigure4 25°C 19 pF ONcapacitance COM(ON) Digitalinputcapacitance C V =V ,0V 25°C 1.5 pF I IN + R =50Ω,C =15pF, Bandwidth BW L L 25°C 475 MHz V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, OFFisolation O L L 25°C –94 dB ISO V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, Totalharmonicdistortion THD L L 25°C 0.08 % V =1V ,f=100kHz NO RMS Supply 25°C 0.05 V supplycurrent I V =0VorV m A + + IN + Full 0.1 (1) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum. (2) TypicalvaluesareatT =25°C. A (3) Leakageparametersare100%testedatmaximum-ratedhotoperatingtemperature,andareensuredbycorrelationat25°C. (4) Specifiedbydesign,notproductiontested Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TS12A4514TS12A4515
TS12A4514,, TS12A4515 SCDS193D–AUGUST2006–REVISEDMARCH2009................................................................................................................................................... www.ti.com Electrical Characteristics for 12-V Supply(1) V =11.4Vto12.6V,V =5V,V =0.8V,T =–40°Cto85°C(unlessotherwisenoted) + INH INL A PARAMETER SYMBOL TESTCONDITIONS T MIN TYP(2) MAX UNIT A AnalogSwitch Analogsignalrange V ,V ,V 0 V V COM NO NC + V =11.4V,V =10V, 25°C 6.5 10 ON-stateresistance r + COM Ω on ICOM=1mA Full 15 V =11.4V, 25°C 1.5 3 ON-stateresistance + r V =2V,5V,10V, Ω flatness on(flat) I COM=1mA Full 4 COM NO,NC I , V =12.6V,V =1V, 25°C 1 OFFleakagecurrent(3) INNOC((OOFFFF)) V+NOorVNC=1C0OMV Full 10 nA COM V =12.6V,V =1V, 25°C 1 OFFleakagecurrent(3) ICOM(OFF) V+NOorVNC=1C0OMV Full 10 nA COM V =12.6V,V =10V, 25°C 1 ONleakagecurrent(3) ICOM(ON) V+NOorVNC=1C0OMV Full 10 nA DigitalControlInput(IN) Inputlogichigh V Full 5 V V IH + Inputlogiclow V Full 0 0.8 V IL Inputleakagecurrent I ,I V =V ,0V Full 0.01 m A IH IL IN + Dynamic 25°C 22 75 Turn-ontime t SeeFigure2 ns ON Full 80 25°C 20 45 Turn-offtime t SeeFigure2 ns OFF Full 50 Chargeinjection(4) Q CL=1nF,VNO=0V, 25°C –11.5 pC C R =0Ω,SeeFigure1 S NO,NC C NO(OFF) f=1MHz,SeeFigure4 25°C 7.5 pF OFFcapacitance C NC(OFF) COM C f=1MHz,SeeFigure4 25°C 7.5 pF OFFcapacitance COM(OFF) COM C f=1MHz,SeeFigure4 25°C 21.5 pF ONcapacitance COM(ON) Digitalinputcapacitance C V =V ,0V 25°C 1.5 pF I IN + R =50Ω,C =15pF, Bandwidth BW L L 25°C 520 MHz V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, OFFisolation O L L 25°C –95 dB ISO V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, Totalharmonicdistortion THD L L 25°C 0.07 % V =1V ,f=100kHz NO RMS Supply 25°C 0.05 V supplycurrent I V =0VorV m A + + IN + Full 0.2 (1) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum. (2) TypicalvaluesareatT =25°C. A (3) Leakageparametersare100%testedatmaximum-ratedhotoperatingtemperature,andareensuredbycorrelationat25°C. (4) Specifiedbydesign,notproductiontested 4 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4514TS12A4515
TS12A4514,, TS12A4515 www.ti.com................................................................................................................................................... SCDS193D–AUGUST2006–REVISEDMARCH2009 Electrical Characteristics for 3-V Supply(1) V =3Vto3.6V,T =–40°Cto85°C(unlessotherwisenoted) + A PARAMETER SYMBOL TESTCONDITIONS T MIN TYP(2) MAX UNIT A AnalogSwitch Analogsignalrange V ,V ,V 0 V V COM NO NC + V =3V,V =1.5V, 25°C 18.5 40 ON-stateresistance r + COM Ω on INO=1mA, Full 50 V =3V, 25°C 1 3 ON-stateresistance + r V =1V,1.5V,2V, Ω flatness on(flat) I COM=1mA Full 4 COM NO,NC I , V =3.6V,V =1V, 25°C 1 OFFleakagecurrent(3) INNOC((OOFFFF)) V+NOorVNC=C3OMV Full 10 nA COM V =3.6V,V =1V, 25°C 1 OFFleakagecurrent(3) ICOM(OFF) V+NOorVNC=C3OMV Full 10 nA COM V =3.6V,V =3V, 25°C 1 ONleakagecurrent(3) ICOM(ON) V+NOorVNC=C3OMV Full 10 nA DigitalControlInput(IN) Inputlogichigh V Full 2.4 V V IH + Inputlogiclow V Full 0 0.8 V IL Inputleakagecurrent I ,I V =V ,0V Full 0.01 m A IH IL IN + Dynamic 25°C 63 120 Turn-ontime(4) t SeeFigure2 ns ON Full 175 25°C 33 80 Turn-offtime(4) t SeeFigure2 ns OFF Full 120 Chargeinjection(4) Q C =1nF,SeeFigure1 25°C –1.5 pC C L NO,NC C , NO(OFF) f=1MHz,SeeFigure4 25°C 7.5 pF OFFcapacitance C NC(OFF) COM C f=1MHz,SeeFigure4 25°C 7.5 pF OFFcapacitance COM(OFF) COM C f=1MHz,SeeFigure4 25°C 17 pF ONcapacitance COM(ON) Digitalinputcapacitance C V =V ,0V 25°C 1.5 pF I IN + R =50Ω,C =15pF, Bandwidth BW L L 25°C 460 MHz V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, OFFisolation O L L 25°C –94 dB ISO V =1V ,f=100kHz NO RMS R =50Ω,C =15pF, Totalharmonicdistortion THD L L 25°C 0.15 % V =1V ,f=100kHz NO RMS Supply 25°C 0.03 V supplycurrent I V =0VorV m A + + IN + Full 0.05 (1) Thealgebraicconvention,wherebythemostnegativevalueisaminimumandthemostpositivevalueisamaximum. (2) TypicalvaluesareatT =25°C. A (3) Leakageparametersare100%testedatmaximum-ratedhotoperatingtemperature,andareensuredbycorrelationat25°C. (4) Specifiedbydesign,notproductiontested Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TS12A4514TS12A4515
TS12A4514,, TS12A4515 SCDS193D–AUGUST2006–REVISEDMARCH2009................................................................................................................................................... www.ti.com PINDESCRIPTION(1) PINNO. TS12A4514 TS12A4515 NAME DESCRIPTION D,P SOT-23 D,P SOT-23 1 1 1 1 COM Common 2,3,5 – 2,3,5 – N.C. Noconnect(notinternallyconnected) 4 5 4 5 V Powersupply + 6 4 6 4 IN DigitalcontroltoconnectCOMtoNOorNC 7 3 7 3 GND Digitalground 8 2 – – NO Normallyopen – – 8 2 NC Normallyclosed (1) NO,NC,andCOMpinsareidenticalandinterchangeable.Anymaybeconsideredasaninputoranoutput;signalspassinboth directions. 6 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4514TS12A4515
TS12A4514,, TS12A4515 www.ti.com................................................................................................................................................... SCDS193D–AUGUST2006–REVISEDMARCH2009 APPLICATION INFORMATION Power-Supply Considerations The TS12A4514/TS12A4515 construction is typical of most CMOS analog switches, except that they have only two supply pins: V and GND. V and GND drive the internal CMOS switches and set their analog voltage limits. + + Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V and GND. + OneofthesediodesconductsifanyanalogsignalexceedsV orGND. + Virtuallyall the analog leakage current comes from the ESD diodes to V or GND. Although the ESD diodes on a + given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is biased by either V or GND and the analog signal. This means their leakages will vary as the signal varies. The + difference in the two diode leakages to the V and GND pins constitutes the analog-signal-path leakage current. + All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal.Thisiswhybothsidesofagivenswitchcanshowleakagecurrentsofthesameoroppositepolarity. Thereisnoconnectionbetweentheanalog-signalpathsandV orGND. + V and GND also power the internal logic and logic-level translators. The logic-level translators convert the logic + levelstoswitchedV andGNDsignalstodrivetheanalogsignalgates. + Logic-Level Thresholds The logic-level thresholds are CMOS/TTL compatible when V is 5 V. As V is raised, the level threshold + + increases slightly. When V reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-level + minimumof2.8V,butstillcompatiblewithCMOSoutputs. CAUTION: If the user is using the TS12A4514 or TS12A4515 with a V+ supply of 3 V, then the control input (IN) voltage should not exceed V+, otherwise the output levels can exceed 3 V and violate the absolute maximum rating, potentially damaging thedevice. High-Frequency Performance In 50-Ω systems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics). Above20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not in turningthe switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencies with less attenuation. At 10 MHz, OFF isolation is about –45 dB in 50-Ω systems, decreasing (approximately 20 dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFF isolationisabout3dBabovethatofabareICsocket,andisdueentirelytocapacitivecoupling. Test Circuits/Timing Diagrams V+ V+ NO VNO or VNC = 0 V VINV+ TS12A4514 0 V TS12A4515 TS12A4514 TS12A4515 VIN IN COM VOUT 50 W GND C10L00 pF VOUT D VOUT D VOUT is the measured voltage due to charge transfer error Q when the channel turns off. Q = (cid:1)VOUT x CL Figure1.ChargeInjection Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TS12A4514TS12A4515
TS12A4514,, TS12A4515 SCDS193D–AUGUST2006–REVISEDMARCH2009................................................................................................................................................... www.ti.com V+ V+ V+ VIN 50% NO VNO 0 V TS12A4514 VIN VNOPEAK 90% 90% IN COM VOUT GND VOUT 50 W 300 W 35 pF 0 V tON tOFF V+ V+ V+ VIN 50% NC VNO 0 V VIN TS12A4515 VNOPEAK 90% 90% IN COM VOUT GND VOUT 35 pF 50 W 300 W 0 V tOFF tON Figure2.SwitchingTimes V+ 10 nF V+ NO VIN 50 W 50 W TS12A4514 V+ TS12A4515 VOUT MEAS REF IN COM GND 50 W 50 W Measurements are standardized against short at socket terminals. OFF isolation is measured between COM and OFF OFF Isolation = 20logVOUT terminals on each switch. ON loss is measured between COM VIN and ON terminals on each switch. Signal direction through switch is reversed; worst values are recorded. ON Loss = 20logVOUT VIN Figure3.OFFIsolationandONLoss V+ V+ NO or NC TS12A4514 TS12A4515 As 1-MHz IN COM Capacitance Required Analyzer GND Figure4.NO,NC,andCOMCapacitance 8 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):TS12A4514TS12A4515
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TS12A4514D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD514 & no Sb/Br) TS12A4514DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 9CJE & no Sb/Br) TS12A4514DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD514 & no Sb/Br) TS12A4514P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TS12A4514P & no Sb/Br) TS12A4515D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD515 & no Sb/Br) TS12A4515DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 9CKE & no Sb/Br) TS12A4515DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD515 & no Sb/Br) TS12A4515DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 YD515 & no Sb/Br) TS12A4515P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TS12A4515P & no Sb/Br) TS12A4515PE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TS12A4515P & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TS12A4514DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TS12A4514DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TS12A4515DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TS12A4515DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TS12A4514DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 TS12A4514DR SOIC D 8 2500 367.0 367.0 35.0 TS12A4515DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 TS12A4515DR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2
PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com
EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com
PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com
EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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