TRS232E www.ti.com................................................................................................................................................. SLLS791C–JUNE2007–REVISEDSEPTEMBER2008 DUAL RS-232 DRIVER/RECEIVER WITH IEC61000-4-2 PROTECTION FEATURES 1 • MeetsorExceedsTIA/RS-232-FandITU 2 D, DW, N, NS, OR PW PACKAGE RecommendationV.28 (TOP VIEW) • OperatesFromaSingle5-VPowerSupply With1.0-m FCharge-PumpCapacitors C1+ 1 16 VCC • Operatesupto250kbit/s VS+ 2 15 GND • TwoDriversandTwoReceivers C1− 3 14 DOUT1 • ±30-VInputLevels C2+ 4 13 RIN1 C2− 5 12 ROUT1 • LowSupplyCurrent...8mATypical V 6 11 DIN1 S− • ESDProtectionforRS-232BusPins DOUT2 7 10 DIN2 – ±15-kVHuman-BodyModel(HBM) RIN2 8 9 ROUT2 – ±8-kVIEC61000-4-2,ContactDischarge – ±15-kVIEC61000-4-2,Air-GapDischarge APPLICATIONS • TIA/RS-232-F • Battery-PoweredSystems • Terminals • Modems • Computers DESCRIPTION/ORDERING INFORMATION The TRS232E is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/RS-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/RS-232-F inputs to 5-V TTL/CMOS levels. This receiver has a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each driver converts TTL/CMOS input levels into TIA/RS-232-F levels. The driver, receiver, and voltage-generator functionsareavailableascellsintheTexasInstrumentsLinASIC™library. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. LinASICisatrademarkofTexasInstruments. 2 UNLESS OTHERWISE NOTED this document contains Copyright©2007–2008,TexasInstrumentsIncorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TRS232E SLLS791C–JUNE2007–REVISEDSEPTEMBER2008................................................................................................................................................. www.ti.com ORDERINGINFORMATION T PACKAGE(1)(2) ORDERABLEPARTNUMBER TOP-SIDEMARKING A PDIP–N Tubeof25 TRS232ECN TRS232ECN Tubeof40 TRS232ECD SOIC–D TRS232EC Reelof2500 TRS232ECDR Tubeof40 TRS232ECDW 0°Cto70°C SOIC–DW TRS232EC Reelof2000 TRS232ECDWR SOP–NS Reelof2000 TRS232ECNSR PREVIEW Tubeof25 TRS232ECPW TSSOP–PW RU32EC Reelof2000 TRS232ECPWR PDIP–N Tubeof25 TRS232EIN TRS232EIN Tubeof40 TRS232EID SOIC–D TRS232EI Reelof2500 TRS232EIDR Tubeof40 TRS232EIDW –40°Cto85°C SOIC–DW TRS232EI Reelof2000 TRS232EIDWR SOP–NS Reelof2000 TRS232EINSR PREVIEW Tubeof25 TRS232EIPW TSSOP–PW RU32EI Reelof2000 TRS232EIPWR (1) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (2) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseethe TIwebsiteatwww.ti.com. FUNCTIONTABLES ABC EachDriver(1) INPUT OUTPUT DIN DOUT L H H L (1) H=highlevel,L=lowlevel EachReceiver(1) INPUT OUTPUT RIN ROUT L H H L (1) H=highlevel,L=lowlevel LOGICDIAGRAM(POSITIVELOGIC) 11 14 DIN1 DOUT1 10 7 DIN2 DOUT2 12 13 ROUT1 RIN1 9 8 ROUT2 RIN2 2 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TRS232E

TRS232E www.ti.com................................................................................................................................................. SLLS791C–JUNE2007–REVISEDSEPTEMBER2008 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Inputsupplyvoltagerange(2) –0.3 6 V CC V Positiveoutputsupplyvoltagerange V –0.3 15 V S+ CC V Negativeoutputsupplyvoltagerange –0.3 –15 V S– Driver –0.3 V +0.3 CC V Inputvoltagerange V I Receiver ±30 DOUT V –0.3 V +0.3 S– S+ V Outputvoltagerange V O ROUT –0.3 V +0.3 CC Short-circuitduration DOUT Unlimited Dpackage 73 DWpackage 57 q Packagethermalimpedance(3)(4) Npackage 67 °C/W JA NSpackage 64 PWpackage 108 T Operatingvirtualjunctiontemperature 150 °C J T Storagetemperaturerange –65 150 °C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttonetworkGND. (3) MaximumpowerdissipationisafunctionofT(max),q ,andT .Themaximumallowablepowerdissipationatanyallowableambient J JA A temperatureisP =(T(max)–T )/q .OperatingattheabsolutemaximumT of150°Ccanaffectreliability. D J A JA J (4) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. Recommended Operating Conditions MIN NOM MAX UNIT V Supplyvoltage 4.5 5 5.5 V CC V High-levelinputvoltage(DIN1,DIN2) 2 V IH V Low-levelinputvoltage(DIN1,DIN2) 0.8 V IL Receiverinputvoltage(RIN1,RIN2) ±30 V TRS232EC 0 70 T Operatingfree-airtemperature °C A TRS232EI –40 85 Electrical Characteristics(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure4) PARAMETER TESTCONDITIONS MIN TYP(2) MAX UNIT I Supplycurrent V =5.5V, Alloutputsopen,T =25°C 8 10 mA CC CC A (1) TestconditionsareC1–C4=1m FatV =5V±0.5V. CC (2) AlltypicalvaluesareatV =5VandT =25°C. CC A Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TRS232E

TRS232E SLLS791C–JUNE2007–REVISEDSEPTEMBER2008................................................................................................................................................. www.ti.com DRIVER SECTION abc Electrical Characteristics(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperaturerange PARAMETER TESTCONDITIONS MIN TYP(2) MAX UNIT V High-leveloutputvoltage DOUT R =3kΩtoGND 5 7 V OH L V Low-leveloutputvoltage(3) DOUT R =3kΩtoGND –7 –5 V OL L r Outputresistance DOUT V =V =0, V =±2V 300 Ω o S+ S– O I (4) Short-circuitoutputcurrent DOUT V =5.5V, V =0 ±10 mA OS CC O I Short-circuitinputcurrent DIN V =0 200 m A IS I (1) TestconditionsareC1–C4=1m FatV =5V±0.5V. CC (2) AlltypicalvaluesareatV =5VandT =25°C. CC A (3) Thealgebraicconvention,inwhichtheleast-positive(mostnegative)valueisdesignatedminimum,isusedinthisdatasheetforlogic voltagelevelsonly. (4) Notmorethanoneoutputshouldbeshortedatatime. Switching Characteristics(1) V =5V,T =25°C(seeNote4) CC A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SR Driverslewrate R =3kΩto7kΩ,SeeFigure2 30 V/m s L SR(t) Drivertransitionregionslewrate SeeFigure3 3 V/m s Datarate OneDOUTswitching 250 kbit/s (1) TestconditionsareC1–C4=1m FatV =5V±0.5V. CC ESD protection PARAMETER TESTCONDITIONS TYP UNIT HBM ±15 kV DOUT,RIN IEC61000-4-2,Air-GapDischarge ±15 kV IEC61000-4-2,ContactDischarge ±8 kV 4 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TRS232E

TRS232E www.ti.com................................................................................................................................................. SLLS791C–JUNE2007–REVISEDSEPTEMBER2008 RECEIVER SECTION abc Electrical Characteristics(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperaturerange PARAMETER TESTCONDITIONS MIN TYP(2) MAX UNIT V High-leveloutputvoltage ROUT I =–1mA 3.5 V OH OH V Low-leveloutputvoltage(3) ROUT I =3.2mA 0.4 V OL OL V Receiverpositive-goinginputthresholdvoltage RIN V =5V, T =25°C 1.7 2.4 V IT+ CC A V Receivernegative-goinginputthresholdvoltage RIN V =5V, T =25°C 0.8 1.2 V IT– CC A V Inputhysteresisvoltage RIN V =5V 0.2 0.5 1 V hys CC r Receiverinputresistance RIN V =5V, T =25°C 3 5 7 kΩ i CC A (1) TestconditionsareC1–C4=1m FatV =5V±0.5V. CC (2) AlltypicalvaluesareatV =5VandT =25°C. CC A (3) Thealgebraicconvention,inwhichtheleast-positive(mostnegative)valueisdesignatedminimum,isusedinthisdatasheetforlogic voltagelevelsonly. Switching Characteristics(1) V =5V,T =25°C(seeFigure1) CC A PARAMETER TYP UNIT t Receiverpropagationdelaytime,low-tohigh-leveloutput 500 ns PLH(R) t Receiverpropagationdelaytime,high-tolow-leveloutput 500 ns PHL(R) (1) TestconditionsareC1–C4=1m FatV =5V±0.5V. CC Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TRS232E

TRS232E SLLS791C–JUNE2007–REVISEDSEPTEMBER2008................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION VCC RL = 1.3 kW Pulse RIN ROUT See Note C Generator (see Note A) CL = 50 pF (see Note B) TEST CIRCUIT ≤10 ns ≤10 ns 3 V 90% 90% Input 10% 50% 50% 10% 0 V 500 ns tPHL tPLH VOH Output 1.5 V 1.5 V VOL WAVEFORMS A. Thepulsegeneratorhasthefollowingcharacteristics:Z =50Ω,dutycycle≤50%. O B. C includesprobeandjigcapacitance. L C. Alldiodesare1N3064orequivalent. Figure1.ReceiverTestCircuitandWaveformsfort andt Measurements PHL PLH 6 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TRS232E

TRS232E www.ti.com................................................................................................................................................. SLLS791C–JUNE2007–REVISEDSEPTEMBER2008 PARAMETER MEASUREMENT INFORMATION (continued) Pulse DIN DOUT Generator RS-232 Output (see Note A) RL CL = 10 pF (see Note B) TEST CIRCUIT ≤10 ns ≤10 ns 3 V 90% 90% Input 50% 50% 10% 10% 0 V 5 m s tPLH tPHL 90% 90% VOH Output 10% 10% VOL tTHL tTLH 0.8(V –V ) 0.8(V –V ) SR(cid:1) OH OL or OL OH t t TLH THL WAVEFORMS A. Thepulsegeneratorhasthefollowingcharacteristics:Z =50Ω,dutycycle≤50%. O B. C includesprobeandjigcapacitance. L Figure2.DriverTestCircuitandWaveformsfort andt Measurements(5-m sInput) PHL PLH Pulse DIN DOUT Generator RS-232 Output (see Note A) 3 kW CL = 2.5 nF TEST CIRCUIT ≤10 ns ≤10 ns Input 90% 90% 10% 1.5 V 1.5 V 10% 20 m s tTHL tTLH 3 V 3 V VOH Output −3 V −3 V VOL 6V SR(cid:1) t ort THL TLH WAVEFORMS A. Thepulsegeneratorhasthefollowingcharacteristics:Z =50Ω,dutycycle≤50%. O Figure3.TestCircuitandWaveformsfort andt Measurements(20-m sInput) THL TLH Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TRS232E

TRS232E SLLS791C–JUNE2007–REVISEDSEPTEMBER2008................................................................................................................................................. www.ti.com APPLICATION INFORMATION 5 V + CBYPASS = 1 m F − 16 C3† 1 m F VCC 1 2 C1 1 m F 3 C1+ VS+ 8.5 V C1− 6 4 C2+ VS− −8.5 V C2 1 m F 5 C4 1 m F C2− + 11 14 RS-232 Output From CMOS or TTL 10 7 RS-232 Output 12 13 RS-232 Input To CMOS or TTL 9 8 RS-232 Input 0 V 15 GND †C3 can be connected to VCC or GND. A. Resistorvaluesshownarenominal. B. Nonpolarizedceramiccapacitorsareacceptable.Ifpolarizedtantalumorelectrolyticcapacitorsareused,theyshould beconnectedasshown.Inadditiontothe1-m Fcapacitorsshown,theTRS202Ecanoperatewith0.1-m Fcapacitors. Figure4.TypicalOperatingCircuit 8 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):TRS232E

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TRS232ECD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TRS232EC & no Sb/Br) TRS232ECDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TRS232EC & no Sb/Br) TRS232ECDWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 TRS232EC & no Sb/Br) TRS232ECN ACTIVE PDIP N 16 25 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 TRS232ECN (RoHS) TRS232ECPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 RU32EC & no Sb/Br) TRS232ECPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 RU32EC & no Sb/Br) TRS232EID ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TRS232EI & no Sb/Br) TRS232EIDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TRS232EI & no Sb/Br) TRS232EIDWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 TRS232EI & no Sb/Br) TRS232EIN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 TRS232EIN & no Sb/Br) TRS232EIPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RU32EI & no Sb/Br) TRS232EIPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RU32EI & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TRS232ECDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TRS232ECDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TRS232ECDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 TRS232ECPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TRS232EIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TRS232EIDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 TRS232EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TRS232ECDR SOIC D 16 2500 333.2 345.9 28.6 TRS232ECDR SOIC D 16 2500 367.0 367.0 38.0 TRS232ECDWR SOIC DW 16 2000 350.0 350.0 43.0 TRS232ECPWR TSSOP PW 16 2000 367.0 367.0 35.0 TRS232EIDR SOIC D 16 2500 367.0 367.0 38.0 TRS232EIDWR SOIC DW 16 2000 350.0 350.0 43.0 TRS232EIPWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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