Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 TRF7963A Fully Integrated 13.56-MHz RFID Reader/Writer IC For ISO/IEC 14443A, ISO/IEC 14443B, and NFC Standards 1 Device Overview 1.1 Features 1 • CompletelyIntegratedProtocolHandlingfor • DualReceiverArchitectureWithRSSIfor ISO/IEC14443AandB,NFCForumDevice Eliminationof"ReadHoles"andAdjacentReader Types1to4,andFeliCa™ SystemorAmbientIn-BandNoiseDetection • InputVoltageRange:2.7VDCto5.5VDC • ProgrammablePowerModesforUltra-Low-Power • ProgrammableOutputPower: SystemDesign(PowerDown<0.5 µA) +20dBm(100mW)or+23dBm(200mW) • ParallelorSPIInterface • ProgrammableI/OVoltageLevels: • IntegratedVoltageRegulatorforMicrocontroller 1.8VDCto5.5VDC Supply • ProgrammableSystemClockFrequencyOutput • TemperatureRange:–25°Cto85°C (RF,RF/2,RF/4) • 32-PinQFNPackage(5mm× 5mm)(RHB) • ProgrammableModulationDepth 1.2 Applications • SecureAccessControl • TransportTicketing • DigitalDoorLocks • EventTicketing • MedicalSystems 1.3 Description The TRF7963A device is an integrated analog front-end (AFE) and data-framing device for a 13.56-MHz RFID reader/writer system that supports ISO/IEC 14443 A and B and Sony FeliCa. Built-in programming optionsmakeitsuitableforawiderangeofapplicationsfor proximity identificationsystems. The reader is configured by selecting the desired protocol in the control registers. Direct access to all controlregistersallowsfinetuningofvariousreaderparametersasneeded. The TRF7963A device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO protocols onboard. The device also supports reader/writer mode for NFC Forum tag types 1, 2, 3, and 4. NFC Forum tag types 2, 3, and 4 are supported with the built-in protocol decoders used in Direct Mode 2. NFC Forum tag type 1 requires the use of Direct Mode 0. Other standards and custom protocols can also be implemented by using Direct Mode 0. Direct Mode 0 lets the user fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated(extracted)clocksignal. The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength fromtransponders,ambientsources,orinternallevelsisavailableintheRSSIregister. A SPI or parallel interface can be used for the communication between the MCU and the TRF7963A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 12-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed sotheMCUcanprocessthedatainrealtime. The TRF7963A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication levelsfrom1.8Vto5.5VfortheMCUI/Ointerface. The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectablemodulationdepth. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additionalexternalcircuitswithinthereadersystem. ToevaluatethelatestproductsintheTRF79xxproductfamily –TRF7970A and TRF7964A – see the NFC TransceiverBoosterPack. Documentation, Tools,ReferenceDesigns,andSoftware, Samples DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE TRF7963ARHB VQFN(32) 5mm×5mm (1) Formoreinformation,seeSection9,MechanicalPackagingandOrderableInformation. 1.4 Application Block Diagram Figure1-1showsatypicalapplicationblockdiagram. V DD VDD_X VDD_I/O VDD TX_OUT Matching TRF796xA Parallel MCU RX_IN 1 or SPI (MSP430 orARM) RX_IN 2 VSS VIN XIN Crystal Supply 13.56 MHz 2.7 V to 5.5 V Copyright © 2017,Texas Instruments Incorporated Figure1-1.ApplicationBlockDiagram 2 DeviceOverview Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Table of Contents 1 DeviceOverview......................................... 1 6.7 Receiver–DigitalSection........................... 18 .............................................. ................................... 1.1 Features 1 6.8 OscillatorSection 21 ........................................... ........................ 1.2 Applications 1 6.9 Transmitter-AnalogSection 22 ............................................ ........................ 1.3 Description 1 6.10 Transmitter-DigitalSection 22 1.4 ApplicationBlockDiagram........................... 2 6.11 Transmitter–ExternalPowerAmplifieror ................................. 2 Revision History......................................... 4 Subcarrier Detector 23 ............................ 3 DeviceCharacteristics.................................. 5 6.12 CommunicationInterface 23 ............ ..................................... 6.13 DirectCommandsfromMCUtoReader 39 3.1 RelatedProducts 5 ................................. 4 TerminalConfigurationandFunctions.............. 6 6.14 RegisterDescription 42 ......................................... 7 Applications,Implementation,andLayout........ 58 4.1 PinDiagrams 6 ................................... 7.1 TRF7963AReaderSystemUsingSPIWithSS 4.2 SignalDescriptions 6 ................................................ Mode 58 5 Specifications ............................................ 8 ...................................... 7.2 SystemDesign 59 .......................... 5.1 AbsoluteMaximumRatings 8 8 DeviceandDocumentationSupport............... 61 .......................................... 5.2 ESDRatings 8 ..................... 8.1 GettingStartedandNextSteps 61 ................ 5.3 RecommendedOperatingConditions 8 ............................... 8.2 Device Nomenclature 61 ............................. 5.4 ElectricalCharacteristics 9 ................................. 8.3 ToolsandSoftware 62 ................ 5.5 ThermalResistanceCharacteristics 10 ............................. 8.4 DocumentationSupport 62 ........................... 5.6 Switching Characteristics 10 .................................. 8.5 SupportResources 62 6 DetailedDescription................................... 11 .......................................... 8.6 Trademarks 62 ........................... 6.1 FunctionalBlockDiagram 11 ..................... 8.7 ElectrostaticDischargeCaution 63 ..................................... 6.2 PowerSupplies 11 ............................... 8.8 ExportControlNotice 63 ............................... 6.3 Supply Arrangements 12 ............................................. 8.9 Glossary 63 .......................... 6.4 SupplyRegulatorSettings 13 9 Mechanical,Packaging,andOrderable ....................................... 6.5 PowerModes 14 Information.............................................. 64 .......................... 6.6 Receiver–AnalogSection 17 Copyright©2011–2020,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromMay18,2017toMarch11,2020 Page • RemovedreferencestoobsoleteEVMs .......................................................................................... 2 • Correctedtypo(changed"...and3.4VforVDD_AandVDD_A"to"...and3.4VforVDD_AandVDD_X")in Section6.3,SupplyArrangements................................................................................................ 13 4 RevisionHistory Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 3 Device Characteristics Table3-1liststhesupportedprotocols. Table3-1.SupportedProtocols ISO/IEC14443AANDB NFCForum DEVICE 106kbps 212kbps 424kbps 848kbps TYPES1TO4 TRF7963A ✓ ✓ ✓ ✓ ✓ 3.1 Related Products Forinformationaboutotherdevicesinthisfamilyofproductsorrelatedproducts,seethefollowinglinks. ProductsforTIWirelessConnectivity Connect more with the industry’s broadest wireless connectivity portfolio. ProductsforNFC/RFID TI provides one of the industry’s most differentiated NFC and RFID product portfolios and is your solution to meet a broad range of NFC connectivity and RFID identificationneeds. CompanionProductsforTRF7963A Review products that are frequently purchased or used with this product. ReferenceDesignsforTRF7963A The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designsat ti.com/tidesigns. Copyright©2011–2020,TexasInstrumentsIncorporated DeviceCharacteristics 5 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure4-1showsthepinoutforthe32-pinRHBpackage. D_X C_IN C_OUT S_D S_CLK TA_CLK 2 D S S S N Y A N V O O V E S D E 32 31302928272625 VDD_A 1 24 I/O_7 VIN 2 23 I/O_6 VDD_RF 3 22 I/O_5 VDD_PA 4 Thermal Pad 21 I/O_4 TX_OUT 5 (connect to ground) 20 I/O_3 VSS_PA 6 19 I/O_2 VSS_RX 7 18 I/O_1 RX_IN1 8 17 I/O_0 9 10 11 1213141516 2 S G K Q D A O RX_IN VS B SK/OO IR MO VSS_ VDD_I/ A Figure4-1.32-PinRHBPackage(TopView) 4.2 Signal Descriptions Table4-1describesthesignals. Table4-1.SignalDescriptions TERMINAL TYPE (1) DESCRIPTION NO. NAME 1 VDD_A OUT Internalregulatedsupply(2.7Vto3.4V)foranalogcircuitry 2 VIN SUP Externalsupplyinputtochip(2.7Vto5.5V) 3 VDD_RF OUT Internalregulatedsupply(2.7Vto5V);normallyconnectedtoVDD_PA(pin4) 4 VDD_PA INP SupplyforPA;normallyconnectedexternallytoVDD_RF(pin3) 5 TX_OUT OUT RFoutput(selectableoutputpower:100mWor200mW,withV =5V) DD 6 VSS_PA SUP NegativesupplyforPA;normallyconnectedtocircuitground 7 VSS_RX SUP Negativesupplyforreceiveinputs;normallyconnectedtocircuitground 8 RX_IN1 INP Mainreceiveinput 9 RX_IN2 INP Auxiliaryreceiveinput 10 VSS SUP Chipsubstrateground 11 BAND_GAP OUT Bandgapvoltage(V =1.6V);internalanalogvoltagereference BG SelectionbetweenASKandOOKmodulation(0=ASK,1=OOK)fordirectmode0and1. 12 ASK/OOK BID Itcanbeconfiguredasanoutputtoprovidethereceivedanalogsignaloutput. 13 IRQ OUT Interruptrequest INP Externaldatamodulationinputfordirectmode0or1 14 MOD OUT Subcarrierdigitaldataoutput(seeregister0x1Aand0x1Bdefinitions) 15 VSS_A SUP Negativesupplyforinternalanalogcircuits.ConnectedtoGND. 16 VDD_I/O INP SupplyforI/Ocommunications(1.8VtoVIN)levelshifter.VINshouldbeneverexceeded. 17 I/O_0 BID I/Opinforparallelcommunication 18 I/O_1 BID I/Opinforparallelcommunication 19 I/O_2 BID I/Opinforparallelcommunication (1) SUP=Supply,INP=Input,BID=Bidirectional,OUT=Output 6 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Table4-1.SignalDescriptions(continued) TERMINAL TYPE (1) DESCRIPTION NO. NAME 20 I/O_3 BID I/Opinforparallelcommunication I/Opinforparallelcommunication 21 I/O_4 BID SlaveselectsignalinSPImode I/Opinforparallelcommunication 22 I/O_5 BID Dataclockoutputindirectmode1 I/Opinforparallelcommunication 23 I/O_6 BID MISOforserialcommunication(SPI) Serialbitdataoutputindirectmode1orsubcarriersignalindirectmode0 I/Opinforparallelcommunication. 24 I/O_7 BID MOSIforserialcommunication(SPI) Selectionofpowerdownmode.IfEN2isconnectedtoVIN,thenVDD_Xisactiveduringpower 25 EN2 INP downmode2(forexample,tosupplytheMCU). 26 DATA_CLK INP DataclockinputforMCUcommunication(parallelandserial) IfEN=1(EN2=don'tcare)thesystemclockfortheMCUisconfiguredwithregister0x09(off, 27 SYS_CLK OUT 3.39MHz,6.78MHz,or13.56MHz). IfEN=0andEN2=1,thesystemclockissetto60kHz. 28 EN INP Chipenableinput(ifEN=0,thenthechipisinsleeporpower-downmode) 29 VSS_D SUP Negativesupplyforinternaldigitalcircuits 30 OSC_OUT OUT Crystaloroscillatoroutput 31 OSC_IN INP Crystaloroscillatorinput Internallyregulatedsupply(2.7Vto3.4V)fordigitalcircuitandexternaldevices(forexample,an 32 VDD_X OUT MCU) PAD PAD SUP Chipsubstrateground Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 7 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) (2) MIN MAX UNIT Inputvoltagerange,V –0.3 6 V IN Maximumcurrent,I 150 mA IN Anycondition 140 Maximumoperatingvirtualjunctiontemperature,T (3) °C J Continuousoperation,long-termreliability 125 Storagetemperature,T –55 150 °C STG (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsarenotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttosubstrategroundterminalVSS. (3) Themaximumjunctiontemperatureforcontinuousoperationislimitedbypackageconstraints.Operationabovethistemperaturemay resultinreducedreliabilityorlifetimeofthedevice. 5.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22‑C101(2) ±500 V (ESD) Machinemodel(MM) ±200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 5.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Operatinginputvoltage 2.7 5 5.5 V IN T Operatingambienttemperature –25 25 85 °C A T Operatingvirtualjunctiontemperature –25 25 125 °C J 8 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 5.4 Electrical Characteristics TYPoperatingconditionsareT =25°C,V =5V,full-powermode(unlessotherwisenoted) A IN MINandMAXoperatingconditionsareoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature (unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Allbuildingblocksdisabled,includingsupply- I Supplycurrentinpowerdownmode1 voltageregulators;measuredafter500-ms <0.5 5 µA PD1 settlingtime(EN=0,EN2=0) TheSYS_CLKgeneratorandVDD_Xremain Supplycurrentinpowerdownmode2 I activetosupportexternalcircuitry,measured 120 200 µA PD2 (sleepmode) after100-mssettlingtime(EN=0,EN2=1) Oscillatorrunning,supply-voltageregulatorsin I Supplycurrentinstandbymode 1.9 3.5 mA STBY low-consumptionmode(EN=1,EN2=x) Supplycurrentwithoutantennadriver Oscillator,regulators,RX,andAGCareactive, I 10.5 14 mA ON1 current TXisoff Oscillator,regulators,RX,AGC,andTX I SupplycurrentinTX(halfpower) 70 78 mA ON2 active,P =100mW OUT Oscillator,regulators,RX,AGC,andTX I SupplycurrentinTX(fullpower) 130 170 mA ON3 active,P =200mW OUT V Power-onresetvoltage InputvoltageatVIN 1.4 2 2.6 V POR V Bandgapvoltage(pin11) Internalanalogreferencevoltage 1.5 1.6 1.7 V BG Regulatedoutputvoltageforanalog V V =5V 3.1 3.5 3.8 V DD_A circuitry(pin1) IN V Regulatedsupplyforexternalcircuitry Outputvoltagepin32,V =5V 3.1 3.4 3.8 V DD_X IN I MaximumoutputcurrentofVDD_X Outputcurrentpin32,V =5V 20 mA VDD_Xmax IN Half-powermode,V =2.7Vto5.5V 8 12 R Antennadriveroutputresistance(1) IN Ω RFOUT Full-powermode,V =2.7Vto5.5V 4 6 IN R RX_IN1andRX_IN2inputresistance 4 10 20 kΩ RFIN MaximumRFinputvoltageatRX_IN1 V V shouldnotexceedVIN 3.5 V RF_INmax orRX_IN2 RF_INmax pp MinimumRFinputvoltageatRX_IN1 fSUBCARRIER=424kHz 1.4 2.5 VRF_INmin orRX_IN2(inputsensitivity)(2) f =848kHz 2.1 3 mVpp SUBCARRIER f SYS_CLKfrequency Inpowermode2,EN=0,EN2=1 25 60 120 kHz SYS_CLK f Carrierfrequency Definedbyexternalcrystal 13.56 MHz C Timeuntiloscillatorstablebitisset(register tCRYSTAL Crystalrun-intime 0x0F) (3) 5 ms fD_CLKmax MaximumDATA_CLKfrequency(4) Dreecpoemnmdsenodnactiaopnaicsit2iveMHloza(d4)ontheI/Olines, 2 4 10 MHz I/Olines,IRQ,SYS_CLK,DATA_CLK,EN, 0.2× V Inputvoltage,logiclow V IL EN2 V DD_I/O I/Olines,IRQ,SYS_CLK,DATA_CLK,EN, 0.8× V Inputvoltagethreshold,logichigh V IH EN2 V DD_I/O R Outputresistance,I/O_0toI/O_7 500 800 Ω OUT R OutputresistanceR 200 400 Ω SYS_CLK SYS_CLK (1) Antennadriveroutputresistance (2) MeasuredwithsubcarriersignalatRX_IN1orRX_IN2andmeasuredthedigitaloutputatMODpinwithregister0x1Abit6=1 (3) Dependingonthecrystalparametersandcomponents (4) RecommendedDATA_CLKspeedis2MHz;higherdataclockdependsonthecapacitiveload.MaximumSPIclockspeedshouldnot exceed10MHz.Thisclockspeedisacceptableonlywhenexternalcapacitiveloadislessthan30pF.MISOdriverhasatypicaloutput resistanceof400Ω(12-nstimeconstantwhen30-pFloadisused). Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 9 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 5.5 Thermal Resistance Characteristics POWERRATING(2) PACKAGE Rθ Rθ (1) JC JA T ≤25°C T ≤85°C A A RHB(32) 31°C/W 36.4°C/W 2.7W 1.1W (1) ThisdatawastakenusingtheJEDECstandardhigh-KtestPCB. (2) Powerratingisdeterminedwithajunctiontemperatureof125°C.Thisisthepointwheredistortionstartstoincreasesubstantially. ThermalmanagementofthefinalPCBshouldstrivetokeepthejunctiontemperatureatorbelow125°Cforbestperformanceandlong- termreliability. 5.6 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t DATA_CLKtime,highorlow(onehalf DependsoncapacitiveloadontheI/Olines (1) 50 62.5 250 ns LO/HI ofDATA_CLKat50%dutycycle) Slaveselectleadtime,slaveselect t 200 ns STE,LEAD lowtoclock Slaveselectlagtime,lastclockto t 200 ns STE,LAG slaveselecthigh t MOSIinputdatasetuptime 15 ns SU,SI t MOSIinputdataholdtime 15 ns HD,SI t MISOinputdatasetuptime 15 ns SU,SO t MISOinputdataholdtime 15 ns HD,SO t MISOoutputdatavalidtime DATA_CLKedgetoMISOvalid,C =<30pF 30 50 75 ns VALID,SO L (1) RecommendedDATA_CLKspeedis2MHz;higherdataclockdependsonthecapacitiveload.MaximumSPIclockspeedshouldnot exceed10MHz.Thisclockspeedisacceptableonlywhenexternalcapacitiveloadislessthan30pF.MISOdriverhasatypicaloutput resistanceof400Ω(12-nstimeconstantwhen30-pFloadisused). 10 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6 Detailed Description 6.1 Functional Block Diagram Figure6-1showsthefunctionalblockdiagram. VDD_I/O RX_IN1 MUX PAhmapsleituadned Gain (RASUSXI) Logic I/O_0 Detector State I/O_1 Control Logic I/O_2 RX_IN2 RSSI (Control I/O_3 (External) Registersand Phaseand (RMSaSinI) CoLmogmica)nd Level II//OO__45 Amplitude Gain Sh Detector anFdilAteGrC Digitizer MCU ifter I/O_6 VDD_PA Interface I/O_7 ISO Protocol Decoder IRQ Handling SYS_CLK TX_OUT Transmitter Framing Bit 12-Byte Analog Front End Framing FIFO DATA_CLK VIN Serial Conversion VDD_A VSS_PA CRC and Parity BAND_GAP EN VSS_A EN2 Digital Control VDD_RF ASK/OOK State Machine MOD Voltage SupplyRegulator Systems VSS_RF (SupplyRegulatorsand ReferenceVoltages) VDD_X OSC_IN VSS Crystal or Oscillator OSC_OUT Timing System VSS_D Copyright © 2017,Texas Instruments Incorporated Figure6-1.FunctionalBlockDiagram 6.2 Power Supplies The TRF7963A positive supply input VIN (pin 2) sources three internal regulators with output voltages VDD_RF, VDD_A, and VDD_X. All regulators require external bypass capacitors for supply noise filtering and must be connected as indicated in reference schematics. These regulators provide a high power supplyrejectratio(PSRR)asrequiredforRFIDreadersystems.AllregulatorsaresuppliedbyVIN(pin2). The regulators are not independent and have common control bits in register 0x0B for output voltage setting.Theregulatorscanbeconfiguredtooperateineitherautomaticormanualmode(register 0x0B, bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode lets the usermanuallyconfiguretheregulatorsettings. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 11 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.3 Supply Arrangements RegulatorSupplyInput:VIN The positive supply at VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. VIN provides the supply input sources for three internal regulators with the output voltages VDD_RF, VDD_A, and VDD_X. Externalbypasscapacitorsforsupplynoisefilteringmustbeused(perreferenceschematics). NOTE VINmustbethehighestvoltagesuppliedtotheTRF7963A. RFPowerAmplifierRegulator:VDD_RF The VDD_RF (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 5-V manual operation, the VDD_RF output voltage can be set from 4.3 V to 5 V in 100-mV steps. In 3-V manual operation, the output can be programmed from 2.7 V to 3.4 V in 100-mV steps (see Table 6-2). The maximum output current capability for 5-V operation is 150 mAandfor3-Voperationis100mA. AnalogSupplyRegulator:VDD_A Regulator VDD_A (pin 1) supplies the analog circuits of the device. The output voltage setting depends on the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual operation, the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 3-V manual operation, the VDD_A output can be set from 2.7 Vto3.4Vin100-mVsteps(seeTable6-2). NOTE The configuration of VDD_A and VDD_X regulators are not independent from each other. TheVDD_Aoutputcurrentshouldnotexceed20mA. DigitalSupplyRegulator:VDD_X The digital supply regulator VDD_X (pin 32) provides the power for the internal digital building blocks and can also be used to supply external electronics within the reader system. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for supplynoisefilteringmustbeused(refertothereferenceschematics). NOTE TheconfigurationoftheVDD_AandVDD_Xregulatorsarenotindependentfromeachother. TheVDD_Xoutputcurrentshouldnotexceed20mA. The RF power amplifier regulator (VDD_RF), analog supply regulator (VDD_A), and digital supply regulator (VDD_X) can be configured to operate in either automatic or manual mode described in Table 6- 1. The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possiblesupplyvoltagetoensuremaximumRFpoweroutput. By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are automatically set every time the system is activated by setting EN input High or each time the automatic regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit isalreadyhigh,theautomaticsettingbit(B7inregister0x0B)shouldbechanged:1-0-1. 12 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_X. The "Delta Voltage" in automatic regulator mode can be increased up to 400 mV (for more details, see bits B0 to B2 in register 0x0B). PowerAmplifierSupply:VDD_PA The power amplifier of the TRF7963A is supplied through VDD_PA (pin 4). The positive supply pin for the RFpoweramplifierisexternallyconnectedtotheregulatoroutputVDD_RF(pin3). I/OLevelShifterSupply:VDD_I/O The TRF7963A has a separate supply input VDD_I/O (pin 16) for the build in I/O level shifter. The supported input voltage ranges from 1.8 V to VIN, however not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is directly connected to VDD_X while VDD_X also supplies the MCU. This ensures thattheI/OsignallevelsoftheMCUmatchwiththelogiclevelsoftheTRF7963A. NegativeSupplyConnections:VSS,VSS_RX,VSS_A,VSS_PA ThenegativesupplyconnectionsVSS_XofeachfunctionalblockareallexternallyconnectedtoGND. The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the negativesupplyfortheRFreceiverVSS_RX(pin7). 6.4 Supply Regulator Settings The input supply voltage mode of the reader must be selected. This is done in the Chip Status Control register (0x00). Bit 0 in register 0x00 selects either 5-V or 3-V input supply voltage. The default configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply voltageisbelow4.3V,the3-Vconfigurationshouldbeused. Thevariousregulatorscanbeconfiguredtooperateinautomaticormanualmode.Thisisdoneinthe RegulatorandI/OControlregister(0x0B)(seeTable6-1andTable6-2). Table6-1.SupplyRegulatorSetting:5-VSystem OPTIONBITSSETTINGINREGULATORCONTROL REGISTER REGISTER(1) COMMENTS ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 AutomaticMode(default) 0B 1 x x x x x 1 1 Automaticregulatorsettingwith250-mVdifference 0B 1 x x x x x 1 0 Automaticregulatorsettingwith350-mVdifference 0B 1 x x x x x 0 0 Automaticregulatorsettingwith400-mVdifference ManualMode 0B 0 x x x x 1 1 1 VDD_RF=5V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 1 1 0 VDD_RF=4.9V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 1 0 1 VDD_RF=4.8V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 1 0 0 VDD_RF=4.7V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 0 1 1 VDD_RF=4.6V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 0 1 0 VDD_RF=4.5V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 0 0 1 VDD_RF=4.4V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 0 0 0 VDD_RF=4.3V,VDD_A=3.4V,VDD_X=3.4V (1) x=don'tcare Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 13 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Table6-2.SupplyRegulatorSetting:3-VSystem OPTIONBITSSETTINGINREGULATORCONTROL REGISTER REGISTER(1) COMMENTS ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 AutomaticMode(default) 0B 1 x x x x x 1 1 Automaticregulatorsettingwith250-mVdifference 0B 1 x x x x x 1 0 Automaticregulatorsettingwith350-mVdifference 0B 1 x x x x x 0 0 Automaticregulatorsettingwith400-mVdifference ManualMode 0B 0 x x x x 1 1 1 VDD_RF=3.4V,VDD_A=3.4V,VDD_X=3.4V 0B 0 x x x x 1 1 0 VDD_RF=3.3V,VDD_A=3.3V,VDD_X=3.3V 0B 0 x x x x 1 0 1 VDD_RF=3.2V,VDD_A=3.2V,VDD_X=3.2V 0B 0 x x x x 1 0 0 VDD_RF=3.1V,VDD_A=3.1V,VDD_X=3.1V 0B 0 x x x x 0 1 1 VDD_RF=3.0V,VDD_A=3.0V,VDD_X=3.0V 0B 0 x x x x 0 1 0 VDD_RF=2.9V,VDD_A=2.9V,VDD_X=2.9V 0B 0 x x x x 0 0 1 VDD_RF=2.8V,VDD_A=2.8V,VDD_X=2.8V 0B 0 x x x x 0 0 0 VDD_RF=2.7V,VDD_A=2.7V,VDD_X=2.7V (1) x=don'tcare The regulator configuration function adjusts the regulator outputs by default to 250 mV below VIN level, but not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio). To further improve the PSRR, it is possible to increase the target voltage difference across VDD_X and VDD_A from its default to 350 mV or even 400 mV (for details, see Regulator and I/O Control register 0x0BdefinitionandTable6-2.) 6.5 Power Modes The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits intheChipStatusControlregister(0x00). Table 6-3 lists the configuration for the different power modes when using a 5-V or 3-V system supply. The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled, the 13.56-MHz oscillator is running, and the SYS_CLK (output clock for external microcontroller) is also available. The Regulator Control register settings shown are for optimized power out. The automatic setting (normally0x87)isoptimizedforbestPSRRandnoisereduction. 14 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Table6-3.PowerModes(1) CHIPSTATUS REGULATOR TIME TYPICAL TYPICAL CONTROL CONTROL TRANS- SYS_CLK SYS_CLK (FROM MODE EN2 EN RECEIVER VDD_X CURRENT POWER REGISTER REGISTER MITTER (13.56MHz) (60kHz) PREVIOUS (mA) OUT(dBm) (0X00) (0X0B) STATE) Mode4 (fullpower) x 1 21 07 On On On x On 130 23 20to25µs 5VDC Mode4 (fullpower) x 1 20 07 On On On x On 67 18 3.3VDC Mode3 (halfpower) x 1 31 07 On On On x On 70 20 20to25µs 5VDC Mode3 (halfpower) x 1 30 07 On On On x On 53 15 3.3VDC Mode2 x 1 03 07 Off On On x On 10.5 — 20to25µs 5VDC Mode2 x 1 02 00 Off On On x On 9 — 3.3VDC Mode1 x 1 01 07 Off Off On x On 5 — 20to25µs 5VDC Mode1 x 1 00 00 Off Off On x On 3 3.3VDC Standbymode x 1 81 07 Off Off On x On 3 — 4.8ms 5VDC Standbymode x 1 80 00 Off Off On x On 2 — 3.3VDC Sleepmode 1 0 x x Off Off Off On On 0.120 — 1.5ms Powerdown 0 0 x x Off Off Off Off Off <0.001 — Start (1) x=don'tcare Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 15 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com TheinputpinEN2hastwofunctions: • A direct connection from EN2 to VIN to ensure the availability of the regulated supply VDD_X and an auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is intended for systems in which the MCU is also being supplied by the reader supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets the MCU supply and clockbeavailableduringsleepmode. • EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case, the EN input is being controlled by the MCU (or other system device) that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56‑MHzoscillator(identicaltoconditionEN=1). When the user MCU controls EN and EN2, use a delay of 5 ms between EN and EN2. When the MCU controls only EN, TI recommends connecting EN2 to either VIN or GND, depending on the application MCUrequirementsforVDD_XandSYS_CLK. NOTE Using EN = 1 and EN2 = 1 in parallel at start-up should not be done as it may cause incorrectoperation. This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. IftheENinputissethigh(EN=1)bythe MCU (or other system device), the reader stays active. If the EN input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete Power-Down Mode 1. This option can be used to wake the reader system from complete power down(PDMode1)byusingapush-buttonswitchorbysendingasinglepulse. After the reader EN line is high, the other power modes are selected by control bits within the Chip Status Controlregister(0x00).ThepowermodeoptionsandstatesarelistedinTable6-3. When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform the required tasks. The MCU can then program the Chip Status Control register 0x00 and select the operationmodebyprogrammingtheadditionalregisters. • Standby mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in 100µs. • Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low-power modethatletsthereaderrecovertofulloperationwithin25µs. • Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollisionisimplemented. • Mode 3 and Mode 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the modesusedfortypicaltransmitandreceiveoperations. 16 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.6 Receiver – Analog Section 6.6.1 Main and Auxiliary Receiver The TRF7963A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the inputs is connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is available on at least one of the two inputs. This architecture eliminates any possible communication holes thatmayoccurfromthetagtothereader. The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers–the main receiver and the auxiliary receiver. Only the main receiver is used for reception; the auxiliary receiver is used for signal quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register (address0x00). Afterstart-up,RX_IN1ismultiplexedtothemainreceiverwhichiscomposedofanRF envelope detection, first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver is connected to the digitizing stage which output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal (subcarriersignal). The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of the demodulated subcarrier signal (internal RSSI). After start-up, RX_IN2 is multiplexed to the auxiliary receiver.Theauxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage andfinallytheauxiliaryRSSIblock. The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver.Todeterminethesignalquality,theresponsefromthetagisdetectedbythe"main"(pin RX_IN1) and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI level register (address 0x0F). The MCU can read the RSSI values from the TRF7963A RSSI register and decide if swapping the input signals is preferable or not. Setting B3 in the Chip Status Control register (address 0x00) to 1 connectsRX_IN1(pin8)totheauxiliaryreceiverandRX_IN2(pin9)tothemainreceiver. ThemainandauxiliaryreceiverinputstagesareRF envelope detectors. The RF amplitude at RX_IN1 and RX_IN2 should be approximately 3 V for a VIN supply level greater than 3.3 V. If the VIN level is lower, PP theRFinputpeak-to-peakvoltagelevelshouldnotexceedtheVINlevel. 6.6.2 Receiver Gain and Filter Stages The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has programmable 3-dB corner frequencies from 110 kHz to 450 kHz for the high-pass filter and from 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gain- and-filteringstagewithanominalgainof8dBandwithfrequencycharacteristicsidenticaltothefirstband- passstage. The internal filters are configured automatically depending on the selected ISO communication standard in the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly totheRXspecialsettingregisters(address0x0A). Table 6-4 shows the various settings for the receiver analog section. Setting B4, B5, B6, and B7 to 0 results in a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for ISO/IEC 14443 B data rate of 106 kbps, ISO/IEC 14443 A or B data rates of 212 kbps and 424 kbps, and FeliCa data rate of424kbps. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 17 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Table6-4.RXSpecialSettingRegister(0x0A) BIT FUNCTION COMMENTS B7 Band-passfilterfrom110kHzto570kHz Appropriateforany212-kHzsubcarriersystemslikeFeliCa B6 Band-passfilterfrom200kHzto900kHz AppropriateforManchester-coded106-kbps848-kHzsubcarriersystems(for B5 Band-passfilterfrom450kHzto1.5MHz example,usedinISO/IEC14443A). Appropriateforhighestbitrate(848kbps)usedinhigh-bit-rateISO/IEC14443B. B4 Band-passfilterfrom100kHzto1.5MHz Gainisreducedby7dB. B3 00=Nogainreduction 01=Gainreductionfor5dB SetstheRXdigitalgainreduction(changingthewindowofthedigitizing B2 10=Gainreductionfor10dB comparator). 11=Gainreductionfor15dB B1 Reserved B0 Reserved 6.7 Receiver – Digital Section The output of the TRF7963A analog receiver block is a digitized subcarrier signal and is the input to the digital receiver block, which consists of two sections that partly overlap. The digitized subcarrier signal is a digital representation of the modulation signal on the RF envelope. The two sections of the digital receiver blockaretheprotocolbitdecodersectionandtheframinglogicsection. The protocol bit decoder section converts the subcarrier coded signal into a serial bit stream and a data clock. The decoder logic is designed for maximum error tolerance. This tolerance lets the decoder section successfully decode even partly corrupted subcarrier signals that would otherwise be lost due to noise or interference. The framing logic section formats the serial bit stream data from the protocol bit decoder stage into data bytes. During the formatting process, special signals such as the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are also checked and removed. The end result is "clean" or "raw" data that is then sent to the 12-byte FIFO register where it can be read by the external microcontroller system. Providing the data this way, in conjunction with the timing register settings of the TRF7963A, means the firmware developer must know about much less of the finer details of the ISO protocols to create a very robust application, especiallyinlow-costplatformswherecodespaceisatapremiumandhighperformanceisstillrequired. The start of the receive operation (successfully received SOF) sets the IRQ flags in the IRQ Status register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13 (IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is data to be read from the FIFO. The FIFO Status register (0x1C) should be used to provide the number of bytes that should be clocked out during the actual FIFO read. Additionally, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed fromtheFIFO.Thatinterruptistriggeredwhenthereceiveddatapacketislongerthan9bytes. Any error in the data format, parity, or CRC is detected and notified to the external system by an interrupt request pulse. The source condition of the interrupt request pulse is available in the IRQ Status register (0x0C). The main register controlling the digital part of the receiver is the ISO Control register (0x01). By writing to this register, the user selects the protocol to be used. With each new write in this register, the default presets are reloaded in all related registers, so no further adjustments in other registers are neededforproperoperation. NOTE Ifadditionalregistersettingchangesareneededtofine-tunethesystem, set theISOControl register(0x01)beforemakingtheadditionalchanges. 18 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 The framing section also supports the bit-collision detection as specified in ISO/IEC 14443 A and ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ Status register (0x0C). For ISO/IEC 14443 A specifically, the position of the bit collision is written in two registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt Maskregister(0x0D)(bitsB6andB7). The collision position is presented as sequential bit number, where the count starts immediately after the start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these registers when their contents are combined after being read. (the count starts with 0 and the first 16 bits arethecommandcodeandthenumberofvalidbits[NVB]byte). The receive section also includes two timers. The RX wait time timer is controlled by the value in the RX Wait Time register (0x08). This timer defines the time interval after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents false detections resulting from transients following the transmit operation. The value of the RX Wait Time register (0x08) defines the time in increments of 9.44 µs. This register is preset at every write to ISO Control register (0x01) accordingtotheminimumtagresponsetimedefinedbyeachstandard. The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer measuresthetimefromthestartofslotintheanticollisionsequenceuntilthestartoftagresponse.If there is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status register(0x0C).Thisenablestheexternalcontrollertoberelievedofthe task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also automatically preset for everynewprotocolselection. 6.7.1 Received Signal Strength Indicator (RSSI) The TRF7963A incorporates three independent RSSI building blocks: Internal Main RSSI, Internal Auxiliary RSSI, and External RSSI. The internal RSSI blocks are measuring the amplitude of the subcarrier signal, and the external RSSI block measures the amplitude of the RF carrier signal at the receiverinput. 6.7.1.1 InternalRSSI– MainandAuxiliaryReceivers Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal (subcarrier).InternalMainRSSIandInternalAuxiliaryRSSIareidenticalexcept that they are connected to different RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path conditions. The Internal RSSI values can be used to adjust the RX gain settings or decide which RX path (main or auxiliary) provides the greater amplitude and, hence, to decide if the MUX may need to be reprogrammed toswap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by thereader.ThisguaranteesanupdatedRSSImeasurementforeachnewtagresponse. The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range is 600 mVpp to 4.2 Vpp with a typical step size of approximately 600 mV. Both RSSI values "Internal Main"and"InternalAux"RSSIarestoredintheRSSILevelsandOscillatorStatusregister(0x0F). Figure6-2showsthenominalrelationshipbetweentheinputRFpeaklevelandtheRSSIvalue. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 19 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com F) 7 0 x 0 e ( u 6 al V er gist 5 e R s u at 4 St or at cill 3 s O d an 2 s el v e SI L 1 S R 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 Input RF Carrier Level (V ) PP Figure6-2.DigitalInternalRSSI(MainandAuxiliary)ValuevsRFInputLevel This RSSI measurement is done during the communication to the Tag; this means the TX must be on. Bit1intheChipStatusControlregister (0x00) defines if internal RSSI or the external RSSI value is stored in the RSSI Levels and Oscillator Status register 0x0F. Direct command 0x18 is used to trigger an internal RSSImeasurement. 6.7.1.2 ExternalRSSI The external RSSI is mainly used for test and diagnostic to sense the amplitude of any 13.56-MHz signal at the receiver's RX_IN1 input. The external RSSI measurement is typically done in active mode when the receiver is on but transmitter output is off. The level of the RF signal received at the antenna is measured andstoredintheRSSILevelsandOscillatorStatusregister(0x0F). Figure6-3showstherelationshipbetweenthevoltageattheRX_IN1inputandthe3-bitcode. F) 7 0 x 0 e ( alu 6 V er st gi 5 e R s u at 4 St or at cill 3 s O d an 2 s el v e L 1 SI S R 0 0 25 50 75 100 125 150 175 200 225 250 275 300 325 RF Input Voltage Level at Pin RF_IN1 (mV ) PP Figure6-3.DigitalExternalRSSIValuevsRFInputLevel 20 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 The relation between the 3-bit code and the external RF field strength (A/m) sensed by the antenna must be determined by calculation or by experiments for each antenna design. The antenna Q-factor and connection to the RF input influence the result. Direct command 0x19 is used to trigger an internal RSSI measurement. TochecktheinternalorexternalRSSIvalueindependentofanyotheroperation: 1. Settransmittertodesiredstate(onoroff)usingBit5oftheChipStatusControlregister(0x00)and enablereceiverusingBit1. 2. CheckinternalorexternalRSSIusingdirectcommands0x18or0x19,respectively.Thisactionplaces theRSSIvalueintheRSSIregister. 3. Delayatleast50µs. 4. ReadtheRSSIregisterusingdirectcommand0x0F.Valuescanrangefrom0x40to0x7F. 5. Repeatsteps1to4asdesired;theregisterisresetafterread. 6.8 Oscillator Section The 13.56-MHz oscillator is controlled by the Chip Status Control register (0x00) and the EN and EN2 signals. The oscillator generates the RF frequency for the RF output stage and the clock source for the digital section. The buffered clock signal is available at pin 27 (SYS_CLK) for external circuits. B4 and B5 insidetheModulationand SYS_CLK register (0x09) can be used to divide the external SYS_CLK signal at pin27by1,2,or4. Typicalstart-uptimefromcompletepowerdownisintherangeof3.5ms. DuringPowerDownMode2(EN=0,EN2=1)thefrequencyofSYS_CLKisswitchedto60kHz(typical). The 13.56-MHz crystal must be connected between pin 30 and pin 31. The external shunt capacitors values for C and C must be calculated based on the specified load capacitance of the crystal being 1 2 used. The external shunt capacitors are calculated as two identical capacitors in series plus the stray capacitanceoftheTRF7963AandparasiticPCBcapacitanceinparalleltothecrystal. The parasitic capacitance (C , stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF S (typical). Asan example, using a crystal with a required load capacitance (C ) of 18 pF, the calculation is as follows L (seeFigure6-4): C =C =2 ×(C – C )=2×(18pF– 4.5pF)=27pF 1 2 L S Placea27-pFcapacitoronpins30and31toensurepropercrystaloscillatoroperation. C S TRF796xA Pin 30 Pin 31 C Crystal C 1 2 Figure6-4.CrystalBlockDiagram Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 21 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Table6-5showstheminimumcharacteristicsrecommendedforanycrystalusedwithTRF7963A. Table6-5.MinimumCrystalRecommendations PARAMETER SPECIFICATION Frequency 13.56MHz Modeofoperation Fundamental Typeofresonance Parallel Frequencytolerance ±20ppm Aging <5ppm/year Operationtemperaturerange –40°Cto85°C As an alternative, an external clock oscillator source can be connected to pin 31 to provide the system clock,andpin30canbeleftopen. 6.9 Transmitter - Analog Section The 13.56-MHz oscillator generates the RF signal for the PA stage. The power amplifier consists of a driver with selectable output resistance of 4 Ω or 8 Ω (typical). The transmit power levels are selectable between 100 mW (half power) or 200 mW (full power) when configured for 5-V automatic operation. Selection of the transmit power level is set by bit B4 in the Chip Status Control register (0x00). When configured for 3-V automatic operation, the transmit power level is typically in the range of 33 mW (half power)or70mW(fullpower). The ASK modulation depth is controlled by bits B0, B1, and B2 in the Modulator and SYS_CLK Control register(0x09).TheASKmodulationdepthrangecanbeadjustedfrom7%to30%or100%(OOK). External control of the transmit modulation depth is possible by setting the ISO Control register (0x01) to direct mode. While operating the TRF7963A in direct mode, the transmit modulation is made possible by selecting the modulation type ASK or OOK at pin 12. External control of the modulation type is made possibleonlyifenabledbysettingB6intheModulatorandSYS_CLKControlregister(0x09)to1. In normal operation mode, the length of the modulation pulse is defined by the protocol selected in the ISO Control register (0x01). In case of a high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length must be correctedbyusingtheTXPulseLengthregister(0x06). If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 0x00, the pulse length is equal to the value of the register multiplied by 73.7ns.Thismeansthepulselengthcanbeadjustedfrom73.7nsto18.8 µsin73.7-nsincrements. 6.10 Transmitter - Digital Section The digital part of the transmitter is a mirror of the receiver. The settings controlled the ISO Control register (0x01) are applied to the transmitter just like the receiver. In the TRF7963A default mode (ISO Mode), the TRF7963A automatically adds all the special signals like start of communication, end of communication,SOF,EOF,paritybitsandCRCbytes. Thedataisthencoded to modulation pulse levels and sent to the RF output stage modulation control unit. Just like with the receiver, this means that the external system MCU only must load the FIFO with data and all the microcoding is done automatically, again saving the firmware developer code space and time. Additionally, all the registers used for transmit parameter control are automatically preset to optimum valueswhenanewselectionisenteredintotheISOControlregister(0x01). NOTE TheFIFOmustberesetbeforestartinganytransmissionwithdirectcommand0x0F. 22 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Therearetwowaystostartthetransmitoperation: • Send the transmit command and the number of bytes to be transmitted first, and then start to send the datatotheFIFO.ThetransmissionstartswhenfirstdatabyteiswrittenintotheFIFO. • Loadthenumberofbytestobesentintoregisters0x1Dand0x1Eandload the data to be sent into the FIFO (address 0x1F), followed by sending a transmit command (see Direct Commands section). The transmissionthenstartswhenthetransmitcommandisreceived. NOTE If the data length is longer than the FIFO, the external system MCU is warned when the majorityofdatafromtheFIFOwasalreadytransmittedbysendingandinterruptrequestwith flag in IRQ register to indicate a FIFO low or high status. The external system should respondbyloadingnextdatapacketintotheFIFO. At the end of a transmit operation, the external system MCU is notified by interrupt request (IRQ) with a flagintheIRQregister(0x0C)indicatingTXiscomplete(examplevalue=0x80). The TX Length registers also support incomplete byte transmission. The high two nibbles in register 0x1D and the nibble composed of bits B4 to B7 in register 0x1E store the number of complete bytes to be transmitted. Bit B0 in register 0x1E is a flag indicating that there are also additional bits to be transmitted which do not form a complete byte. The number of bits is stored in bits B1 to B3 of the same register (0x1E). Some protocols have options so there are two sublevel configuration registers to select the TX protocol options. • ISO14443B TX Options register (0x02). It controls the SOF and EOF selection and EGT selection for theISO/IEC14443Bprotocol. • ISO14443A High-Bit-Rate and Parity Options register (0x03). This register enables the use of different bit rates for RX and TX operations in ISO/IEC 14443 high-bit-rate protocol. Besides that, it also selects theparitymethodincaseofISO/IEC14443Ahighbitrate. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector The TRF7963A can be used in conjunction with an external TX power amplifier or external subcarrier detector for the receiver path. If this is the case, Bit B6 of the Regulator and I/O Control register (0x0B) must be set to 1. This setting has two functions: First, to provide a modulated signal for the transmitter, if needed. Second, to configure the TRF7963A receiver inputs for an external demodulated subcarrier input. The design of an external power amplifier requires detailed RF knowledge. There are also readily designedandcertifiedhigh-powerHFreadermodulesonthemarket. 6.12 Communication Interface 6.12.1 General Introduction The communication interface to the reader can be configured in two ways: with a eight line parallel interface (D0:D7) plus DATA_CLK, or with a 3- or 4-wire Serial Peripheral Interface (SPI). The SPI interface uses traditional master out/slave in (MOSI), master in/slave out (MISO), IRQ, and DATA_CLK lines.TheSPIcanbeoperatedwithorwithoutusingtheslaveselectline. These communication modes are mutually exclusive, which means that only one mode can be used at a timeintheapplication. WhentheSPIinterfaceisselected,theunusedI/O_2,I/O_1,andI/O_0pinsmustbe hard-wired according to Table 6-6. At power up, the TRF7963A IC samples the status of these three pins and then enters one ofthepossibleSPImodesinTable6-6. samples the status of these three pins. If they are not the same (all high or all low), the IC enters one of thepossibleSPImodes. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 23 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com The TRF7963A always behaves as the slave, while the microcontroller (MCU) behaves as the master device. The MCU initiates all communications with the TRF7963A. The TRF7963A makes use of the InterruptRequest(IRQ)pininbothparallelandSPImodestoprompttheMCUforservicingattention. Table6-6.PinAssignmentinParallelandSerialInterfaceConnectionorDirectMode PIN PARALLEL PARALLELDIRECT SPIWITHSS SPIWITHOUTSS DATA_CLK DATA_CLK DATA_CLK DATA_CLKfrommaster DATA_CLKfrommaster I/O_7 A/D[7] MOSI(1)=datain(readerin) MOSI(1)=datain(readerin) I/O_6 A/D[6] Directmode,dataout MISO(2)=dataout(MCUout) MISO(2)=dataout(MCUout) (subcarrierorbitstream) I/O_5(3) A/D[5] Directmode,strobe(bitclockout) See (3) See (3) I/O_4 A/D[4] SS(slaveselect)(4) – I/O_3 A/D[3] – – – I/O_2 A/D[2] – AtVDD AtVDD I/O_1 A/D[1] – AtVDD AtVSS I/O_0 A/D[0] – AtVSS AtVSS IRQ IRQinterrupt IRQinterrupt IRQinterrupt IRQinterrupt (1) MOSI=Masterout,slavein (2) MISO=Masterin,slaveout (3) TheI/O_5pinisusedonlyforinformationwhendataisputoutofthechip(forexample,reading1bytefromthechip).Itisnecessary firsttowriteintheaddressoftheregister(8clocks)andthentogenerateanother8clocksforreadingoutthedata.TheI/O_5pingoes highduringthesecond8clocks.ButfornormalSPIoperationsI/O_5pinisnotused. (4) Theslaveselectpinisactivelow. Communication is initialized by a start condition, which is expected to be followed by an Address/Commandword(Adr/Cmd).TheAdr/Cmdwordis8bitslong,andTable6-7describesitsformat. Table6-7.Address/CommandWordBitDistribution BIT DESCRIPTION BITFUNCTION ADDRESS COMMAND 0=Address B7 Commandcontrolbit 0 1 1=Command 1=Read B6 Read/Write R/W 0 0=Write B5 Continuousaddressmode 1=Continuousmode R/W 0 B4 Address/commandbit4 Adr4 Cmd4 B3 Address/commandbit3 Adr3 Cmd3 B2 Address/commandbit2 Adr2 Cmd2 B1 Address/commandbit1 Adr1 Cmd1 B0 Address/commandbit0 Adr0 Cmd0 The MSB (bit 7) determines if the word is to be used as a command or as an address. The last two columns of Table 6-7 list the function of the separate bits if either address or command is written. Data is expected once the address word is sent. In continuous address mode (continuous mode = 1), the first data that follows the address is written (or read) to (from) the given address. For each additional data, the address is incremented by one. Continuous mode can be used to write to a block of control registers in a single stream without changing the address; for example, setup of the predefined standard control registers from the MCU nonvolatile memory to the reader. In noncontinuous address mode (simple addressedmode),onlyonedatawordisexpectedaftertheaddress. Address Mode is used to write or read the configuration registers or the FIFO. When writing more than 12bytestotheFIFO,theContinuousAddressModeshouldbesetto1. The Command Mode is used to enter a command that results in reader action (for example, initialize transmission,enablereader,andturnreaderonoroff). 24 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 ThefollowingexamplesshowtheexpectedcommunicationsbetweenanMCUandtheTRF7963A. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 25 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Table 6-8 lists the format of a continuous address register read, and Figure 6-5 and Figure 6-6 show examples. Table6-8.ContinuousAddressMode Start Adrx Data(x) Data(x+1) Data(x+2) Data(x+3) Data(x+4) ... Data(x+n) StopCont Figure6-5.ContinuousAddressRegisterWriteExampleStartingWithRegister0x00(UsingSPIWithSS Mode) Figure6-6.ContinuousAddressRegisterReadExampleStartingWithRegister0x00(UsingSPIWithSS Mode) 26 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Table6-9liststheformatofasingleaddressregisterread,andFigure6-7 andFigure6-8showexamples. Table6-9.NoncontinuousAddressMode(SingleAddressMode) Start Adrx Data(x) Adry Data(y) ... Adrz Data(z) StopSgl Figure6-7.SingleAddressRegisterWriteExampleofRegister0x00(UsingSPIWithSSMode) Figure6-8.SingleAddressRegisterReadExampleofRegister0x00(UsingSPIWithSSMode) Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 27 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Table6-10liststheformatofthedirectcommandmode,andFigure6-9 showsanexample. Table6-10.DirectCommandMode Start Cmdx (Optionaldataorcommand) Stop Figure6-9.DirectCommandExampleofSending0x0F(Reset)(UsingSPIWithSSMode) TheotherDirectCommandCodesfromMCUtoTRF7963AaredescribedinSection6.13. 6.12.2 FIFO Operation The FIFO is a 12-byte register at address 0x1F with byte storage locations 0 to 11. FIFO data is loaded in a cyclical manner and can be cleared by a reset command (0x0F, see Figure 6-9 showing this Direct Command). Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 4-bit FIFO byte counter (bits B0 to B3 in register 0x1C) that keeps track of the number of bytes loaded into the FIFO. If the number of bytes in the FIFO is n, the register value is n – 1 (number of bytes in FIFO register). If 8 bytesareintheFIFO,theFIFOcounter(bitsB0toB3inregister0x1C)hasthevalue7. A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 0x1D and 0x1E) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided in register 0x1E (bits B0 to B3). Together these counters make up the TX length value that determineswhenthereadergeneratestheEOFbyte. FIFOstatusflagsareasfollows: 1. FIFOoverflow(bitB4ofregister0x1C):IndicatesthattheFIFOwasloadedtoosoon 2. FIFOleveltoolow(bitB5ofregister0x1C):Indicatesthatonlythreebytesarelefttobetransmitted (Canbeusedduringtransmission.) 3. FIFOlevelhigh(bitB6ofregister0x1C):IndicatesthatninebytesarealreadyloadedintotheFIFO (CanbeusedduringreceptiontogenerateaFIFOreceptionIRQ.ThisistonotifytheMCUtoservice thereaderintimetoensureacontinuousdatastream.) 28 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 During transmission, the FIFO is checked for an almost-empty condition, and during reception for an almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single sequenceis12bytes. NOTE Thenumberofbytesinaframe,transmittedorreceived,canbegreaterthan12bytes. During transmission, the MCU loads the TRF7963A FIFO (or, during reception, the MCU removes data from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the number of bytes in the FIFO is less than 3 or greater than 9, so that MCU can send new data or remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not surpass the value defined in TX length bytes. The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the firstbyteiswrittenintoFIFO. Figure6-10.CheckingtheFIFOStatusRegister(UsingSPIWithSSMode) 6.12.3 Parallel Interface Mode Inparallelmode,thestartconditionisgeneratedontherisingedgeoftheI/O_7pinwhiletheCLKishigh. This is used to reset the interface logic. Figure 6-11, Figure 6-12, and Figure 6-13 show the sequence of thedata,withan8-bitaddresswordfirst,followedbydata. Communicationisendedby: • TheStopSmplcondition,whereafallingedgeontheI/O_7pinisexpectedwhileCLKishigh • TheStopContcondition,where the I/O_7 pin must have a successive rising and falling edge while CLK islowtoresettheparallelinterfaceandbereadyforthenewcommunicationsequence • TheStopSmplconditionisalsousedtoterminatethedirectmode. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 29 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Start StopSmpl Condition Condition CLK 50 ns I/O_[7] a1 [7] d1 [7] a2 [7] d2 [7] aN [7] dN [7] I/O_[6:0] a1 [6:0] d1 [6:0] a2 [6:0] d2 [6:0] aN [6:0] dN [6:0] Figure6-11.ParallelInterfaceCommunicationWithSimpleStopCondition(StopSmpl) Start StopCont Condition Continuous Mode CLK 50 ns I/O_[7] a0 [7] d0 [7] d1 [7] d2 [7] d3 [7] dN [7] I/O_[6:0] xx a0 [6:0] d0 [6:0] d1 [6:0] d2 [6:0] d3 [6:0] dN [6:0] xx Figure6-12.ParallelInterfaceCommunicationWithContinuousStopCondition(StopCont) Figure6-13.ParallelInterfaceCommunicationWithContinuousStopCondition 6.12.4 Reception of Air Interface Data At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to determine the reason for the interrupt by reading the IRQ Status register (address 0x0C), after which the MCUreadsthedatafromtheFIFO. If the received packet is longer than 8 bytes, the interrupt is sent before the end of the receive operation when the ninth byte is loaded into the FIFO (75% full). The MCU must read the FIFO status register (0x1C) to determine the number of bytes to be read from the FIFO. Next, the MCU must read the data in the FIFO. It is optional but recommended to read the FIFO Status register (0x1C) after reading the FIFO data to determine if the receive is complete. In the case of an IRQ_FIFO, the MCU should expect either anotherIRQ_FIFOorRXcompleteinterrupt.ThisisrepeateduntilanRXcompleteinterruptisgenerated. If the reader detects a receive error, the corresponding error flag is set (framing error, CRC error) in the IRQStatusregister,indicatingtotheMCUthatreceptionwasnotcompletedcorrectly. 30 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.12.5 Data Transmission to MCU Before beginning data transmission, the FIFO should always be cleared with a reset command (0x0F). Data transmission is initiated with a selected command (see Section 6.13). The MCU then commands the reader to do a continuous write command (0x3D) (see Table 6-7) starting from register 0x1D. Data written into register 0x1D is the TX length byte 1 (upper and middle nibbles), while the following byte in register 0x1E is the TX length byte 2 (lower nibble and broken byte length). The TX byte length determines when the reader sends the EOF byte. After the TX length bytes are written, FIFO data is loaded in register 0x1F with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the FIFO. The loading of TX length bytes and the FIFO can be done with a continuous write command,astheaddressesaresequential. At the start of transmission, the flag B7 (IRQ_TX) is set in the IRQ Status register. If the transmit data is shorter than or equal to 4 bytes, the interrupt is sent only at the end of the transmit operation. If the number of bytes to be transmitted is higher or equal to 5, then the interrupt is generated. This occurs also when the number of bytes in the FIFO reaches 3. The MCU should check the IRQ Status register and FIFO Status register and then load additional data to the FIFO, if needed. At the end of the transmit operation,aninterruptissenttoinformtheMCUthatthetaskiscomplete. 6.12.6 Serial Interface Communication (SPI) When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard-wired as specified in Table 6-6. On power up, the TRF7963A looks for the status of these pins; if they are not the same (not all high,ornotalllow),thereaderentersintooneoftwopossibleSPImodes: • SPIwithslaveselect or • SPIwithoutslaveselect The choice of one of these modes over the other should be made based on the available GPIOs and the desiredcontrolofthesystem. The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the TRF7963A IRQ Status register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ Status register. The dummy read is required in SPI mode, because the reader's IRQ Status register needs an additional clock cycle to clear the register. This is not required inparallelmode,becausetheadditionalclockcycleisincludedintheStopcondition. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 31 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Aprocedureforadummyreadisasfollows: 1. Startingthedummyread 1. Whenusingslaveselect(SS):setSSbitlow 2. WhennotusingSS:startconditioniswhenSCLKishigh 2. SendaddresswordtoIRQStatusregister(0x0C)withreadandcontinuousaddressmodebitssetto1 3. Read1byte(8bits)fromIRQStatusregister(0x0C) 4. Dummyread1bytefromregister0Dh(collisionpositionandinterruptmask) 5. Stoppingthedummyread 1. Whenusingslaveselect(SS):setSSbithigh 2. WhennotusingSS:stopconditionwhenSCLKishigh WriteAddress Read Data in Dummy Read Byte (0x6C) IRQ Status Register DATA_CLK No DataTransitions No DataTransitions MOSI 0 1 1 0 1 1 0 0 (All High/Low) (All High/Low) MISO Don't Care B7 B6 B5 B4 B3 B2 B1 B0 Ignore SLAVE SELECT Figure6-14.ProcedureforDummyRead Figure6-15.DummyReadUsingSPIWithSS 6.12.6.1 SerialInterfaceModeWithoutSlaveSelect(SS) The serial interface without the slave select pin must use delimiters for the start and stop conditions. Betweenthesedelimiters,theaddress,data,andcommandwords can be transferred. All words must be 8 bitslongwithMSBtransmittedfirst(seeFigure6-16). 32 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Start Stop Condition Condition Data Clock 50 ns Data In b7 b6 b5 b4 b3 b2 b1 b0 Data Out Figure6-16.SPIWithoutSlaveSelectTiming In this mode, a rising edge on data in (I/O_7, pin 24) while SCLK is high resets the serial interface and prepares it to receive data. Data in can change only when SCLK is low, and it is read by the reader on the SCLKrisingedge.Communicationisterminatedbythestop condition when the data in falling edge occurs duringahighSCLKperiod. 6.12.6.2 SerialInterfaceModeWithSlaveSelect(SS) The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the falling edge and is validated in the reader on the rising edge (see Figure 6-17). Communication is terminatedwhentheSlaveSelectsignalgoeshigh. Allwordsmustbe8bitslongwiththeMSBtransmittedfirst. Write Mode Switch Read Mode CKPH = 1, CKPL= 0 DATA_CLK CKPH = 0, CKPL= 0 t DataTransition is on t Polarity DataTransition is on t STE,LEAD Data Clock Falling Edge STE,LAG Data Clock Rising Edge STE,LAG Slave MOSI Valid on Data Clock Rising Edge MOSI Valid on Data Clock Falling Edge Select 1/f UCxCLK Data Clock tLO/HI tLO/HI tHD,SI tSU,SO t SU,SI No DataTransitions MOSI b7 b6 to b1 b0 (All High, Low) t HD,SO tVALID,SO tSTE,DIS MISO Don't Care b7 b6... ...b1 b0 Figure6-17.SPIWithSlaveSelectTiming The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 6-17. During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pinatthefallingedgeofSCLK.Ittakeseightclockedgestoreadoutthefullbyte(MSBfirst). When using the hardware SPI (for example, an MSP430 hardware SPI) to implement this feature, care must be taken to switch the SCLK polarity after write phase for proper read operation. The example clock polarity for the Figure 6-17 shows the MSP430-specific environment in the write-mode and read-mode boxes. See the USART-SPI chapter for any specific microcontroller family for further information on the setting the appropriate clock polarity. This clock polarity switch must be done for all read (single or continuous) operations. The MOSI (serial data out) should not have any transitions (all high or all low) duringthereadcycle.TheSlaveSelectshouldbelowduringthewholewriteandreadoperation. SeeSection5.6,SwitchingCharacteristics,forthetimingvaluesshowninFigure6-17. Figure6-18showsthecontinuousreadoperation. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 33 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Write Read Read Address Byte Data Byte 1 Data Byte n DATA_CLK No DataTransitions No DataTransitions MOSI B7 B6 B5 B4 B3 B2 B1 B0 (All High or Low) (All High or Low) MISO Don't Care B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 SLAVE SELECT Figure6-18.ContinuousReadOperationUsingSPIWithSlaveSelect Figure6-19.ContinuousReadofRegisters0x00to0x05UsingSPIWithSS 34 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.12.7 Direct Mode Directmodeletsthereaderbeconfiguredinoneoftwoways: Direct mode 0 (bit 6 = 0, as defined in ISO Control register) lets the application use only the front-end functionsofthereader,bypassingtheprotocolimplementationinthereader.Fortransmitfunctions, the application has direct access to the transmit modulator through the MOD pin (pin 14). On the receive side, the application has direct access to the subcarrier signal (digitized RF envelope signal) on I/O_6 (pin23). Direct mode 1 (bit 6 = 1, as defined in ISO Control register) uses the subcarrier signal decoder of the selected protocol (as defined in ISO Control register). This means that the receive output is not the subcarrier signal but the decoded serial bit stream and bit clock signals. The serial data is available on I/O_6 (pin 23), and the bit clock is available on I/O_5 (pin 22). The transmit side is identical; the applicationhasdirect control over the RF modulation through the MOD input. This mode is provided so that the application can implement a protocol that has the same bit coding as one of the protocols implementedinthereader,butneedsadifferentframingformat. To select direct mode, first choose which direct mode to enter by writing B6 in the ISO Control register. This bit determines if the receive output is the direct subcarrier signal (B6 = 0) or the serial data of the selected decoder. If B6 = 1, then the application must also define which protocol should be used for bit decodingbywritingtheappropriatesettingintheISOControlregister. The reader actually enters the direct mode when B6 (direct) is set to 1 in the Chip Status Control register. Direct mode starts immediately. The write command should not be terminated with a stop condition (see communication protocol), because the stop condition terminates the direct mode and clears B6. This is necessary as the direct mode uses one or two I/O pins (I/O_6 and I/O_5). Normal parallel communication isnotpossibleindirectmode.Sendingastopconditionterminatesdirectmode. Figure6-20showsthedifferentconfigurationsavailableindirectmode. • Inmode0,thereaderisusedasanAFEonly,andprotocolhandlingisbypassed. • In mode 1, framing is not done, but SOF and EOF are present. This allows for a user-selectable framinglevelbasedonanexistingISOstandard. • In mode 2, data is ISO standard formatted. SOF, EOF, and error checking are removed, so the microprocessorreceivesonlybytesofrawdatathrougha12-byteFIFO. Analog Front End (AFE) Direct Mode 0: Raw RF Subcarrier Data Stream ISO Encoders and Decoders 14443A 14443B FeliCa Direct Mode 1: Raw Digital ISO Coded Data Without Protocol Frame Packetization and Framing ISO Mode: Full ISO Framing and Error Checking Microcontroller (Typical Mode) Figure6-20.User-ConfigurableModes Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 35 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com The steps to enter direct mode follow, using SPI with SS communication method only as one example, as direct modes are also possible with parallel and SPI without SS. The application must enter direct mode 0 to accommodate non-ISO standard compliant card type communications. direct mode can be entered at any time, so that if a card type started with ISO standard communications, then deviated from the standardafterbeingidentifiedandselected,theabilitytogointodirectmode0becomesveryuseful. Step1:ConfigurepinsI/O_0toI/O_2forSPIwithSS Step2:Setpin12oftheTRF7963A(ASK/OOKpin)to0forASKor1forOOK Step3:ProgramtheTRF7963Aregisters Thefollowingregistersmustbeexplicitlysetbeforegoingintodirectmode. 1. ISOControlregister(0x01)totheappropriatestandard: – 0x08forISO/IEC14443A(106kbps) – 0x1AforFeliCa212kbps – 0x1BforFeliCa424kbps 2. ModulatorandSYS_CLKRegister(0x09)totheappropriateclockspeedandmodulation: – 0x21for6.78-MHzclockandOOK(100%)modulation – 0x20for6.78-MHzclockandASK10%modulation – 0x22for6.78-MHzclockandASK7%modulation – 0x23for6.78-MHzclockandASK8.5%modulation – 0x24for6.78-MHzclockandASK13%modulation – 0x25for6.78-MHzclockandASK16%modulation Seeregister0x09definitionforallotherpossiblevalues. ExampleregistersettingforISO/IEC14443Aat106kbps: – ISOControlregister(0x01)to0x08 – RXNoResponseWaitTimeregister(0x07)to0x0E – RXWaitTimeregister(0x08)to0x07 – ModulatorControlregister(0x09)to0x21(oranycustommodulation) – RXSpecialSettingsregister(0x0A)to0x20 Step4:Enterdirectmode Thefollowingregistersmustbereprogrammedtoenterdirectmode: 1. SetbitB6oftheModulatorandSYS_CLKControlregister(0x09)to1. 2. SetbitB6oftheISOControlregister(0x01)to0fordirectmode0(defaultits0) 3. SetbitB6oftheChipStatusControlregister(0x00)to1toenterdirectmode(donotsendaStop conditionafterthiscommand) NOTE • Do not terminate last write with a Stop condition. For SPI, this means that Slave Select (I/O_4)continuestostaylow. • SendingaStopconditionterminatesthedirectmodeandclearsbitB6intheChipStatus Controlregister(0x00). NOTE Accesstoregisters,FIFO,andIRQisnotavailableduringdirectmode0. Remember that the reader enters direct mode 0 when bit 6 of the Chip Status Control register (0x00) is settoa1,anditstaysindirectmode0untilaStopconditionissentfromthemicrocontroller. 36 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 NOTE The write command should not be terminated with a Stop condition (for example, in SPI mode this is done by bringing the SS line high after the register write), because the Stop condition terminates the direct mode and clears bit 6 of the Chip Status Control register (0x00),makingita0. Figure6-21.EnteringDirectMode0 Step5:Transmitdatausingdirectmode TheusernowhasdirectcontrolovertheRFmodulationthroughtheMODinput. TRF796xA Microcontroller Drive the MOD pin MOD according to the data-coding (pin 14) specified by the standard Decode the subcarrier IO_6 information according (pin 23) to the standard Figure6-22.ControlofRFModulationUsingMOD The microcontroller is responsible for generating data according to the coding specified by the particular standard. The microcontroller must generate SOF, EOF, data, and CRC. In direct mode, the FIFO is not used and no IRQs are generated. See the applicable ISO standard to understand bit and frame definitions. Step6:Receivedatausingdirectmode After the TX operation is complete, the tag responds to the request and the subcarrier data is available on pin I/O_6. The microcontroller must decode the subcarrier signal according to the standard. This includes decoding the SOF, data bits, CRC, and EOF. The CRC then must be checked to verify data integrity. The receivedatabytesmustbebufferedlocally. Figure 6-23 shows an example of the receive data bits and framing level according to the ISO/IEC 14443 Astandard(sourcedfromtheISO/IEC14443specificationandTRF7963Aairinterface). Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 37 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com Figure6-23.ReceiveDataBitsandFramingLevel(ISO/IEC14443A) Step7:Exitdirectmode0 When an EOF is received, data transmission is over, and direct mode 0 can be terminated by sending a Stopcondition(theSSsignalgoeshigh).TheTRF7963AreturnstoISOMode(normalmode). 38 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.13 Direct Commands from MCU to Reader 6.13.1 Command Codes Table6-11liststhevalidcommandsthattheMCUcansendtothereader. Table6-11.CommandCodes COMMAND COMMAND COMMENTS CODE 0x00 Idle 0x03 SoftwareInitialization Sameaspower-onreset 0x0F ResetFIFO 0x10 TransmissionWithoutCRC 0x11 TransmissionWithCRC 0x16 BlockReceiver 0x17 EnableReceiver 0x18 TestInternalRF RSSIatRXinputwithTXoff 0x19 TestExternalRF RSSIatRXinputwithTXoff 0x1A ReceiverGainAdjust The command code values from Table 6-11 are substituted in Table 6-12, Bits 0 to 4. Also, the most significantbit(MSB)inTable6-12 mustbesetto1. Table6-12.Address/CommandWordBitDistribution BIT DESCRIPTION BITFUNCTION ADDRESS COMMAND 0=Address B7 Commandcontrolbit 0 1 1=Command 0=Write B6 Read/Write R/W 0 1=Read Continuous B5 Continuousaddressmode Notused mode B4 Address/Commandbit4 Adr4 Cmd4 B3 Address/Commandbit3 Adr3 Cmd3 B2 Address/Commandbit2 Adr2 Cmd2 B1 Address/Commandbit1 Adr1 Cmd1 B0 Address/Commandbit0 Adr0 Cmd0 The MSB determines if the word is to be used as a command or address. The last two columns of Table 6-12 show the function of separate bits depending on whether address or command is written. Command mode is used to enter a command resulting in reader action (for example, initialize transmission,enablereader,orturnthereaderonoroff). 6.13.2 Reset FIFO (0x0F) The reset command clears the FIFO contents and FIFO Status register (0x1C). It also clears the register storingthecollisionerrorlocation(0x0E). 6.13.3 Transmission With CRC (0x11) The transmission command must be sent first, followed by transmission length bytes, and FIFO data. The reader starts transmitting after the first byte is loaded into the FIFO. The CRC byte is included in the transmittedsequence. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 39 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.13.4 Transmission Without CRC (0x10) The transmission command must be sent first, followed by transmission length bytes, and FIFO data. The reader starts transmitting after the first byte is loaded into the FIFO. This is the same as described in Section6.13.3,exceptthattheCRCisnotincluded. 6.13.5 Block Receiver (0x16) The block receiver command puts the digital part of receiver (bit decoder and framer) in reset mode. This is useful in an extremely noisy environment, where the noise level could otherwise cause a constant switching of the subcarrier input of the digital part of the receiver. The receiver (if not in reset) would try to catch a SOF signal, and if the noise pattern matched the SOF pattern, an interrupt would be generated, falsely signaling the start of an receive operation. A constant flow of interrupt requests can be a problem for the external system (MCU), so the external system can stop this by putting the receive decoders in resetmode. Theresetmodecanbeterminatedintwoways: Theexternalsystemcansendtheenablereceivercommand(seeSection6.13.6). Theresetmodeisautomaticallyterminatedattheendofatransmitoperation. The receiver can stay in reset after end of transmit if the RX Wait Time register (0x08) is set. In this case, thereceiverisenabledattheendofthewaittimefollowingthetransmitoperation. 6.13.6 Enable Receiver (0x17) This command clears the reset mode in the digital part of the receiver if the reset mode was entered by theblockreceivercommand. 6.13.7 Test Internal RF (RSSI at RX Input With TX On) (0x18) The level of the RF carrier at RF_IN1 and RF_IN2 inputs is measured. THe operating range is 300 mV to P 2.1 V (the step size is 300 mV). The two values are reported in the RSSI Levels register (0x0F). The P command is intended for diagnostic purposes to set correct RF_IN levels. Optimum RFIN input level is approximately 1.6 V or code 5 to 6. The nominal relationship between the RF peak level and RSSI code P isdescribedinTable6-13andinSection6.7.1.1. NOTE If the command is executed immediately after power-up and before any communication with tag was performed, the command must be preceded by the Enable RX command. The Check RF commands require full operation, so the receiver must be activated by enable receiveorbyanormaltagcommunicationfortheCheckRFcommandtoworkproperly. Table6-13.TestInternalRF RF_IN1(mV ): 300 600 900 1200 1500 1800 2100 P DecimalCode: 1 2 3 4 5 6 7 BinaryCode: 001 010 011 001 101 011 111 40 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.13.8 Test External RF (RSSI at RX Input With TX Off) (0x19) This command can be used in active mode when the RF receiver is on but RF output is off. This means bit B1 = 1 in the Chip Status Control register. The level of RF signal received on the antenna is measured and reported in the RSSI Levels register (0x0F). The relation between the 3-bit code and the external RF field strength [A/m] must be determinate by calculation or by experiments for each antenna type, because the antenna Q and connection to the RF input influence the result. Table 6-14 and Section 6.7.1.2 describe the nominal relation between the RF peak-to-peak voltage in the RF_IN1 input and RSSI code, respectively. NOTE If the command is executed immediately after power-up and before any communication with tag was performed, the command must be preceded by the Enable RX command. The Check RF commands require full operation, so the receiver must be activated by enable RX orbyanormaltagcommunicationfortheCheckRFcommandtoworkproperly. Table6-14.TestExternalRF RF_IN1(mV ): 40 60 80 100 140 180 300 P DecimalCode: 1 2 3 4 5 6 7 BinaryCode: 001 010 011 001 101 011 111 6.13.9 Register Preset After power-up and the EN pin low-to-high transition, the registers are in a default mode, which must be changed by writing the desired ISO protocol settings to the ISO Control register. The low-level option registers (0x02 to 0x0B) are automatically configured to the new protocol parameters. After selecting the protocol, it is possible to change some low-level register contents if needed. However, changing to another protocol and then back reloads the default settings; therefore, the custom settings must be reloaded. The Clo0 and Clo1 bits in the Modulator and SYS_CLK Control register (0x09), which define the microcontroller frequency available on the SYS_CLK pin, are the only 2 bits in the configuration registers thatarenotclearedduringprotocolselection. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14 Register Description 6.14.1 Register Overview Table 6-15 lists the registers available in the TRF7963A. These registers are described in the following sections. Table6-15.RegisterOverview ADDRESS REGISTER READ/WRITE SECTION (hex) MainControlRegisters 0x00 ChipStatusControl R/W Section6.14.1.1.1 0x01 ISOControl R/W Section6.14.1.1.2 ProtocolSubsettingRegisters 0x02 ISO14443BTXOptions R/W Section6.14.1.2.1 0x03 ISO14443AHigh-Bit-RateOptions R/W Section6.14.1.2.2 0x06 TXPulse-LengthControl R/W Section6.14.1.2.3 0x07 RXNoResponseWait R/W Section6.14.1.2.4 0x08 RXWaitTime R/W Section6.14.1.2.5 0x09 ModulatorandSYS_CLKControl R/W Section6.14.1.2.6 0x0A RXSpecialSetting R/W Section6.14.1.2.7 0x0B RegulatorandI/OControl R/W Section6.14.1.2.8 StatusRegisters 0x0C IRQStatus R Section6.14.1.3.1 0x0D CollisionPositionandInterruptMaskRegister R/W Section6.14.1.3.2 0x0E CollisionPosition R Section6.14.1.3.2 0x0F RSSILevelsandOscillatorStatus R Section6.14.1.3.3 FIFORegisters 0x1A Test R/W Section6.14.1.4.1 0x1B Test R/W Section6.14.1.4.2 0x1C FIFOStatus R Section6.14.1.5.1 0x1D TXLengthByte1 R/W Section6.14.1.5.2 0x1E TXLengthByte2 R/W Section6.14.1.5.2 0x1F FIFOI/ORegister R/W 42 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.14.1.1 MainConfigurationRegisters 6.14.1.1.1 ChipStatusControlRegister(0x00) Table 6-16 describes the bit fields of the Chip Status Control register. This register controls the power mode,RFonoroff,AMorPM,anddirectmode. DefaultValue: 0x01,setatEN=LorPOR=H Table6-16.ChipStatusControlRegister(0x00) BITNO. BITNAME FUNCTION DESCRIPTION Standbymodekeepsallsupplyregulatorsandthe13.56-MHzSYS_CLK 1=Standbymode B7 stby oscillatorrunning(typicalstart-uptimetofulloperationis100µs). 0=Activemode Activemode(default) ProvidesuserdirectaccesstoAFE(directmode0)orletstheuseradd 1=Directmode0or1 customframing(directmode1).Bit6oftheISOControlregistermustbeset B6 direct beforeenteringdirectmode0or1. UsesSPIorparallelcommunicationwithautomaticframingandISO 0=ISOmode(default) decoders 1=RFoutputactive Transmitteron,receiverson B5 rf_on 0=RFoutputnotactive Transmitteroff TX_OUT(pin5)=8-Ωoutputimpedance 1=Halfoutputpower P=100mW(+20dBm)at5V,P=33mW(+15dBm)at3.3V B4 rf_pwr TX_OUT(pin5)=4-Ωoutputimpedance 0=Fulloutputpower P=200mW(+23dBm)at5V,P=70mW(+18dBm)at3.3V 1=SelectsauxRXinput RX_IN2inputisused B3 pm_on 0=SelectsmainRX RX_IN1inputisused input B2 Reserved 1=Receiveractivated ForcesenablingofreceiverandTXoscillator.Usedforexternalfield forexternalfield B1 rec_on measurement measurement. 0=Automaticenable Allowsenableofthereceiverbybit5ofthisregister 1=5-Voperation B0 vrs5_3 SelectstheVINvoltagerange 0=3-Voperation Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.1.2 ISOControlRegister(0x01) Table 6-17 describes the bit fields of the ISO Control register. This register controls the selection of ISO standardprotocol,directmode,andreceiveCRC. DefaultValue: 0x02,resetatEN=LorPOR=H Table6-17.ISOControlRegister(0x01) BITNO. BITNAME FUNCTION DESCRIPTION 1=NoRXCRC(CRCnotpresentintheresponse) B7 rx_crc_n CRCreceiveselection 0=RXCRC(CRCispresentintheresponse) Directmodetype 0=Directmode0 B6 dir_mode selection 1=Directmode1 0=RFIDmode B5 rfid RFIDmode 1=Reserved(shouldbesetto0) B4 iso_4 RFID B3 iso_3 RFID SeeTable6-18forB0:B4settingsbasedontheISOprotocolthatthe B2 iso_2 RFID applicationrequires. B1 iso_1 RFID B0 iso_0 RFID Table6-18.ISOControlRegister:ISO_4toISO_0 iso_4 iso_3 iso_2 iso_1 iso_0 PROTOCOL REMARKS 0 1 0 0 0 ISO/IEC14443ARXbitrate,106kbps 0 1 0 0 1 ISO/IEC14443ARXhighbitrate,212kbps RXbitrate(1) 0 1 0 1 0 ISO/IEC14443ARXhighbitrate,424kbps 0 1 0 1 1 ISO/IEC14443ARXhighbitrate,848kbps 0 1 1 0 0 ISO/IEC14443BRXbitrate,106kbps 0 1 1 0 1 ISO/IEC14443BRXhighbitrate,212kbps RXbitrate(1) 0 1 1 1 0 ISO/IEC14443BRXhighbitrate,424kbps 0 1 1 1 1 ISO/IEC14443BRXhighbitrate,848kbps 1 1 0 1 0 FeliCa212kbps 1 1 0 1 1 FeliCa424kbps (1) ForISO/IEC14443AorB,whenbitrateofTXisdifferentfromRX,settingscanbemadeinregister0x02or0x03. 44 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.14.1.2 ProtocolSubsettingRegisters 6.14.1.2.1 ISO14443BTXOptionsRegister(0x02) Table 6-19 describes the bit fields of the ISO14443B TX Options register. This register selects the ISO subsetsforISO/IEC14443Btransmit. DefaultValue: 0x00,setatPOR=HorEN=L Table6-19.ISO14443BTXOptionsRegister(0x02) BITNO. BITNAME FUNCTION DESCRIPTION B7 egt2 TXEGTtimeselect.B7isthe This3-bitcodedefinesthenumberofetu(0to7)thatseparatetwo B6 egt1 MSB. characters.ISO/IEC14443BTXonly. B5 egt0 1=EOF→0length11etu B4 eof_l0 0=EOF→0length10etu 1=SOF→1length03etu B3 sof_l1 0=SOF→1length02etu ISO/IEC14443BTXonly 1=SOF→0length11etu B2 sof_l0 0=SOF→0length10etu 1=EGTaftereachbyte B1 l_egt 0=EGTafterlastbyteisomitted B0 Unused 6.14.1.2.2 ISO14443AHigh-Bit-RateandParityOptionsRegister(0x03) Table 6-20 describes the bit fields of the ISO14443A High-Bit-Rate and Parity Options register. This registerltheISOsubsetsforISO/IEC14443Atransmit. DefaultValue: 0x00,setatPOR=HorEN=LandateachwritetoISOControlregister Table6-20.ISO14443AHigh-Bit-RateandParityOptionsRegister(0x03) BITNO. BITNAME FUNCTION DESCRIPTION TXbitratedifferentfromRXbit B7 dif_tx_br ValidforISO/IEC14443AorBhighbitrate rateenable B6 tx_br1 tx_br1=0,tx_br=0:106kbps tx_br1=0,tx_br=1:212kbps TXbitrate B5 tx_br0 tx_br1=1,tx_br=0:424kbps tx_br1=1,tx_br=1:848kbps 1=Parityoddexceptlastbyte, B4 parity-2tx whichisevenforTX ForISO/IEC14443Ahigh-bit-ratecodinganddecoding 1=Parityoddexceptlastbyte, B3 parity-2rx whichisevenforRX B2 Unused B1 Unused B0 Unused Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.2.3 TXPulseLengthControlRegister(0x06) Table6-21describesthebitfieldsoftheTXPulseLengthControlregister.Thisregistercontrolsthelength ofTXpulse. DefaultValue: 0x00,setatPOR=HorEN=LandateachwritetoISOControlregister The length of the modulation pulse is defined by the protocol selected in the ISO Control register (0x01). With a high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length can be corrected by using the TX pulse length register 0x06. If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 0x00, the pulse length is equal to the value of the register in 73.7-nsincrements.Thismeanstherangeofadjustmentcanbe73.7nsto18.8 µs. Table6-21.TXPulseLengthControlRegister(0x06) BITNO. BITNAME FUNCTION DESCRIPTION B7 Pul_p2 B6 Pul_p1 Thepulserangeis73.7nsto18.8µs(1to255),stepsize73.7ns B5 Pul_p0 Allbitslow(00)=Pulselengthcontrolisdisabled B4 Pul_c4 Pulselength.B7isthe ThefollowingdefaulttimingsarepresetbytheISOControlregister(0x01): B3 Pul_c3 MSB. 2.36µsforISO/IEC14443Aat106kbps B2 Pul_c2 1.4µsforISO/IEC14443Aat212kbps 737nsforISO/IEC14443Aat424kbps B1 Pul_c1 442nsforISO/IEC14443Aat848kbps;pulselengthcontroldisabled B0 Pul_c0 6.14.1.2.4 RXNoResponseWaitTimeRegister(0x07) Table 6-22 describes the bit fields of the RX No Response Wait Time register. This register defines the timewhennoresponseinterruptissent. DefaultValue: 0x0E,setatPOR=HorEN=LandateachwritetoISOControlregister The RX no response timer is controlled by the RX No Response Wait Time register. This timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ Status Control register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically, for every newprotocolselection. Table6-22.RXNoResponseWaitTimeRegister(0x07) BITNO. BITNAME FUNCTION DESCRIPTION B7 NoResp7 B6 NoResp6 B5 NoResp5 Definesthetimewhenthenoresponseinterrupt is sent. Timingstartsfrom B4 NoResp4 Noresponse.B7isthe theendofTXEOF.RXnoresponsewaitrangeis37.76µsto9628µs(1to 255).Stepsizeis37.76µs. B3 NoResp3 MSB. ThefollowingdefaulttimingsarepresetbytheISOControlregister(0x01): B2 NoResp2 529µsforforallprotocols B1 NoResp1 B0 NoResp0 46 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.14.1.2.5 RXWaitTimeRegister(0x08) Table 6-23 describes the bit fields of the RX Wait Time register. This register defines the time after TX EOF when the RX input is disregarded; for example, to block out electromagnetic disturbance generated bytherespondingcard. DefaultValue: 0x1F,setatPOR=HorEN=LandateachwritetotheISOControlregister The RX wait time timer is controlled by the value in the RX Wait Time register. This timer defines the time after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents incorrect detections resulting from transients following the transmit operation. The value of the RX wait time register defines this time in increments of 9.44 µs. This register is preset at every write to ISOControlregisteraccordingtotheminimumtagresponsetimedefinedbyeachstandard. Table6-23.RXWaitTimeRegister(0x08) BITNO. BITNAME FUNCTION DESCRIPTION B7 Rxw7 B6 Rxw6 Defines the time after the TX EOF during which the RX input is ignored. B5 Rxw5 TimestartsfromtheendofTXEOF. B4 Rxw4 RXwaittime.B7isthe RXwaitrangeis9.44µsto2407µs(1to255).Stepsizeis:9.44µs. B3 Rxw3 MSB. ThefollowingdefaulttimingsarepresetbytheISOControlregister(0x01): B2 Rxw2 9.44µsforFeliCa B1 Rxw1 66µsforISO/IEC14443AandB B1 Rxw0 Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.2.6 ModulatorandSYS_CLKControlRegister(0x09) Table 6-24 describes the bit fields of the Modulator and SYS_CLK Control register. This register controls themodulationinputanddepth,ASK/OOKpincontrol,andclockoutputtoanexternalsystem(anMCU). Default Value: 0x11, set at POR = H or EN = L at each write to the ISO Control register for all bits except Clo1andClo0 The frequency of SYS_CLK (pin 27) is programmable by bits B4 and B5 of this register. The frequency of the TRF7963A system clock oscillator is divided by 1, 2, or 4 resulting in available SYS_CLK frequencies of13.56MHz,6.78MHz,or3.39MHz,respectively. The ASK modulation depth is controlled by bits B0, B1, and B2. The range of ASK modulation is 7% to 30% or 100% (OOK). The selection between ASK and OOK (100%) modulation can also be done using direct input OOK (pin 12). The direct control of OOK or ASK using the OOK pin is only possible if the functionis enabled by setting B6 = 1 (en_ook_p) in this register (0x09) and the ISO Control register (0x01, B6=1).Whenconfiguredthisway,theMODpin(pin14)isusedasinputforthemodulationsignal. Table6-24.ModulatorandSYS_CLKControlRegister(0x09) BITNO. BITNAME FUNCTION DESCRIPTION B7 Unused EnableASK/OOKpin(pin12)forchangebetweenanypreselected 1 =Enables external selection of ASKmodulationasdefinedbyB0toB2andOOKmodulation. ASKorOOKmodulation B6 en_ook_p IfB6issetto1,pin12isconfiguredas: 0 = Default operation as defined 1=OOKmodulation inbitsB0toB2ofthisregister 0=ModulationasdefinedinB0toB2(0x09) Clo1 Clo0 SYS_CLKOutput B5 Clo1 0 0 Disabled SYS_CLKoutputfrequency.B5 0 1 3.39MHz istheMSB. 1 0 6.78MHz B4 Clo0 1 1 13.56MHz 1 = Sets pin 12 (ASK/OOK) as Fortestandmeasurementpurpose.ASK/OOKpin12canbeused B3 en_ana ananalogoutput tomonitortheanalogsubcarriersignalbeforethedigitizingwithDC levelequaltoAGND. 0=Default Pm2 Pm1 Pm0 ModulationTypeandPercentage B2 Pm2 0 0 0 ASK10% 0 0 1 OOK(100%) 0 1 0 ASK7% B1 Pm1 Modulationdepth.B2istheMSB. 0 1 1 ASK8.5% 1 0 0 ASK13% 1 0 1 ASK16% B0 Pm0 1 1 0 ASK22% 1 1 1 ASK30% 48 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.14.1.2.7 RXSpecialSettingRegister(0x0A) Table 6-25 describes the bit fields of the RX Special Setting register. This register sets the gains and filters directly. When bits B7, B6, B5, and B4 are all zero, the filters are set for ISO/IEC 14443B (240 kHz to1.4MHz). DefaultValue: 0x40,setatPOR=HorEN=LandateachwritetotheISOControlregister(0x01) Table6-25.RXSpecialSettingRegister(0x0A) BITNO. BITNAME FUNCTION DESCRIPTION B7 C212 Band-pass110kHzto570kHz Appropriatefor212-kHzsubcarriersystem(FeliCa) B6 C424 Band-pass200kHzto900kHz AppropriateforManchester-coded848-kHzsubcarrierusedin B5 M848 Band-pass450kHzto1.5MHz ISO/IEC14443A Band-pass100kHzto1.5MHz Appropriateforhighestbitrate(848kbps)usedinhigh-bit-rate B4 hbt Gainreducedfor18dB ISO/IEC14443 B3 gd1 00=Gainreduction0dB 01=Gainreductionfor5dB SetstheRXgainreductionandreducessensitivity B2 gd2 10=Gainreductionfor10dB 11=Gainreductionfor15dB B1 Reserved B0 Reserved NOTE ThesettingofbitsB4,B5,B6,andB7tozeroselectsband-passcharacteristicof240kHz to 1.4 MHz. This is appropriate for ISO/IEC 14443 B, FeliCa protocol, and ISO/IEC 14443 A higherbitrates(212kbpsand424kbps). Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.2.8 RegulatorandI/OControlRegister(0x0B) Table 6-26 describes the bit fields of the Regulator and I/O Control register. This register controls the threevoltageregulators. DefaultValue: 0x87,setatPOR=HorEN=L Table6-26.RegulatorandI/OControlRegister(0x0B) BITNO. BITNAME FUNCTION DESCRIPTION Automaticsystemsettings: VDD_RF=VIN–250mV 0=Manualsystem VDD_A=VIN–250mV B7 auto_reg 1=Automaticsystem VDD_X=VIN–250mV,butnothigherthan3.4V Manualsystemsettings: SeeB2toB0 Internalpeakdetectorsaredisabled,receiverinputs(RX_IN1and Supportforexternalpower RX_IN2)acceptexternallydemodulatedsubcarrier.Atthesame B6 en_ext_pa amplifier time,theASK/OOKpinbecomesmodulationoutputforexternalTX amplifier. WhenB5=1,maintainstheoutputdrivingcapabilitiesoftheI/O 1=Enablelowperipheral B5 io_low pinsconnectedtothelevelshifterunderlow-voltageoperation. communicationvoltage Shouldbeset1whenVDD_I/Ovoltageis1.8Vto2.7V. B4 Unused Nofunction Defaultis0. B3 Unused Nofunction Defaultis0. B2 vrs2 vrs3_5=L: B1 vrs1 Voltageset.B2istheMSB. VDD_RF,VDD_A,VDD_Xrangeis2.7Vto3.4V. B0 vrs0 SeeTable6-27,Table6-28,Table6-29,andTable6-30. Table6-27.SupplyRegulatorSetting,Manual5-VSystem OPTIONBITSSETTINGINCONTROLREGISTER REGISTER ACTION B7 B6 B5 B4 B3 B2 B1 B0 00 1 5-Vsystem 0B 0 Manualregulatorsetting 0B 0 1 1 1 VDD_RF=5V,VDD_A=3.5V,VDD_X=3.4V 0B 0 1 1 0 VDD_RF=4.9V,VDD_A=3.5V,VDD_X=3.4V 0B 0 1 0 1 VDD_RF=4.8V,VDD_A=3.5V,VDD_X=3.4V 0B 0 1 0 0 VDD_RF=4.7V,VDD_A=3.5V,VDD_X=3.4V 0B 0 0 1 1 VDD_RF=4.6V,VDD_A=3.5V,VDD_X=3.4V 0B 0 0 1 0 VDD_RF=4.5V,VDD_A=3.5V,VDD_X=3.4V 0B 0 0 0 1 VDD_RF=4.4V,VDD_A=3.5V,VDD_X=3.4V 0B 0 0 0 0 VDD_RF=4.3V,VDD_A=3.5V,VDD_X=3.4V 50 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Table6-28.SupplyRegulatorSetting,Manual3-VSystem OPTIONBITSSETTINGINCONTROLREGISTER REGISTER ACTION B7 B6 B5 B4 B3 B2 B1 B0 00 0 3-Vsystem 0B 0 Manualregulatorsetting 0B 0 1 1 1 VDD_RF=3.4V,VDD_A=3.4V,VDD_X=3.4V 0B 0 1 1 0 VDD_RF=3.3V,VDD_A=3.3V,VDD_X=3.3V 0B 0 1 0 1 VDD_RF=3.2V,VDD_A=3.2V,VDD_X=3.2V 0B 0 1 0 0 VDD_RF=3.1V,VDD_A=3.1V,VDD_X=3.1V 0B 0 0 1 1 VDD_RF=3.0V,VDD_A=3.0V,VDD_X=3.0V 0B 0 0 1 0 VDD_RF=2.9V,VDD_A=2.9V,VDD_X=2.9V 0B 0 0 0 1 VDD_RF=2.8V,VDD_A=2.8V,VDD_X=2.8V 0B 0 0 0 0 VDD_RF=2.7V,VDD_A=2.7V,VDD_X=2.7V Table6-29.SupplyRegulatorSetting,Automatic5-VSystem OPTIONBITSSETTINGINCONTROLREGISTER REGISTER ACTION B7 B6 B5 B4 B3 B2 (1) B1 B0 00 1 5-Vsystem 0B 1 x 1 1 Automaticregulatorsettingwith250-mVdifference 0B 1 x 1 0 Automaticregulatorsettingwith350-mVdifference 0B 1 x 0 0 Automaticregulatorsettingwith400-mVdifference (1) x=don'tcare Table6-30.SupplyRegulatorSetting,Automatic3-VSystem OPTIONBITSSETTINGINCONTROLREGISTER REGISTER ACTION B7 B6 B5 B4 B3 B2 (1) B1 B0 00 0 3-Vsystem 0B 1 x 1 1 Automaticregulatorsettingwith250-mVdifference 0B 1 x 1 0 Automaticregulatorsettingwith350-mVdifference 0B 1 x 0 0 Automaticregulatorsettingwith400-mVdifference (1) x=don'tcare Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.3 StatusRegisters 6.14.1.3.1 IRQStatusRegister(0x0C) Table 6-31 describes the bit fields of the IRQ Status register. This register provides information available aboutTRF7963AIRQ,TX,andRXstatus. Default Value: 0x00, set at POR = H or EN = L and at each write to the ISO Control register (0x01). The registerisalsoautomaticallyresetattheendofareadphase.TheresetalsoremovestheIRQflag. To reset (clear) the register and the IRQ line, the register must be read. During transmit, the decoder is disabled, and only bits B5 and B7 can be changed. During receive, only bit B6 can be changed, but does nottriggertheIRQlineimmediately.TheIRQsignalissetattheendofthetransmitorreceivephase. Table6-31.IRQStatusRegister(0x0C) BITNO. BITNAME FUNCTION DESCRIPTION SignalsthatTXisinprogress.TheflagissetatthestartofTXbut B7 Irq_tx IRQsetduetoendofTX theinterruptrequest(IRQ=1)issentwhenTXisfinished. SignalsthatRXSOFwasreceivedandRXisinprogress.Theflag B6 Irg_srx IRQsetduetoRXstart issetatthestartofRXbuttheinterruptrequest(IRQ=1)issent whenRXisfinished. SignalswhentheFIFOishighorlow(morethan8bitsduringRXor B5 Irq_fifo FIFOishighorlow lessthan4bitsduringTX).SeeSection6.12.2fordetails. IndicatesreceiveCRCerroronlyifB7(noRXCRC)ofISOControl B4 Irq_err1 CRCerror registerissetto0. B3 Irq_err2 Parityerror IndicatesparityerrorforISO/IEC14443A B2 Irq_err3 ByteframingorEOFerror Indicatesframingerror Collision error for ISO/IEC 14443 A . Bit is set if more then 6 or 7 (as defined in register 0x01) are detected inside 1 bit period of B1 Irq_col Collisionerror ISO/IEC14443A106kbps. Collisionerrorbitcanalsobetriggeredbyexternalnoise. Noresponsewithinthe"No-responsetime"definedinRXNo- B0 Irq_noresp No-responsetimeinterrupt responseWaitTimeregister(0x07). 52 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.14.1.3.2 CollisionPositionandInterruptMaskRegisters(0x0Dand0x0E) Table6-32describesthebitfieldsoftheCollisionPositionandInterruptMaskregister. DefaultValue: 0x3E,setatPOR=HandEN=L.Collisionbitsresetautomaticallyafterreadoperation. Table6-32.CollisionPositionandInterruptMaskRegister(0x0D) BITNO. BITNAME FUNCTION DESCRIPTION B7 Col9 BitpositionofcollisionMSB SupportsISO/IEC14443A B6 Col8 Bitpositionofcollision B5 En_irq_fifo InterruptenableforFIFO Default=1 B4 En_irq_err1 InterruptenableforCRC Default=1 B3 En_irq_err2 InterruptenableforParity Default=1 InterruptenableforFraming B2 En_irq_err3 Default=1 errororEOF B1 En_irq_col Interruptenableforcollisionerror Default=1 B0 En_irq_noresp Enablesnoresponseinterrupt Default=0 Table6-33describesthebitfieldsoftheCollisionPositionregister.Thisregisterdisplaysthebitpositionof collisionorerror. DefaultValue: 0x00,setatPOR=HandEN=L.Theregisterisalsoautomaticallyresetafteraread. Table6-33.CollisionPositionRegister(0x0E) BITNO. BITNAME FUNCTION DESCRIPTION B7 Col7 B6 Col6 B5 Col5 B4 Col4 Bitpositionofcollision.B7isthe ISO/IEC14443Amainlysupported;intheotherprotocols,this registershowsthebitpositionoferror.Eitherframe,SOF/EOF, B3 Col3 MSB. parity,orCRCerror. B2 Col2 B1 Col1 B0 Col0 Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.3.3 RSSILevelsandOscillatorStatusRegister(0x0F) Table 6-34 describes the bit fields of the RSSI Levels and Oscillator Status register. This register reports the signal strength on both reception channels and RF amplitude during RF off conditions. The RSSI valuesarevalidfromreceptionstartuntilthestartofthenexttransmission. RSSI measurement block is measuring the demodulated envelope signal (except in case of direct command for RF amplitude measurement described later in direct commands section). The measuring system is latching the peak value, so the RSSI level can be read after the end of receive packet. The RSSI value is reset during next transmit action of the reader, so the new tag response level can be measured. Section 6.7.1.1 and Section 6.7.1.2 describe the RSSI levels calculated to RF_IN1 and RF_IN2. The RSSI has 7 steps (3 bits) with 4-dB increment. The input level is the peak to peak modulationlevelofRFsignalmeasuredononesideenvelope(positiveornegative). Table6-34.RSSILevelsandOscillatorStatusRegister(0x0F) BITNO. BITNAME FUNCTION DESCRIPTION B7 Unused B6 osc_ok Crystaloscillatorstableindicator 13.56-MHzfrequencystable(approximately200µs) MSBRSSIvalueofauxiliaryRX B5 rssi_x2 (RX_IN2) AuxiliarychannelisbydefaultRX_IN2.Theinputcanbeswapped byB3=1(ChipStateControlregister).If"swapped",theauxiliary B4 rssi_x1 AuxiliarychannelRSSI channelisconnectedtoRX_IN1andtheauxiliaryRSSIrepresents MSBRSSIvalueofauxiliaryRX thesignallevelatRX_IN1. B3 rssi_x0 (RX_IN2) MSBRSSIvalueofMainRX B2 rssi_2 (RX_IN1) ActivechannelisthedefaultandcanbesetwithoptionbitB3=0of B1 rssi_1 MainchannelRSSI theChipStatusControlregister(0x00). LSBRSSIvalueofMainRX B0 rssi_0 (RX_IN1) 54 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 6.14.1.4 TestRegisters 6.14.1.4.1 TestRegister(0x1A) Table6-35describesthebitfieldsoftheTestregisterat0x1A. DefaultValue: 0x00,setatPOR=HandEN=L Table6-35.TestRegister(0x1A)(forTestorDirectUse) BITNO. BITNAME FUNCTION DESCRIPTION B7 OOK_Subc_In Subcarrierinput OOKpinbecomesdecoderdigitalinput B6 MOD_Subc_Out Subcarrieroutput MODpinbecomesreceiversubcarrieroutput B5 MOD_Direct DirectTXmodulationandRXreset MODpinbecomesreceiversubcarrieroutput 0 = First stage output used for analog out and digitizing B4 o_sel Firststageoutputselection 1 = Second stage output used for analog out and digitizing B3 low2 Secondstagegain–6dB,HPcornerfrequency/2 B2 low1 Firststagegain–6dB,HPcornerfrequency/2 B1 zun Inputfollowerstest B0 Test_AGC AGCtest,AGClevelisseenonrssi_210bits 6.14.1.4.2 TestRegister(0x1B) Table 6-36 describes the bit fields of the Test register at 0x1B. When a test_dec or test_io is set, the IC is switched to test mode. Test mode persists until a stop condition arrives. At stop condition, the test_dec andtest_iobitsarecleared. DefaultValue: 0x00,setatPOR=HandEN=L Table6-36.TestRegister2(0x1B)(forTestorDirectUse) BITNO. BITNAME FUNCTION DESCRIPTION B7 test_rf_level RFleveltest B6 B5 B4 B3 test_io1 I/Otest Notimplemented B2 test_io0 B1 test_dec Decodertestmode B0 clock_su Coderclock13.56MHz Forfastertestofcoders Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 6.14.1.5 FIFOControlRegisters 6.14.1.5.1 FIFOStatusRegister(0x1C) Table 6-37 describes the bit fields of the FIFO Status register. This register contains the low nibbles of the completebytestobetransferredthroughthe FIFO and information about a broken byte and the number of bitstobetransferredfromit. Table6-37.FIFOStatusRegister(0x1C) BITNO. BITNAME FUNCTION DESCRIPTION B7 RFU B7=0 Reservedforfutureuse(RFU) Indicatesthat9bytesarealreadyintheFIFO(forRX)(alsosee B6 Fhil FIFOlevelhigh register0x0Cbit5) Indicatesthatonly3bytesareintheFIFO(forTX)(alsoseeregister B5 Flol FIFOlevellow 0x0Cbit5) B4 Fove FIFOoverflowerror ToomanybyteswerewrittentotheFIFO B3 Fb3 FIFObytesfb[3] B2 Fb2 FIFObytesfb[2] BitsB0:B3indicatehowmanybytesthatareloadedinFIFOwere notreadoutyet(displaysN–1numberofbytes).If8bytesarein B1 Fb1 FIFObytesfb[1] theFIFO,thisnumberis7(alsoseeregister0x0Cbit6). B0 Fb0 FIFObytesfb[0] 6.14.1.5.2 TXLengthByte1Register(0x1D)andTXLengthByte2Register(0x1E) Table 6-38 describes the bit fields of the TX Length Byte1 register. This register contains the high two nibblesofcompleteintendedbytestobetransferredthroughFIFO. DefaultValue: 0x00,setatPORandEN=0.TheregisterisalsoautomaticallyresetatTXEOF. Table6-38.TXLengthByte1Register(0x1D) BITNO. BITNAME FUNCTION DESCRIPTION B7 Txl11 Numberofcompletebytebn[11] B6 Txl10 Numberofcompletebytebn[10] Highnibbleofcompleteintendedbytestobetransmitted B5 Txl9 Numberofcompletebytebn[9] B4 Txl8 Numberofcompletebytebn[8] B3 Txl7 Numberofcompletebytebn[7] B2 Txl6 Numberofcompletebytebn[6] Middlenibbleofcompleteintendedbytestobetransmitted B1 Txl5 Numberofcompletebytebn[5] B0 Txl4 Numberofcompletebytebn[4] 56 DetailedDescription Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 Table 6-39 describes the bit fields of the TX Length Byte2 register. This register contains the low nibble of the complete bytes to be transferred through FIFO, and information about a broken byte and number of bitstobetransferredfromit. DefaultValue: 0x00,setatPORandEN=0.TheregisterisalsoautomaticallyresetatTXEOF. Table6-39.TXLengthByte2Register(0x1E) BITNO. BITNAME FUNCTION DESCRIPTION B7 Txl3 Numberofcompletebytebn[3] B6 Txl2 Numberofcompletebytebn[2] Lownibbleofcompleteintendedbytestobetransmitted B5 Txl1 Numberofcompletebytebn[1] B4 Txl0 Numberofcompletebytebn[0] B3 Bb2 Brokenbytenumberofbitsbb[2] Numberofbitsinthelastbrokenbytetobetransmitted. B2 Bb1 Brokenbytenumberofbitsbb[1] Thisvalueistakenintoaccountonlywhenbrokenbyteflagisset. B1 Bb0 Brokenbytenumberofbitsbb[0] B0 Bbf Brokenbyteflag B0=1indicatesthatlastbyteisnotcomplete8bitswide. Copyright©2011–2020,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 7 Applications, Implementation, and Layout NOTE InformationinthefollowingApplicationssectionisnotpartoftheTIcomponentspecification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test theirdesignimplementationtoconfirmsystemfunctionality. 7.1 TRF7963A Reader System Using SPI With SS Mode 7.1.1 General Application Considerations Figure 7-1 shows the TRF7963A application schematic using the serial port interface (SPI). Short SPI lines, proper isolation to radio frequency lines, and a proper ground area are essential to avoid interference.TherecommendedclockfrequencyontheDATA_CLKlineis2MHz. This schematic shows matching to a 50-Ω port, which allows connection to a properly matched 50-Ω antennacircuitorRFmeasurementequipment(forexample,aspectrumanalyzerorpowermeter). 7.1.2 Schematic Figure7-1showsasampleapplicationschematicwithaserialinterfacetotheMCU. Figure7-1.ApplicationSchematic,SPIWithSSModeMCUInterface Minimum MCU requirements depend on application requirements and coding style. If only one ISO protocoloralimitedcommandsetofaprotocolmustbesupported,MCUflashandRAMrequirementscan be significantly reduced. Recursive inventory and anticollision commands require more RAM than single slotted operations. For example, an application for ISO/IEC 15693 only that supports anticollision needs approximately 7KB of flash memory and 500 bytes of RAM. In contrast, a full NFC reader/writer application with NDEF message support needs approximately 45KB of flash memory and 3KB of RAM. An MCUthatcanrunitsGPIOsat13.56MHzisrequiredfordirectmode0operations. 58 Applications,Implementation,andLayout Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 7.2 System Design 7.2.1 Layout Considerations Keep all decoupling capacitors as close to the IC as possible, with the high-frequency decoupling capacitors(10nF)closerthanthelow-frequencydecouplingcapacitors(2.2 µF). Placegroundviasascloseaspossibletothegroundsideofthe capacitors and reader IC pins to minimize anypossiblegroundloops. It is not recommend using any inductor sizes below 0603 as the output power can be compromised. If smallersizedinductorsareabsolutelynecessary,thedesignermustconfirmoutputperformance. Pay close attention to the required load capacitance of the used crystal and adjust the two external shunt capacitorsaccordingly.Followtherecommendationsofthecrystalmanufacturerforthosevalues. There should be a common ground plane for the digital and analog sections. The multiple ground sections or"islands"shouldhaveviasthattiethedifferentsectionsoftheplanestogether. Ensurethattheexposedthermalpadatthecenter of the IC is properly laid out. It should be tied to ground tohelpdissipateheatfromthepackage. Trace line lengths should be minimized whenever possible, particularly the RF output path, crystal connections, and control lines from the reader to the microprocessor. Proper placement of the TRF7963A, microprocessor,crystal,andRFconnection/connectorhelpfacilitatethis. Avoid crossing of digital lines under RF signal lines. Also, avoid crossing of digital lines with other digital lines whenever possible. If the crossings are unavoidable, 90° crossings should be used to minimize couplingofthelines. Depending on the production test plan, the designer should consider possible implementations of test padsortestviasfor use during testing. The necessary pads and vias should be placed in accordance with theproposedtestplantohelpenableeasyaccesstothosetestpoints. If the system implementation is complex (for example, if the RFID reader module is a subsystem of a larger system with other modules such as Bluetooth®, Wi-Fi®, microprocessors, and clocks), special considerations should be taken to ensure that there is no noise coupling into the supply lines. If needed, special filtering or regulator considerations should be used to minimize or eliminate noise in these systems. For more information and details on layout considerations, see the TRF796x HF-RFID Reader Layout DesignGuide. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω Theoutputimpedanceof the TRF7963A when operated at full power out setting is nominally 4 + j0 Ω (4 Ω real). This impedance must be matched to a resonant circuit, and TI recommends a matching circuit from 4 Ω to 50 Ω, as commercially available test equipment (for example, spectrum analyzers, power meters, and network analyzers) are 50-Ω systems. See Figure 7-2 and Figure 7-3 for an impedance match referencecircuit.Thissectionexplainshowthevalueswerecalculated. Starting with the 4-Ω source, Figure 7-2 and Figure 7-3 shows the process of going from 4 Ω to 50 Ω by showing it represented on a Smith Chart simulator (available from http://www.fritz.dellsperger.net/). The elementsaregroupedtogetherwhereappropriate. Copyright©2011–2020,TexasInstrumentsIncorporated Applications,Implementation,andLayout 59 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com TX_OUT L1 L2 Pin 5 Z L C2 and C3 Combination Z IN (4.00 + j0 3.0 nF 150.0 nH 1.2 nF 330.0 nH 256.0 pF 50W .0 0 ) W C4, C5, and C7 a t 1 Combination C8, C9, C10, and C11 3.6 Combination M H z Figure7-2.ImpedanceMatchingCircuit ThisyieldsthefollowingSmithChartsimulation. Figure7-3.ImpedanceMatchingSmithChart Resulting power out can be measured with a power meter, spectrum analyzer with power meter function, or other equipment capable of making a "hot" measurement. Take care to observe maximum power input levels on test equipment and use attenuators whenever available to avoid any possibility of damage to expensiveequipment.Table6-3liststheexpectedoutputpowerlevelsundervariousoperatingconditions. 7.2.3 Reader Antenna Design Guidelines ForHFantennadesignconsiderationsusingtheTRF7963A,seethefollowingdocumentation: AntennaMatchingfortheTRF7960RFIDReader TRF7960TBHFRFIDReaderModuleUser'sGuide,withantennadetailsatendofmanual 60 Applications,Implementation,andLayout Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 8 Device and Documentation Support 8.1 Getting Started and Next Steps For more information on the TI NFC/RFID devices and the tools and software that are available to help withyourdevelopment,visitOverviewforNFC/RFID. 8.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of devices. Each commercial family member has one of three prefixes: x, p, or no prefix. These prefixes represent evolutionary stages of product development from engineering prototypes (with prefix x) through fullyqualifiedproductiondevices(withnoprefix). Devicedevelopmentevolutionaryflow: xTRF... – Experimental device that is not necessarily representative of the electrical specifications of the finaldevice pTRF... – Final device that conforms to the electrical specifications of the final product but has not completedqualityandreliabilityverification TRF...–Fullyqualifiedproductiondevice Deviceswithaprefixofxorpareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Production devices have been characterized fully, and the quality and reliability of the device have been demonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failureratestillisundefined.Onlyqualifiedproductiondevicesaretobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type and, optionally, the temperature range. Figure 8-1 provides a legend for reading the completedevicename. TRF79 60 A RHB R Device Family Distribution Feature Set Package Revision Device Family TRF79 = NFC/RFIDTransceiver Feature Set 60 = Feature set Revision A= Silicon revision SeePackaging Information Package or www.ti.com/package Distribution R = Large reel T= Small reel Figure8-1.DeviceNomenclature Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 61 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 8.3 Tools and Software Software TRF7960ACCodeSamples Samplesourcecodefordirectregistercontrolofthedevicefunctions. 8.4 Documentation Support The following documents describe the TRF7963A device. Copies of these documents are available on the Internetatwww.ti.com. ReceivingNotificationofDocumentUpdates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for example, TRF7963A). In the upper-right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details,checktherevisionhistoryofanyreviseddocument. ApplicationNotes TRF79xxAHF-RFIDReaderLayoutDesignGuide Describes some suggested guidelines for use in the layingouttheTRF79xxAfamilyofHFRFIDreaders. AntennaMatchingfortheTRF7960RFIDReader Describes the design method for determining an antennamatchingcircuit. TRF7960AFirmwareDesignHintsA reference for the firmware developer using the TRF7960A in conjunctionwithmicrocontroller(forexample,anMSP430™orARM™device). ManagementoftheTRF7960andTRF7960AStart-upSequence System developers concerned about minimizing the current draw of TRF7960, TRF7960A, and their variants systems at start-up time need guidance about handling the Regulator Control register (0x0B) value. Valid application use case for this guidance is battery-powered RFID applications in which controllingtheentiresystemcurrentdrawovertimeisoftheutmostconcern. TRF7960ARFIDMultiplexerExampleSystem This application report describes the 16-channel high- frequency (HF) (13.56 MHz) RFID reader system (based on the TRF7960A IC) designed by TI for customer use. The system firmware resides on an MSP430F2370 MCU and supports theISO/IEC15693protocolinadditiontocommunicationwithahost. TRF7960AReferenceFirmwareDescription This application report describes the firmware implemented in the MSP430F2370 for use with the TI TRF7960A evaluation module (EVM). The TRF7960AEVM is a multiple-standard fully integrated 13.56-MHz RFID analog front end anddataframingreadersystem.This document is designed for readers who may or may not be experienced with firmware development for RFID and want to understand the reference firmwareanddeveloptheirownfirmwarefortheTRF7960A. ComparisonofTRF7960andTRF7960A This application report helps current and new users of the TRF7960 high-frequency RFID/NFC reader understand the differences between the TRF7960 and the TRF7960A devices. Understanding these differences in detail and applying this knowledge to application-specific requirements helps designers make informed decisionsaboutwhetherornotabillofmaterialschangeisneeded. 8.5 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help youneed. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications anddonotnecessarilyreflectTI'sviews;seeTI's TermsofUse. 8.6 Trademarks E2EisatrademarkofTexasInstruments. BluetoothisaregisteredtrademarkofBluetoothSIG. FeliCaisatrademarkofSonyCorporation. Wi-FiisaregisteredtrademarkofWi-FiAlliance. 62 DeviceandDocumentationSupport Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A www.ti.com SLOS758G–DECEMBER2011–REVISEDMARCH2020 8.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 8.8 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extentrequiredbythoselaws. 8.9 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 63 SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

TRF7963A SLOS758G–DECEMBER2011–REVISEDMARCH2020 www.ti.com 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 64 Mechanical,Packaging,andOrderableInformation Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TRF7963A

PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TRF7963ARHBR ACTIVE VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -20 to 85 TRF & no Sb/Br) 7963A TRF7963ARHBT ACTIVE VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -20 to 85 TRF & no Sb/Br) 7963A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TRF7963ARHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TRF7963ARHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TRF7963ARHBR VQFN RHB 32 3000 367.0 367.0 35.0 TRF7963ARHBT VQFN RHB 32 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height 5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com

PACKAGE OUTLINE RHB0032E VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 5.1 B 4.9 PIN 1 INDEX AREA 5.1 (0.1) 4.9 SIDE WALL DETAIL OPTIONAL ME20.000TAL THICKNESS C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 3.45 0.1 (0.2) TYP 9 16 EXPOSED THERMAL PAD 28X 0.5 8 17 SEE SIDE WALL DETAIL 2X 33 SYMM 3.5 0.3 32X 0.2 24 0.1 C A B 1 0.05 C 32 25 PIN 1 ID SYMM (OPTIONAL) 0.5 32X 0.3 4223442/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 3.45) SYMM 32 25 32X (0.6) 1 24 32X (0.25) (1.475) 28X (0.5) 33 SYMM (4.8) ( 0.2) TYP VIA 8 17 (R0.05) TYP 9 16 (1.475) (4.8) LAND PATTERN EXAMPLE SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.49) (R0.05) TYP (0.845) 32 25 32X (0.6) 1 24 32X (0.25) 28X (0.5) (0.845) SYMM 33 (4.8) 8 17 METAL TYP 9 16 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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