TPS92020 www.ti.com SLUSA54 –JULY2010 Resonant-Switching Driver Controller for LED Lighting CheckforSamples:TPS92020 FEATURES 1 DESCRIPTION • LLCResonantSwitchingDriverControllerfor Multi-StringLEDLightingApplications The TPS92020 is a high-performance resonant- • Half-BridgeTopology switching LED driver controller. It is designed for use in higher power LED lighting systems. The TPS92020 • FixedorVariableSwitchingFrequencyControl uses resonant switching in an LLC topology to • ProgrammableSoft-StartTime achieve a very high efficiency compared to traditional • ProgrammableDeadTimeforBestEfficiency half-bridgeconverters. • EasyON/OFFControl The programmable dead time enables zero-voltage • OvercurrentProtection switching with minimum magnetizing current, maximizing system efficiency across a variety of • Over-TemperatureProtection applications. • BiasVoltageUVLOandOVP The TPS92020 can operate in two switching • IntegratedGateDriverWith0.4-ASourceand frequency modes. Fixed frequency allows for simple 0.8-ASinkCapability design when the load current is constant while • OperatingTemperatureRange:–40°Cto125°C variable switching allows for optimal closed-loop • SOIC8-PinPackage control for loads with varying currents. The internal oscillator supports the switching frequencies from 30 APPLICATIONS kHz to 350 kHz. This high-accuracy oscillator realizes the minimum switching frequency limiting with 4% • Commercial/IndustrialLEDLightingDrivers tolerance, allowing the designer to avoid over-design • HighBayLEDLighting of the power stage and, thus, further reducing overall • LowBayLEDLighting systemcost. • StreetLEDLighting • AreaLEDLighting • StadiumLEDLighting • LEDWallWashing • LEDDTVandMonitorBack-lighting • ElectronicLightingBallasts UCC28810 TPS92020 Bias 1 VSENSVEDD 8 3 OC VCC 7 2 EAOUGTDRV 7 2 RT GD1 8 3 VINS GND 6 1 DT GND 6 4 ISENSE 4 SS TZE 5 GD2 5 UDG-10043 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS92020 SLUSA54 –JULY2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. DESCRIPTION (CONTINUED) The programmable soft-start timer maximizes design flexibility demanded by the varied requirements of end equipments utilizing a half-bridge topology. The TPS92020 incorporates a 0.4-A source and 0.8-A sink for driving a low-cost gate driver transformer, delivering complete system protection functions including overcurrent, UVLO, biassupplyOVPandOTP. Table1. PACKAGEINFORMATION(1) OPERATING DEVICE PACKAGE OPERATINGFREQUENCY TEMPERATURE TPS92020D 8-PinSOIC Variable -40°Cto125°C (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orvisitthe deviceproductfolderonti.com. ABSOLUTE MAXIMUM RATINGS(1) (2) (3) (4) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNITS MIN MAX VCC 22 Voltagerange V GD1,GD2 -0.5 V +0.5 VCC Gatedrivecurrent–continuous GD1,GD2 ±25 RT –5 mA Currentrange DT -0.7 Operatingjunctiontemperature T −40 125 J °C Storagetemperature T −65 150 stg HumanBodyModel(HBM) 2,000 ElectrostaticDischarge V ChargedDeviceModel(CDM) 500 Leadtemperature(10seconds) 260 (1) Thesearestresslimits.Stressbeyondtheselimitsmaycausepermanentdamagetothedevice.Functionaloperationofthedeviceat theseoranyconditionsbeyondthoseindicatedunderRECOMMENDEDOPERATINGCONDITIONSisnotimplied.Exposureto absolutemaximumratedconditionsforextendedperiodsoftimemayaffectdevicereliability. (2) AllvoltagesarewithrespecttoGND. (3) Allcurrentsarepositiveintotheterminal,negativeoutoftheterminal. (4) Innormaluse,terminalsGD1andGD2areconnectedtoanexternalgatedriverandareinternallylimitedinoutputcurrent. DISSIPATION RATINGS THERMALIMPEDANCE, PACKAGE T =25°CPOWERRATING T =85°CPOWERRATING JUNCTION-TO-AMBIENT A A 8-PinSOIC 150°C/watt (1)(2) 667mW (1) 267mW (1) (1) Thermalresistanceisastrongfunctionofboardconstructionandlayout.Airflowwillreducethermalresistance.Thisnumberisonlya generalguide. (2) Thermalresistancecalculatedwithalow-Kmethodology. 2 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT V VCCinputvoltagefromalow-impedancesource 11.5 18.0 V VCC R RTresistor 1 8.666 RT kΩ R DTresistor 3.3 39 DT C SScapacitor 0.01 1 mF SS ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange,−40°C<T <125°C,T =T ,V =12V,GND=0V,R =4.7kΩ,R =16.9 A J A VCC RT DT kΩ,C =1mF,(unlessotherwisenoted) VCC PARAMETER TESTCONDITIONS MIN TYP MAX UNITS BIASSUPPLY(VCC) VCCcurrent,disabled SS=0V 1 1.5 mA VCCcurrent,enabled SS=5V,C =C =1nF 2.5 5 7.5 GD1 GD2 VCCcurrent,UVLO VCC=9V 100 400 mA UVLOturn-onthreshold MeasuredatVCCrising 9.9 10.5 11.1 V UVLOturn-offthreshold MeasuredatVCCfalling 8.9 9.5 10.1 UVLO UVLOhysteresis MeasuredatVCC 0.7 1 1.3 V OVPturn-offthreshold MeasuredatVCCrising 18 20 22 V OVPturn-onthreshold MeasuredatVCCfalling 16 18 20 OVP OVPhysteresis MeasuredatVCC 1.5 2 2.5 DEADTIME(DT) t Deadtime R =16.9kΩ 390 420 450 ns DT DT OSCILLATOR MinimumswitchingfrequencyatGD1, -40°C≤TA≤125°C 40.04 41.70 43.36 f kHz SW(min) GD2 -20°C≤T ≤105°C 40.45 41.70 42.95 A K Switchingfrequencygain/I(RT) R =4.7kΩ,I =0to1mA 60 80 100 Hz/mA ICO RT RT t GD1,GD2on-timemismatching -50 50 ns Switchingfrequencystartingburst f V =5V 300 350 400 SW(bm) mode SS Switchingfrequencytocomeoutof burstmode VSS=5V 280 330 380 kHz -40°C≤T ≤125°C 122 142.5 162 A f Switchingfrequencyatsoftstart SW(start) -20°C≤T ≤105°C 125 142.5 160 A EXTERNALDISABLE/SOFTSTART Enablethreshold MeasureatSSrising 1.1 1.2 1.3 Disablethreshold MeasuredatSSfalling 0.85 1 1.1 V Disablehysteresis MeasuredatSS 0.15 0.35 MeasuredbetweenSS(falling) Disableprop.delay 250 500 750 ns andGD2(falling) SourcecurrentonSSpin V =0.5V -225 -175 -125 SS I mA SS SourcecurrentonSSpin V =1.35V -5.5 -5 -4.5 SS Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,−40°C<T <125°C,T =T ,V =12V,GND=0V,R =4.7kΩ,R =16.9 A J A VCC RT DT kΩ,C =1mF,(unlessotherwisenoted) VCC PARAMETER TESTCONDITIONS MIN TYP MAX UNITS PEAKCURRENTLIMIT Level1overcurrentthreshold–V V OC 0.9 1 1.1 OC1(off) rising Level2overcurrentlatchthreshold– V 1.8 2.0 2.2 V OC2(off) V rising OC Level1overcurrentthreshold–V V OC 0.5 0.6 0.7 OC1(on) falling t Propagationdelay 60 200 500 ns dOC I OCbiascurrent V =0.8V -200 200 nA OC OC GATEDRIVE GD1,GD2outputvoltagehigh I =−20mA,I =−20mA 9 11 V GD1 GD2 GD1,GD2on-resistancehigh I =−20mA,I =−20mA 12 30 Ω GD1 GD2 GD1,GD2outputvoltagelow I =−20mA,I =20mA 0.08 0.2 V GD1 GD2 GD1,GD2on-resistancelow I =−20mA,I =20mA 4 10 Ω GD1 GD2 V risingfrom1Vto9V, t RisetimeGDx VCC 18 35 RISE C =1nF LOAD ns V fallingfrom9Vto1V, t FalltimeGDx VCC 12 25 FALL C =1nF LOAD V =6V,I =1.2mA, GD1,GD2outputvoltageduringUVLO VCC GD1 0.5 1.75 V I =1.2mA GD2 THERMALSHUTDOWN T Thermalshutdownthreshold 160 SD °C Thermalshutdownrecoverythreshold 140 4 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 DEVICE INFORMATION TPS92020(TopView) DT 1 8 GD1 RT 2 7 VCC OC 3 6 GND SS 4 5 GD2 TERMINALFUNCTIONS TERMINAL DESCRIPTION NAME NO. I/O Setsthedeadtimeofhigh-sideandlow-sideswitchdrivingsignals.Connectaresistortoground.Withinternal 2.25-Vvoltagereference,thecurrentflowingthroughtheresistorsetsthedeadtime.Topreventshootthrough DT 1 I whenthispinisaccidentallyshorttoground,theminimumdeadtimeissetto120ns.Anydeadtimesetting lessthan120nsdefaultsto120-nsdeadtime. GD1 8 O High-sideandlow-sideswitchgatedriver.Connectgatedrivertransformerprimarysidetothesetwopinsto GD2 5 O drivethehalfbridge. GND 6 - Ground. Overcurrentprotection.Whenthevoltageonthispinisabove1V,gatedriversignalsareactivelypulledlow. OC 3 I Afterthevoltagefallsbelow0.6V,thegatedriversignalrecoverswithsoftstart.WhenOCpinvoltageis above2V,thedeviceislatchedoff.BringingVCCbelowUVLOlevelresetstheovercurrentlatchoff. Thecurrentflowingoutofthispinsetsthefrequencyofthegatedriversignals.Connecttheopto-coupler collectortothispintocontroltheswitchingfrequencyforregulationpurpose.Parallelaresistortogroundto RT 2 I settheminimumcurrentflowingoutofthepinandsettheminimumswitchingfrequency.Tosetthemaximum switchingfrequencylimiting,placearesistorinserieswiththeopto-couplertransistor.Thisresistorsetsthe maximumcurrentflowingoutofthepinandlimitsthemaximumswitchingfrequency. Soft-start.Thispinsetsthesoft-starttimeofthesystem.Connectacapacitortoground.Pullingthispinbelow SS 4 I 1VdisablesthedevicetoalloweasyON/OFFcontrol.Thesoft-startfunctionisenabledafterallfault conditions,includingbiassupplyOV,UVLO,overcurrentprotectionandover-temperatureprotection. Biassupply.Connectthispintoapowersupplylessthan20V.Placea1-mFcapacitorinparalleltogroundto VCC 7 - filteroutnoise. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com BLOCKDIAGRAM 2.25V T + J TSD 20V 160oC/140oC 18V OV DT Thermal 1 ShutDown + R Deadtime 10.5V + UVLO DT 9.5V generator 2.5V 7 VCC Feed RT 2 back Ic OSC 8 GD1 Vss UVLO Q SET D VCC OV OC FAULT 5 GD2 TSD Q CLR 6V GD_Stop 6 GND 5uA 170uA OC OC + 3 Vss 1V SS 4 OC_latch + Css + 2V 1.2V/1V FAULT SSETQ RCLRQ 6 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 TYPICAL CHARACTERISTICS AtV =12V,R =4.7kΩ,R =16.9kΩ,V =5V,V =0V;allvoltagesarewithrespecttoGND,T =T VCC RT DT SS OC J A =25°C,unlessotherwisenoted. 1.0 350 0.9 300 0.8 A) Hz) 250 m 0.7 k ( y( nt 0.6 nc rre ue 200 u q yC 0.5 Fre pl g 150 p 0.4 n Su chi as 0.3 wit 100 Bi S 0.2 –40°C 50 25°C 0.1 V =OPEN OC 125°C 0 0 6 7 8 9 10 11 12 13 14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 BiasSupplyVoltage(V) TimingResistanceCurrent(mA) Figure1.BiasSupplyCurrentvs.BiasSupplyVoltage Figure2.SwitchingFrequencyvs.TimingResistance 1000 1000 –40°C 900 900 25°C 800 125°C 800 700 700 s) s) 600 (n 600 n e ( m me Ti Ti 500 ad 500 d e a 400 D 400 e D 300 300 200 200 –40°C 25°C 100 100 125°C 0 0 0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 35 40 45 DeadTimeCurrent (mA) DeadTimeResistance (kW) Figure3.DeadTimevs.DeadTimeCurrent Figure4.DeadTimevs.DeadTimeResistance Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 16 1.6 16 0.8 GateDriveVoltage V =15V V =15V 14 CC 1.4 14 GateDriveVoltage CC 0.7 12 1.2 12 0.6 V) 10 1.0 A) V) 10 0.5 A) ( ( ( ( ge nt ge nt olta 8 0.8 urre olta 8 0.4 urre V C V C ve 6 0.6 ve ve 6 0.3 ve Dri Dri Dri Dri ate 4 0.4 ate ate 4 0.2 ate G G G G 2 0.2 2 GateDriveCurrent 0.1 GateDriveCurrent 0 0 0 0 –2 –0.2 –2 –0.1 0 100 200 300 400 500 600 0 200 400 600 800 1000 Time(ns) Time(ns) Figure5.GateDriveVoltagevs.GateDriveCurrentvs. Figure6.GateDriveVoltagevs.GateDriveCurrentvs. Time Time 300 12.0 UVLO-OnThreshold(VCCRising) 11.5 UVLO-OffThreshold(VCCFalling) 250 s) V) 11.0 n ( e( 200 ge m a 10.5 Ti olt y V Dela 150 old 10.0 h n s o e gati 100 Thr 9.5 a O Prop UVL 9.0 50 8.5 0 8.0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JunctionTemperature(°C) JunctionTemperature(°C) Figure7.PropagationDelayTimevs.Temperature Figure8.UVLOThresholdVoltagevs.Temperature 8 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 TYPICAL CHARACTERISTICS (continued) 22.0 2.4 21.5 OVP-OffThreshold(VCCRising) 2.2 OVP-OnThreshold(VCCFalling) 21.0 V) 2.0 ( shold(V) 221009...505 dVoltage 11..68 OCOffThreshold(VOCRising) Thre 19.0 shol 1.4 OOCCOLantcThhrTehsrheoslhdo(lVdO(VCFalRliinsgin)g) vervoltage 1188..05 urrentThre 11..02 OC O 17.5 c r e 0.8 v 17.0 O 0.6 16.5 16.0 0.4 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JunctionTemperature(°C) JunctionTemperature(°C) Figure9.OvervoltageThresholdvs.Temperature Figure10.OvercurrentThresholdVoltagevs.Temperature 100 90 80 s) n 70 ( e m Ti 60 h c at 50 m s Mi 40 e m Ti 30 n- O 20 10 0 0 50 100 150 200 250 300 350 SwitchingFrequency(kHz) Figure11.On-TimeMismatchvs.SwitchingFrequency Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com APPLICATION INFORMATION Principle of Operation The soft-switching capability, high efficiency and long holdup time make the LLC resonant converter attractive for many applications, such as digital TV, ac/dc adapters and computer power supplies. Figure 12 shows the schematicoftheLLCresonantconverter. The LLC resonant converter is based on the series resonant converter (SRC). By using the transformer magnetizing inductor, zero-voltage switching can be achieved over a wide range of input voltage and load. As a result of multiple resonances, zero-voltage switching can be maintained even when the switching frequency is higher or lower than resonant frequency. This simplifies the converter design to avoid the zero-current switching region, which can lead to system damage. The converter achieves the best efficiency when operated close to its resonant frequency at a nominal input voltage. As the switching frequency is lowered the voltage gain is significantly increased. This allows the converter to maintain regulation when the input voltage falls low. These features make the converter ideally suited to operate from the output of a high-voltage boost PFC pre-regulator, allowingittoholdupthroughbriefperiodsofacline-voltagedropout. Due to the nature of resonant converter, all the voltages and currents on the resonant components are approximately sinusoidal. The gain characteristic of LLC resonant converter is analyzed based on the First Harmonic Approximation (FHA), which means all the voltages and currents are treated as sinusoidal shape with thefrequencysameasswitchingfrequency. According to the operation principle of the converter, the LLC resonant converter can be draw as the equivalent circuitasshowninFigure13. C L R R C L R R n:1:1 V LM GE L R V M E OE UDG-10044 UDG-10045 Figure12.LLCResonantConverter Figure13.LLCResonantConverterEquivalent Circuit In this equivalent circuit, the V and V are the fundamental harmonics of the voltage generated by the half ge oe bridge and the voltage on the transformer primary side, respectively. These voltages can be calculated through Fourieranalysis.TheloadresistorR istheequivalentresistoroftheload,anditcanbecalculatedas: e æ ö R =ç 8 ÷´(n)2´R E ç( )2 ÷ p è ø (1) Basedonthisequivalentcircuit,theconvertergainatdifferentswitchingfrequenciescanbecalculatedas: æ ö jw´L ´R M E ç ÷ ( ) V jw´L +R ç OUT ÷= M E çæV ö÷ jw´L ´R 1 çèçè D2C ÷ø÷ø (jw´LMM)+REE + jw´CR +jw´LR where • V /2istheequivalentinputvoltageduetothehalf-bridgestructure (2) DC 10 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 Table2.CircuitDefinitionCalculations RESONANT NORMALIZED NORMALIZEDGAIN QUALITYFACTOR INDUCTORRATIO FREQUENCY FREQUENCY æ ö ç ÷ 1 L M=çççèæçèVVOD2UCTö÷ø÷÷÷ø f0 = 2p´ LR´CR(4) QE = RRECR (5) fn =æçèff0 ö÷ø (6) Ln =æçèLLMR ö÷ø (7) (3) Following the definitions in Table 2, the converter gain at different switching frequencies can be calculated in Equation8. ( )2 L ´ f M= n n ( )2 ( ) ( ) L ´ f + f -1 ´ f +1+j´f ´L ´Q n n n n n n e where • Mistheconvertervoltagegain • Lnistheratioofthemagnetizinginductancetotheresonantinductance • f isthenormalizedswitchingfrequency n • Q isthequalityfactor (8) e Because of the FHA, Equation 8 is an approximation. When the switching frequency moves away from the resonant frequency, the error becomes larger. However, this equation can be used as the design tool. The final resultsneedtobeverifiedbythetimebasedsimulationorhardwaretest. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com From Equation 8, when switching frequency is equal to resonant frequency, f = 1 and converter voltage gain is n equal to 1. Converter gain at different loads and inductor ratio conditions are shown in Figure 14 through Figure17. 2 2 Q =0.1 Q =0.1 Qe=0.2 Qe=0.2 Qe=0.5 Qe=0.5 Qe=1 Qe=1 1.5 Qe=2 1.5 Qe=2 Qe=5 Qe=5 e e M M 1 1 0.5 0.5 0 0 0.1 0.5 1 1.5 2 0.1 0.5 1 1.5 2 f f n n Figure14.NormalizedSwitchingFrequency Figure15.NormalizedSwitchingFrequency vs.ConverterVoltageGain,Ln=1 vs.ConverterVoltageGain,Ln=5 2 2 Q =0.1 Q =0.1 Qe=0.2 Qe=0.2 Qe=0.5 Qe=0.5 Qe=1 Qe=1 1.5 Qe=2 1.5 Qe=2 Qe=5 Qe=5 e e M M 1 1 0.5 0.5 0 0 0.1 0.5 1 1.5 2 0.1 0.5 1 1.5 2 f f n n Figure16.NormalizedSwitchingFrequency Figure17.NormalizedSwitchingFrequency vs.ConverterVoltageGain,Ln=10 vs.ConverterVoltageGain,Ln=20 Based on its theory of operation the LLC resonant converter is controlled through Pulse Frequency Modulation (PFM). The output voltage is regulated by adjusting the switching frequency according to the input and output conditions. Optimal efficiency is achieved at the nominal input voltage by setting the switching frequency close to the resonant frequency. When the input voltage droops low the switching frequency is decreased to boost the gainandmaintainregulation. The TPS92020 resonant half-bridge controller uses variable switching frequency control to adjust the resonant tank impedance and regulate output voltage. This 8-pin package device integrates the critical functions for optimizingthesystemperformancewhilegreatlysimplifyingthedesignandlayout. 12 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 Adjustable Dead Time Resonant half-bridge converter relies on the resonant tank current at MOSFETs turn-off to achieve soft switching andreduceswitchingloss.Higherturn-offcurrentprovidesmoreenergytodischargethejunctioncapacitor,while it generates more turn-off loss. Smaller turn-off current reduces turn-off loss, but it requires longer time to discharge MOSFETs junction capacitors and achieve soft switching. By choosing an appropriate dead time, turn-off current is minimized while still maintaining zero-voltage switching, and best system performance is realized. In TPS92020, dead time can be adjusted through a single resistor from DT pin to ground. With internal 2.25-V voltagereference,thecurrentflowthroughtheresistorsetsthedeadtime. t =20ns+R ´24ns D DT (9) To prevent shoot through when the DT pin accidentally connects to ground, the two gate driver outputs limit the dead-timetoaminimumof120-ns.Anydead-timesettinglessthan120-ns,defaultstotheminimum120-nslimit. Oscillator With variable switching frequency control, TPS92020 relies on the internal oscillator to vary the switching frequency. The oscillator is controlled by the current flowing out of RT pin. Except during soft start, the relationship between the gate signal frequency and the current flowing out of RT pin can be represented in Equation10. 1 1 f = ´ »I ´83Hz mA SW RT 2 æ6ns´1Aö ç ÷+150ns è IRT ø (10) Since the switching frequency is proportional to the current, by limiting the maximum and minimum current flowing out of RT pin, the minimum and maximum switching frequency of the converter could be easily limited. As shown in Figure 18, putting a resistor from RT pin to ground limits the minimum current and putting a resistor inserieswiththeopto-couplerlimitsthemaximumcurrent. Maximum FrequencyLimiting TPS92020 R1 2 RT Minimum FrequencyLimiting R2 UDG-10046 Figure18. MaximumandMinimumFrequencySettingforTPS92020 ThefrequencylimitingresistorcanbecalculatedinEquation11throughEquation14. 6ns IF(max)= æçç(2´f1 )ö÷÷-150ns IF(max)=2.5VæçèR11 +R12 ö÷ø è MAX ø (12) (11) 6ns IF(min)= æç 1 ö÷-150ns IF(min)= 2R.5V ç(2´f )÷ 2 è MIN ø (14) (13) Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com Soft Start Duringstartupandfaultrecoveryconditions,softstartisalwaysimplementedtopreventexcessiveresonanttank current and ensure Zero-Voltage Switching (ZVS). During soft start, the switching frequency is increased. The soft-starttimecanbeprogrammedbyplacingacapacitorfromSSpintoground. The soft-start pin also serves as an ON/OFF control pin of the device. By actively pulling the SS pin below 1 V, the device is disabled. When the pull down is removed, SS pin voltage is increased because of internal charging current. Once SS pin becomes above 1.2 V, the device starts to generated gate-driver signal and enters soft-startmode.ThetimesequenceofsoftstartisshowninFigure19. 4V 1.2V V SS GateDriver t SS t SS(delay) UDG-10047 Figure19. Soft-StartSequence To prevent a long delay between the ON command and appearance of a gate driver signal, the SS pin current is set as two different levels. When SS pin voltage is below 1.2 V, its output current is 175 mA. This high current could charge the soft-start pin capacitor to 1.2 V in a short period of time, and reduces the time delay. This time delayiscalculatedinEquation15. 1.2V tSS(delay)=175mA´CSS (15) The switching frequency during soft start is determined by both the current flowing out of the RT pin and the voltageonSSpin.TheswitchingfrequencycanbecalculatedbasedontheEquation16. 1 1 f = ´ SW 2 6ns´1A +150ns æ V ö IRT +çè1.81mA-2.V2SkSW÷ø (16) After SS pin voltage reaches 4 V, soft-start period is finished and switching frequency becomes the same as demanded by the RT pin current. The time used to charge SS pin from 1.2 V to 4 V is defined as soft-start time andcanbecalculatedinEquation17. 2.8V t = ´C SS SS 5mA (17) To ensure reliable operation, the gate drivers restart with GD2 turning high. This prevents uncertainty during systemstartup. 14 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

TPS92020 www.ti.com SLUSA54 –JULY2010 Burst-Mode Operation During light load condition, the resonant converter tends to increase its switching frequency and maintain the output voltage regulation. However, due to ringing caused by transformer parasitic capacitor and the rectification-diode-junction capacitors, the energy could be directly transferred to the load through these capacitors. When this power becomes more than the load requires, output voltage become higher than the regulationlevel.Inthiscase,furtherincreasingtheswitchingfrequencywillnothelpthesituationbecauseenergy transfertotheloadisnotthroughthepowerstageitself. To prevent output over voltage during this condition, the TPS92020 includes the burst-mode operation function. When the control loop demands switching frequency higher than 350 kHz, the gate driver is disabled and the power stage stops switching. When the output voltage drops, the control loop begins to demand switching frequency less than 330 kHz, the gate driver recovers and the power stage begins to deliver power again. This allowsoutputvoltagetoberegulated. Thisburstmodecanbeeasilydisabledbylimitingthemaximumswitchingfrequencytolessthan350kHz.Inthis way, the control loop never demands a switching frequency higher than 350 kHz and as a result, burst mode operationdoesnotoccur. Overcurrent Protection To prevent power stage failure under excessive load current condition, the TPS92020 includes an overcurrent protection function. With a dedicated OC pin, the power stage is shut down when OC pin voltage is above 1 V. Once the OC pin voltage falls below 0.6 V, the gate driver recovers with a soft start. To enhance system safety, the TPS92020 latches up the entire system when the OC pin voltage rises above 2 V. Bringing the VCC voltage belowtheUVLOvoltagelevelresetsthedevice. The current can be indirectly sensed through the voltage across resonant capacitor by using the sensing network showninFigure20. L R Fromhalf-bridge TR L M ToOC D2 RS CS C CP RP D1 R UDG-10048 Figure20. CurrentSensingforLLCResonantConverter Thegeneralconceptofthissensingmethodisthattheacvoltageacrosstheresonantcapacitorisproportionalto loadcurrent. According to the FHA model, peak voltage of the ac component on the resonant capacitor can be calculated in Equation18. ( ) 4 jw ´L ´ Q +1 n n e VCR(pk)= p´n´VOUT ( )2 w ´L n n (18) Therefore, the resonant capacitor voltage reaches its maximum value at the minimum switching frequency and maximumload.AccordingtoEquation18,thecurrentsensingnetworkcomponentscanbecalculated.Duetothe natureofFHA,thefinalcircuitparametersmustbeverifiedthroughactualhardwaretest. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TPS92020

TPS92020 SLUSA54 –JULY2010 www.ti.com Table3.CalculatedCurrentSensingNetworkComponents SYMBOL FUNCTION DESIGNEQUATION ( )2 VCR(pk)MAX RS Transferacvoltageacrossresonantcapacitorintocurrentsource Rs = 2´PRS(max) (19) 10 C = CS Blockingdcvoltageonresonantcapacitor S R ´f S MIN (20) R p R = S ´ RP Loadresistorofthecurrentsource P VCR(pk)MAX 2 (21) 10 C = C Filtercapacitor P ( ) P R f P´MIN (22) Gate Driver Half-bridge resonant converter is controlled by the nearly 50% duty cycle variable frequency square wave voltage. This allows the half bridge to be easily driven by the gate-driver transformer. Compared with a half-bridgedriverdevice,agate-drivertransformerprovidesasimpleandreliablesolution,which: • Eliminatetheneedforgatedriverpowersupply • Enablesimplifiedlayout • Preventingshootthroughduetothetransformercoupling • Nolatchup The TPS92020 integrates two-gate drivers with 0.4-A source and 0.8-A sink capability to directly drive the gate drivertransformer. For LLC resonant converter, it is critical for the gate-driver signal to be precisely symmetrical. Otherwise, the resonant tank operation will be symmetrical. The load current distribution will be unbalanced for the output rectifiers,whichinturnrequiresoverdesignofthepowerstagesandthermalmanagement. In TPS92020, the gate-driver output is precisely trimmed to have less than 50 ns mismatch. Although the gate-driver signal is quite symmetrical, it is still recommended to insert the dc blocking capacitor in the gate-drivertransformerprimarysidetopreventtransformersaturationduringfasttransients. VCC Pin Connect a regulated bias supply to VCC pin. When VCC becomes above 10.5 V the device is enabled and after all fault conditions are cleared the gate driver starts with soft start. When the VCC voltage drops below 9.5 V, the device enters UVLO protection mode and both gate drivers are actively pulled low. When VCC rises above 20 V the device enters VCC overvoltage protection mode and the device is disabled with both gate drivers actively pulledlow.VCCover-voltageprotectionwillrecoverwithsoftstartwhentheVCCvoltagereturnsbelow18V. Over-Temperature Protection TPS92020 continuously senses its junction temperature. When the junction temperature rises above 160°C the device enters over-temperature protection mode with both gate drivers actively pulled low. When junction temperaturedropsbelow140°C,gatedriverrestartswithsoftstart. 16 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS92020

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS92020D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 92020D & no Sb/Br) TPS92020DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 92020D & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS92020DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS92020DR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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