Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 TPS7A65-Q1 300-mA, 40-V, Low-Dropout Regulator With 25-µA Quiescent Current 1 Features 3 Description • Lowdropoutvoltage: The TPS7A65-Q1 low-dropout linear voltage 1 regulator is designed for low power consumption and – 300mVatI =150mA OUT quiescent current less than 25 µA in light-load • 7-Vto40-Vwideinputvoltagerange applications. This device features integrated withupto45-Vtransients overcurrent protection and a design to achieve stable • 300-mAmaximumoutputcurrent operation even with low-ESR ceramic output capacitors. A low-voltage tracking feature allows for a • 25-µA(typical)ultralowquiescentcurrentatlight smaller input capacitor and can possibly eliminate the loads need of using a boost converter during cold crank • 3.3-Vand5-Vfixedoutputvoltagewith±2% conditions. Because of these features, this device is tolerance well-suited in power supplies for various automotive applications. • Low-ESRceramicoutputstabilitycapacitor • Integratedfaultprotection: DeviceInformation(1) – Short-circuitandovercurrentprotection PARTNUMBER PACKAGE BODYSIZE(NOM) – Thermalshutdown TPS7A65-Q1 TO-252(3) 6.60mm×6.10mm • Lowinput-voltagetracking (1) Forallavailablepackages,seethepackageoptionaddendum • Thermallyenhancedpowerpackage: attheendofthedatasheet. – 3-PinTO-252(KVU,DPAK) 2 Applications • Hybridinstrumentclusters • Shiftersystems • Headupdisplays • Automotiveclusterdisplays TypicalApplicationSchematic TypicalRegulatorStability 10 TPS7A65-Q1 VIN= 14V COUT= 10µF, 47µF TA= 27°C VIN VIN VOUT VOUT VOUT= 5V, 3.3V CIN COUT Ω() 1 T U O C Stable Operation GND of Over Entire Region R S E 0.1 0.01 0.01 0.1 1 10 100 300 IOUT(mA) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription.................................................10 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................13 3 Description............................................................. 1 8 ApplicationandImplementation........................ 14 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................14 8.2 TypicalApplication .................................................14 5 PinConfigurationandFunctions......................... 4 9 PowerSupplyRecommendations...................... 16 6 Specifications......................................................... 5 10 Layout................................................................... 16 6.1 AbsoluteMaximumRatings......................................5 6.2 ESDRatings..............................................................5 10.1 LayoutGuidelines.................................................16 6.3 RecommendedOperatingConditions.......................5 10.2 LayoutExample....................................................19 6.4 ThermalInformation..................................................5 11 DeviceandDocumentationSupport................. 20 6.5 ElectricalCharacteristics...........................................6 11.1 ReceivingNotificationofDocumentationUpdates20 6.6 DissipationRatings...................................................6 11.2 CommunityResources..........................................20 6.7 TypicalCharacteristics..............................................7 11.3 Trademarks...........................................................20 7 DetailedDescription............................................ 10 11.4 ElectrostaticDischargeCaution............................20 7.1 Overview.................................................................10 11.5 Glossary................................................................20 7.2 FunctionalBlockDiagram.......................................10 12 Mechanical,Packaging,andOrderable Information........................................................... 20 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(May2018)toRevisionF Page • Changed11Vto7VinInputVoltageRangeFeaturesbulletofFeaturessection............................................................... 1 • ChangedApplicationssection ............................................................................................................................................... 1 • ChangedV parameterminimumspecificationinRecommendedOperatingConditionstablefrom11Vto7Vand IN addedfootnote........................................................................................................................................................................ 5 • ChangedV parameterminimumspecificationinElectricalCharacteristicstablefrom11Vto7Vandaddedfootnote....6 IN • Changed11Vto7VinInputvoltagerangerowinDesignParameterstable ................................................................... 14 • Changedinputvoltagerangefrom11Vto40Vto7Vto40VinPowerSupplyRecommendationssection....................16 ChangesfromRevisionD(December2015)toRevisionE Page • Changed4Vto11VinInputVoltageRangeFeaturesbullet .............................................................................................. 1 • ChangedV parameterminspecificationsto11Vfrom5.3Vand3.6V ............................................................................ 6 IN • Changed4Vto11VinInputvoltagerangerowinDesignParameterstable..................................................................... 14 • Changed4Vto40VinfirstsentenceofPowerSupplyRecommendationssection........................................................... 16 ChangesfromRevisionC(December2011)toRevisionD Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modessection,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection, DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection ..................1 ChangesfromRevisionB(November2011)toRevisionC Page • DeletedtheTPS7A6533QKVURQ1device............................................................................................................................ 1 • ChangedtheRegulatedOutputVoltage(5.1).AddedtoTestConditions"10mAto300mA,V =V +1Vto16V".........6 IN OUT 2 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 ChangesfromRevisionA(November2011)toRevisionB Page • Changedtheθ valueintheAbsMaxTableFrom:12.7To:1.2°C/W................................................................................. 5 JP ChangesfromOriginal(May2010)toRevisionA Page • RemovedallKKTinformation................................................................................................................................................. 5 Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com 5 Pin Configuration and Functions KVUPackage 3-PinTO-252 TopView 1 2 3 GND VIN VOUT PinFunctions PIN I/O DESCRIPTION NO. NAME Inputvoltagepin:Theunregulatedinputvoltageissuppliedtothispin.Abypasscapacitorisconnected 1 VIN I betweenVINpinandGNDpintodampeninputlinetransients. 2 GND I/O Groundpin:ThisissignalgroundpinoftheIC. Regulatedoutputvoltagepin:Thisisaregulatedvoltageoutput(V =3.3Vor5V,asapplicable)pin OUT 3 VOUT O withalimitationonmaximumoutputcurrent.Toachievestableoperationandpreventoscillation,an externaloutputcapacitor(C )withlowESRisconnectedbetweenthispinandtheGNDpin. OUT 4 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Unregulatedinput(2)(3) 45 V IN V Regulatedoutput 7 V OUT θ Thermalimpedancejunctiontoexposedpad 1.2 °C/W JP T Operatingambienttemperature 125 °C A T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Absolutenegativevoltageonthesepinsnottogobelow–0.3V. (3) Absolutemaximumvoltagefordurationlessthan480ms. 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Humanbodymodel(HBM),perAECQ100-002(1) ±2000 V (ESD) (1) AECQ100-002indicatesHBMstressingisdoneinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 6.3 Recommended Operating Conditions MIN MAX UNIT V Unregulatedinputvoltage 7(1) 40 V IN V Enablepinvoltage 4 40 V EN T Operatingjunctiontemperature –40 150 °C J (1) V cangodownto4Vfor130msorlessandremainfunctional.IfV islessthan7Vforlongerthan130ms,thensomedevicesmay IN IN turnoffuntiltheinputvoltagerisesabove7V. 6.4 Thermal Information TPS7A65-Q1 THERMALMETRIC(1) KVU(TO-252) UNIT 3PINS High-Kprofile(2) 29.3 °C/W R Junction-to-ambientthermalresistance θJA Low-Kprofile(3) 38.6 °C/W R Junction-to-case(top)thermalresistance N/A °C/W θJC(top) R Junction-to-boardthermalresistance 8.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 3.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 8.1 °C/W JB R Junction-to-case(bottom)thermalresistance 1.1 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) ThethermaldataisbasedonJEDECstandardhigh-Kprofile–JESD51-5.Thecopperpadissolderedtothethermallandpattern.Also correctattachmentproceduremustbeincorporated. (3) ThethermaldataisbasedonJEDECstandardlow-Kprofile–JESD51-3.Thecopperpadissolderedtothethermallandpattern.Also correctattachmentproceduremustbeincorporated. Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com 6.5 Electrical Characteristics V =14V,T =–40ºCto+150ºC(unlessotherwisenoted) IN J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTVOLTAGE(VINPin) Fixed5-Voutput,I =1mA 7(1) 40 OUT V Inputvoltage V IN Fixed3.3-Voutput,I =1mA 7(1) 40 OUT I Quiescentcurrent V =8.2Vto18V,I =0.01mAto0.75mA 25 40 µA QUIESCENT IN OUT V Undervoltagelockoutvoltage RampV downuntiloutputisturnedOFF 3.16 V IN-UVLO IN V Power-upvoltage RampV upuntiloutputisturnedON 3.45 V IN(POWERUP) IN REGULATEDOUTPUTVOLTAGE(VOUTPin) FixedV value(3.3Vor5Vasapplicable), OUT V Regulatedoutputvoltage I =10mA,10mAto300mA, –2% 2% OUT OUT V =V +1Vto16V IN OUT V =6Vto28V,I =10mA,V =5V 15 IN OUT OUT ∆V Lineregulation mV LINE-REG V =6Vto28V,I =10mA,V =3.3V 20 IN OUT OUT I =10mAto300mA,V =14V,V =5V 25 OUT IN OUT ∆VLOAD-REG Loadregulation IOUT=10mAto300mA,VIN=14V,VOUT=3.3 35 mV V V (2) Dropoutvoltage IOUT=250mA 500 mV DROPOUT (VIN–VOUT) IOUT=150mA 300 R (3) Switchresistance VINtoVOUTresistance 2 Ω SW I Outputcurrent V inregulation 0 300 mA OUT OUT I Outputcurrentlimit V =0V(VOUTpinisshortedtoground) 350 1000 mA CL OUT V =0.5Vpp,I =300mA, IN-RIPPLE OUT 60 frequency=100Hz,V =5V,V =3.3V PSRR(3) Power-supplyripplerejection OUT OUT dB V =0.5Vpp,I =300mA, IN-RIPPLE OUT 30 frequency=150kHz,V =5V,V =3.3V OUT OUT TEMPERATURE T Thermalshutdowntrippoint 165 ºC SHUTDOWN T Thermalshutdownhysteresis 10 ºC HYST (1) V cangodownto4Vfor130msorlessandremainfunctional.IfV islessthan7Vforlongerthan130ms,thensomedevicesmay IN IN turnoffuntiltheinputvoltagerisesabove7V. (2) ThistestisdonewithV inregulationandV –V parameterismeasuredwhenV (3.3Vor5V)dropsby100mVatspecified OUT IN OUT OUT loads. (3) Specifiedbydesign;nottested. 6.6 Dissipation Ratings T <25°CPOWER DERATINGFACTOR T =85°CPOWER JEDECSTANDARD PACKAGE A A RATING(W) ABOVET =25°C(°C/W) RATING(W) A JEDECStandardPCB- 3-pinKVU 3.24 38.6 1.68 lowK,JESD51-3 JEDECStandardPCB- 3-pinKVU 4.27 29.3 2.22 highK,JESD51-5 6 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 6.7 Typical Characteristics 10 10 VIN= 14V VIN= 14V COUT= 1µF COUT= 1µF TA= 27°C TA= 27°C VOUT= 5V VOUT= 3.3V Ω) 1 Ω) 1 C(OUT Stable Operation C(OUT Stable Operation R of R of ES 0.1 ES 0.1 Unstable 0.06 0.06 Operation 0.03 Unstable 0.03 Operation 0.01 0.01 0.01 0.1 1 10 30 100 300 0.01 0.1 1 10 30 100 300 IOUT(mA) IOUT(mA) Figure1.ESRvsLoadCurrent Figure2.ESRvsLoadCurrent 80 55 VIN= 14V VIN=14V 70 TVAO=U 2T5=° C5V, 3.3V 50 VOUT=5V, 3.3V 60 45 IOUT= 250mA A) A) µ 50 µ 40 ( ( ENT 40 ENT 35 C C S S UIE 30 UIE 30 IQ IQ IOUT= 1mA 20 25 10 20 0 15 0.001 0.01 0.1 1 10 100 1000 -50 0 50 100 150 IOUT(mA) TA(°C) Figure3.QuiescentCurrentvsLoadCurrent Figure4.QuiescentCurrentvsAmbientAirTemperature 700 0.4 VOUT= 5V, 3.3V VOUT= 5V 0.35 600 TA= 25°C 0.3 µA)500 (V)0.25 TA= 125°C (400 UT TA= 25°C UIESCENT 300 IOUT= 100mA VDROPO00.1.25 TA= -40°C Q I200 0.1 No Load 0.05 100 0 0 4 14 24 34 40 0 50 100 150 200 250 300 VIN(V) IOUT(mA) Figure5.QuiescentCurrentvsInputVoltage Figure6.DropoutVoltagevsLoadCurrent (1) (1) Dropoutvoltageismeasuredwhentheoutputvoltagedropsby100mVfromtheregulatedoutputvoltagelevel.(Forexample,thedrop outvoltageforTPS7A6550ismeasuredwhentheoutputvoltagedropsdownto4.9Vfrom5V.) Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com Typical Characteristics (continued) 5.1 6 VIN= 14V IOUT= 100mA 5.08 IOUT = 1mA 5 TA= 25°C 5.06 5.04 4 V) 5.02 V) V(OUT 4.958 V(OUT 3 2 4.96 4.94 1 4.92 4.9 0 -50 0 50 100 150 2 3 4 5 6 7 TA(°C) VIN(V) Figure7.OutputVoltagevsAmbientAirTemperature Figure8.OutputVoltagevsInputVoltage 0.12 750 ILOAD= 100mA VIN= 14V 0.1 VOUT = 5V, 3.3V 700 VOUT= 5V, 3.3V 0.08 650 TA= 125°C I(A)OUT0.06 TAT=A =-4 205°C°C I(mA)CL 600 0.04 550 0.02 500 0 450 0 10 20 30 40 50 -50 0 50 100 150 V (V) T (°C) IN A Figure9.OutputCurrentvsInputVoltage Figure10.OutputCurrentLimitvsAmbientAirTemperature 12 3 mV)111.51 VVI1O0IONUmUT=TAs =1tt e4o5pVV 3 ,f 0r3o0.3mmVA mV) 2.5 IVV8OVOIUN UTtTos= t= 2e1 85p0VV mf,r Ao3m.3V ulation(101.50 ulation ( 1.52 g g e e R 9.5 R d e 1 a n o 9 Li L 0.5 8.5 8 0 -50 0 50 100 150 -50 0 50 100 150 TA(°C) TA(°C) Figure11.LoadRegulationvsAmbientAirTemperature Figure12.LineRegulationvsAmbientAirTemperature 8 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 Typical Characteristics (continued) 120 120 VIN= 14V VIN = 14V IOUT= 250mA IOUT= 1mA 100 TA= 25°C 100 TA= 25°C COUT= 10µF COUT= 10µF 80 VOUT= 5V, 3.3V 80 VOUT= 5V, 3.3V B) B) d d R( 60 R( 60 R R S S P P 40 40 20 20 0 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure13.PSRRatHeavyLoadCurrent Figure14.PSRRatLightLoadCurrent Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com 7 Detailed Description 7.1 Overview The TPS7A65-Q1 is a monolithic low-dropout linear voltage regulator designed for low-power consumption and quiescent current less than 25 µA in light-load applications. Because of an integrated fault protection, this device iswell-suitedinpowersuppliesforvariousautomotiveapplications. Thisdeviceisavailableintwofixed-output-voltageversionsasfollows: • 5-Voutputversion(TPS7A6550-Q1) • 3.3-Voutputversion(TPS7A6533-Q1) SeeFeatureDescriptionforfulldescriptionsofthefeaturesoftheTPS7A65-Q1voltageregulator. 7.2 Functional Block Diagram VRef1 Temperature Sensor/ Band Gap Thermal Shutdown Q1 UVLO Comp. with VRef1 VIN Internal Regulator Error VIN Reference Control Amp CIN Logic Control VOUT VOUT COUT Over Current Detection Charge Oscillator Pump GND 7.3 Feature Description 7.3.1 PowerUp During power up, the regulator incorporates a protection scheme to limit the current through the pass element and output capacitor. When the input voltage exceeds a certain threshold (V ) level, the output voltage IN(POWERUP) beginstorampup;seeFigure15. 10 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 Feature Description (continued) VIN VIN(POWERUP) 0 VOUT 5V or 3.3V 0 Figure15. Power-UpSequence 7.3.2 Charge-PumpOperation This device has an internal charge pump that turns on or off depending on the input voltage and the output current. The charge pump switching circuitry does not cause conducted emissions to exceed required thresholds on the input voltage line. For a given output current, the charge pump stays on at lower input voltages and turns off at higher input voltages. The charge-pump switching thresholds are hysteretic. Figure 16 and Figure 17 show typical switching thresholds for the charge pump at light (I < approximately 2 mA) and heavy (I > OUT OUT approximately2mA)loads,respectively. e at St ON p m u P Hysteresis e g r a h COFF 7.8 7.9 V (V) IN Figure16. Charge-PumpOperationatLightLoads e at ON St p m u Hysteresis P e g r a Ch OFF 9.2 9.6 V (V) IN Figure17. Charge-PumpOperationatHeavyLoads Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com Feature Description (continued) 7.3.3 Low-PowerMode At light loads and high input voltages (V > approximately 8 V such that charge pump is off) the device operates IN inthelow-powermodeandthequiescentcurrentconsumptiondecreasesto25 µA(typical)asshowninTable1. Table1.TypicalQuiescentCurrentConsumption I CHARGEPUMPON CHARGEPUMPOFF OUT I <approximately2mA 25µA OUT 250µA (lightload) (low-powermode) I >approximately2mA OUT 280µA 70µA (heavyload) 7.3.4 UndervoltageShutdown This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage (V ) falls below an internally fixed UVLO threshold level (V ) as shown in Figure 18. This ensures that the IN IN-UVLO regulator does not latch into an unknown state during low input-voltage conditions. The regulator normally powersupwhentheinputvoltageexceedstheV threshold. IN(POWERUP) 7.3.5 Low-VoltageTracking At low input voltages, the regulator drops out of regulation, and the output voltage tracks input minus a voltage based on the load current (I ) and switch resistance (R ) as shown in Figure 18. This allows for a smaller OUT SW inputcapacitorandcanpossiblyeliminatetheneedofusingaboostconvertorduringcold-crankconditions. VIN-UVLO VIN 0 5V or 3.3V VOUT 0 Tracking Figure18. UndervoltageShutdownandLow-VoltageTracking 7.3.6 IntegratedFaultProtection This device features integrated fault protection to make them ideal for use in automotive applications. To keep the device in a safe area of operation during certain fault conditions, the device uses internal current limit protection and current limit foldback to limit the maximum output current. This protects the device from excessive power dissipation. For example, during a short-circuit condition on the output, limiting current through the pass elementtoI protectsthedevicefromexcessivepowerdissipation. CL 7.3.7 ThermalShutdown This device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. For continuous normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature exceedstheTSDtrippoint,theoutputturns off. When the junction temperature falls below the TSD trip point, the outputturnsonagain.Figure19showsthis. 12 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 Feature Description (continued) Figure19. ThermalCyclingWaveformforTPS7A6550-Q1(V =24V,I =300mA,V =5V) IN OUT OUT 7.4 Device Functional Modes 7.4.1 OperationWithV LowerThan4V IN The TPS7A65-Q1 device operates with input voltage above 4 V. The typical UVLO voltage is 3.16 V, the device canoperateatinputvoltagelowerthan4V.ButatinputvoltagebelowtheactualUVLO,thedeviceshutsdown. 7.4.2 OperationWithV LargerThan4V IN When V is greater than 4 V, if the input voltage is higher than V plus the dropout voltage, the output voltage IN OUT isequaltothesetvalue.Otherwise,theoutputvoltageisequaltoV minusthedropoutvoltage. IN Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS7A65-Q1 is a low-dropout linear voltage regulator designed for low power consumption and quiescent current less than 25 µA in light-load applications. This device features integrated overcurrent protection and a design to achieve stable operation even with low-ESR ceramic output capacitors. A low-voltage tracking feature allows for a smaller input capacitor and can possibly eliminate the need of using a boost converter during cold crank conditions. Because of these features, this device is well-suited in power supplies for various automotive applications. 8.2 Typical Application A typical application circuit for TPS7A65-Q1 is Figure 20. Depending on the end application, one may use different values of external components. An application may require a larger output capacitor during fast load steps to prevent the output from temporarily dropping down. TI recommends a low-ESR ceramic capacitor with dielectric of type X5R or X7R. The user can additionally connect a bypass capacitor at the output to decouple high-frequencynoiseaspertheendapplication. TPS7A65-Q1 VIN VIN VOUT VOUT 10µF 1µF 0.1µF to to 0.1µF 22µF 10µF GND Figure20. TypicalApplicationSchematic 8.2.1 DesignRequirements Table2liststheparametersforthisdesignexample. Table2.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Inputvoltagerange 7Vto40V Outputvoltage 3.3V,5V Outputcurrentrating 300mAmaximum Outputcapacitorrange 1µFto10µF 14 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 8.2.2 DetailedDesignProcedure Whenusing the TPS7A6533-Q1, TPS7A6550-Q1, TI recommends adding a 10-μF to 22-μF capacitor to the input to keep the input voltage stable. TI also recommends adding a 1-μF to 10-μF low ESR ceramic capacitor to get a stableoutput. 8.2.3 ApplicationCurve Figure21. TPS7A6533-Q1LoadTransientWaveform Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com 9 Power Supply Recommendations The device is designed to operate from an input-voltage supply range from 7 V to 40 V. This input supply must be well regulated. If the input supply is located more than a few inches from the TPS7A65-Q1 device, TI recommendsaddinganelectrolyticcapacitorwithavalueof10 μFandaceramicbypasscapacitorattheinput. 10 Layout 10.1 Layout Guidelines For the LDO power supply, especially these high voltage and large current ones, layout is an important step. If layout is not carefully designed, the regulator could not deliver enough output current because of the thermal limitation. To improve the thermal performance of the device, and maximize the current output at high ambient temperature, TI recommends spreading the thermal pad as large as possible and putting enough thermal vias on thethermalpad. 10.1.1 PowerDissipationandThermalConsiderations CalculatethepowerdissipatedinthedeviceusingEquation1. P =I ×(V -V )+I ×V D OUT IN OUT) QUIESCENT IN where • P =continuouspowerdissipation D • I =outputcurrent OUT • V =inputvoltage IN • V =outputvoltage OUT • I =quiescentcurrent. (1) QUIESCENT I <<I ;therefore,ignorethetermI × V inEquation1. QUIESCENT OUT QUIESCENT IN For a device under operation at a given ambient air temperature (T ), calculate the junction temperature (T ) A J usingEquation2. T =T +(θ ×P ) J A JA D where • θ =junction-to-ambientairthermalimpedance. (2) JA CalculatetheriseinjunctiontemperatureduetopowerdissipationusingEquation3. ΔT=T –T =(θ ×P ) (3) J A JA D For a given maximum junction temperature (T ), calculate the maximum ambient air temperature (T ) at J-Max A-Max whichthedevicecanoperateusingEquation4. T =T –(θ ×P ) (4) A-Max J-Max JA D Example If I = 100 mA, V = 5 V, V = 14 V, I = 250 µA and θ = 30˚C/W, the continuous power dissipated OUT OUT IN QUIESCENT JA inthedeviceis0.9W.Theriseinjunctiontemperature due to power dissipation is 27˚C. For a maximum junction temperatureof150˚C,maximumambientairtemperatureatwhichthedevicecanoperateis123˚C. For adequate heat dissipation, TI recommends soldering the power pad (exposed heat sink) to the thermal land pad on the PCB. Doing this provides a heat conduction path from the die to the PCB and reduces overall packagethermalresistance.Figure22showspowerderatingcurves for the TPS7A65-Q1 family of devices in the KVU(DPAK)package. 16 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 Layout Guidelines (continued) 4 3.5 3 W) JESD 51-5 (KVU) d ( 2.5 e at sip 2 JESD 51-3 (KVU) s Di er w 1.5 o P 1 0.5 0 0 25 50 75 100 125 150 AmbientAir Temperature (°C) Figure22. PowerDeratingCurves For optimum thermal performance, TI recommends using a high-K PCB with thermal vias between the ground plane and solder pad or thermal land pad. Figure 23 (a) and (b) show this. Further, a design can improve the heat-spreading capabilities of a PCB considerably by using a thicker ground plane and a thermal land pad with a largersurfacearea. Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com Layout Guidelines (continued) ExposedTab Thermal Via Thermal Land Pad PCB Ground Plane (a) Before soldering (b)After soldering Figure23. UsingaMultilayerPCBandThermalViasforAdequateHeatDissipation Keeping other factors constant, the surface area of the thermal land pad contributes to heat dissipation only to a certain extent. Figure 24 shows the variation of θ with surface area of the thermal land pad (soldered to the JA exposedpad)fortheKVUpackage. 55 50 45 W) KVU (DPAK) (JESD 51-3) C/ ° ( A J q 40 35 30 0 200 400 600 800 1000 Thermal PadArea (sq. mm) Figure24. θ vsThermalPadArea JA 18 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 www.ti.com SLVSA98F–MAY2010–REVISEDMARCH2020 10.2 Layout Example GND VIN VOUT Figure25. LayoutRecommendation Copyright©2010–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS7A65-Q1

TPS7A65-Q1 SLVSA98F–MAY2010–REVISEDMARCH2020 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.2 Community Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight fromtheexperts.Searchexistinganswersoraskyourownquestiontogetthequickdesignhelpyouneed. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do notnecessarilyreflectTI'sviews;seeTI'sTermsofUse. 11.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©2010–2020,TexasInstrumentsIncorporated ProductFolderLinks:TPS7A65-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS7A6533QKVURQ1 ACTIVE TO-252 KVU 3 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 7A6533Q1 & no Sb/Br) TPS7A6550QKVURQ1 ACTIVE TO-252 KVU 3 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 7A6550Q1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 7-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS7A6533QKVURQ1 TO-252 KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 TPS7A6550QKVURQ1 TO-252 KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS7A6533QKVURQ1 TO-252 KVU 3 2500 340.0 340.0 38.0 TPS7A6550QKVURQ1 TO-252 KVU 3 2500 340.0 340.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE KVU0003A TO-252 - 2.52 mm max height SCALE 1.500 TO-252 10.41 9.40 6.22 1.27 B A 5.97 0.89 1 2.29 6.70 2 5.460 6.35 4.58 4.953 3 0.890 3X 1.02 0.635 OPTIONAL NOTE 3 0.61 0.25 C A B 0.61 2.52 MAX C 0.46 0.61 0.46 SEE DETAIL A 5.21 MIN 3 4.32 2 4 MIN 1 EXPOSED 0.51 THERMAL PAD GAGE PLANE NOTE 3 0.13 0 -8 1.78 0.00 1.40 DETA 7.000AIL A TYPICAL 4218915/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Shape may vary per different assembly sites. 4. Reference JEDEC registration TO-252. www.ti.com

EXAMPLE BOARD LAYOUT KVU0003A TO-252 - 2.52 mm max height TO-252 2X (2.75) (6.15) 2X (1) 1 4 SYMM (4.58) (5.55) 3 (R0.05) TYP (4.2) (2.5) PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4218915/A 02/2017 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004). 6. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN KVU0003A TO-252 - 2.52 mm max height TO-252 (1.18) TYP 2X (2.75) 2X (1) (0.14) 1 (R0.05) (1.33) TYP SYMM (4.58) 4 3 20X (1.13) (4.2) 20X (0.98) PKG SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 65% PRINTED SOLDER COVERAGE BY AREA SCALE:8X 4218915/A 02/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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