(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 (cid:1) Open Drain Power-On Reset With 200 ms PWP PACKAGE Delay (TPS777xx) (TOP VIEW) (cid:1) Open Drain Power Good (TPS778xx) GND/HSINK 1 20 GND/HSINK (cid:1) 750-mA Low-Dropout Voltage Regulator GND/HSINK 2 19 GND/HSINK (cid:1) Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed GND 3 18 NC NC 4 17 NC Output and Adjustable Versions (cid:1) EN 5 16 RESET/PG Dropout Voltage to 260 mV (Typ) at 750 mA IN 6 15 FB/NC (TPS77x33) IN 7 14 OUT (cid:1) Ultralow 85 (cid:1)A Typical Quiescent Current NC 8 13 OUT (cid:1) Fast Transient Response GND/HSINK 9 12 GND/HSINK (cid:1) GND/HSINK 10 11 GND/HSINK 2% Tolerance Over Specified Conditions for Fixed-Output Versions NC − No internal connection (cid:1) 8-Pin SOIC and 20-Pin TSSOP PowerPAD (PWP) Package D PACKAGE (cid:1) (TOP VIEW) Thermal Shutdown Protection GND 1 8 RESET/PG description EN 2 7 FB/NC TPS777xx and TPS778xx are designed to have a IN 3 6 OUT fast transient response and be stable with a 10 µF IN 4 5 OUT low ESR capacitor. This combination provides high performance at a reasonable cost. TPS77x33 DROPOUT VOLTAGE vs TPS77x33 FREE-AIR TEMPERATURE LOAD TRANSIENT RESPONSE 103 e in− mV 50 CESoR = =2 x14/27x µ1F00 mΩ age − mV 110021 IO = 750 mA ∆V− ChangOutput Voltage −500 VVIO = = 4 3.3.3 V V olt O V ut mA 1000 Dropo 100 IO = 10 mA ent − 500 − rr O u VD 10−1 ut C 0 p ut 10−2 Co = 10 µF IO = 0 I − OO −60 −40 −20 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160 180 200 TA − Free-Air Temperature − °C t − Time − µs Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (cid:2)(cid:16)(cid:18)(cid:29)(cid:19)(cid:30)(cid:1)(cid:25)(cid:18)(cid:24) (cid:29)(cid:22)(cid:1)(cid:22) (cid:13)(cid:31)!"#(cid:26)$(cid:14)(cid:13)"(cid:31) (cid:13)% &’##((cid:31)(cid:14) $% "! )’*+(cid:13)&$(cid:14)(cid:13)"(cid:31) ,$(cid:14)(- (cid:2)#",’&(cid:14)% Copyright  1999 − 2004, Texas Instruments Incorporated1 &"(cid:31)!"#(cid:26) (cid:14)" %)(&(cid:13)!(cid:13)&$(cid:14)(cid:13)"(cid:31)% )(# (cid:14)(cid:15)( (cid:14)(#(cid:26)% "! (cid:1)(.$% (cid:25)(cid:31)%(cid:14)#’(cid:26)((cid:31)(cid:14)% %(cid:14)$(cid:31),$#, (cid:12)$##$(cid:31)(cid:14)/- (cid:2)#",’&(cid:14)(cid:13)"(cid:31) )#"&(%%(cid:13)(cid:31)0 ,"(% (cid:31)"(cid:14) (cid:31)(&(%%$#(cid:13)+/ (cid:13)(cid:31)&+’,( (cid:14)(%(cid:14)(cid:13)(cid:31)0 "! $++ )$#$(cid:26)((cid:14)(#%-

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 260 mV at an output current of 750 mA for the TPS77x33) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 µA over the full range of output current, 0 mA to 750 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at T = 25°C. J The RESET output of the TPS777xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS777xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. Power good (PG) of the TPS778xx is an active high output, which can be used to implement a power-on reset or a low-battery indicator. The TPS777xx and TPS778xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V for the TPS77701 option and 1.2 V to 5.5 V for the TPS77801 option). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS777xx and TPS778xx families are available in 8-pin SOIC and 20-pin PWP packages. AVAILABLE OPTIONS OUTPUT VOLTAGE PACKAGED DEVICES (V) TTJJ TSSOP SOIC TYP (PWP) (D) 3.3 TPS77733PWP TPS77833PWP TPS77733D TPS77833D 2.5 TPS77725PWP TPS77825PWP TPS77725D TPS77825D 1.8 TPS77718PWP TPS77818PWP TPS77718D TPS77818D 1.5 TPS77715PWP TPS77815PWP TPS77715D TPS77815D −−4400°°CC ttoo 112255°°CC Adjustable TPS77701PWP — TPS77701D — 1.5 V to 5.5 V Adjustable — TPS77801PWP — TPS77801D 1.2 V to 5.5 V The TPS77x01 is programmable using an external resistor divider (see application information). The D and PWP packages are available taped and reeled. Add an R suffix to the device type (e.g., TPS77701DR). 6 RESET/ 16 VI IN RESET/PG PG 7 IN 14 OUT VO 0.1 µF 5 13 EN OUT Co(1) + 10 µF GND 3 (1)See application information section for capacitor selection details. Figure 1. Typical Application Configuration for Fixed Output Options 2

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 functional block diagram—adjustable version IN EN PG or RESET _ + OUT + 200 ms Delay R1 _ (for RESET Option) Vref = 1.1834 V FB/NC R2 GND External to the device functional block diagram—fixed-voltage version IN EN PG or RESET _ + OUT + 200 ms Delay _ (for RESET Option) R1 Vref = 1.1834 V R2 GND 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 Terminal Functions SOIC Package (TPS777xx) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. EN 2 I Enable input FB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options) GND 1 Regulator ground IN 3, 4 I Input voltage OUT 5, 6 O Regulated output voltage RESET 8 O RESET output TSSOP Package (TPS777xx) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. EN 5 I Enable input FB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options) GND 3 Regulator ground GND/HSINK 1, 2, 9, 10, 11, Ground/heatsink 12, 19, 20 IN 6, 7 I Input NC 4, 8, 17, 18 No connect OUT 13, 14 O Regulated output voltage RESET 16 O RESET output SOIC Package (TPS778xx) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. EN 2 I Enable input FB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options) GND 1 Regulator ground IN 3, 4 I Input voltage OUT 5, 6 O Regulated output voltage PG 8 O PG output TSSOP Package (TPS778xx) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. EN 5 I Enable input FB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options) GND 3 Regulator ground GND/HSINK 1, 2, 9, 10, 11, Ground/heatsink 12, 19, 20 IN 6, 7 I Input NC 4, 8, 17, 18 No connect OUT 13, 14 O Regulated output voltage PG 16 O PG output 4

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 TPS777xx RESET timing diagram VI Vres(1) Vres t VO VIT+(2) VIT+(2) Threshold Voltage Less than 5% of the VIT−(2) output voltage VIT−(2) t RESET Output 200 ms 200 ms Delay Delay ÎÎ ÎÎ OutputÎÎ ÎÎ Output Undefined Undefined ÎÎ ÎÎ ÎÎ ÎÎ t ÎÎ ÎÎ (1)Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. (2)VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage. 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)(1) Input voltage range(2), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V I Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16.5 V Maximum RESET voltage (TPS777xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Maximum PG voltage (TPS778xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Output voltage, V (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 − FREE-AIR TEMPERATURES AIR FLOW TA < 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE (CFM) POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING 0 568 mW 5.68 mW/°C 312 mW 227 mW DD 250 904 mW 9.04 mW/°C 497 mW 361 mW DISSIPATION RATING TABLE 2 − FREE-AIR TEMPERATURES AIR FLOW TA < 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE (CFM) POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING 0 2.9 W 23.5 mW/°C 1.9 W 1.5 W PPWWPP§§ 300 4.3 W 34.6 mW/°C 2.8 W 2.2 W 0 3 W 23.8 mW/°C 1.9 W 1.5 W PPWWPP¶¶ 300 7.2 W 57.9 mW/°C 4.6 W 3.8 W (1)This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5 in × 5 in PCB, 1 oz. copper, 2 in × 2 in coverage (4 in2). (2)This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5 in × 2 in PCB, 1 oz. copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002. recommended operating conditions MIN MAX UNIT Input voltage, VI(1) 2.7 10 V TPS77701 1.5 5.5 OOuuttppuutt vvoollttaaggee rraannggee,, VVOO VV TPS77801 1.2 5.5 Operating junction temperature, TJ −40 125 °C (1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. 6

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 electrical characteristics over recommended operating temperature range (TJ = −40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C VO TTPPSS7777770011 1.5 V ≤ VO ≤ 5.5 V, 0.98VO 1.02VO 1.2 V ≤ VO ≤ 5.5 V, TJ = 25°C VO TTPPSS7777880011 1.2 V ≤ VO ≤ 5.5 V, 0.98VO 1.02VO TJ = 25°C, 2.7 V < VIN < 10 V 1.5 TTPPSS7777xx1155 TJ = −40°C to 125°C, 2.7 V < VIN < 10 V 1.470 1.530 OOuuttppuutt vvoollttaaggee ((1100 µAA ttoo 775500 mmAA llooaadd)) VV TJ = 25°C, 2.8 V < VIN < 10 V 1.8 TTPPSS7777xx1188 TJ = −40°C to 125°C, 2.8 V < VIN < 10 V 1.764 1.836 TJ = 25°C, 3.5 V < VIN < 10 V 2.5 TTPPSS7777xx2255 TJ = −40°C to 125°C, 3.5 V < VIN < 10 V 2.450 2.550 TJ = 25°C, 4.3 V < VIN < 10 V 3.3 TTPPSS7777xx3333 TJ = −40°C to 125°C, 4.3 V < VIN < 10 V 3.234 3.366 10 µA < IO < 750 mA, TJ = 25°C 85 QQuuiieesscceenntt ccuurrrreenntt ((GGNNDD ccuurrrreenntt)) µAA IO = 750 mA 125 Output voltage line regulation (∆VO/VO) VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.01 %/V Load regulation 3 mV Output noise voltage (TPS77x18) BW = 200 Hz to 100 kHz, Co = 10 µF, 54 µVrms TJ = 25°C, IC = 750 µA Output current limit VO = 0 V 1.2 1.7 2 A Thermal shutdown junction temperature 150 °C EN = VI, TJ = 25°C, 1 µA 2.7 V < VI < 10 V SSttaannddbbyy ccuurrrreenntt EN = VI, 10 µA 2.7 V < VI < 10 V FB input current TPS77x01 FB = 1.5 V 2 nA High level enable input voltage 1.7 V Low level enable input voltage 0.9 V f = 1 KHz, Co = 10 µF, Power supply ripple rejection 60 dB TJ = 25°C Minimum input voltage for valid RESET IO(RESET) = 300 µA 1.1 V Trip threshold voltage VO decreasing 92 98 %VO RReesseett Hysteresis voltage Measured at VO 0.5 %VO ((TTPPSS777777xxxx)) Output low voltage VI = 2.7 V, IO(RESET) = 1 mA 0.15 0.4 V Leakage current V(RESET) = 5 V 1 µA RESET time-out delay 200 ms 7

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(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) EQUIVALENT SERIES RESISTANCE(1) vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Ω Region of Instability Ω Region of Instability − − e ance stanc st si Resi 1 s Re 1 ent Series VTCVAIOo = === 4 243.35..73 °V C µVF Region of Stability alent Serie CVTVJIOo = = == 4 1 43.23..753 V ° µVCF Region of Stability quival 0.1 Equiv 0.1 E − − R R S S E Region of Instability E Region of Instability 0.01 0.01 0 125 250 375 500 625 750 0 125 250 375 500 625 750 IO − Output Current − mA IO − Output Current − mA Figure 21 Figure 22 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) EQUIVALENT SERIES RESISTANCE(1) vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Ω Region of Instability Ω Region of Instability − ce e − n c a n Resist 1 esista 1 es VO = 3.3 V s R ent Seri VTCAIo = == 4 22.352 ° VµCF Region of Stability nt Serie VTCVJIOo = = == 4 1 23.232.53 Vµ° VCF Region of Stability quival 0.1 uivale 0.1 E q SR − R − E E Region of Instability S Region of Instability E 0.01 0.01 0 125 250 375 500 625 750 0 125 250 375 500 625 750 IO − Output Current − mA IO − Output Current − mA Figure 23 Figure 24 (1)Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 14

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 APPLICATION INFORMATION The TPS777xx and TPS778xx families include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3V), and an adjustable regulator, the TPS77x01 (adjustable from 1.5 V to 5.5 V for TPS77701 option and 1.2V to 5.5 V for TPS77801 option). device operation The TPS777xx and TPS778xx feature very low quiescent current, which remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (I = I /β). The TPS777xx and TPS778xx use a PMOS transistor to pass current; because the gate B C of the PMOS is voltage driven, operating current is low and invariable over the full load range. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates to large start-up currents. B Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS777xx and TPS778xx quiescent currents remain low even when the regulator drops out, eliminating both problems. The TPS777xx and TPS778xx families also feature a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdown feature is not used, EN should be tied to ground. minimum load requirements The TPS777xx and TPS778xx families are stable even at zero load; no minimum load is required for operation. FB—pin connection (adjustable version only) The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output voltage is sensed through a resistor divider network to close the loop as it is shown in Figure 26. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit to improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is essential. external capacitor requirements An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improves load transient response and noise rejection if the TPS777xx or TPS778xx are located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Like all low dropout regulators, the TPS777xx and TPS778xx require an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR (equivalent series resistance) must be between 50 mΩ and 1.5 Ω. Capacitor values 10 µF or larger are acceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously. 15

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(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:4)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:3)(cid:17)(cid:1) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:10)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:9)(cid:11)(cid:11) (cid:12)(cid:13)(cid:14)(cid:15) (cid:2)(cid:20) (cid:18)(cid:19)(cid:1)(cid:2)(cid:19)(cid:1) (cid:21)(cid:22)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:22)(cid:24)(cid:3)(cid:25)(cid:17)(cid:24)(cid:1)(cid:23)(cid:16)(cid:17)(cid:3)(cid:2)(cid:18)(cid:24)(cid:3)(cid:17) (cid:4)(cid:8)(cid:5)(cid:23)(cid:26)(cid:22) (cid:27)(cid:18)(cid:28)(cid:23)(cid:29)(cid:16)(cid:18)(cid:2)(cid:18)(cid:19)(cid:1) (cid:27)(cid:25)(cid:24)(cid:17)(cid:22)(cid:16) (cid:16)(cid:17)(cid:20)(cid:19)(cid:27)(cid:22)(cid:1)(cid:18)(cid:16)(cid:3) www.ti.com SLVS230G − SEPTEMBER 1999 − REVISED JANUARY 2004 APPLICATION INFORMATION reset indicator The TPS777xx features a RESET output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer to timing diagram for start-up sequence). power-good indicator The TPS778xx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as a low-battery indicator. regulator protection The TPS777xx and TPS778xx PMOS-pass transistors have a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS777xx and TPS778xx also feature internal current limiting and thermal protection. During normal operation, the TPS777xx and TPS778xx limit output current to approximately 1.7 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. 17

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PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS77701D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77701 & no Sb/Br) TPS77701DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77701 & no Sb/Br) TPS77701PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77701 & no Sb/Br) TPS77701PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77701 & no Sb/Br) TPS77715D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77715 & no Sb/Br) TPS77715DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77715 & no Sb/Br) TPS77715PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77715 & no Sb/Br) TPS77715PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77715 & no Sb/Br) TPS77718D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77718 & no Sb/Br) TPS77718DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77718 & no Sb/Br) TPS77718DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77718 & no Sb/Br) TPS77718PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77718 & no Sb/Br) TPS77718PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77718 & no Sb/Br) TPS77718PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77718 & no Sb/Br) TPS77725D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77725 & no Sb/Br) TPS77725PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77725 & no Sb/Br) TPS77725PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77725 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS77725PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77725 & no Sb/Br) TPS77733D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77733 & no Sb/Br) TPS77733DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77733 & no Sb/Br) TPS77733PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77733 & no Sb/Br) TPS77733PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77733 & no Sb/Br) TPS77801D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77801 & no Sb/Br) TPS77801DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77801 & no Sb/Br) TPS77801DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77801 & no Sb/Br) TPS77801PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77801 & no Sb/Br) TPS77801PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77801 & no Sb/Br) TPS77801PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77801 & no Sb/Br) TPS77801PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77801 & no Sb/Br) TPS77815D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77815 & no Sb/Br) TPS77815DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77815 & no Sb/Br) TPS77815PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77815 & no Sb/Br) TPS77815PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77815 & no Sb/Br) TPS77815PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77815 & no Sb/Br) TPS77818D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77818 & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS77818PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77818 & no Sb/Br) TPS77818PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77818 & no Sb/Br) TPS77818PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77818 & no Sb/Br) TPS77818PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77818 & no Sb/Br) TPS77825D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77825 & no Sb/Br) TPS77825DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77825 & no Sb/Br) TPS77825PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77825 & no Sb/Br) TPS77825PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77825 & no Sb/Br) TPS77833D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77833 & no Sb/Br) TPS77833DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 77833 & no Sb/Br) TPS77833PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77833 & no Sb/Br) TPS77833PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 PT77833 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS77701DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77701PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77715DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77718DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77718PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77725PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77733DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77733PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77801DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77801PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77815DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77815PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77818PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77825DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77825PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS77833DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS77833PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS77701DR SOIC D 8 2500 350.0 350.0 43.0 TPS77701PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS77715DR SOIC D 8 2500 350.0 350.0 43.0 TPS77718DR SOIC D 8 2500 350.0 350.0 43.0 TPS77718PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77725PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77733DR SOIC D 8 2500 350.0 350.0 43.0 TPS77733PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77801DR SOIC D 8 2500 350.0 350.0 43.0 TPS77801PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77815DR SOIC D 8 2500 350.0 350.0 43.0 TPS77815PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77818PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77825DR SOIC D 8 2500 350.0 350.0 43.0 TPS77825PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 TPS77833DR SOIC D 8 2500 350.0 350.0 43.0 TPS77833PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0 PackMaterials-Page2

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