Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 (cid:1) Open Drain Power-On Reset With 220-ms TPS771xx Delay (TPS771xx) DGK Package (cid:1) Open Drain Power-Good (PG) Status (TOP VIEW) Output (TPS772xx) FB/SENSE 1 8 OUT (cid:1) 150-mA Low-Dropout Voltage Regulator RESET 2 7 OUT (cid:1) Available in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, EN 3 6 IN 5.0-V Fixed Output and Adjustable Versions GND 4 5 IN (cid:1) Dropout Voltage Typically 115 mV at 150 mA (TPS77133, TPS77233) TPS772xx (cid:1) Ultralow 92-µA Quiescent Current (Typ) DGK Package (TOP VIEW) (cid:1) 8-Pin MSOP (DGK) Package (cid:1) Low Noise (55 µV ) Without External FB/SENSE 1 8 OUT rms Filter (Bypass) Capacitor (TPS77118, PG 2 7 OUT TPS77218) EN 3 6 IN (cid:1) GND 4 5 IN 2% Tolerance Over Specified Conditions for Fixed-Output Versions TPS77x33 (cid:1) Fast Transient Response DROPOUT VOLTAGE (cid:1) Thermal Shutdown Protection vs JUNCTION TEMPERATURE 300 description The TPS771xx and TPS772xx are low-dropout 250 regulators with integrated power-on reset and V power good (PG) function respectively. These m 200 devices are capable of supplying 150 mA of output e – IO = 150 mA current with a dropout of 115 mV (TPS77133, g a TPS77233). Quiescent current is 92 µA at full load olt 150 V dropping down to 1 µA when device is disabled. ut These devices are optimized to be stable with a po 100 o wide range of output capacitors including low ESR Dr IO = 10 mA ceramic (10µF) or low capacitance (1µF) – O 50 tantalum capacitors. These devices have ex- D IO = 0 A V tremely low noise output performance (55 µV ) rms 0 without using any added filter capacitors. TPS771xx and TPS772xx are designed to have fast transient response for larger load current –50 –40 0 40 80 120 160 changes. TJ – Junction Temperature – °C The TPS771xx or TPS772xx is offered in 1.5 V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK) packages. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 µA over the full range of output current, 0 mA to 150 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 description (continued) The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at T = 25°C. J The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS) or reset output voltage. The RESET output of the TPS771xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after a 220 ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage. For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage. AVAILABLE OPTIONS OUTPUT VOLTAGE PACKAGED DEVICES (V) MSOP (DGK) TTJ TPS771xx TPS772xx TYP SYMBOL SYMBOL 5.0 TPS77150DGK AFV TPS77250DGK AGE 3.3 TPS77133DGK AFU TPS77233DGK AGD 2.8 TPS77128DGK AFS TPS77228DGK AGB 2.7 TPS77127DGK AFR TPS77227DGK AGA ––4400°°CC ttoo 112255°°CC 1.8 TPS77118DGK AFP TPS77218DGK AFY 1.5 TPS77115DGK AFO TPS77215DGK AFX Adjustable TPS77101DGK AFN TPS77201DGK AFW 1.5 V to 5.5 V NOTE: The TPS77101 and TPS77201 are programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77101DGKR). 5 7 VI IN OUT VO 6 8 IN OUT 1 SENSE 0.1 µF 3 EN PG or 2 PG or RESET RESET + 10 µF GND 4 Figure 1. Typical Application Configuration (For Fixed Output Options) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 functional block diagrams adjustable version IN EN PG or RESET _ + OUT + 220 ms Delay R1 _ (for TPS771xx Option) Vref = 1.1834 V FB/SENSE R2 GND External to the Device fixed-voltage version IN EN PG or RESET _ + OUT SENSE + 220 ms Delay _ (for TPS771xx Option) R1 Vref = 1.1834 V R2 GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. TPS771XX FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) RESET 2 O Reset output EN 3 I Enable input GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage TPS772XX FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) PG 2 O Power good EN 3 I Enable input GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage TPS771xx RESET timing diagram VI Vres† Vres† t VO VIT+‡ VIT+‡ Threshold Voltage VIT–‡ VIT–‡ t RESET Output 220 ms 220 ms Delay Delay ÎÎ ÎÎ Output ÎÎ ÎÎOutput Undefined Undefined ÎÎ ÎÎ ÎÎ ÎÎ t †Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TPS772xx PG timing diagram VI Vres† Vres† t VO VIT+‡ VIT+‡ Threshold Voltage VIT–‡ VIT–‡ t PG Output ÎÎ ÎÎ OutputÎÎ ÎÎ Output Undefined Undefined ÎÎ ÎÎ ÎÎ ÎÎt †Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡VIT – Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage. (cid:1) absolute maximum ratings over operating junction temperature range (unless otherwise noted) Input voltage range, V, (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 13.5 V I Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V Maximum RESET voltage (TPS771xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Maximum PG voltage (TPS772xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output voltage, V (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V O Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network terminal ground. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES AIR FLOW θJA θJC TA < 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE (CFM) (°C/W) (°C/W) POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING 0 266.2 3.84 376 mW 3.76 mW/°C 207 mW 150 mW DDGGKK 150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW 250 242.8 4.21 412 mW 4.12 mW/°C 227 mW 165 mW recommended operating conditions MIN MAX UNIT Input voltage, VI† 2.7 10 V Output voltage range, VO 1.5 5.5 V Output current, IO (see Note 2) 0 150 mA Operating virtual junction temperature, TJ (see Note 2) –40 125 °C † To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 2: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 electrical characteristics over recommended operating junction temperature range (–40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C VO AAddjjuussttaabbllee vvoollttaaggee VV 1.5 V ≤ VO ≤ 5.5 V 0.98VO 1.02VO TJ = 25°C, 2.7 V < VIN < 10 V 1.5 11.55-VV OOuuttppuutt 2.7 V < VIN < 10 V 1.470 1.530 TJ = 25°C, 2.8 V < VIN < 10 V 1.8 11.88-VV OOuuttppuutt 2.8 V < VIN < 10 V 1.764 1.836 OOuuttpuutt vvoollttaaggee TJ = 25°C, 3.7 V < VIN < 10 V 2.7 22.77-VV OOuuttppuutt VV (see Notes 3 and 4) 3.7 V < VIN < 10 V 2.646 2.754 TJ = 25°C, 3.8 V < VIN < 10 V 2.8 22.88-VV OOuuttppuutt 3.8 V < VIN < 10 V 2.744 2.856 TJ = 25°C, 4.3 V < VIN < 10 V 3.3 33.33-VV OOuuttppuutt 4.3 V < VIN < 10 V 3.234 3.366 TJ = 25°C, 6 V < VIN < 10 V 5.0 55.00-VV OOuuttppuutt VV 6 V < VIN < 10 V 4.900 5.100 TJ = 25°C 92 QQuuiieesscceenntt ccuurrrreenntt ((GGNNDD ccuurrrreenntt)) ((sseeee NNootteess 33 aanndd 44)) µAA 125 VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.005 %/V OOuuttppuutt vvoollttaaggee lliinnee rreegguullaattiioonn ((∆∆VVO//VVO)) ((sseeee NNoottee 55)) VO + 1 V < VI ≤ 10 V 0.05 %/V Load regulation TJ = 25°C 1 mV Output noise voltage BW = 300 Hz to 100 kHz, TJ = 25°C, 55 µVrms TPS77118, TPS77218 Output current Limit VO = 0 V 0.9 1.3 A Peak output current 2 ms pulse width, 50% duty cycle 400 mA Thermal shutdown junction temperature 144 °C EN = VI, TJ = 25°C 1 µA SSttaannddbbyy ccuurrrreenntt EN = VI 3 µA FB input current Adjustable voltage FB = 1.5 V 1 µA High level enable input voltage 2 V Low level enable input voltage 0.7 V Enable input current –1 1 µA Power supply ripple rejection (TPS77118, TPS77218) f = 1 KHz, TJ = 25°C 55 dB NOTES: 3. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output current 1mA. 4. If VO < 1.8 V then VI(max) = 10 V, VI(min) = 2.7 V: (cid:2) (cid:4) V V (cid:6)2.7V O I(max) Lineregulation(mV) (cid:1) (cid:2)%(cid:3)V(cid:4) (cid:5) (cid:5)1000 100 If VO > 2.5 V then VI(max) = 10 V, VI(min) = Vo + 1 V: (cid:2) (cid:2) (cid:4)(cid:4) V V (cid:6) V (cid:7)1 O I(max) O Lineregulation(mV) (cid:1) (cid:2)%(cid:3)V(cid:4) (cid:5) (cid:5)1000 100 5. IO = 1 mA to 150 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 electrical characteristics over recommended operating junction temperature range (–40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Minimum input voltage for valid PG I(PG) = 300µA V(PG) ≤ 0.8 V 1.1 V Trip threshold voltage VO decreasing 79 85 %VO PPGG Hysteresis voltage Measured at VO 0.5 %VO ((TTPPSS777722xxxx)) Output low voltage VI = 2.7 V, I(PG) = 1mA 0.15 0.4 V Leakage current V(PG) = 5 V 1 µA Minimum input voltage for valid RESET I(RESET) = 300 µA 1.1 V Trip threshold voltage VO decreasing 92 98 %VO RReesseett Hysteresis voltage Measured at VO 0.5 %VO (TPS771xx) Output low voltage VI = 2.7 V, I(RESET) = 1 mA 0.15 0.4 V Leakage current V(RESET) = 5 V 1 µA RESET time-out delay 220 ms IO = 150 mA, TJ = 25°C 150 22.88-VV OOuuttppuutt IO = 150 mA, 265 IO = 150 mA, TJ = 25°C 115 VVDO DDrrooppoouutt vvoollttaaggee ((sseeee NNoottee 66)) 33.33-VV OOuuttppuutt mmVV IO = 150 mA 200 IO = 150 mA, TJ = 25°C 75 55.00-VV OOuuttppuutt IO = 150 mA 115 NOTE 6: IN voltage equals VO(typ) – 100 mV; 1.5 V, 1.8 V, and 2.7 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage needs to drop to 3.2 V for purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 2, 3 VVO OOuuttppuutt vvoollttaaggee vs Junction temperature 4, 5 Ground current vs Junction temperature 6 Power supply rejection ratio vs Frequency 7 Output spectral noise density vs Frequency 8 Zo Output impedance vs Frequency 9 vs Input voltage 10 VVDO DDrrooppoouutt vvoollttaaggee vs Junction temperature 11 Line transient response 12, 14 Load transient response 13, 15 Output voltage and enable pulse vs Time 16 Equivalent series resistance (ESR) vs Output current 18 – 21 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x33 TPS77x18 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT 3.302 1.802 3.301 1.801 V V – – e e g g a a olt olt V V ut 3.3 ut 1.800 p p ut ut O O – – O O V V 3.299 1.799 3.298 1.798 0 50 100 150 0 50 100 150 IO – Output Current – mA IO – Output Current – mA Figure 2 Figure 3 TPS77x33 TPS77x18 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 3.35 1.86 VI = 4.3 V VI = 2.8 V 3.33 1.84 V V – – e IO = 150 mA e g g a 3.31 a 1.82 Volt Volt IO = 150 mA ut ut p p ut 3.29 ut 1.80 O O – – O O V V 3.27 1.78 3.25 1.76 –40 0 40 80 120 160 –40 0 40 80 120 160 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77xxx GROUND CURRENT vs JUNCTION TEMPERATURE 115 110 IO = 150 mA A 105 µ – ent 100 r r u C nd 95 IO = 1 mA u o r G 90 85 80 –40 10 60 110 160 TJ – Junction Temperature – °C Figure 6 TPS77x33 TPS77x33 POWER SUPPLY REJECTION RATIO OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY 100 10 – dB 90 IO = 1 mA CTJO = = 2 150° CµF Hz CTJO = = 2 150° CµF atio 80 µV IO = 150 mA R – ection 7600 ensity 1 IO = 1 mA ej D R e ply 50 ois p N Su 40 al ower 30 IO = 150 mA Spectr 0.1 – P 20 ut RR utp S 10 O P 0 0.01 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k f – Frequency – Hz f – Frequency – Hz Figure 7 Figure 8 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x33 OUTPUT IMPEDANCE vs FREQUENCY 10 IO = 1 mA Ω – e 1 c n a d e p m ut I p Out 0.1 – o Z IO = 150 mA 0.01 10 100 1k 10k 100k 1M 10M f – Frequency – Hz Figure 9 TPS77x01 TPS77x33 DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs INPUT VOLTAGE JUNCTION TEMPERATURE 250 300 IO = 150 mA 250 200 TJ = 125 °C V V ge – m TJ = 25 °C ge – m 200 IO = 150 mA Volta 150 TJ = –40 °C Volta 150 ut ut po po 100 o 100 o – Dr – Dr IO = 10 mA O O 50 D D IO = 0 A V V 50 0 0 –50 2.7 3.2 3.7 4.2 4.7 –40 0 40 80 120 160 VI – Input Voltage – V TJ – Junction Temperature – °C Figure 10 Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x18 TPS77x18 LINE TRANSIENT RESPONSE A LOAD TRANSIENT RESPONSE m – V nt e – 3.8 urre 150 g C olta ut ut V 2.8 Outp 0 np – – I I O VI 10 V nm V 0 ge ie – 0 ∆V– Change inOutput Voltage – m –10 CTIOJO == = 12 15500° C µmFA ∆V– ChanOOutput Voltag ––15000 CTIOJO == = 12 15500° C µmFA O 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t – Time – ms t – Time – ms Figure 12 Figure 13 TPS77x33 TPS77x33 LINE TRANSIENT RESPONSE A LOAD TRANSIENT RESPONSE m – nt V e nge inge – m 5.3 ut Curr 150 aa 4.3 p 0 Cholt ut ∆V– Output V I – OO O +10 V Voltage – 0 nge inge – mV 0 V– Input I –10 CTIOJO == = 12 15500° C µmFA ∆V– ChaOutput Volta––15000 CTIOJO == = 12 15500° C µmFA O 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t – Time – ms t – Time – ms Figure 14 Figure 15 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TPS77x33 OUTPUT VOLTAGE AND ENABLE PULSE vs TIME (AT STARTUP) e – V EN CTJO = = 2 150° CµF s ul P e 0 bl a n E V – e g a olt V ut p ut O – 0 O V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 t – Time – ms Figure 16 To Load VI IN OUT + CO RL EN GND ESR Figure 17. Test Circuit for Typical Regions of Stability (Figures 18 through 21) (Fixed Output Options) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† EQUIVALENT SERIES RESISTANCE† vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Region of Instability Ω Region of Instability Ω – – e e sistanc CVVIOO = == 4 3.13. 3 µV FV sistanc 1 Re TJ = 25°C Re s s e e Seri 1 Seri Region of Stability nt nt e e al al uiv Region of Stability uiv 0.1 q q VO = 3.3 V – E – E CO = 10 µF R R VI = 4.3 V ES ES TJ = 25°C Region of Instability Region of Instability 0.1 0.01 0 50 100 150 0 50 100 150 IO – Output Current – mA IO – Output Current – mA Figure 18 Figure 19 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† EQUIVALENT SERIES RESISTANCE† vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Region of Instability Region of Instability Ω Ω Resistance – CVTVJIOO == == 41 3.123. 53 µV F°VC Resistance – 1 Series 1 Series Region of Stability nt nt uivale Region of Stability uivale 0.1 ESR – Eq ESR – Eq CVTVJIOO == == 41 3.123.053 V ° µVCF Region of Instability Region of Instability 0.1 0.01 0 50 100 150 0 50 100 150 IO – Output Current – mA IO – Output Current – mA Figure 20 Figure 21 †Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. power good (PG) (TPS772xx) The PG terminal is an open drain, active high output that indicates the status of V (output of the LDO). When out Vout reaches 82% of the regulated voltage, PG will go to a high-impedance state. It will go to a low-impedance state when V falls below 82% (i.e. over load condition) of the regulated voltage. The open drain output of the out PG terminal requires a pullup resistor . sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and V to filter noise is not recommended because it may cause the regulator to oscillate. out feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and V to filter noise is not out recommended because it may cause the regulator to oscillate. reset (RESET) (TPS771xx) The RESET terminal is an open drain, active low output that indicates the status of V . When V reaches 95% out out of the regulated voltage, RESET will go to a high-impedance state after a 220-ms delay. RESET will go to a low-impedance state when V is below 95% of the regulated voltage. The open-drain output of the RESET out terminal requires a pullup resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION external capacitor requirements An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load transient response and noise rejection if the TPS771xx or TPS772xx is located more than a few inches from the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board space. The TPS771xx and TPS772xx have very low noise specification requirements without using any external components. Like all low dropout regulators, the TPS771xx or TPS772xx requires an output capacitor connected between OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum recommended capacitance value is 1 µF provided the ESR meets the requirement in Figures 19 and 21. In addition, a low-ESR capacitor can be used if the capacitance is at least 10 µF and the ESR meets the requirements in Figures 18 and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously. Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature; therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the requirement specified in Figures 18 – 21. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage. IO LDO – VESR RESR + + VI VO RLOAD – CO Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V = V . This means no current is flowing into the C Cout out) out branch. If I suddenly increases (transient condition), the following occurs: out (cid:1) The LDO is not able to supply the sudden current need due to its response time (t in Figure 23). Therefore, 1 capacitor C provides the current for the new load condition (dashed arrow). C now acts like a battery out out with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at R . This voltage is shown as V in Figure 22. ESR ESR (cid:1) When C is conducting current to the load, initial voltage at the load will be V = V – V . Due to out out Cout ESR the discharge of C , the output voltage V will drop continuously until the response time t of the LDO out out 1 is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t in Figure 23. 2 The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: (cid:1) The higher the ESR, the larger the droop at the beginning of load transient. (cid:1) The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. Iout Vout 1 2 3 ESR 1 ESR 2 ESR 3 t1 t2 Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of V at a out Load Step From Low-to-High Output Current 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION programming the TPS77x01 adjustable LDO regulator The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using: (cid:2) (cid:4) V (cid:1)V (cid:5) 1(cid:7)R1 (1) O ref R2 Where: V = 1.1834 V typ (the internal reference voltage) ref Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1kΩ to set the divider current at 50 µA and then calculate R1 using: (cid:2) (cid:4) V R1(cid:1) O (cid:6)1 (cid:5)R2 (2) V ref OUTPUT VOLTAGE TPS77x01 PROGRAMMING GUIDE OUTPUT R1 R2 UNIT VI IN PG or PG or RESET Output VOLTAGE 0.1 µF RESET 2.5 V 33.5 30.1 kΩ 250 kΩ 3.3 V 53.8 30.1 kΩ EN OUT VO 3.6 V 61.5 30.1 kΩ R1 CO NOTE: To reduce noise and prevent FB/SENSE oscillation, R1 and R2 need to be as GND close as possible to the FB/SENSE R2 terminal. Figure 24. TPS77x01 Adjustable LDO Regulator Programming POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

Obsolete Devices: TPS77127, TPS77201, TPS77215, TPS77218 TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000 APPLICATION INFORMATION regulator protection The TPS771xx or TPS772xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS771xx or TPS772xx also features internal current limiting and thermal protection. During normal operation, the TPS771xx or TPS772xx limits output current to approximately 0.9 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P , and the actual dissipation, P , which must be less than D(max) D or equal to P . D(max) The maximum-power-dissipation limit is determined using the following equation: T max(cid:6)T P (cid:1) J A D(max) R(cid:1)JA Where: TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package, i.e., 266.2°C/W for the 8-terminal MSOP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: (cid:2) (cid:4) P (cid:1) V (cid:6)V (cid:5)I D I O O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS77101DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFN & no Sb/Br) TPS77101DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFN & no Sb/Br) TPS77101DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFN & no Sb/Br) TPS77115DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFO & no Sb/Br) TPS77115DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFO & no Sb/Br) TPS77118DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFP & no Sb/Br) TPS77128DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFS & no Sb/Br) TPS77133DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AFU & no Sb/Br) TPS77133DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AFU & no Sb/Br) TPS77133DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 AFU & no Sb/Br) TPS77150DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFV & no Sb/Br) TPS77150DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFV & no Sb/Br) TPS77150DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFV & no Sb/Br) TPS77201DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFW & no Sb/Br) TPS77218DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AFY & no Sb/Br) TPS77227DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AGA & no Sb/Br) TPS77233DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AGD & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS77250DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AGE & no Sb/Br) TPS77250DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 AGE & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS77101DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS77115DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS77133DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS77150DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS77101DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TPS77115DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TPS77133DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TPS77150DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 PackMaterials-Page2

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