(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 (cid:1) 100-mA Low-Dropout Regulator DBV PACKAGE (cid:1) (TOP VIEW) Adjustable Output Voltage (0.7 V to 5.5 V) (cid:1) Only 23 µA Quiescent Current at 100 mA IN 1 5 OUT (cid:1) 1 µA Quiescent Current in Standby Mode GND 2 (cid:1) Over Current Limitation (cid:1) −40°C to 125°C Operating Junction EN 3 4 FB Temperature Range (cid:1) 5-Pin SOT-23 (DBV) Package GROUND CURRENT vs description JUNCTION TEMPERATURE 27 VI = 2.7 V The TPS76201 low-dropout (LDO) voltage VO = 0.7 V IO = 100 mA 25 regulator features an adjustable output voltage as A low as 0.7 V. It is an ideal regulator for sub 1.2-V µ 23 DfoSr Ps icmoirlaer voalptapglieca stiuopnpsl iewsi tahn do tihse er qluoawll-yv oslutaitgeed ent − 21 IO = 10 µA processors and controllers. SOT-23 packaging Curr and the high-efficiency that results from the und 19 o regulator’s ultralow power operation make the Gr 17 TPS76201 especially useful in handheld and portable battery applications. This regulator 15 features low dropout voltages and ultralow −40−25−10 5 20 35 50 65 80 95 110125 TJ − Junction Temperature − °C quiescent current compared to conventional LDO regulators. Offered in a 5-terminal small outline integrated-circuit SOT-23 package, the TPS76201 is ideal for micropower operations and where board space is at a premium. A combination of new circuit design and process innovation has enabled the usual PNP pass transistor to be replaced by a PMOS pass element. Since the PMOS pass element is a voltage-driven device, the quiescent current is ultralow (30 µA maximum) and is stable over the entire range of output load current (10 µA to 100 mA). Intended for use in portable systems such as laptops and cellular phones, the ultralow-power operation results in a significant increase in the system battery operating life. The TPS76201 also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current to 1 µA typical at T = 25°C. The TPS76201 is offered in an adjustable version (programmable over the range J of 0.7 V to 5.5 V). AVAILABLE OPTIONS† TJ VOLTAGE PACKAGE PART NUMBER SYMBOL Variable SOT-23 −40°C to 125°C TPS76201DBVT‡ TPS76201DBVR§ PFUI 0.7 V to 5.5 V (DBV) †Contact the factory for availability of fixed output options. ‡The DBVT indicates tape and reel of 250 parts. §The DBVR indicates tape and reel of 3000 parts. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (cid:2)(cid:18)(cid:10)(cid:14)(cid:12)(cid:24)(cid:1)(cid:21)(cid:10)(cid:22) (cid:14)(cid:13)(cid:1)(cid:13) (cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:20)(cid:30)(cid:31)(cid:25)(cid:28)(cid:26) (cid:25)! "#(cid:29)(cid:29)$(cid:26)(cid:31) (cid:30)! (cid:28)(cid:27) %#&’(cid:25)"(cid:30)(cid:31)(cid:25)(cid:28)(cid:26) ((cid:30)(cid:31)$) Copyright  2001−2007, Texas Instruments Incorporated (cid:2)(cid:29)(cid:28)(#"(cid:31)! "(cid:28)(cid:26)(cid:27)(cid:28)(cid:29)(cid:20) (cid:31)(cid:28) !%$"(cid:25)(cid:27)(cid:25)"(cid:30)(cid:31)(cid:25)(cid:28)(cid:26)! %$(cid:29) (cid:31)*$ (cid:31)$(cid:29)(cid:20)! (cid:28)(cid:27) (cid:1)$+(cid:30)! (cid:21)(cid:26)!(cid:31)(cid:29)#(cid:20)$(cid:26)(cid:31)! !(cid:31)(cid:30)(cid:26)((cid:30)(cid:29)( ,(cid:30)(cid:29)(cid:29)(cid:30)(cid:26)(cid:31)-) (cid:2)(cid:29)(cid:28)(#"(cid:31)(cid:25)(cid:28)(cid:26) %(cid:29)(cid:28)"$!!(cid:25)(cid:26). ((cid:28)$! (cid:26)(cid:28)(cid:31) (cid:26)$"$!!(cid:30)(cid:29)(cid:25)’- (cid:25)(cid:26)"’#($ (cid:31)$!(cid:31)(cid:25)(cid:26). (cid:28)(cid:27) (cid:30)’’ %(cid:30)(cid:29)(cid:30)(cid:20)$(cid:31)$(cid:29)!) www.ti.com 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 (cid:1) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range (cid:1)(cid:2)(cid:3)(cid:3) (cid:4)(cid:5)(cid:6)(cid:3) (cid:7)(cid:8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V I Voltage on OUT, FB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE DERATING FACTOR TA ≤ 25°C TA = 70°C TA = 85°C BOARD PACKAGE RθJC RθJA ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING Low K‡ DBV 65.8°C/W 259°C/W 3.9 mW/°C 386 mW 212 mW 154 mW High K§ DBV 65.8°C/W 180°C/W 5.6 mW/°C 555 mW 305 mW 222 mW ‡The JEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two layer board with 2 ounce copper traces on top of the board. §The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. recommended operating conditions MIN NOM MAX UNIT Input voltage, VI (see Note 2) 2.7 10 V Output voltage range, VO 0.7 5.5 V Continuous output current, IO (see Note 3) 0.01 100 mA Operating junction temperature, TJ −40 125 °C NOTES: 2. To calculate the minimum input voltage for your maximum output current, use the following formula: VImin = VOmax + VDO(max load) 3. Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. www.ti.com 2

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 electrical characteristics over recommended operating free-air temperature range, µ VI = VO(typ) + 1 V, IO = 100 mA, EN = 0 V, Co = 4.7 F (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.7 V ≤ VO ≤ 5.5 V, TJ = 25°C VO OOuuttppuutt vvoollttaaggee ((1100 µAA ttoo 110000 mmAA llooaadd)) ((sseeee NNoottee 44)) VV 0.7 V ≤ VO ≤ 5.5 V, TJ = −40°C to 125°C 0.97VO 1.03VO EN = 0V, TJ = 25°C 23 QQuuiieesscceenntt ccuurrrreenntt ((GGNNDD ccuurrrreenntt)) 10 µA < IO < 100 mA µAA (see Notes 4 and 5) EN = 0 V, TJ = −40°C to 125°C, 30 10 µA < IO < 100 mA EN = 0 V, TJ = 25°C Load regulation 12 mV 10 µA < IO < 100 mA 2.7 V < VI ≤ 10 V, TJ = 25°C, 0.04 See Note 4 OOuuttppuutt vvoollttaaggee lliinnee rreegguullaattiioonn ((∆∆VVOO//VVOO)) ((sseeee NNoottee 55)) 2.7 V < VI ≤ 10 V, %%//VV 0.1 TJ = −40°C to 125°C, See Note 4 Output noise voltage BVWO == 03.070 V H,z to 50 kHz,T J C =o 2 =5 °1C0 µF, 60 µVRMS Output current limit VO = 0 V, See Note 4 350 750 mA EN = VI, 2.7 < VI < 10 V 1 µA SSttaannddbbyy ccuurrrreenntt TJ = −40°C to 125°C 2 µA FB input current FB = 0.666 V −1 1 µA High level enable input voltage 2.7 V < VI < 10 V 1.7 V Low level enable input voltage 2.7 V < VI < 10 V 0.8 V f = 1 kHz, Co = 10 µF, Power supply ripple rejection 60 dB TJ = 25°C, See Note 4 EN = 0 V −1 0 1 µA IInnppuutt ccuurrrreenntt ((EENN)) EN = VI −1 1 µA NOTES: 4. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 10 V, minimum output current 10 µA, maximum output current 100 mA. 5. If VO≤ 1.8 V then VImin = 2.7 V, VImax = 10 V: (cid:2) (cid:4) V V (cid:6)2.7V LineReg.(mV) (cid:1) (cid:2)%(cid:3)V(cid:4) (cid:5) O Imax (cid:5)1000 100 If VO ≥ 2.5 V then VImin = VO + 1 V, VImax = 10 V: (cid:2) (cid:2) (cid:4)(cid:4) V V (cid:6) V (cid:7)1V O Imax O LineReg.(mV) (cid:1) (cid:2)%(cid:3)V(cid:4) (cid:5) (cid:5)1000 100 www.ti.com 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 functional block diagram TPS76201 IN OUT EN Current Limit / Thermal VREF Protection FB GND Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. GND 2 Ground EN 3 I Enable input FB 4 I Feedback voltage IN 1 I Input supply voltage OUT 5 O Regulated output voltage TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 1, 2 VVOO OOuuttppuutt vvoollttaaggee vs Junction temperature 3 Ground current vs Junction temperature 4 Output spectral noise density vs Frequency 5 zo Output impedance vs Frequency 6 vs Input voltage 7 VVDDOO DDrrooppoouutt vvoollttaaggee vs Junction temperature 8 Power supply ripple rejection vs Frequency 9 Output voltage and enable voltage vs Time (start-up) 10 Line transient response 11, 13 Load transient response 12, 14 Equivalent series resistance (ESR) vs Output current 15, 16 www.ti.com 4

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs vs OUTPUT CURRENT OUTPUT CURRENT JUNCTION TEMPERATURE 2.520 0.720 0.6680 V− Output Voltage − VO222222......445555990011050505 VVCTJIOo = = == 3 2 42.55..7°5 V CµVF V− Output Voltage − VO 00000.....677779001150505 VVCTJIOo = = == 2 2 40.57..7°7 V CµVF V− Output Voltage − VO00000.....66666666665667750505 VVCIOo = == 2 4V.7.r7 eV µfF IO =I O10 =0 1m mAA 2.485 0.690 0.6650 2.480 0.685 0.6645 0 20 40 60 80 100 0 20 40 60 80 100 −40−25−10 5 20 35 50 65 80 95110125 IO − Output Current − mA IO − Output Current − mA TJ − Junction Temperature − °C Figure 1 Figure 2 Figure 3 GROUND CURRENT OUTPUT SPECTRAL NOISE DENSITY OUTPUT IMPEDANCE vs vs vs JUNCTION TEMPERATURE FREQUENCY FREQUENCY 27 500 3.5 µA 2235 VVIO = = 2 0.7.7 V V IO = 100 mA VHzsity − n 344505000 VVICOIOo = = == 2 1 40. 7.m.77 V A µV,F, Ωance − 2.235 VVCRIOoE = S == R2 40. 7.≈.77 V 0 µV.F3 Ground Current − 112791 IO = 10 µA ut Spectral Noise Den 112230505000000 − Output Impedzo −100...10555 IO = 1 mAIO = 100 mA utp 50 −1 15 O 0 −1.5 −40−25−10 5 20 35 50 65 80 95 110125 100 1 k 10 k 100 k 10 100 1k 10 k 100 k 1 M TJ − Junction Temperature − °C f − Frequency − Hz f − Frequency − Hz Figure 4 Figure 5 Figure 6 DROPOUT VOLTAGE DROPOUT VOLTAGE POWER SUPPLY RIPPLE REJECTION vs vs vs INPUT VOLTAGE JUNCTION TEMPERATURE FREQUENCY 180 1000 90 V− Dropout Voltage − mVDO 1111024668000000 TTJJ = = 2 152°C5°CIO = 100 mA V− Dropout Voltage − mVDO 10100 VCIO = = 3 .42.7 V µF IOIO = = 1 100 m0 AmA ower Supply Ripple Rejection − dB 5823674100000000 IO = 100 mAIVVCOIOo = = == 2 1 40. 7.m.77 V A µVF 40 TJ = −40°C P 0 20 1 −10 2 4 6 8 10 −40−25−10 5 20 35 50 65 80 95 110125 10 100 1 k 10 k 100 k 1 M 10 M VI − Input Voltage − V TJ − Junction Temperature − °C f − Frequency − Hz Figure 7 Figure 8 Figure 9 www.ti.com 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE Enable Voltage − V 50 VVCIToJIOo = = = = = 1 2 2 400.57.0.7°7 VC m µVFA − Input Voltage − V 32..77 Current Load − mA 1000 VI V − Output Voltage − VO 0.1050 20 40 60 80 100120140 160180200 V − Output Voltage − mVO−110000 5IVCO0Oo = ==1 1 04000..7 7m 1 µVA5F0200250300350400 450 500 ∆ − Change InVO Output Voltage − mV--12000000 50 100 1502002503VVC0IO0o = == 32 510.700.7 Vµ4 VF00 450500 t − Time (Start-Up) − µs t − Time − µs t − Time − µs Figure 10 Figure 11 Figure 12 LOAD TRANSIENT RESPONSE ge − V LINE TRANSIENT RESPONSE − mA V− Input VoltaI 34..55 Current Load 1000 mV 20 100 mV − Output Voltage − −200 VICOOo = == 1 420..705 µmVFA VVCOIo = == 3 12.50.5 Vµ VF −0100 ∆ − Change InVO Output Voltage − V O 0 50 100150t 2−0 T0im25e0 −3 µ0s0 350400450 500 0 20 40 60t 8−0 Ti1m0e0 −1 2µ0s 140160180 200 Figure 13 Figure 14 TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) EQUIVALENT SERIES RESISTANCE (ESR) vs vs OUTPUT CURRENT OUTPUT CURRENT 100 100 ΩESR − Equivalent Series Resistance − 101 RegRioeng ioofn I nosf tIanbsCitliaotyb =ili t4y.7 µF ΩESR − Equivalent Series Resistance − 101 RegioRne goifo Inn sotfa IbnilsittyaCboili t=y 10 µF 0.1 0.1 0 0.02 0.04 0.06 0.08 0.10 0 0.02 0.04 0.06 0.08 0.10 IO − Output Current − A IO − Output Current − A Figure 15 Figure 16 www.ti.com 6

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 APPLICATION INFORMATION The TPS76201 low-dropout (LDO) regulator has been optimized for use in battery-operated equipment including, but not limited to, the sub 1.2-V DSP core voltage supplies. It features low quiescent current (23 µA nominally) and enable inputs to reduce supply currents to 1 µA when the regulators are turned off. A typical application circuit is shown in Figure 17. TPS76201 1 VI IN 5 OUT VO C1 1 µF 3 EN 4 + FB 4.7 µF GND 2 ESR = 0.5 Ω Figure 17. Typical Application Circuit external capacitor requirements Although not required, a 0.047-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS76201, is recommended to improve transient response and noise rejection. A higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. Like all low dropout regulators, the TPS76201 requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 4.7 µF. The ESR (equivalent series resistance) of the capacitor should be between 0.3 Ω and 1.5 Ω. to ensure stability. Capacitor values larger than 4.7 µF are acceptable, and allow the use of smaller ESR values. Capacitances less than 4.7 µF are not recommended because they require careful selection of ESR to ensure stability. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Most of the commercially available 4.7 µF surface-mount solid tantalum capacitors, including devices from Sprague, Kemet, and Nichico, meet the ESR requirements stated above. Multilayer ceramic capacitors may have very small equivalent series resistances and may thus require the addition of a low value series resistor to ensure stability. CAPACITOR SELECTION PART NO. MFR. VALUE MAX ESR† SIZE (H × L × W)‡ T494B475K016AS KEMET 4.7 µF 1.5 Ω 1.9 × 3.5 × 2.8 195D106x0016x2T SPRAGUE 10 µF 1.5 Ω 1.3 × 7.0 × 2.7 695D106x003562T SPRAGUE 10 µF 1.3 Ω 2.5 × 7.6 × 2.5 TPSC475K035R0600 AVX 4.7 µF 0.6 Ω 2.6 × 6.0 × 3.2 †ESR is maximum resistance in Ohms at 100 kHz and TA = 25°C. Contact manufacturer for minimum ESR values. ‡Size is in mm. www.ti.com 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 APPLICATION INFORMATION output voltage programming The output voltage of the TPS76201 adjustable regulator is programmed using an external resistor divider as shown in Figure 18. The output voltage is calculated using: (cid:2) (cid:4) V (cid:1)V (cid:5) 1(cid:7)R1 (1) O ref R2 Where: V = 0.6663 V typ (the internal reference voltage) ref Resistors R1 and R2 should be chosen for approximately 10-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 66.5kΩ to set the divider current at 10 µA and then calculate R1 using: (cid:2) (cid:4) V R1(cid:1) O (cid:6)1 (cid:5)R2 (2) V ref OUTPUT VOLTAGE TPS76201 PROGRAMMING GUIDE OUTPUT DIVIDER RESISTANCE VOLTAGE (kΩ)‡ VI 1 IN (V) R1 R2 1 µF 0.7 3.36 66.5 OUT 5 VO 0.9 23.2 66.5 ≥1.7 V 3 R1 EN 1.2 53.6 66.5 4 1.5 83.5 66.5 ≤0.9 V FB 4.7 µF GND 1.8 113 66.5 R2 2 ESR = 0.5 Ω 2.5 182 66.5 3.3 246 66.5 3.6 294 66.5 4 332 66.5 5 432 66.5 ‡1% values shown. Figure 18. TPS76201 Adjustable LDO Regulator Programming www.ti.com 8

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8) (cid:9)(cid:10)(cid:11) (cid:10)(cid:12)(cid:1)(cid:2)(cid:12)(cid:1) (cid:13)(cid:14)(cid:15)(cid:12)(cid:3)(cid:1)(cid:13)(cid:16)(cid:9)(cid:17) (cid:12)(cid:9)(cid:1)(cid:18)(cid:13)(cid:9)(cid:10)(cid:11)(cid:19)(cid:2)(cid:10)(cid:11)(cid:17)(cid:18) (cid:8)(cid:7)(cid:7)(cid:19)(cid:20)(cid:13) (cid:9)(cid:14)(cid:10) (cid:9)(cid:21)(cid:22)(cid:17)(cid:13)(cid:18) (cid:18)(cid:17)(cid:23)(cid:12)(cid:9)(cid:13)(cid:1)(cid:10)(cid:18) SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007 APPLICATION INFORMATION power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P , and the actual dissipation, P , which must be less than D(max) D or equal to P . D(max) The maximum-power-dissipation limit is determined using the following equation: T max(cid:6)T P (cid:1) J A D(max) R(cid:1)JA Where: TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package, see the dissipation rating table. TA is the ambient temperature. The regulator dissipation is calculated using: (cid:2) (cid:4) P (cid:1) V (cid:6)V (cid:5)I D I O O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. regulator protection The TPS76201 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. The TPS76201 features internal current limiting and thermal protection. During normal operation, the TPS76201 limits output current to approximately 350 mA. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation resumes. www.ti.com 9

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) HPA00500DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 PFUI & no Sb/Br) TPS76201DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 PFUI & no Sb/Br) TPS76201DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 PFUI & no Sb/Br) TPS76201DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 PFUI & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS76201 : •Automotive: TPS76201-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS76201DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS76201DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS76201DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS76201DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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