(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 (cid:1) 3-A Low-Dropout Voltage Regulator TO−220 (KC) PACKAGE (cid:1) (TOP VIEW) Available in 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed-Output and Adjustable Versions EN 1 (cid:1) IN 2 Open Drain Power-Good (PG) Status GND 3 Output (Fixed Options Only) OUTPUT 4 (cid:1) FB/PG 5 Dropout Voltage Typically 150 mV at 3 A (TPS75733) TO−263 (KTT) PACKAGE (cid:1) Low 125 µA Typical Quiescent Current (TOP VIEW) (cid:1) Fast Transient Response EN 1 (cid:1) 3% Tolerance Over Specified Conditions for IN 2 Fixed-Output Versions GND 3 (cid:1) Available in 5-Pin TO−220 and TO−263 OUTPUT 4 Surface-Mount Packages FB/PG 5 (cid:1) Thermal Shutdown Protection description The TPS757xx family of 3-A low dropout (LDO) regulators contains four fixed voltage option regulators with integrated power-good (PG) and an adjustable voltage option regulator. These devices are capable of supplying 3 A of output current with a dropout of 150 mV (TPS75733). Therefore, the device is capable of performing a 3.3-V to 2.5-V conversion. Quiescent current is 125 µA at full load and drops down to less than 1 µA when the device is disabled. The TPS757xx is designed to have fast transient response for large load current changes. TPS75733 DROPOUT VOLTAGE vs TPS75715 JUNCTION TEMPERATURE LOAD TRANSIENT RESPONSE 250 150 IO = 3 A mV VO = 1.5 V VO = 3.3 V − 100 Co = 100 µF e ge − mV 200 ut Voltag 50 olta 150 utp 0 V O − Dropout 100 Change in −−15000 ddti(cid:1)0.7(cid:1)5sA 4rent − A O − ur D O C V 50 ∆V−150 2put ut 0O − 0 I O −40 −25 −10 5 20 35 50 65 80 95 110 125 0 20 40 60 80 100 120 140 160 180 200 TJ − Junction Temperature − °C t − Time − µs Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:2)(cid:16)(cid:14)(cid:18)(cid:25)(cid:27)(cid:1)(cid:12)(cid:14)(cid:20) (cid:18)(cid:19)(cid:1)(cid:19) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$(- Copyright  2009, Texas Instruments Incorporated (cid:2)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $.( $(!"% (cid:31)(cid:30) (cid:1)(/#% (cid:12)(cid:29)%$!’"((cid:29)$% %$#(cid:29),#!, 0#!!#(cid:29)$1- (cid:2)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is low (typically 150 mV at an output current of 3 A for the TPS75733) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and independent of output loading (typically 125 µA over the full range of output current). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when EN is connected to a low-level voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at T = 25°C. The power-good terminal (PG) is an active low, open drain output, which can be used to J implement a power-on reset or a low-battery indicator. The TPS757xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.22 V to 5 V). Output voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The TPS757xx family is available in a 5-pin TO−220 (KC) and TO−263 (KTT) packages. AVAILABLE OPTIONS OUTPUT VOLTAGE TJ (TYP) TO−220 (KC) TO−263(KTT) 3.3 V TPS75733KC TPS75733KTT 2.5 V TPS75725KC TPS75725KTT −−4400°CC ttoo 112255°CC 1.8 V TPS75718KC TPS75718KTT 1.5 V TPS75715KC TPS75715KTT Adjustable 1.22 V to 5 V TPS75701KC TPS75701KTT NOTE: The TPS75701 is programmable using an external resistor divider (see application information). The KTT package is available taped and reeled. Add an R suffix to the device type (e.g., TPS75701KTTR) to indicate tape and reel. 2 5 VI IN PG PG 4 OUT VO 1 µF 1 EN Co† + 47 µF GND 3 †See application information section for capacitor selection details. Figure 1. Typical Application Configuration (For Fixed Output Options) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 functional block diagram—adjustable version VIN VOUT UVLO Current Sense SHUTDOWN ILIM R1 GND _ + FB EN UVLO R2 Thermal Shutdown External to the Device Vref = 1.22 V Bandgap VIN Reference functional block diagram—fixed version VIN VOUT UVLO Current Sense SHUTDOWN ILIM R1 _ + GND UVLO EN R2 Thermal Shutdown Vref = 1.22 V VIN Bandgap PG Reference Falling Edge Delay Terminal Functions (TPS757xx) TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. EN 1 I Enable input FB/PG 5 I Feedback input voltage for adjustable device/PG output for fixed options GND 3 Regulator ground IN 2 I Input voltage OUTPUT 4 O Regulated output voltage Thermal Pad − Connect to GND or Float POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 TPS757xx PG timing diagram VIN1 VUVLO VUVLO t VOUT VIT+(see Note A) Threshold Voltage VIT− (see Note A) t PG Output t NOTE: VIT −Trip voltage is typically 9% lower than the output voltage (91%VO). VIT− to VIT+ is the hysteresis voltage. detailed description The TPS757xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an adjustable regulator, the TPS75701 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V. pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, the device will be enabled. power-good (PG) The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status of VO (output of the LDO). When VO reaches approximately 91% of the regulated voltage, PG will go to a low impedance state. It will go to a high-impedance state when V falls below approximately 89% (i.e. over load O condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. feedback (FB) FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and V to filter noise is O not recommended because it may cause the regulator to oscillate. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 detailed description (continued) input voltage (IN) The V terminal is an input to the regulator. IN output voltage (OUTPUT) The V terminal is an output to the regulator. OUTPUT (cid:1) absolute maximum ratings over operating junction temperature range (unless otherwise noted) Input voltage range‡, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V I Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Maximum PG voltage (fixed options only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables Output voltage, V (OUTPUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V O Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV ESD rating, CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE PACKAGE RθJC (°C/W) RθJA (°C/W)§ TO−220 2 58.7¶ TO−263 2 38.7# §For both packages, the RθJA values were computed using JEDEC high K board (2S2P) with 1 ounce internal copper plane and ground plane. There was no air flow across the packages. ¶RθJA was computed assuming a vertical, free standing TO-220 package with pins soldered to the board. There is no heatsink attached to the package. #RθJA was computed assuming a horizontally mounted TO-263 package with pins soldered to the board. There is no copper pad underneath the package. recommended operating conditions MIN MAX UNIT Input voltage, VI|| 2.8 5.5 V Output voltage range, VO 1.22 5 V Output current, IO 0 3 A Operating virtual junction temperature, TJ −40 125 °C || To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 electrical characteristics over recommended operating junction temperature range (T = −40°C to J 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 100 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.22 V ≤ VO ≤ 5.5 V, TJ = 25°C VO 1.22 V ≤ VO ≤ 5.5 V 0.97 VO 1.03 VO AAddjjuussttaabbllee vvoollttaaggee VV 1.22 V ≤ VO ≤ 5.5 V, TJ = 0 to 125°C (see Note 1) 0.98 VO 1.02 VO TJ = 25°C, 2.8 V < VI < 5.5 V 1.5 11..55 VV OOuuttppuutt VV OOuuttppuutt vvoollttaaggee 2.8 V ≤ VI ≤ 5.5 V 1.455 1.545 ((sseeee NNoottee 22)) TJ = 25°C, 2.8 V < VI < 5.5 V 1.8 11..88 VV OOuuttppuutt VV 2.8 V ≤ VI ≤ 5.5 V 1.746 1.854 TJ = 25°C, 3.5 V < VI < 5.5 V 2.5 22..55 VV OOuuttppuutt VV 3.5 V ≤ VI ≤ 5.5 V 2.425 2.575 TJ = 25°C, 4.3 V < VI < 5.5 V 3.3 33..33 VV OOuuttppuutt VV 4.3 V ≤ VI ≤ 5.5 V 3.201 3.399 QQuuiieesscceenntt ccuurrrreenntt ((GGNNDD ccuurrrreenntt)) TJ = 25°C 125 µAA (see Notes 2 and 3) 200 OOuuttppuutt vvoollttaaggee lliinnee rreegguullaattiioonn ((∆∆VVOO//VVOO)) VO + 1 V ≤ VI ≤ 5.5 V, TJ = 25°C 0.04 %%//VV (see Note 3) VO + 1 V ≤ VI < 5.5 V 0.1 Load regulation (see Note 2) 0.35 %/V Output noise voltage TPS75715 BW = 300 Hz to 50 kHz, TJ = 25°C, VI = 2.8 V 35 µVrms Output current limit VO = 0 V 5.5 10 14 A Thermal shutdown junction temperature 150 °C EN = VI, TJ = 25°C 0.1 µA SSttaannddbbyy ccuurrrreenntt EN = VI 10 µA FB input current TPS75701 FB = 1.5 V −1 1 µA Power supply ripple f = 100 Hz, TJ = 25°C, TPS75715 62 dB rejection VI = 2.8 V, IO = 3 A Minimum input voltage for valid PG IO(PG) = 300 µA, V(PG) ≤ 0.8 V 0 V PG trip threshold voltage Fixed options only VO decreasing 89 93 %VO PG hysteresis voltage Fixed options only Measured at VO 0.5 %VO PG output low voltage Fixed options only VI = 2.8 V, IO(PG) = 1 mA 0.15 0.4 V PG leakage current Fixed options only V(PG) = 5 V 1 µA NOTES: 1. The adjustable option operates with a 2% tolerance over TJ = 0 to 125 °C. 2. IO = 1 mA to 3 A 3. If VO ≤ 2.5 V then VImin = 2.8 V, VImax = 5.5 V: (cid:2) (cid:4) V V (cid:6)2.8V Lineregulation(mV) (cid:1) (cid:2)%(cid:3)V(cid:4) (cid:5) O Imax (cid:5)1000 100 If VO > 2.5 V then VImin = VO + 1 V, VImax = 5.5 V: (cid:2) (cid:2) (cid:4)(cid:4) V V (cid:6) V (cid:7)1V O Imax O Lineregulation(mV) (cid:1) (cid:2)%(cid:3)V(cid:4) (cid:5) (cid:5)1000 100 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 electrical characteristics over recommended operating junction temperature range (T = −40°C to J 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 100 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN = VI −1 1 µA IInnppuutt ccuurrrreenntt ((EENN)) EN = 0 V −1 0 1 µA High level EN input voltage 2 V Low level EN input voltage 0.7 V IO = 3 A, VI = 3.2 V, TJ = 25°C 150 DDrrooppoouutt vvoollttaaggee,, ((33..33 VV oouuttppuutt)) ((sseeee NNoottee 44)) mmVV VVOO IO = 3 A, VI = 3.2 V 300 Discharge transistor current VO = 1.5 V, TJ = 25°C 10 25 mA UVLO TJ = 25°C, VI rising 2.2 2.75 V VVII UVLO hysteresis TJ = 25°C, VI falling 100 mV NOTE 4: IN voltage equals VO(typ) − 100 mV; TPS75715, TPS75718, and TPS75725 dropout voltage limited by input voltage range limitations (i.e., TPS75733 input voltage is set to 3.2 V for the purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 2, 3 VVOO OOuuttppuutt vvoollttaaggee vs Junction temperature 4, 5 Ground current vs Junction temperature 6 Power supply ripple rejection vs Frequency 7 Output spectral noise density vs Frequency 8 zo Output impedance vs Frequency 9 vs Input voltage 10 VVDDOO DDrrooppoouutt vvoollttaaggee vs Junction temperature 11 VI Minimum required input voltage vs Output voltage 12 Line transient response 13, 15 Load transient response 14, 16 VO Output voltage and enable voltage vs Time (start-up) 17 Equivalent series resistance vs Output current 19, 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS TPS75733 TPS75715 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT 3.345 1.545 VI = 4.3 V VI = 2.8 V TJ = 25°C TJ = 25°C 3.330 1.530 V V − 3.315 − 1.515 e e g g a a olt olt V 3.3 V 1.5 ut ut p p ut ut O O − 3.285 − 1.485 O O V V 3.270 1.470 3.255 1.455 0 1 2 3 0 1 2 3 IO − Output Current − A IO − Output Current − A Figure 2 Figure 3 TPS75733 TPS75715 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 3.345 1.545 VI = 4.3 V VI = 2.8 V 3.33 1.530 V V − 3.315 − 1.515 e e g g a a olt olt V 3.3 V 1.5 ut ut p p ut ut O O − 3.285 − 1.485 O O V V 3.270 1.470 3.255 1.455 −40 −25 10 5 20 35 50 65 80 95 110125 −40−25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 4 Figure 5 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS TPS757xx TPS75733 GROUND CURRENT POWER SUPPLY RIPPLE REJECTION vs vs JUNCTION TEMPERATURE FREQUENCY 150 90 VI = 5 V B VI = 4.3 V IO = 3 A n − d 80 CTJo == 2150°0C µF o 70 ecti IO = 1 mA A 125 Rej 60 µnt − pple 50 urre y Ri 40 C pl Ground 100 wer Sup 3200 Po IO = 3 A − 10 R R S 0 P 75 −40 −25 −10 5 20 35 50 65 80 95 110 125 10 100 1k 10k 100k 1M 10M TJ − Junction Temperature − °C f − Frequency − Hz Figure 6 Figure 7 TPS75733 TPS75733 OUTPUT SPECTRAL NOISE DENSITY OUTPUT IMPEDANCE vs vs FREQUENCY FREQUENCY 2.5 100 Hz VVIO = = 4 3.3.3 V V 10 VCIo = = 4 1.30 0V µF µV/− 2 TCJo == 2150°0C µF Ω ITOJ == 12 5m°CA IO = 1 mA nsity nce − 1 De 1.5 da 0.1 e IO = 3 A pe s m Noi IO = 1 mA ut I 0.01 ctral 1 Outp IO = 3 A pe − 0.001 S o ut z p 0.5 ut O 0.0001 0 0.00001 1100 100 1k 10k 100k 10 100 1k 10k 100k 1M 10M f − Frequency − Hz f − Frequency − Hz Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS TPS75701 TPS75733 DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs INPUT VOLTAGE JUNCTION TEMPERATURE 250 250 IO = 3 A IO = 3 A TJ = 125°C VO = 3.3 V 200 V 200 V m m ge − TJ = 25°C age − olta 150 Volt 150 ut V TJ = −40°C out o p p o ro 100 Dr 100 − D − O O D D V V 50 50 0 0 2.5 3 3.5 4 4.5 5 −40 −25 −10 5 20 35 50 65 80 95 110 125 VI − Input Voltage − V TJ − Junction Temperature − °C Figure 10 Figure 11 MINIMUM REQUIRED INPUT VOLTAGE vs TPS75715 OUTPUT VOLTAGE LINE TRANSIENT RESPONSE 4 IO = 3 A V VO = 1.5 V ge − V TJ = 125°C nge inge − m 50 ICOo = = 31 0A0 µF olta TJ = 25°C Chaolta 0 nput V TJ = −40°C ∆V− Output V −50 d I O re 3 −100 ui Req 2.8 − V m ge u a nim Volt 3.8 Mi ut − p VI − In 2.8 2 VI 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 0 50 100 150 200 250 300 350 400 450 500 VO − Output Voltage − V t − Time − µs Figure 12 Figure 13 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS TPS75715 V TPS75733 m LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE − 150 ge 100 e − mV 100 CVOo == 110.50 VµF ut Volta 50 ICVOOo = == 3 13 0A.30 VµF g p olta 50 Out 0 V n ut e i p 0 g −50 Out han e in −50 A − C−100 Chang−100 ddti(cid:1)0.7(cid:1)5sA 4rent − ∆VO ge − V ∆− VO−150 2put Cur 5.3ut Volta 0− Out 4.3− Inp I O VI 0 20 40 60 80 100 120 140 160 180 200 0 50 100 150 200 250 300 350 400 450 500 t − Time − µs t − Time − µs Figure 14 Figure 15 TPS75733 OUTPUT VOLTAGE AND ENABLE VOLTAGE TPS75733 vs LOAD TRANSIENT RESPONSE TIME (START-UP) V m − V utput Voltage 120000 VCOo == 130.30 VµF put Voltage − 3.3 VITOJI === 412.053 ° mVCA O ut n 0 O e i − hang−100 ddti(cid:1)0.7(cid:1)5sA A VO 0 − CVO 4 ent − − V4.3 ∆ rr e u g 2 ut C olta 0 p V 0 Out ble − na I O E 0 20 40 60 80 100 120 140 160 180 200 0 0.2 0.4 0.6 0.8 1 t − Time − µs t − Time (Start-Up) − ms Figure 16 Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS To Load VI IN OUT + Co RL EN GND ESR Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options) TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† EQUIVALENT SERIES RESISTANCE† vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Ωce − CTJo = = 2 658°C0 µF Ωe − CTJo == 2457° CµF n c a n esist sista R 1 e 1 es Region of Stability s R Region of Stability eri rie S e ent nt S val ale 0.2 qui 0.1 uiv E q SR − R − E Region of Instability E S E 0.015 Region of Instability 0.01 0.01 0 1 2 3 0 1 2 3 IO − Output Current − A IO − Output Current − A Figure 19 Figure 20 †Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 THERMAL INFORMATION The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (T max) J above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (T ) does not exceed the maximum junction temperature (T max). The J J two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (P ) consumed by a linear regulator is computed as: D(max) (cid:2) (cid:4) P max(cid:1) V (cid:6)V (cid:5)I (cid:7) V xI (1) D I(avg) O(avg) O(avg) I(avg) (Q) Where: V is the average input voltage. I(avg) V is the average output voltage. O(avg) I is the average output current. O(avg) I is the quiescent current. (Q) For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term V x I can be neglected. The operating junction temperature is computed by adding I(avg) (Q) the ambient temperature (T ) and the increase in temperature due to the regulator’s power dissipation. The A temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RθJC), the case to heatsink (RθCS), and the heatsink to ambient (RθSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object’s thermal resistance. Figure 21 illustrates these thermal resistances for (a) a TO−220 package attached to a heatsink, and (b) a TO−263 package mounted on a JEDEC High-K board. C B A TJ A RθJC A B B TC RθCS C RθSA C TO−263 Package TA (b) TO−220 Package (a) Figure 21. Thermal Resistances POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 THERMAL INFORMATION Equation 2 summarizes the computation: (cid:2) (cid:4) T (cid:1) T (cid:7)P maxx R (cid:7) R (cid:7) R (2) J A D θJC θCS θSA The RθJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator’s datasheet. The RθSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks, like the one attached to the TO−220 package in Figure 21(a), can have RθCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small heatsinks. The RθCS is a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a TO−220 package, RθCS of 1°C/W is reasonable. Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted will provide some heatsinking through the pin solder connections. Some packages, like the TO−263 and TI’s TSSOP PowerPAD packages, use a copper plane underneath the package or the circuit board’s ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal modeling can be used to compute very accurate approximations of an integrated circuit’s thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RθJA). This RθJA is valid only for the specific operating environment used in the computer model. Equation 2 simplifies into equation 3: TJ (cid:1) TA(cid:7)PDmaxx RθJA (3) Rearranging equation 3 gives equation 4: T –T R (cid:1) J A (4) θJA P max D Using equation 3 and the computer model generated curves shown in Figures 22 and 25, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment. PowerPAD is a trademark of Texas Instruments. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 THERMAL INFORMATION TO−220 power dissipation The TO−220 package provides an effective means of managing power dissipation in through-hole applications. The TO−220 package dimensions are provided in the Mechanical Data section at the end of the data sheet. A heatsink can be used with the TO−220 package to effectively lower the junction-to-ambient thermal resistance. To illustrate, the TPS75725 in a TO−220 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P max (cid:1) (3.3–2.5)Vx3A (cid:1) 2.4W (5) D Substituting T max for T into equation 4 gives equation 6: J J RθJAmax (cid:1) (125–55)°C(cid:3)2.4W (cid:1) 29°C(cid:3)W (6) From Figure 22, RθJA vs Heatsink Thermal Resistance, a heatsink with RθSA = 22°C/W is required to dissipate 2.4 W. The model operating environment used in the computer model to construct Figure 22 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Since the package pins were soldered to the board, 450 mm2 of the board was modeled as a heatsink. Figure 23 shows the side view of the operating environment used in the computer model. THERMAL RESISTANCE vs HEATSINK THERMAL RESISTANCE 65 Natural Convection W 55 C/ ° − Air Flow = 150 LFM e 45 nc Air Flow = 250 LFM a st Air Flow = 500 LFM esi 35 R al m er 25 h T − A J 15 θ R No Heatsink 5 25 20 15 10 5 0 RθSA − Heatsink Thermal Resistance − °C/W Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 THERMAL INFORMATION TO−220 power dissipation (continued) 0.21 mm 0.21 mm 1 oz. Copper 1 oz. Copper Power Plane Ground Plane Figure 23 From the data in Figure 22 and rearranging equation 4, the maximum power dissipation for a different heatsink RθSA and a specific ambient temperature can be computed (see Figure 24). POWER DISSIPATION vs HEATSINK THERMAL RESISTANCE 10 TA = 55°C W Air Flow = 500 LFM − mit Air Flow = 250 LFM Li n o ati Air Flow = 150 LFM p si s Di r e w o P − D P Natural Convection No Heatsink 1 20 10 0 RθSA − Heatsink Thermal Resistance − °C/W Figure 24 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 THERMAL INFORMATION TO−263 power dissipation The TO−263 package provides an effective means of managing power dissipation in surface mount applications. The TO−263 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the TO−263 package enhances the thermal performance of the package. To illustrate, the TPS75725 in a TO−263 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P max (cid:1) (3.3–2.5)Vx3A (cid:1) 2.4W (7) D Substituting T max for T into equation 4 gives equation 8: J J RθJAmax (cid:1) (125–55)°C(cid:3)2.4W (cid:1) 29°C(cid:3)W (8) From Figure 25, RθJA vs Copper Heatsink Area, the ground plane needs to be 2 cm2 for the part to dissipate 2.4 W. The model operating environment used in the computer model to construct Figure 25 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows the side view of the operating environment used in the computer model. THERMAL RESISTANCE vs COPPER HEATSINK AREA 40 No Air Flow W C/ 35 ° − e 150 LFM c n a st 30 si e R 250 LFM al m r 25 e h T − A J Rθ 20 15 0 0.01 0.1 1 10 100 Copper Heatsink Area − cm2 Figure 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 THERMAL INFORMATION TO−263 power dissipation (continued) 2 oz. Copper Solder Pad with 25 Thermal Vias 1 oz. Copper Power Plane 1 oz. Copper Ground Plane Thermal Vias, 0.3 mm Diameter, 1.5 mm Pitch Figure 26 From the data in Figure 25 and rearranging equation 4, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (see Figure 27). MAXIMUM POWER DISSIPATION vs COPPER HEATSINK AREA 5 TA = 55°C W − n atio 4 250 LFM p si s Di r 150 LFM e w 3 o P m u m xi No Air Flow a M 2 − D P 1 0 0.01 0.1 1 10 100 Copper Heatsink Area − cm2 Figure 27 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 APPLICATION INFORMATION programming the TPS75701 adjustable LDO regulator The output voltage of the TPS75701 adjustable regulator is programmed using an external resistor divider as shown in Figure 28. The output voltage is calculated using: (cid:2) (cid:4) V (cid:1)V (cid:5) 1(cid:7)R1 (9) O ref R2 Where: V = 1.224 V typ (the internal reference voltage) ref Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1kΩ to set the divider current at 40 µA and then calculate R1 using: (cid:2) (cid:4) V R1(cid:1) O (cid:6)1 (cid:5)R2 (10) V ref TPS75701 OUTPUT VOLTAGE PROGRAMMING GUIDE VI IN 1 µF OUTPUT ≥2 V VOLTAGE R1 R2 UNIT EN OUT VO 2.5 V 31.4 30.1 kΩ ≤0.7 V R1 Co 3.3 V 51 30.1 kΩ FB 3.6 V 58.3 30.1 kΩ GND R2 Figure 28. TPS75701 Adjustable LDO Regulator Programming regulator protection The TPS757xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS757xx also features internal current limiting and thermal protection. During normal operation, the TPS757xx limits output current to approximately 10 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:9)(cid:5)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:10)(cid:10) (cid:11)(cid:12)(cid:1)(cid:13) (cid:2)(cid:14)(cid:11)(cid:15)(cid:16) (cid:17)(cid:14)(cid:14)(cid:18) (cid:19)(cid:20)(cid:18) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:21)(cid:6) (cid:22)(cid:19)(cid:3)(cid:1)(cid:23)(cid:1)(cid:16)(cid:19)(cid:20)(cid:3)(cid:12)(cid:15)(cid:20)(cid:1) (cid:16)(cid:15)(cid:3)(cid:2)(cid:14)(cid:20)(cid:3)(cid:15) (cid:10)(cid:23)(cid:19) (cid:24)(cid:14)(cid:11)(cid:23)(cid:18)(cid:16)(cid:14)(cid:2)(cid:14)(cid:25)(cid:1) (cid:26)(cid:14)(cid:24)(cid:1)(cid:19)(cid:17)(cid:15) (cid:16)(cid:15)(cid:17)(cid:25)(cid:24)(cid:19)(cid:1)(cid:14)(cid:16)(cid:3) SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009 APPLICATION INFORMATION input capacitor For a typical application, a ceramic input bypass capacitor (0.22 µF − 1 µF) is recommended to ensure device stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply, large transient currents will cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO threshold, the device will turn off. Therefore, it is recommended that a larger capacitor be placed in parallel with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor depends on the output current, response time of the main power supply, and the main power supply’s distance to the regulator. At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum UVLO threshold voltage during normal operating conditions. output capacitor As with most LDO regulators, the TPS757xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF with an ESR (equivalent series resistance) of at least 200 mΩ. As shown in Figure 29, most capacitor and ESR combinations with a product of 47e−6 x 0.2 = 9.4e−6 or larger will be stable, provided the capacitor value is at least 47 µF. Solid tantalum electrolytic and aluminum electrolytic capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors provide a wider range of stability and better load transient response. This information along with the ESR graphs, Figures 19, 20, and 29, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines. OUTPUT CAPACITANCE vs EQUIVALENT SERIES RESISTANCE 1000 Region of Stability F µ − e c n a cit ESR min x Co = Constant pa 100 a C ut p ut 47 O Region of Instability Y = ESRmin x Co 10 0.01 0.1 0.2 ESR − Equivalent Series Resistance − Ω Figure 29 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS75701KC ACTIVE TO-220 KC 5 50 Green (RoHS Call TI | SN N / A for Pkg Type -40 to 125 75701 & no Sb/Br) TPS75701KCG3 ACTIVE TO-220 KC 5 50 Green (RoHS SN N / A for Pkg Type -40 to 125 75701 & no Sb/Br) TPS75701KTTR ACTIVE DDPAK/ KTT 5 500 Green (RoHS Call TI | SN Level-2-260C-1 YEAR -40 to 125 75701 TO-263 & no Sb/Br) TPS75701KTTRG3 ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 75701 TO-263 & no Sb/Br) TPS75715KC ACTIVE TO-220 KC 5 50 Green (RoHS Call TI | SN N / A for Pkg Type -40 to 125 75715 & no Sb/Br) TPS75715KTTR ACTIVE DDPAK/ KTT 5 500 Green (RoHS Call TI | SN Level-2-260C-1 YEAR -40 to 125 75715 TO-263 & no Sb/Br) TPS75718KC ACTIVE TO-220 KC 5 50 Green (RoHS Call TI | SN N / A for Pkg Type -40 to 125 75718 & no Sb/Br) TPS75718KTTR ACTIVE DDPAK/ KTT 5 500 Green (RoHS Call TI | SN Level-2-260C-1 YEAR -40 to 125 75718 TO-263 & no Sb/Br) TPS75725KC ACTIVE TO-220 KC 5 50 Green (RoHS Call TI | SN N / A for Pkg Type -40 to 125 75725 & no Sb/Br) TPS75725KTTR ACTIVE DDPAK/ KTT 5 500 Green (RoHS Call TI | SN Level-2-260C-1 YEAR -40 to 125 75725 TO-263 & no Sb/Br) TPS75725KTTRG3 ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 75725 TO-263 & no Sb/Br) TPS75733KC ACTIVE TO-220 KC 5 50 Green (RoHS Call TI | SN N / A for Pkg Type -40 to 125 75733 & no Sb/Br) TPS75733KTTR ACTIVE DDPAK/ KTT 5 500 Green (RoHS Call TI | SN Level-2-260C-1 YEAR -40 to 125 75733 TO-263 & no Sb/Br) TPS75733KTTRG3 ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 75733 TO-263 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS75701KTTR DDPAK/ KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TO-263 TPS75715KTTR DDPAK/ KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TO-263 TPS75718KTTR DDPAK/ KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TO-263 TPS75725KTTR DDPAK/ KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TO-263 TPS75733KTTR DDPAK/ KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TO-263 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS75701KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS75715KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS75718KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS75725KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS75733KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 PackMaterials-Page2

PACKAGE OUTLINE KC0005A TO-220 - 16.51 mm max height SCALE 0.850 TO-220 4.83 B 4.06 10.67 1.40 AAAAA 8.89 3.05 9.65 1.14 6.86 2.54 6.86 (6.275) 5.69 3.71-3.96 OPTIONAL 12.88 CHAMFER 10.08 16.51 2X (R1) MAX OPTIONAL 9.25 7.67 (4.25) C PIN 1 ID (OPTIONAL) NOTE 3 14.73 12.29 1 5 0.61 1.02 5X 0.30 0.64 3.05 0.25 C A B 2.03 4X 1.7 6.8 1 5 4215009/A 01/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Shape may vary per different assembly sites. www.ti.com

EXAMPLE BOARD LAYOUT KC0005A TO-220 - 16.51 mm max height TO-220 4X (1.45) PKG 0.07 MAX METAL 0.07 MAX ALL AROUND (1.45) TYP ALL AROUND PKG (2) 4X (2) 1 5 (R0.05) TYP SOLDER MASK FULL R (1.7) TYP OPENING, TYP TYP 5X ( 1.2) (6.8) LAND PATTERN NON-SOLDER MASK DEFINED SCALE:12X 4215009/A 01/2017 www.ti.com

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