Product Order Technical Tools & Support & Folder Now Documents Software Community TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 TPS748 1.5-A Low-Dropout Linear Regulator With Programmable Soft-Start 1 Features 3 Description • V Range:0.8Vto3.6V The TPS748 low-dropout (LDO) linear regulator 1 OUT provides an easy-to-use robust power management • UltralowV Range:0.8Vto5.5V IN solution for a wide variety of applications. User- • VBIASRange2.7Vto5.5V programmable soft-start minimizes stress on the input • LowDropout:60mVTypicalat1.5A,V =5V power source by reducing capacitive inrush current BIAS on start-up. The soft-start is monotonic and well- • PowerGood(PG)OutputAllowsSupply suited for powering many different types of MonitoringorProvidesaSequencingSignalfor processors and ASICs. The enable input and power OtherSupplies good output allow easy sequencing with external • 2%AccuracyOverLine,Load,andTemperature regulators.Thiscompleteflexibilitypermitstheuserto • ProgrammableSoft-StartProvidesLinearVoltage configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other Startup applicationswithspecialstart-uprequirements. • V PermitsLowV OperationWithGood BIAS IN TransientResponse A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. • StableWithAnyOutputCapacitor≥ 2.2 μF The device is stable with any type of capacitor • AvailableinaSmall,3-mm×3-mm ×1-mm greater than or equal to 2.2 μF, and is fully specified VSON-10and5×5QFN-20Packages for T = –40°C to 125°C. The TPS748 is offered in a J small, 3-mm × 3-mm, VSON-10 package, yielding a 2 Applications highly compact, total solution size. The device is also available in a 5 × 5 QFN-20 package for compatibility • FPGAApplications withtheTPS744. • DSPCoreandI/OVoltages • Post-RegulationApplications DeviceInformation(1) • ApplicationsWithSpecialStart-upTimeor PARTNUMBER PACKAGE BODYSIZE(NOM) SequencingRequirements VSON(10) 3.00mmx3.00mm TPS748 • Hot-SwapandInrushControls VQFN(20) 5.00mmx5.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SPACE SPACE SPACE TypicalApplicationCircuit(Adjustable) TurnonResponse C = 0nF SS VIN IN PG 0.5V/div CSS= 1nF VOUT CIN BIAS R3 C = 2.2nF EN TPS74801 OUT VOUT SS VBIAS SS R1 C C GND FB OUT 1.2V BIAS V EN CSS R2 1V/div 0V Time (1ms/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com Table of Contents 1 Features.................................................................. 1 7.5 Programming..........................................................14 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 16 3 Description............................................................. 1 8.1 ApplicationInformation............................................16 4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................19 5 PinConfigurationandFunctions......................... 4 9 PowerSupplyRecommendations...................... 22 6 Specifications......................................................... 5 10 Layout................................................................... 23 6.1 AbsoluteMaximumRatings......................................5 10.1 LayoutGuidelines.................................................23 6.2 ESDRatings ............................................................5 10.2 LayoutExample....................................................24 6.3 RecommendedOperatingConditions.......................5 10.3 EstimatingJunctionTemperature.........................25 6.4 ThermalInformation..................................................6 11 DeviceandDocumentationSupport................. 27 6.5 ElectricalCharacteristics...........................................7 11.1 DeviceSupport......................................................27 6.6 TypicalCharacteristicsI =50mA.......................8 11.2 DocumentationSupport .......................................27 OUT 6.7 TypicalCharacteristicsI =1A..........................11 11.3 ReceivingNotificationofDocumentationUpdates27 OUT 7 DetailedDescription............................................ 12 11.4 CommunityResources..........................................27 7.1 Overview.................................................................12 11.5 Trademarks...........................................................27 7.2 FunctionalBlockDiagram.......................................12 11.6 ElectrostaticDischargeCaution............................27 7.3 FeatureDescription.................................................12 11.7 Glossary................................................................28 7.4 DeviceFunctionalModes........................................13 12 Mechanical,Packaging,andOrderable Information........................................................... 28 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionK(February2015)toRevisionL Page • AddedactivepulldowntoFunctionalBlockDiagram........................................................................................................... 12 • AddedEquation1andcorrespondingdescriptiontoEnable/Shutdownsection.................................................................. 13 ChangesfromRevisionJ(January2012)toRevisionK Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • ChangedpartnumberasprintedindocumentfromTPS74801toTPS748 ......................................................................... 1 • ChangedSON-10packagereferencesindocumenttoVSON-10......................................................................................... 1 • ChangedsecondparagraphofDescriptionsection .............................................................................................................. 1 • ChangedpindescriptionsthroughoutPinFunctionstable .................................................................................................... 4 • ChangedconditionstatementforAbsoluteMaximumRatings.............................................................................................. 5 • Changed"free-air"to"junction"temperatureinconditionstatementforRecommendedOperatingConditions.................... 5 • ChangedvaluesforbothpackagesinThermalInformation.................................................................................................. 6 • Changedtestconditionforoutputnoisevoltagefrom0.001µFto1nF................................................................................ 7 • Changedy-axistitleinFigure3fromabbreviation(I )totext(OutputCurrent)................................................................. 8 OUT • Changedy-axistitleinFigure4fromabbreviation(I )totext(OutputCurrent) ................................................................ 8 OUT • ChangedtitleforFigure4 ...................................................................................................................................................... 8 • Changedy-axisandx-axistitlesinFigure5fromabbreviationstotext................................................................................. 8 • Changedx-axistitleinFigure6fromabbreviation(V )totext(DropoutVoltage) .............................................................. 8 DC • Changedx-axistitleinFigure7fromabbreviation(V )totext(DropoutVoltage) .............................................................. 8 DO • Changedy-axisandx-axistitlesinFigure8fromabbreviationstotext ................................................................................ 8 • Changedy-axisandx-axistitlesinFigure13fromabbreviationstotext .............................................................................. 9 • ChangedtitleforFigure13 .................................................................................................................................................... 9 2 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 • Changedx-axistitleinFigure14fromabbreviation(I )totext(BiasCurrent).................................................................. 9 BIAS • ChangedFigure24;addedcapacitorsizeindicationforC .............................................................................................. 16 SS ChangesfromRevisionI(November2010)toRevisionJ Page • ChangedT rangeinAbsoluteMaximumRatingstable......................................................................................................... 5 J ChangesfromRevisionH(October,2010)toRevisionI Page • CorrectedequationforTable2............................................................................................................................................. 15 ChangesfromRevisionG(August,2010)toRevisionH Page • CorrectedtypoinFigure38.................................................................................................................................................. 25 Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 5 Pin Configuration and Functions DRCPackage 10-PinVSONWithThermalPad RGWPackage TopView 20-PinVQFN TopView IN 1 10 OUT T C C C U IN 2 9 OUT N N N N O I Thermal PG 3 Pad 8 FB 5 4 3 2 1 BIAS 4 7 SS EN 5 6 GND IN 6 20 OUT IN 7 19 OUT IN 8 TPS74801 18 OUT GND PG 9 17 NC BIAS 10 16 FB 1 2 3 4 5 1 1 1 1 1 N D C C S E N N N S G PinFunctions PIN I/O DESCRIPTION NAME VSON VQFN Biasinputvoltageforerroramplifier,reference,andinternalcontrolcircuits.A1-µFor BIAS 4 10 I largerinputcapacitorisrecommendedforoptimalperformance.IfINisconnectedto BIAS,a4.7-µForlargercapacitormustbeused. Enablepin.Drivingthispinhighenablestheregulator.Drivingthispinlowputsthe EN 5 11 I regulatorintoshutdownmode.Thispinmustnotbeleftunconnected. Feedbackpin.Thefeedbackconnectiontothecentertapofanexternalresistor FB 8 16 I dividernetworkthatsetstheoutputvoltage.Thispinmustnotbeleftfloating. GND 6 12 — Ground Inputtothedevice.A1-µForlargerinputcapacitorisrecommendedforoptimal IN 1,2 5-8 I performance. 2-4,13,14, Noconnection.ThispincanbeleftfloatingorconnectedtoGNDtoallowbetter NC N/A — 17 thermalcontacttothetop-sideplane. Regulatedoutputvoltage.Asmallcapacitor(totaltypicalcapacitance≥2.2μF, OUT 9,10 1,18-20 O ceramic)isneededfromthispintogroundtoassurestability. PowerGoodpin.Anopen-drain,active-highoutputthatindicatesthestatusofV . OUT WhenV exceedsthePGtripthreshold,thePGpingoesintoahigh-impedance OUT state.WhenV isbelowthisthresholdthepinisdriventoalow-impedancestate.A PG 3 9 O OUT pull-upresistorfrom10kΩto1MΩshouldbeconnectedfromthispintoasupplyof upto5.5V.Thesupplycanbehigherthantheinputvoltage.Alternatively,thePGpin canbeleftunconnectedifoutputmonitoringisnotnecessary. Soft-Startpin.Acapacitorconnectedonthispintogroundsetsthestart-uptime.Ifthis SS 7 15 — pinisleftunconnected,theregulatoroutputsoft-startramptimeistypically200μs. Mustbesolderedtothegroundplaneforincreasedthermalperformance.Internally Thermalpad — connectedtoground. 4 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 6 Specifications 6.1 Absolute Maximum Ratings AtT =–40°Cto125°C,unlessotherwisenoted.AllvoltagesarewithrespecttoGND.(1) J MIN MAX UNIT Inputvoltage V ,V –0.3 6 V IN BIAS Enablevoltage V –0.3 6 V EN Powergoodvoltage V –0.3 6 V PG PGsinkcurrent I 0 1.5 mA PG Soft-startvoltage V –0.3 6 V SS Feedbackvoltage V –0.3 6 V FB Outputvoltage V –0.3 V +0.3 V OUT IN Maximumoutputcurrent I Internallylimited OUT Outputshort-circuitduration Indefinite Continuoustotalpower P SeeThermalInformation dissipation DISS Operatingjunction,T –40 150 J Temperature °C Storage,T –55 150 stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±2000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101, V allpins(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingjunctiontemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Inputsupplyvoltage V +V (V ) V +0.3 5.5 V IN OUT DO IN OUT V Enablesupplyvoltage 0 V 5.5 V EN IN V (1) BIASsupplyvoltage V +V (V )(2) V +1.6(2) 5.5 V BIAS OUT DO BIAS OUT V Outputvoltage 0.8 3.3 V OUT I Outputcurrent 0 1.5 A OUT C Outputcapacitor 2.2 µF OUT C Inputcapacitor(3) 1 µF IN C Biascapacitor 0.1 1 µF BIAS T Operatingjunctiontemperature –40 125 °C J (1) BIASsupplyisrequiredwhenV isbelowV +1.62V. IN OUT (2) V hasaminimumvoltageof2.7VorV +V (V ),whicheverishigher. BIAS OUT DO BIAS (3) IfV andV areconnectedtothesamesupply,therecommendedminimumcapacitorforthesupplyis4.7μF. IN BIAS Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 6.4 Thermal Information TPS748(2) THERMALMETRIC(1) RGW(VQFN) DRC(VSON) UNIT 20PINS 10PINS R Junction-to-ambientthermalresistance(3) 35.6 44.2 °C/W θJA R Junction-to-case(top)thermalresistance(4) 33.3 50.3 °C/W θJC(top) R Junction-to-boardthermalresistance(5) 15 19.6 °C/W θJB ψ Junction-to-topcharacterizationparameter(6) 0.4 0.7 °C/W JT ψ Junction-to-boardcharacterizationparameter(7) 15.2 17.8 °C/W JB R Junction-to-case(bottom)thermalresistance(8) 3.8 4.3 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) ThermaldatafortheRGWandDRCpackagesarederivedbythermalsimulationsbasedonJEDEC-standardmethodologyasspecified intheJESD51series.Thefollowingassumptionsareusedinthesimulations: (a)i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. .ii.DRC:TheexposedpadisconnectedtothePCBgroundlayerthrougha3x2thermalviaarray. (b)i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. .ii.DRC:Thetopandbottomcopperlayersareassumedtohavea20%thermalconductivityofcopperrepresentinga20%copper coverage. (c)ThesedataweregeneratedwithonlyasingledeviceatthecenterofaJEDEChigh-K(2s2p)boardwith3in×3incopperarea.To understand the effects of the copper area on thermal performance, see the Estimating Junction Temperature section of this data sheet. (3) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,as specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a. (4) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthetopofthepackage.NospecificJEDEC- standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. (5) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB temperature,asdescribedinJESD51-8. (6) Thejunction-to-topcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted JT fromthesimulationdatatoobtainθ usingaproceduredescribedinJESD51-2a(sections6and7). JA (7) Thejunction-to-boardcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted JB fromthesimulationdatatoobtainθ usingaproceduredescribedinJESD51-2a(sections6and7). JA (8) Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.Nospecific JEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. 6 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 6.5 Electrical Characteristics AtV =1.1V,V =V +0.3V,C =0.1μF,C =C =10μF,C =1nF,I =50mA,V =5.0V,andT = EN IN OUT BIAS IN OUT NR OUT BIAS J –40°Cto125°C,unlessotherwisenoted.TypicalvaluesareatT =25°C. J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Inputvoltagerange V +V 5.5 V IN OUT DO V BIASpinvoltagerange 2.7 5.5 V BIAS V Internalreference(Adj.) T =25°C 0.796 0.8 0.804 V REF J Outputvoltagerange V =5V,I =1.5A V 3.6 V IN OUT REF VOUT(ΔVIN) Accuracy(1) 2.97V≤VBIAS≤5.5V, –2% ±0.5% 2% 50mA≤I ≤1.5A OUT V Lineregulation V +0.3≤V ≤5.5V 0.03 %/V OUT(ΔIOUT) OUT(nom) IN V Loadregulation 50mA≤I ≤1.5A 0.09 %/A OUT OUT VDO VINdropoutvoltage(2) IVOBUIATS=–1V.5OAUT,(nom)≥3.25V(3) 60 165 mV V dropoutvoltage(2) I =1.5A,V =V 1.31 1.6 V BIAS OUT IN BIAS I Currentlimit V =80%×V 2 5.5 A CL OUT OUT(nom) I BIASpincurrent 1 2 mA BIAS Shutdownsupplycurrent I V ≤0.4V 1 50 μA SHDN (I ) EN GND I Feedbackpincurrent –1 0.150 1 μA FB 1kHz,I =1.5A, OUT 60 Power-supplyrejection VIN=1.8V,VOUT=1.5V dB (VINtoVOUT) 300kHz,IOUT=1.5A, 30 V =1.8V,V =1.5V IN OUT PSRR 1kHz,I =1.5A, OUT 50 Power-supplyrejection VIN=1.8V,VOUT=1.5V dB (VBIAStoVOUT) 300kHz,IOUT=1.5A, 30 V =1.8V,V =1.5V IN OUT 100Hzto100kHz, V Outputnoisevoltage 25×V μV n I =1.5A,C =1nF OUT RMS OUT SS t Minimumstartuptime R forI =1.0A,C =open 200 μs STR LOAD OUT SS I Soft-startchargingcurrent V =0.4V 440 nA SS SS V Enableinputhighlevel 1.1 5.5 V EN(hi) V Enableinputlowlevel 0 0.4 V EN(lo) V Enablepinhysteresis 50 mV EN(hys) V Enablepindeglitchtime 20 μs EN(dg) I Enablepincurrent V =5V 0.1 1 μA EN EN V PGtripthreshold V decreasing 85 90 94 %V IT OUT OUT V PGtriphysteresis 3 %V HYS OUT V PGoutputlowvoltage I =1mA(sinking),V <V 0.3 V PG(lo) PG OUT IT I PGleakagecurrent V =5.25V,V >V 0.1 1 μA PG(lkg) PG OUT IT Operatingjunction T –40 125 °C J temperature Thermalshutdown Shutdown,temperatureincreasing 165 T °C SD temperature Reset,temperaturedecreasing 140 (1) Adjustabledevicestestedat0.8V;resistortoleranceisnottakenintoaccount. (2) DropoutisdefinedasthevoltagefromV toV whenV is3%belownominal. IN OUT OUT (3) 3.25VisatestconditionofthisdeviceandcanbeadjustedbyreferringtoFigure6. Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 6.6 Typical Characteristics I = 50 mA OUT AtT =25°C,V =V +0.3V,V =5V,I =50mA,V =V ,C =1μF,C =4.7μF,andC =10μF, J IN OUT(nom) BIAS OUT EN IN IN BIAS OUT unlessotherwisenoted. 0.20 0.5 0.4 0.15 0.3 0.10 %) -40°C %) 0.2 ( ( -40°C UT 0.05 UT 0.1 O O V V n 0 n 0 ange i -0.05 +25°C +125°C ange i -0.1 +125°C +25°C Ch -0.01 Ch -0.2 -0.3 -0.15 -0.4 -0.20 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V -V (V) V -V (V) IN OUT BIAS OUT Figure1.V LineRegulation Figure2.V LineRegulation IN BIAS 1.2 0.5 0.4 1.0 0.3 %) %) 0.2 ( 0.8 ( +125°C UT UT 0.1 O O V V n 0.6 n 0 ge i ge i -0.1 +25°C -40°C n n a 0.4 a Ch Ch -0.2 -0.3 0.2 -0.4 0 -0.5 0 10 20 30 40 50 0.05 0.5 1.0 1.5 Output Current (mA) Output Current (A) Figure3.LoadRegulation Figure4.LoadRegulationatLightLoad 100 200 I = 1.5A 90 180 OUT 80 160 V) +125°C V) m 70 m 140 age ( 60 age( 120 +125°C olt 50 olt 100 ut V 40 ut V 80 +25°C po +25°C po o 30 o 60 Dr Dr 20 40 -40°C -40°C 10 20 0 0 0 0.5 1.0 1.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Output Current (A) V -V (V) BIAS OUT Figure5.VINDropoutVoltagevsIOUTandTemperature(TJ) Figure6.VINDropoutVoltagevs(VBIAS–VOUT)and Temperature(T ) J 8 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 Typical Characteristics I = 50 mA (continued) OUT AtT =25°C,V =V +0.3V,V =5V,I =50mA,V =V ,C =1μF,C =4.7μF,andC =10μF, J IN OUT(nom) BIAS OUT EN IN IN BIAS OUT unlessotherwisenoted. 200 2200 I = 0.5A OUT 180 2000 160 V) V) 1800 m 140 m age ( 120 age( 1600 +125°C Volt 100 +25°C Volt 1400 pout 80 +125°C pout 1200 Dro 60 Dro 1000 +25°C 40 -40°C -40°C 800 20 0 600 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 V -V (V) Output Current (A) BIAS OUT Figure7.VINDropoutVoltagevs(VBIAS–VOUT)and Figure8.VBIASDropoutVoltagevsIOUTandTemperature Temperature(TJ) (TJ) 90 90 B) 80 B) 80 Ratio (d 70 IOUT= 0.1A IOUT= 1.5A Ratio (d 70 IOUT= 100mA n 60 n 60 o o cti 50 cti 50 e e ej ej R 40 R 40 pply 30 IOUT= 0.5A pply 30 Power-Su 2100 VVVCIOBNIUA=TS= =1 =1 . 18n5.VFV2V Power-Su 2100 VVCVIOSNSU=T= =1 =1 . 18n5.VFV2V I = 1.5A SS BIAS OUT 0 0 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure9.V PSRRvsFrequency Figure10.V PSRRvsFrequency BIAS IN 90 1 Power-Supply Rejection Ratio (dB) 8765432100000000 VICOOSUSUTT=== 11 1n.5.F2AV 11k150H000kz0kHkHzHzz mÖutput Spectral Noise Density (V/)Hz 0.1 IVOOUUTT== 1 10.02mVA CSS= 10nF CSCSS=S =1 n0FnF O 0 0.01 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 100 1k 10k 100k V -V (V) Frequency (Hz) IN OUT Figure11.V PSRRvs(V –V ) Figure12.NoiseSpectralDensity IN IN OUT Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com Typical Characteristics I = 50 mA (continued) OUT AtT =25°C,V =V +0.3V,V =5V,I =50mA,V =V ,C =1μF,C =4.7μF,andC =10μF, J IN OUT(nom) BIAS OUT EN IN IN BIAS OUT unlessotherwisenoted. 2.0 2.0 1.8 1.8 +125°C +125°C 1.6 1.6 A) 1.4 A) 1.4 m m nt ( 1.2 nt ( 1.2 +25°C urre 1.0 urre 1.0 as C 0.8 -40°C +25°C as C 0.8 Bi 0.6 Bi 0.6 -40°C 0.4 0.4 0.2 0.2 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Current (A) V (V) BIAS Figure13.BIASPinCurrentvsOutputCurrentand Figure14.BIASPinCurrentvsV andTemperature(T ) BIAS J Temperature(T ) J 500 1.0 0.9 475 V) 450 ge ( 0.8 a 0.7 A) 425 G Volt 0.6 I(nSS 430705 Level P 00..54 ow- 0.3 350 L OL 0.2 V 325 0.1 300 0 -50 -25 0 25 50 75 100 125 0 2 4 6 8 10 12 Junction Temperature (°C) PG Current (mA) Figure15.Soft-StartChargingCurrent(ISS)vs Figure16.Low-LevelPGVoltagevsCurrent Temperature(T ) J 4.0 V = 0.8V OUT 3.8 +125°C 3.6 A) 3.4 mit ( 3.2 Li 3.0 nt -40°C +25°C urre 2.8 C 2.6 2.4 2.2 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V -V (V) BIAS OUT Figure17.CurrentLimitvs(V –V ) BIAS OUT 10 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 6.7 Typical Characteristics I = 1 A OUT AtT =25°C,V =V +0.3V,V =5V,I =1A,V =V =1.8V,V =1.5V,C =1μF,C =4.7μF,and J IN OUT(nom) BIAS OUT EN IN OUT IN BIAS C =10μF,unlessotherwisenoted. OUT C = 1nF SS COUT= 10mF (Ceramic) COUT= 10mF (Ceramic) 100mV/div 100mV/div C = 2.2mF (Ceramic) OUT 100mV/div C = 1nF SS 3.8V 5.0V 1V/div 1V/div 3.3V 1V/ms 1.8V 1V/ms Time (50ms/div) Time (50ms/div) Figure18.V LineTransient Figure19.V LineTransient BIAS IN COUT= 470mF (OSCON) CSS= 0nF 100mV/div C = 10mF (Ceramic) 100mV/div OUT 0.5V/div CSS= 1nF VOUT C = 2.2nF SS C = 2.2mF (Ceramic) OUT 100mV/div 1.2V 1.5A VEN C = 1nF 1A/div SS 1V/div 0V 50mA 1A/ms Time (50ms/div) Time (1ms/div) Figure20.OutputLoadTransientResponse Figure21.TurnonResponse VPG(500mV/div) VIN= VBIAS= VEN v di V/ 1 V OUT Time (20ms/div) Figure22.Power-Up/Power-Down Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 7 Detailed Description 7.1 Overview The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate verylowinputandoutputvoltages. TheuseofanNMOS-passFEToffersseveralcriticaladvantagesformanyapplications.UnlikeaPMOStopology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularlyforlowV applications. IN The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low V and V IN OUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltagesoftenrequiredbyprocessor-intensivesystems. 7.2 Functional Block Diagram IN CLuirmreitnt OUT VOUT 833 (cid:13) BIAS UVLO Thermal 0.44 µA Limit R1 SS CSS Soft-Start 0.8-V Discharge Reference FB PG Hysteresis EN and Deglitch R2 0.9 x VREF GND 7.3 Feature Description 7.3.1 Enable/Shutdown The enable (EN) pin is active high and is compatible with standard digital signaling levels. V below 0.4 V turns EN the regulator off, while V above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has EN hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the TPS748 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in the V EN signal. The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V and1.1-Vlimits.Ifpreciseturnontimingisrequired,afastrise-timesignalmustbeusedtoenabletheTPS748. 12 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 Feature Description (continued) If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enablecircuit. The TPS748 has an internal active pulldown circuit that connects the output to GND through an 833-Ω resistor whenthedeviceisdisabled.Thisresistordischargestheoutputwithatimeconstantof: §833uR • W ¤ L ‚uC '833(cid:14)R „ OUT L (1) 7.3.2 PowerGood The power good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an externalpull-upresistor.Thispinrequiresatleast1.1VonV inordertohaveavalidoutput.ThePGoutputis BIAS high-impedance when V is greater than V + V . If V drops below V or if V drops below 1.9 V, the OUT IT HYS OUT IT BIAS open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The recommended operating condition of PG pin sink current is up to 1 mA, so the pull-up resistor for PG should beintherangeof10kΩ to1MΩ.Ifoutputvoltagemonitoringisnotneeded,thePGpincanbeleftfloating. 7.3.3 InternalCurrentLimit The TPS748 features a factory-trimmed current limit that is flat over temperature and supply voltage. The current limit allows the device to supply surges of up to 2 A and maintain regulation. The current limit responds in approximately10μstoreducethecurrentduringashort-circuitfault. The internal current limit protection circuitry of the TPS748 is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS748 above theratedcurrentdegradesdevicereliability. 7.3.4 ThermalProtection Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40°C abovethemaximumexpectedambientconditionoftheapplication.Thisconditionproducesaworst-casejunction temperatureof125°Catthehighestexpectedambienttemperatureandworst-caseload. The internal protection circuitry of the TPS748 is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS748 into thermal shutdown degrades devicereliability. 7.4 Device Functional Modes 7.4.1 NormalOperation Thedeviceregulatestothenominaloutputvoltageunderthefollowingconditions: • Theinputvoltageandbiasvoltagearebothatleastattherespectiveminimumspecifications. • The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased belowtheenablefallingthreshold. • Theoutputcurrentislessthanthecurrentlimit. • Thedevicejunctiontemperatureislessthanthemaximumspecifiedjunctiontemperature. Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com Device Functional Modes (continued) 7.4.2 DropoutOperation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO.Lineorloadtransientsindropoutcanresultinlargeoutputvoltagedeviations. 7.4.3 Disabled Thedeviceisdisabledunderthefollowingconditions: • Theinputorbiasvoltagesarebelowtherespectiveminimumspecifications. • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. • Thedevicejunctiontemperatureisgreaterthanthethermalshutdowntemperature. Table1showstheconditionsthatleadtothedifferentmodesofoperation. Table1.DeviceFunctionalModeComparison PARAMETER OPERATINGMODE V V V I T IN EN BIAS OUT J Normalmode V >V +V (V ) V >V V ≥V +1.6V I <I T <125°C IN OUT(nom) DO IN EN EN(high) BIAS OUT OUT CL J Dropoutmode V <V +V (V ) V >V V <V +1.6V — T <125°C IN OUT(nom) DO IN EN EN(high) BIAS OUT J Disabledmode (anytrueconditiondisables V <V V <V V <V — T >165°C IN IN(min) EN EN(low) BIAS BIAS(min) J thedevice) 7.5 Programming 7.5.1 ProgrammableSoft-Start The TPS748 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (C ). This feature is important for many applications because it eliminates power-up initialization SS problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reducespeakinrushcurrentduringstart-up,minimizingstart-uptransienteventstotheinputpowerbus. To achieve a linear and monotonic soft-start, the TPS748 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft- start charging current (I ), soft-start capacitance (C ), and the internal reference voltage (V ), and can be SS SS REF calculatedusingEquation2: (V ´C ) t = REF SS SS I SS (2) If large output capacitors are used, the device current limit (I ) and the output capacitor may set the start-up CL time.Inthiscase,thestart-uptimeisgivenbyEquation3: (V ´C ) OUT(NOM) OUT t = SSCL I CL(MIN) where • V isthenominaloutputvoltage, OUT(nom) • C istheoutputcapacitance,and OUT • I istheminimumcurrentlimitforthedevice. (3) CL(min) In applications where monotonic startup is required, the soft-start time given by Equation 2 should be set greater thanEquation3. 14 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 Programming (continued) The maximum recommended soft-start capacitor is 15 nF. Larger soft-start capacitors can be used and do not damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft- start capacitor when enabled. Soft-start capacitors larger than 15 nF could be a problem in applications where it is necessary to rapidly pulse the enable pin and still require the device to soft-start from ground. C must be SS low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested soft-start capacitorvalues. Table2.StandardCapacitorValuesforProgrammingtheSoft-StartTime(1) C SOFT-STARTTIME SS Open 0.1ms 270pF 0.5ms 560pF 1ms 2.7nF 5ms 5.6nF 10ms 10nF 18ms V ×C 0.8V×C (F) t (s) = REF SS = SS SS I 0.44mA (1) SS wheretSS(s)=soft-starttimeinseconds. Another option to set the start-up rate is to use a feedforward capacitor; see the Pros and Cons of Using a FeedforwardCapacitorwithaLow-DropoutRegulator applicationreportformoreinformation. 7.5.2 SequencingRequirements V , V , and V can be sequenced in any order without causing damage to the device. However, for the soft- IN BIAS EN start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable for most applications, as long as V is greater than 1.1 V and the ramp rate of V and V is faster than the IN IN BIAS setsoft-startramprate. Thereareseveraldifferentstart-upresponsesthatarepossible,butnottypical: • If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply minusthedropoutvoltageuntilitreachesthesetoutputvoltage. • IfENisconnectedtoBIAS,thedevicesoft-startsasprogrammed,providedthatV ispresentbeforeV . IN BIAS • IfV andV arepresentbeforeV isappliedandthesetsoft-starttimehasexpired,thenV tracksV . BIAS EN IN OUT IN • If the soft-start time has not expired, the output tracks V until V reaches the value set by the charging IN OUT soft-startcapacitor. Figure 23 shows the use of an RC-delay circuit to hold off V until V has ramped. This technique can also EN BIAS be used to drive EN from V . An external control signal can also be used to enable the device after V and IN IN V arepresent. BIAS VIN IN OUT VOUT CIN R1 C BIAS TPS74801 FB OUT VBIAS R R2 C EN GND SS BIAS C CSS Figure23. Soft-StartDelayUsinganRCCircuittoEnabletheDevice Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate verylowinputandoutputvoltages. TheuseofanNMOS-passFEToffersseveralcriticaladvantagesformanyapplications.UnlikeaPMOStopology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularlyforlowV applications. IN The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low V and V IN OUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltagesoftenrequiredbyprocessor-intensivesystems. 8.1.1 AdjustingtheOutputVoltage Figure24showsthetypicalapplicationcircuitfortheTPS748adjustableoutputdevice. VIN IN PG C1ImNF BIAS R3 EN TPS74801 OUT VOUT VBIAS SS R1 COUT CBIAS GND FB 10mF 1mF C SS R 1 nF 2 V = 0.8´(1 + R1 ) OUT R 2 Figure24. TypicalApplicationCircuitfortheTPS748(Adjustable) 16 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 Application Information (continued) R and R can be calculated for any output voltage using the formula shown in Figure 24. Table 3 lists sample 1 2 resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R should 2 be≤ 4.99kΩ. Table3.Standard1%ResistorValuesforProgrammingtheOutputVoltage(1) R (kΩ) R (kΩ) V (V) 1 2 OUT Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 (1) V =0.8×(1+R /R ). OUT 1 2 SPACE NOTE WhenV andV arepresentandV isnotsupplied,thisdeviceoutputsapproximately BIAS EN IN 50 μA of current from OUT. Although this condition does not cause any damage to the device, the output current may charge up the OUT node if total resistance between OUT andGND(includingexternalfeedbackresistors)isgreaterthan10kΩ. 8.1.2 Input,Output,andBiasCapacitorRequirements Thedeviceisdesignedtobestableforallavailabletypesandvaluesofoutputcapacitors≥ 2.2 μF.Thedeviceis alsostablewithmultiplecapacitorsinparallel,whichcanbeofanytypeorvalue. The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for V is 1 μF and minimum IN recommendedcapacitorforV is0.1µF.IfV andV areconnectedtothesamesupply,therecommended BIAS IN BIAS minimum capacitor for V is 4.7 μF. Good quality, low ESR capacitors should be used on the input; ceramic BIAS X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for optimumperformance. 8.1.3 TransientResponse The TPS748 was designed to have excellent transient response for most applications with a small amount of output capacitance. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient event; refer to Figure 20 in the Typical Characteristics section. Because the TPS748 is stable with output capacitors as low as 2.2 μF, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output. Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 8.1.4 DropoutVoltage The TPS748 offers very low dropout performance, making it well-suited for high-current, low V /low V IN OUT applications. The low dropout of the TPS748 allows the device to be used in place of a dc/dc converter and still achievegoodefficiency.Equation4providesaquickestimateoftheefficiency. V ´I OUT OUT V Efficiency» » OUT atI >>I V ´(I + I ) V OUT Q IN IN Q IN (4) This efficiency provides designers with the power architecture for their applications to achieve the smallest, simplest,andlowestcostsolutions. There are two different specifications for dropout voltage with the TPS748. The first specification (see Figure 25) is referred to as V Dropout and is used when an external bias voltage is applied to achieve low dropout. This IN specification assumes that V is at least 3.25 V(1) above V , which is the case for V when powered by a BIAS OUT BIAS 5.0-V rail with 5% tolerance and with V = 1.5 V. If V is higher than V +3.25 V(1), V dropout is less OUT BIAS OUT IN thanspecified. The second specification (illustrated in Figure 31) is referred to as V Dropout and applies to applications BIAS where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because V provides the gate drive to the pass FET; therefore, V must be 1.6 V above V . Because of BIAS BIAS OUT this usage, IN and BIAS tied together become a highly inefficient solution that can consume large amounts of power.PayattentionnottoexceedthepowerratingoftheICpackage. 8.1.5 OutputNoise The TPS748 provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 1-nF soft-start capacitor, the output noise is reduced by half and is typically 30 μV for a 1.2-V output (10 Hz to 100 kHz). RMS Further increasing C has little effect on noise. Because most of the output noise is generated by the internal SS reference, the noise is a function of the set output voltage. The RMS noise with a 1-nF soft-start capacitor is giveninEquation5: V (mV ) = 25(mVRMS)x V (V) N RMS OUT V (5) The low output noise of the TPS748 makes it a good choice for powering transceivers, PLLs, or other noise- sensitivecircuitry. (1) 3.25VisatestconditionofthisdeviceandcanbeadjustedbyreferringtoFigure6. 18 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 8.2 Typical Applications 8.2.1 FPGAI/OSupplyat1.5VWithaBiasRail BIAS IN V = 5V±5% BIAS V = 1.8V IN V = 1.5V OUT I = 1.5A OUT Reference Efficiency = 83% OUT V OUT C OUT FB Simplified BlockDiagram Figure25. TypicalApplicationoftheTPS748UsinganAuxiliaryBiasRail 8.2.1.1 DesignRequirements ThisapplicationpowerstheI/OrailsofanFPGA,atV =1.5VandI =1.5A.Theavailableexternal OUT(nom) OUT(dc) supplyvoltagesare1.8V,3.3Vand5V. 8.2.1.2 DetailedDesignProcedure First, determine what supplies to use for the input and bias rails. A 1.8-V input can be stepped down to 1.5 V at 1.5 A if an external bias is provided, because the maximum dropout voltage is 165 mV if V is at least 3.25 V BIAS higher than V . To achieve this voltage step, the bias rail is supplied by the 5-V supply. The approximation in OUT Equation4estimatestheefficiencyat83.3%. The output voltage then must be set to 1.5 V. As Table 3 describes, set R = 4.12 kΩ and R = 4.75 kΩ to obtain 1 2 the required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer to Input, Output, and Bias Capacitor Requirements for C = 1 µF, C = 1 µF, and C = 2.2 µF. Use IN BIAS OUT C =1nFforatypical1.8-msstart-uptime. SS Figure25showsasimplifiedversionofthefinalcircuit. Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com Typical Applications (continued) 8.2.1.3 ApplicationCurves C = 1nF SS COUT= 10mF (Ceramic) COUT= 10mF (Ceramic) 100mV/div 100mV/div C = 2.2mF (Ceramic) OUT 100mV/div C = 1nF SS 3.8V 5.0V 1V/div 1V/div 3.3V 1V/ms 1.8V 1V/ms Time (50ms/div) Time (50ms/div) Figure26.V LineTransient Figure27.V LineTransient BIAS IN COUT= 470mF (OSCON) CSS= 0nF 100mV/div C = 10mF (Ceramic) 100mV/div OUT 0.5V/div CSS= 1nF VOUT C = 2.2nF SS C = 2.2mF (Ceramic) OUT 100mV/div 1.2V 1.5A VEN C = 1nF 1A/div SS 1V/div 0V 50mA 1A/ms Time (50ms/div) Time (1ms/div) Figure28.OutputLoadTransientResponse Figure29.TurnonResponse VPG(500mV/div) VIN= VBIAS= VEN v di V/ 1 V OUT Time (20ms/div) Figure30.Power-Up/Power-Down 20 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 Typical Applications (continued) 8.2.2 FPGAI/OSupplyat1.5VWithoutaBiasRail V IN V = 3.3V±5% BIAS IN BIAS V = 3.3V±5V IN V = 1.5V OUT I = 1.5A OUT Reference Efficiency = 45% OUT V OUT C OUT FB Simplified BlockDiagram Figure31. TypicalApplicationoftheTPS748WithoutanAuxiliaryBiasRail 8.2.2.1 DesignRequirements TheapplicationpowerstheI/OrailsofanFPGA,atV =1.5VandI =1.5A.Theonlyavailablerail OUT(nom) OUT(max) is 3.3 V. The I/O pins are driven for only short durations with a 5% duty cycle, so thermal issues are not a concern. 8.2.2.2 DetailedDesignProcedure There is only one available rail; therefore, the input supply and the bias supply are connected together on the 3.3-Vinputsupply. The output voltage must be set to 1.5 V. As Table 3 describes, set R = 4.12 kΩ and R = 4.75 kΩ to obtain the 1 2 required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer to Input, Output, and Bias Capacitor Requirements for C = C = 4.7 µF, and C = 2.2 µF. Use C = 1 nF IN BIAS OUT SS foratypical1.8-msstart-uptime. Figure31showstheTPS748configuredwithoutabiasrail. Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com Typical Applications (continued) 8.2.2.3 ApplicationCurves 2200 90 2000 B) 80 o (d 70 IOUT= 0.1A IOUT= 1.5A V) 1800 ati e(m 1600 on R 60 Voltag 1400 +125°C Rejecti 5400 Dropout 11200000 -40°C +25°C wer-Supply 3200 VVIONU=T =1 .18.V2V IOUT= 0.5A 800 Po 10 VBIAS= 5V C = 1nF SS 600 0 0 0.5 1.0 1.5 10 100 1k 10k 100k 1M 10M Output Current (A) Frequency (Hz) Figure32.V DropoutVoltagevsI andTemperature Figure33.V PSRRvsFrequency BIAS OUT BIAS (T ) J 4.0 3.8 VOUT= 0.8V CSS= 1nF +125°C C = 10mF (Ceramic) 3.6 OUT 100mV/div A) 3.4 mit ( 3.2 COUT= 2.2mF (Ceramic) Li 3.0 100mV/div nt -40°C +25°C urre 2.8 C 2.6 5.0V 2.4 1V/div 2.2 3.3V 1V/ms 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (50ms/div) V -V (V) Figure35.VBIASLineTransient BIAS OUT Figure34.CurrentLimitvs(V –V ) BIAS OUT 9 Power Supply Recommendations The TPS748 is designed to operate from an input voltage up to 5.5 V, provided the bias rail is at least 1.62 V higher than the input supply and dropout requirements are met. The bias rail and the input supply should both provide adequate headroom and current for the device to operate normally. Connect a low output impedance powersupplydirectlytotheINpinoftheTPS748.Thissupplymusthaveatleast1 μFofcapacitanceneartheIN pin for optimal performance. A supply with similar requirements must also be connected directly to the bias rail with a separate 1-μF or larger capacitor. If the IN pin is tied to the bias pin, a minimum 4.7 μF of capacitance is needed for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferritebeadbeforetheinputcapacitor. 22 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 10 Layout 10.1 Layout Guidelines An optimal layout can greatly improve transient performance, PSR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the top side of R in Figure 24 should be connected as close as possible to the load. If BIAS is connected to IN, it is 1 recommended to connect BIAS as close to the sense point of the input supply as possible. This connection minimizesthevoltagedroponBIASduringtransientconditionsandcanimprovetheturnonresponse. Knowingthedevicepowerdissipationandpropersizingofthethermalplanethatisconnectedtothethermalpad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends oninputvoltageandloadconditionsandcanbecalculatedusingEquation6: P = (V -V )´I D IN OUT OUT (6) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltagenecessarytoachievetherequiredoutputvoltageregulation. On both the VSON (DRC) and QFN (RGW) packages, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum devicejunctiontemperature,andpowerdissipationofthedeviceandcanbecalculatedusingEquation7: (+125°C-T ) R = A qJA P D (7) Knowing the maximum R , the minimum amount of PCB copper area needed for appropriate heatsinking can θJA beestimatedusingFigure36. 140 DRC 120 RGW 100 W) 80 C/ °( A 60 qJ 40 20 0 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area (in2) Note: θ valueatboardsizeof9in2(thatis,3in×3in)isaJEDECstandard. JA Figure36. Θ vsBoardSize JA Figure36showsthevariationof θ asafunctionofgroundplanecopperareaintheboard.Itisintendedonlyas JA a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actualthermalperformanceinrealapplicationenvironments. NOTE When the device is mounted on an application PCB, TI strongly recommends using Ψ JT andΨ ,asexplainedinEstimatingJunctionTemperature. JB Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 10.2 Layout Example Input GND Plane CIN IN NC NC NC OUT VIN Plane 5 4 3 2 1 VOUT Plane IN 6 20 OUT IN 7 19 OUT R(PULLUP) IN 8 Thermal Pad 18 OUT PG 9 17 NC R1 COUT BIAS 10 16 FB/ R1 and R2 should SNS be connected CBIAS 11 12 13 14 15 close to the load, EN GND NC NC SS R2 nCeOaUrT tpsooh tsohsueibl dLle DbeO aass CSS Keep the ground planes on the same side of the PCB if possible to improve thermal Output GND Plane disappation (1) Denotes thermal vias (2) Denotes vias used for application purposes Figure37. LayoutExample(RGWPackage) 24 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 10.3 Estimating Junction Temperature Using the thermal metrics Ψ and Ψ , as shown in the Thermal Information table, the junction temperature can JT JB be estimated with corresponding formulas (given in Equation 8). For backwards compatibility, an older θ ,Top JC parameterislistedaswell. Y : T = T +Y ·P JT J T JT D Y : T = T +Y ·P JB J B JB D (8) Where P is the power dissipation shown by Equation 6, T is the temperature at the center-top of the IC D T package, and T is the PCB temperature measured 1 mm away from the IC package on the PCB surface B (Figure38). NOTE Both T and T can be measured on actual application boards using a thermo-gun (an T B infraredthermometer). For more information about measuring T and T , see the Using New Thermal Metrics application note, available T B fordownloadatwww.ti.com. T on top T of IC T on PCB B T ontopof IC surface T on PCB T B 1mm 1mm (a) Example DRC (SON) Package Measurement (b) Example RGW (QFN) Package Measurement Figure38. MeasuringPointsforT andT T B Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com Estimating Junction Temperature (continued) By looking at Figure 39, the new thermal metrics (Ψ and Ψ ) have very little dependency on board size. That JT JB is, using Ψ or Ψ with Equation 8 is a good way to estimate T by simply measuring T or T , regardless of the JT JB J T B applicationboardsize. 12 10 Y JB W) C/ 8 °( YJB 6 DRC RGW d n a T 4 YJ 2 Y JT 0 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area (in2) Figure39. Ψ andΨ vsBoardSize JT JB For a more detailed discussion of why TI does not recommend using θ to determine thermal characteristics, JC(top) see the Using New Thermal Metrics application report, available for download at www.ti.com. For further information,seetheICPackageThermalMetrics applicationreport,alsoavailableontheTIwebsite. 26 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

TPS748 www.ti.com SBVS074L–JANUARY2007–REVISEDMARCH2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 DevelopmentSupport 11.1.1.1 EvaluationModules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS48. The TPS74801EVM-177 evaluation module (and related user's guide) can be requested at the Texas InstrumentswebsitethroughtheproductfoldersorpurchaseddirectlyfromtheTIeStore. 11.1.1.2 SpiceModels Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS748 is available through the product folders under Tools &Software. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • UsingNewThermalMetrics • ICPackageThermalMetrics • UltimateRegulationofwithFixedOutputVersionsoftheTPS742xx,TPS743xx,andTPS744xx • ProsandConsofUsingaFeedforwardCapacitorwithaLow-DropoutRegulator • TPS74801EVM-177EvaluationModuleUserGuide 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. Copyright©2007–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS748

TPS748 SBVS074L–JANUARY2007–REVISEDMARCH2017 www.ti.com 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 28 SubmitDocumentationFeedback Copyright©2007–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS748

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS74801DRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO & no Sb/Br) TPS74801DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO & no Sb/Br) TPS74801DRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO & no Sb/Br) TPS74801DRCTG4 ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO & no Sb/Br) TPS74801RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74801 TPS74801RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74801 TPS74801RGWT ACTIVE VQFN RGW 20 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74801 TPS74801RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74801 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS74801 : •Automotive: TPS74801-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS74801DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74801RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS74801DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS74801DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS74801DRCT VSON DRC 10 250 210.0 185.0 35.0 TPS74801DRCT VSON DRC 10 250 210.0 185.0 35.0 TPS74801RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74801RGWT VQFN RGW 20 250 210.0 185.0 35.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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