Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 TPS74401 3.0-A, Ultra-LDO with Programmable Soft-Start 1 Features 3 Description • InputVoltageRange:1.1Vto5.5V The TPS74401 low-dropout (LDO) linear regulators 1 provide an easy-to-use robust power-management • Soft-Start(SS)PinProvidesaLinearStartupWith solution for a wide variety of applications. The user- RampTimeSetbyExternalCapacitor programmable soft-start minimizes stress on the input • 1%AccuracyOverLine,Load,andTemperature power source by reducing capacitive inrush current • SupportsInputVoltagesasLowas0.9VWith on start-up. The soft-start is monotonic and well- suited for powering many different types of ExternalBiasSupply processors and application-specific integrated circuits • AdjustableOutput:0.8Vto3.6V (ASICs). The enable input and power-good output • Ultra-LowDropout:115mVat3.0A(typical) allow easy sequencing with external regulators. This • StableWithAnyorNoOutputCapacitor complete flexibility lets the user configure a solution that meets the sequencing requirements of field- • ExcellentTransientResponse programmable gate arrays (FPGAs), digital signal • Open-DrainPower-Good(VQFNOnly) processors (DSPs), and other applications with • Packages:5-mm×5-mm ×1-mmVQFN(RGW), specificstart-uprequirements. 3.5-mm× 3.5-mmVQFN(RGR),andDDPAK A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. 2 Applications The TPS74401 family of LDOs is stable without an • FPGAApplications output capacitor or with ceramic output capacitors. The device family is fully specified from T = –40°C to • DSPCoreandI/OVoltages J 125°C. The TPS74401 is offered in two 20-pin small • Post-RegulationApplications VQFN packages (a 5-mm × 5-mm RGW and a • ApplicationsWithSpecialStart-UpTimeor 3.5-mm × 3.5-mm RGR package), yielding a highly SequencingRequirements compact total solution size. For applications that require additional power dissipation, the DDPAK • Hot-SwapandInrushControls (KTW)packageisalsoavailable. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) TO-263(7) 10.10mm×8.89mm TPS74401 VQFN,RGW(20) 5.00mm×5.00mm VQFN,RGR(20) 3.50mm×3.50mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SPACE SPACE SPACE SPACE TypicalApplicationCircuit Turn-OnResponse VIN IN PG VPG C = 0mF C1mINF EN RPULLUP SSC = 0.001mF VOUT BIAS TPS74401 OUT VOUT SS VBIAS SS R1 COUT 500mV/div CSS= 0.0047mF CBIAS GND FB Optional 1mF CSS R2 1.1V V EN R1= VVOUT -1 ´R2 1V/div 0V REF Time (1ms/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 18 2 Applications........................................................... 1 8.1 ApplicationInformation............................................18 3 Description............................................................. 1 8.2 TypicalApplications................................................20 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 24 5 PinConfigurationandFunctions......................... 5 10 Layout................................................................... 25 6 Specifications......................................................... 6 10.1 LayoutGuidelines.................................................25 6.1 AbsoluteMaximumRatings......................................6 10.2 LayoutExample....................................................25 6.2 ESDRatings ............................................................6 10.3 PowerDissipation.................................................25 6.3 RecommendedOperatingConditions.......................6 10.4 ThermalConsiderations........................................26 6.4 ThermalInformation..................................................7 11 DeviceandDocumentationSupport................. 29 6.5 ElectricalCharacteristics...........................................7 11.1 DeviceSupport......................................................29 6.6 TimingRequirements................................................8 11.2 DocumentationSupport .......................................29 6.7 TypicalCharacteristics..............................................9 11.3 ReceivingNotificationofDocumentationUpdates29 7 DetailedDescription............................................ 14 11.4 CommunityResources..........................................29 7.1 Overview.................................................................14 11.5 Trademarks...........................................................29 7.2 FunctionalBlockDiagram.......................................14 11.6 ElectrostaticDischargeCaution............................29 7.3 FeatureDescription.................................................14 11.7 Glossary................................................................29 7.4 DeviceFunctionalModes........................................15 12 Mechanical,Packaging,andOrderable Information........................................................... 30 7.5 Programming..........................................................16 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionQ(April2015)toRevisionR Page • AddedRGRpackagetodocument........................................................................................................................................ 1 • ChangedTPS744xxtoTPS74401throughoutdocument ..................................................................................................... 1 • ChangedPackagesFeaturesbullet ...................................................................................................................................... 1 • ChangedsecondparagraphofDescriptionsection:addedRGRpackageandchangedsecondtolastsentence...............1 • DeletedfixedvoltageversionofTypicalApplicationCircuitdiagram..................................................................................... 1 • AddedRGRpackagetoPinConfigurationandFunctionssection........................................................................................ 5 • ChangedFB/SNStoFBinbothpinoutdrawings,deletedTPS744xxfromVQFNpackage ............................................... 5 • ChangedSurfaceMounttoTopViewinKTWpinoutdrawing.............................................................................................. 5 • ChangedinputcapacitortobiascapacitorinBIASpindescription ....................................................................................... 5 • Deleted(adjustableversiononly)fromdescriptionofFBpininPinFunctionstable ............................................................ 5 • ChangedI/Ocolumnvalueto—fromOforNCpinsofPinFunctionstable ........................................................................ 5 • DeletedSNSpinfromPinFunctionstable ............................................................................................................................ 5 • AddedRGRpackagetoThermalInformationtable .............................................................................................................. 7 • Deleted(adjustableversion)fromV parameternameinElectricalCharacteristicstable ................................................ 7 REF • DeletedSNSpinreferencefromI ,I parameter:changedsymbolfromI ,I toI ,deletedsensefrom FB SNS FB SNS FB parametername..................................................................................................................................................................... 7 • Deletedadjustablefromfootnote1anddeletedI fromfootnote4ofElectricalCharacteristicstable.............................. 7 SNS • ChangedconditionsofR ,R inNoiseSpectralDensityfigure........................................................................................... 11 1 2 • DeletedFixedVoltageVersionsfigurefromFunctionalBlockDiagramsection.................................................................. 14 • ChangedfirstparagraphofApplicationInformationsection:deletedandtrackingcapabilitiesfromfirstsentenceand changedverylowinputandoutputvoltagestoverylowoutputvoltageswithlowV toV headroominlastsentence 18 IN OUT • ChangedtitleoffirsttypicalapplicationfromAdjustableVoltagePartandSettingtoSettingtheTPS74401.....................20 • DeletedreferencetoadjustableversioninfirstsentenceandTypicalApplicationCircuitfortheTPS74401figurein firsttypicalapplicationsection.............................................................................................................................................. 20 • ChangedBecauseV ≥V +1.62VtoBecauseV islessthanV plustheV dropoutandV =V to IN OUT IN OUT BIAS BIAS IN 2 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Revision History (continued) V =V inlastparagraphofDetailedDesignProcedureinfirsttypicalapplicationsection......................................... 21 BIAS OUT • DeletedFixedVoltageandSensePinsection..................................................................................................................... 23 • DeletedBIASrecommendationfromLayoutGuidelinessection.......................................................................................... 25 • ChangedRGWPackagetoVQFNPackagesincaptionofLayoutSchematicfigure.......................................................... 25 • AddedRGRpackagetoVQFNdescriptioninPowerDissipationsection............................................................................ 26 • AddedRGRpackagetoThermalConsiderationssection ................................................................................................... 27 ChangesfromRevisionP(January2015)toRevisionQ Page • ChangedQFNtoVQFNthroughoutdocument...................................................................................................................... 1 • ChangedTPS744xxtoTPS74401throughoutdocument ..................................................................................................... 1 • DeletedfixedoutputFeaturesbullet....................................................................................................................................... 1 • ChangedV minimumvalueinRecommendedOperatingConditionstable...................................................................... 6 BIAS • Changedfootnote1forRecommendedOperatingConditionstable...................................................................................... 6 • AddedsecondrowtoV accuracyparameter ................................................................................................................... 7 OUT • AddedlastfourrowstoV ,V dropoutvoltageparameter.............................................................................................. 7 DO BIAS • AddedTimingRequirementstable......................................................................................................................................... 8 • AddedDeviceFunctionalModessection............................................................................................................................. 15 • ChangedthirdparagraphofDropoutVoltage...................................................................................................................... 19 • ChangedfirstsentenceofWithoutanAuxiliaryBiassection............................................................................................... 24 • ChangedPowerDissipationsectionlocation;movedtoafterLayoutExamplesection....................................................... 25 • AddedDevelopmentSupportsection................................................................................................................................... 29 • AddedinformationaboutreferencedesignTIDU421anduserguideSLVU143toRelatedDocumentationsection .........29 ChangesfromRevisionO(March2013)toRevisionP Page • DeletedActiveHighEnablebulletfromFeatureslist ............................................................................................................ 1 • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 6 • Changedfootnote3cforThermalInformationtable .............................................................................................................. 7 • Changedy-axisinFigure1,Figure2,Figure4,andFigure7fromabbreviation(I )totext(OutputCurrent).................. 9 OUT • Added"V"toV =1.8VconditioninFigure9,Figure10,andFigure11 ............................................................................ 9 IN • y-axisandgraphtitleinFigure15fromabbreviation(I )totext(OutputCurrent) .......................................................... 10 OUT • ChangedFigure25;madeV traceredtoshowdatatrendseparation .......................................................................... 12 OUT • ChangedOverviewsectiontext............................................................................................................................................ 14 • ChangedsecondparagraphofDropoutVoltage ................................................................................................................. 19 • ChangedFigure27;updatedequationinfigure .................................................................................................................. 20 ChangesfromRevisionN(December2012)toRevisionO Page • ChangedRGWandKTWvaluesinThermalInformationtable.............................................................................................. 7 ChangesfromRevisionM(November2010)toRevisionN Page • ChangedT maxvaluefrom125to150inAbsoluteMaximumRatingstable....................................................................... 6 J Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com ChangesfromRevisionL(August,2010)toRevisionM Page • CorrectedequationforTable2............................................................................................................................................ 17 ChangesfromRevisionK(December,2009)toRevisionL Page • ReplacedtheDissipationRatingstablewiththeThermalInformationtable.......................................................................... 7 • RevisedLayoutRecommendationsandPowerDissipationsection.................................................................................... 25 • RevisedThermalConsiderationssection............................................................................................................................. 26 4 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 5 Pin Configuration and Functions RGW,RGRPackage KTWPackage 5-mm×5-mmand3.5-mm×3.5-mm,20-PinVQFN 7-PinDDPAK TopView TopView T C C C U N N N N O I 5 4 3 2 1 IN 6 20 OUT IN 7 19 OUT 1 2 3 4 5 6 7 IN 8 GND 18 OUT PG 9 17 NC BIAS 10 16 FB SS OUT IN EN FB GND BIAS 1 2 3 4 5 1 1 1 1 1 N D C C S E N N N S G PinFunctions PIN RGW, I/O DESCRIPTION NAME KTW RGR Biasinputvoltageforerroramplifier,reference,andinternalcontrolcircuits. BIAS 6 10 I A1-µForlargerbiascapacitorisrecommendedforoptimalperformance. IfINisconnectedtoBIAS,usea4.7µForlargercapacitor. Enablepin.Drivingthispinhighenablestheregulator.Drivingthispinlowputsthe EN 7 11 I regulatorintoshutdownmode.Thispinmustnotbeleftfloating. Thispinisthefeedbackconnectiontothecentertapofanexternalresistordivider FB 2 16 I networkthatsetstheoutputvoltage.Thispinmustnotbeleftfloating. GND 4 12 — Ground Unregulatedinputtothedevice. IN 5 5–8 I Aninputcapacitorof1µForgreaterisrecommendedforoptimalperformance. 2–4,13, Noconnection.ThispincanbeleftfloatingorconnectedtoGNDtoallowbetterthermal NC N/A — 14,17 contacttothetop-sideplane. Regulatedoutputvoltage.Nocapacitorisrequiredonthispinforstability,butis OUT 3 1,18–20 O recommendedforoptimalperformance. Mustbesolderedtothegroundplaneforincreasedthermalperformance. PAD/TAB — — — Internallyconnectedtoground. Power-good(PG)isanopen-drain,active-highoutputthatindicatesthestatusofV . OUT WhenV exceedsthePGtripthreshold,thePGpingoesintoahigh-impedancestate. OUT WhenV isbelowthisthreshold,thepinisdriventoalow-impedancestate.Connect PG N/A 9 O OUT apullupresistorfrom10kΩto1MΩfromthispintoasupplyupto5.5V.Thesupply canbehigherthantheinputvoltage. Alternatively,thePGpincanbeleftfloatingifoutputmonitoringisnotnecessary. Soft-startpin.Acapacitorconnectedonthispintogroundsetsthestart-uptime. SS 1 15 — Ifthispinisleftfloating,theregulatoroutputsoft-startramptimeistypically100µs. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V ,V Inputvoltage –0.3 6 V IN BIAS V Enablevoltage –0.3 6 V EN V Power-goodvoltage –0.3 6 V PG I PGsinkcurrent 0 1.5 mA PG V SSpinvoltage –0.3 6 V SS V Feedbackpinvoltage –0.3 6 V FB V Outputvoltage –0.3 V +0.3 V OUT IN I Maximumoutputcurrent Internallylimited OUT Outputshort-circuitduration Indefinite P Continuoustotalpowerdissipation SeeThermalInformation DISS T Operatingjunctiontemperature –40 150 °C J T Storagetemperature –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Inputsupplyvoltagerange 1.1 5.5 V IN V Enablesupplyvoltagerange 0 5.5 V EN V (1) BIASsupplyvoltagerange V +V (V ) 5.5 V BIAS OUT DO BIAS I Outputcurrent 0 3 A OUT C Outputcapacitor 0 µF OUT C (2) Inputcapacitor 1 µF IN C Biascapacitor 1 µF BIAS T Operatingjunctiontemperature –40 125 °C J (1) BIASsupplyisrequiredwhenV isbelowV +V (V ). IN OUT DO BIAS (2) IfV andV areconnectedtothesamesupply,therecommendedminimumcapacitorforthesupplyis4.7µF. IN BIAS 6 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 6.4 Thermal Information TPS74401(3) THERMALMETRIC(1)(2) RGW RGR KTW UNIT (VQFN) (VQFN) (DDPAK) 20PINS 20PINS 7PINS R Junction-to-ambientthermalresistance 35.4 39.1 26.6 °C/W θJA R Junction-to-case(top)thermalresistance 32.4 29.3 41.7 °C/W θJC(top) R Junction-to-boardthermalresistance 14.7 10.2 12.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.4 0.4 4.0 °C/W JT ψ Junction-to-boardcharacterizationparameter 14.8 10.1 7.3 °C/W JB R Junction-to-case(bottom)thermalresistance 3.9 2.0 0.3 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) ForthermalestimatesofthisdevicebasedonPCBcopperarea,seetheTIPCBThermalCalculator. (3) ThermaldatafortheRGW,RGR,andKTWpackagesarederivedbythermalsimulationsbasedonJEDEC-standardmethodologyas specifiedintheJESD51series.Thefollowingassumptionsareusedinthesimulations: (a)i.RGWandRGR:TheexposedpadisconnectedtothePCBgroundlayerthrougha4x4thermalviaarray. -ii.KTW:TheexposedpadisconnectedtothePCBgroundlayerthrougha6x6thermalviaarray. (b)Eachoftopandbottomcopperlayershasadedicatedpatternfor20%coppercoverage. (c) ThesedataweregeneratedwithonlyasingledeviceatthecenterofaJEDEChigh-K(2s2p)boardwith3in×3incopperarea.To understandtheeffectsofthecopperareaonthermalperformance,refertotheThermalConsiderationssection. 6.5 Electrical Characteristics AtV =1.1V,V =V +0.3V,C =C =0.1μF,C =10μF,I =50mA,V =5.0V,andT =–40°Cto125°C, EN IN OUT IN BIAS OUT OUT BIAS J unlessotherwisenoted.TypicalvaluesareatT =25°C. J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VIN Inputvoltagerange VOUT+VDO 5.5 V VBIAS Biaspinvoltagerange 2.375 5.25 V VREF Internalreference TJ=25°C 0.796 0.8 0.804 V Outputvoltagerange VIN=5V,IOUT=1.5A,VBIAS=5V VREF 3.6 V VOUT 25.097mAV≤≤VIOBUIATS≤≤35.0.2A5(1V),VOUT+1.62V≤VBIAS, –1% ±0.2% 1% Accuracy V10O0UTm+AV≤DOIOUBTIA≤SIV≤DVOBBIAIASS≤,V5.Q25FNV(,2) –1% ±0.2% 1% VOUT(nom)+0.3≤VIN ≤5.5V,VQFN 0.0005 0.05 ΔVOUT(ΔVIN) Lineregulation %/V VOUT(nom)+0.3≤VIN ≤5.5V,DDPAK 0.0005 0.06 0mA≤IOUT≤50mA 0.013 %/mA ΔVOUT(ΔIOUT) Loadregulation 50mA≤IOUT≤3.0A 0.03 %/A VINdropoutvoltage(3) IOUT=3.0A,VBIAS–VOUT(nom)≥1.62V,VQFN 115 195 mV IOUT=3.0A,VBIAS–VOUT(nom)≥1.62V,DDPAK 120 240 IOUT=3.0A,VIN=VBIAS 1.62 VDO IOUT=3.0A 1.62 VBIASdropoutvoltage(3) IOUT=1.0A 1.35 V IOUT=500mA 1.27 IOUT=100mA 1.16 VOUT=80%×VOUT(nom),VQFN 3.8 6.0 ICL Currentlimit A VOUT=80%×VOUT(nom),DDPAK 3.5 6.0 IBIAS Biaspincurrent IOUT=0mAto3.0A 2 4 mA ISHDN Shutdownsupplycurrent(VIN) VEN≤0.4V 1 100 μA IFB Feedbackpincurrent(4) IOUT=50mAto3.0A –250 95 250 nA (1) Devicestestedat0.8V;externalresistortoleranceisnottakenintoaccount. (2) V issetto1.5VtoavoidminimumV restrictions. OUT BIAS (3) DropoutisdefinedasthevoltagefromtheinputtoV whenV is2%belownominal. OUT OUT (4) I currentflowisoutofthedevice. FB Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Electrical Characteristics (continued) AtV =1.1V,V =V +0.3V,C =C =0.1μF,C =10μF,I =50mA,V =5.0V,andT =–40°Cto125°C, EN IN OUT IN BIAS OUT OUT BIAS J unlessotherwisenoted.TypicalvaluesareatT =25°C. J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Power-supplyrejection 1kHz,IOUT=1.5A,VIN=1.8V,VOUT=1.5V 73 dB PSRR(5) (VINtoVOUT) 800kHz,IOUT=1.5A,VIN=1.8V,VOUT=1.5V 42 Power-supplyrejection 1kHz,IOUT=1.5A,VIN=1.8V,VOUT=1.5V 62 dB (VBIAStoVOUT) 800kHz,IOUT=1.5A,VIN=1.8V,VOUT=1.5V 50 Vn Outputnoisevoltage 100Hzto100kHz,IOUT=1.5A,CSS=0.001µF 16×VOUT µVRMS VTRAN %traVnOsUieTndtroopduringload IOUT=100mAto3.0Aat1A/µs,COUT=0µF 4 %VOUT ISS Soft-startchargingcurrent VSS=0.4V 0.5 0.73 1 μA VEN(high) Enableinputhighlevel 1.1 5.5 V VEN(low) Enableinputlowlevel 0 0.4 V VEN(hys) Enablepinhysteresis 50 mV IEN Enablepincurrent VEN=5V 0.1 1 μA VIT PGtripthreshold VOUTdecreasing 86.5 90 93.5 %VOUT VHYS PGtriphysteresis 3 %VOUT VPG(low) PGoutputlowvoltage IPG=1mA(sinking),VOUT<VIT 0.3 V IPG(lkg) PGleakagecurrent VPG=5.25V,VOUT>VIT 0.03 1 μA TJ Operatingjunctiontemperature –40 125 °C Shutdown,temperatureincreasing 155 TSD Thermalshutdowntemperature °C Reset,temperaturedecreasing 140 (5) SeeFigure8toFigure11forPSRRatdifferentconditions. 6.6 Timing Requirements AtV =1.1V,V =V +0.3V,C =C =0.1μF,C =10μF,I =50mA,V =5.0V,andT =–40°Cto125°C, EN IN OUT IN BIAS OUT OUT BIAS J unlessotherwisenoted.TypicalvaluesareatT =25°C. J MIN NOM MAX UNIT t Minimumstartuptime(I =1.5A,C =open) 100 μs STR OUT SS V Enablepinde-glitchtime 20 μs EN(dg) 8 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 6.7 Typical Characteristics AtT =25°C,V =1.5V,V =V +0.3V,V =3.3V,I =50mA,C =1μF,C =1μF,C =0.01μF,and J OUT IN OUT(nom) BIAS OUT IN BIAS SS C =10μF,unlessotherwisenoted. OUT 1.0 0.050 0.9 Referred to IOUT= 50mA Referred to IOUT= 50mA 0.025 0.8 %) 0.7 %) 0 V(OUT 00..65 -40°C V(OUT -0.025 +25°C n n -0.050 nge i 00..43 +25°C nge i -0.075 -40°C ha ha +125°C C 0.2 C -0.100 0.1 +125°C -0.125 0 -0.1 -0.150 0 10 20 30 40 50 50 500 1000 1500 2000 2500 3000 Output Current (mA) Output Current (mA) Figure1.LoadRegulation Figure2.LoadRegulation 0.05 200 0.04 0.03 V) 150 n V(%)OUT 00..00210 TJ=-40°C oltage (m 100 +125°C Change i --00..0012 TJ= +125°C TJ= +25°C opout V Dr 50 -0.03 +25°C -0.04 -40°C -0.05 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 500 1000 1500 2000 2500 3000 VIN-VOUT(V) Output Current (mA) Figure3.LineRegulation Figure4.V DropoutVoltagevsI andTemperature(T ) IN OUT J 300 200 I = 3.0A I = 1.5A OUT OUT 180 250 160 V) +125°C V) m 200 m 140 age ( +25°C age ( 120 +125°C olt 150 olt 100 ut V ut V 80 +25°C o o p 100 p o o 60 Dr Dr 40 50 -40°C -40°C 20 0 0 0.9 1.4 1.9 2.4 2.9 3.4 3.9 0.9 1.4 1.9 2.4 2.9 3.4 3.9 V -V (V) V -V (V) BIAS OUT BIAS OUT Figure5.V DropoutVoltagevsV –V and Figure6.V DropoutVoltagevsV –V and IN BIAS OUT IN BIAS OUT Temperature(T ) Temperature(T ) J J Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Typical Characteristics (continued) AtT =25°C,V =1.5V,V =V +0.3V,V =3.3V,I =50mA,C =1μF,C =1μF,C =0.01μF,and J OUT IN OUT(nom) BIAS OUT IN BIAS SS C =10μF,unlessotherwisenoted. OUT 1400 80 11320000 VIN= VBIAS +125°C +25°C o (dB) 70 IOUT= 3.0A V) ati 60 age (m 11100000 ction R 50 Dropout Volt 980000 -40°C Supply Reje 432000 700 er- w 600 Po 10 500 0 0 500 1000 1500 2000 2500 3000 10 100 1k 10k 100k 1M 10M Output Current (mA) Frequency (Hz) Figure7.VBIASDropoutVoltagevsIOUTandTemperature Figure8.VBIASPSRRvsFrequency (T ) J 100 100 V = 1.8V, V = 1.5V, I = 100mA V = 1.8V, V = 1.5V, I = 1.5A B) 90 IN OUT OUT B) 90 IN OUT OUT d d Ratio ( 8700 COUT= 100mF COUT= 10mF Ratio ( 8700 n n COUT= 100mF ejectio 6500 ejectio 6500 COUT= 10mF R R y 40 y 40 pl pl up 30 up 30 S S er- 20 er- 20 w C = 0mF w Po 10 OUT Po 10 C = 0mF 0 0 OUT 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure9.V PSRRvsFrequency Figure10.V PSRRvsFrequency IN IN 100 90 B) 90 VIN= 1.8V, VOUT= 1.5V, IOUT= 3A B) 80 1kHz Ratio (d 8700 Ratio (d 70 700kHz upply Rejection 65430000 COUT= 100mF COUT= 10mF upply Rejection 65430000 300kHz 100kHz S S er- 20 er- 20 Pow 10 COUT= 0mF Pow 10 CIOOUUTT== 1 2.52AmF 0 0 10 100 1k 10k 100k 1M 10M 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 Frequency (Hz) V -V (V) IN OUT Figure11.VINPSRRvsFrequency Figure12.VINPSRRvsVIN –VOUT 10 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Typical Characteristics (continued) AtT =25°C,V =1.5V,V =V +0.3V,V =3.3V,I =50mA,C =1μF,C =1μF,C =0.01μF,and J OUT IN OUT(nom) BIAS OUT IN BIAS SS C =10μF,unlessotherwisenoted. OUT 1 1 mÖDensity (V/)Hz IVOOUUTT== 3 1A.1V CSS= 1nF CSS= 0nF Density (V/)HzmÖ VOUT= 3.3 VVOUT= 2.5 V VICCROBIO1UN,IUAT :R :TS1 ::32 1:mV A(FOm1 UF%(TC ( +eRC ree1asr.m6ais2mict o)Vicrs)) Noise 0.1 Noise 0.1 Output Spectral 0.01 CSS= 10nF Output Spectral 0.01 VOUT= 1.5 V VOUT= 1.1 V VOUT= 0.8 V 100 1k 10k 100k 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure13.NoiseSpectralDensity Figure14.NoiseSpectralDensity 2.85 3.0 +125°C 2.65 2.8 2.6 TJ=+125°C 2.45 A) A) 2.4 m 2.25 m nt ( nt ( 2.2 as Curre 21..0855 +25°C as Curre 21..08 TJ= +25°C Bi Bi 1.6 1.65 T =-40°C -40°C 1.4 J 1.45 1.2 1.25 1.0 0 500 1000 1500 2000 2500 3000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Current (mA) V (V) BIAS Figure15.IBIASvsOutputCurrentandTemperature Figure16.IBIASvsVBIASandVOUT 0.45 765 0.40 V = 2.375V 750 BIAS 0.35 A) 0.30 735 m nt ( 0.25 VBIAS= 5.5V A) s Curre 0.20 I(nSS 720 Bia 0.15 705 0.10 690 0.05 0 675 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Junction Temperature (°C) Junction Temperature (°C) Figure17. IBIASShutdownvsTemperature Figure18.Soft-StartChargingCurrent(ISS)vsTemperature Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Typical Characteristics (continued) AtT =25°C,V =1.5V,V =V +0.3V,V =3.3V,I =50mA,C =1μF,C =1μF,C =0.01μF,and J OUT IN OUT(nom) BIAS OUT IN BIAS SS C =10μF,unlessotherwisenoted. OUT 1.0 C =2 x 470mF (OSCON) 0.9 50mV/div OUT e (V) 0.8 50mV/div COUT=100mFCer. g olta 0.7 50mV/div COUT=10mFCer. G V 0.6 el P 0.5 C =0mF ev 0.4 50mV/div OUT L Low- 0.3 3.0A OL 0.2 1A/ms V 2A/div 0.1 100mA 0 Time (50ms/div) 0 2 4 6 8 10 12 PG Current (mA) Figure19.Low-LevelPGVoltagevsPGCurrent Figure20.LoadTransientResponse 10mV/div COUT= 2 x 470mF (OSCON) 10mV/div COUT= 2 x 47(0OmSFCON) VOUT= 1.2V C = 100mF (Cer.) C = 100mF (Cer.) OUT OUT 10mV/div 10mV/div COUT= 10mF (Cer.) COUT= 10mF(Cer.) 10mV/div 10mV/div C = 0mF 10mV/div OUT C = 0mF OUT 10mV/div 4.3V 2.5V 1V/ms 1V/ms 500mV/div 500mV/div 3.3V 1.5V Time (50ms/div) Time (50ms/div) Figure21.V LineTransient(3A) Figure22.V LineTransient(3A) BIAS IN C = 0mF SS V OUT C = 0.001mF SS 500mV/div CSS= 0.0047mF VIN= VBIAS= VEN V (500mV/div) v PG di V/ 1 1.1V V EN 1V/div 0V VOUT Time (1ms/div) Time (20ms/div) Figure23.Turn-OnResponse Figure24.Power-Up,Power-Down 12 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Typical Characteristics (continued) AtT =25°C,V =1.5V,V =V +0.3V,V =3.3V,I =50mA,C =1μF,C =1μF,C =0.01μF,and J OUT IN OUT(nom) BIAS OUT IN BIAS SS C =10μF,unlessotherwisenoted. OUT V = 0.8V OUT V Output Shorted OUT I 50mV/div OUT 1A/div Output Open Time (20ms/div) Figure25.OutputShort-CircuitRecovery Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 7 Detailed Description 7.1 Overview The TPS74401 family of low-dropout regulators (LDOs) incorporates many features to ensure a wide range of uses. Hysteresis and de-glitch on the EN input improve the ability to sequence multiple devices without worrying about false start-up. The soft-start is fully programmable and allows the user to control the startup time of the LDO output. Hysteresis is also available on the PG comparator to ensure no false PG signals. The TPS74401 familyofLDOsisidealforFPGAs,DSPs,andanyotherdevicethatrequireslinearsupplyandsequencing. 7.2 Functional Block Diagram Current OUT IN Limit VOUT BIAS UVLO Thermal 0.73mA Limit R1 SS C SS R V = 0.8 x (1 + 1) Soft-Start 0.8V OUT R2 Discharge Reference FB PG Hysteresis EN and De-Glitch R2 0.9´V REF GND 7.3 Feature Description 7.3.1 Enable,Shutdown The enable (EN) pin is active high and compatible with standard digital signaling levels. V lower than 0.4 V EN turns the regulator off, whereas V above 1.1 V turns the regulator on. Unlike many regulators, the enable EN circuitry has hysteresis and de-glitching for use with relatively slow-ramping analog signals. This configuration allows the TPS74401 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50 mV of hysteresis and a de-glitch circuit to help avoid on-off cycling resulting from small glitchesintheV signal. EN The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature variation is approximately –1 mV/°C; therefore, process variation accounts for most of the variation in the enable threshold.Ifpreciseturn-ontimingisrequired,useafastrise-timesignaltoenabletheTPS74401. Ifnotused,ENcanbeconnectedtoeitherINorBIAS.IfENisconnectedtoIN,connectENascloseaspossible tothelargestcapacitanceontheinputtopreventvoltagedroopsonthatlinefromtriggeringtheenablecircuit. 14 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Feature Description (continued) 7.3.2 Power-Good(VQFNPackageOnly) The power-good (PG) pin is an open-drain output and can be connected to any 5.5 V or lower rail through an external pullup resistor. This pin requires at least 1.1 V on V in order to have a valid output. The PG output is BIAS high-impedancewhenV isgreaterthan(V +V ).IfV dropsbelowV orifV dropsbelow1.9V,the OUT IT HYS OUT IT BIAS open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The recommended operating condition of the PG pin sink current is up to 1 mA, thus the pullup resistor for PG must be in the range of 10 kΩ to 1 MΩ. PG is only provided on the VQFN package. If output voltage monitoring isnotneeded,thePGpincanbeleftfloating. 7.3.3 InternalCurrentLimit The TPS74401 features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage. The current limit allows the device to supply surges of up to 3.5 A and maintain regulation. The current limit responds in approximately 10 μs to reduce the current during a short-circuit fault. Recovery from a short-circuit condition is well-controlled and results in very little output overshoot when the load is removed. See Figure 25 in theTypicalCharacteristicssectionforshort-circuitrecoveryperformance. The internal current limit protection circuitry of the TPS74401 is designed to protect against overload conditions. This circuitry is not intended to allow operation above the rated current of the device. Continuously running the TPS74401abovetheratedcurrentdegradesdevicereliability. 7.3.4 ThermalProtection Thermal protection disables the output when the junction temperature rises to approximately 155°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst- case loads and signal conditions. For good reliability, trigger thermal protection at least 30°C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperatureof125°Catthehighestexpectedambienttemperatureandworst-caseload. The internal protection circuitry of the TPS74401 is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS74401 into thermal shutdown degradesdevicereliability. 7.4 Device Functional Modes 7.4.1 NormalOperation Thedeviceregulatestothenominaloutputvoltageunderthefollowingconditions: • Theinputvoltageandbiasvoltagearebothatleastattherespectiveminimumspecifications. • The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased belowtheenablefallingthreshold. • Theoutputcurrentislessthanthecurrentlimit. • Thedevicejunctiontemperatureislessthanthemaximumspecifiedjunctiontemperature. • Thedeviceisnotoperatingindropout. 7.4.2 DropoutOperation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO.Lineorloadtransientsindropoutcanresultinlargeoutputvoltagedeviations. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Device Functional Modes (continued) 7.4.3 Disabled Thedeviceisdisabledunderthefollowingconditions: • Theinputorbiasvoltagesarebelowtherespectiveminimumspecifications. • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. • Thedevicejunctiontemperatureisgreaterthanthethermalshutdowntemperature. Table1showstheconditionsthatleadtothedifferentmodesofoperation. Table1.DeviceFunctionalModeComparison PARAMETER OPERATINGMODE V V V I T IN EN BIAS OUT J Normalmode V >V +V (V ) V >V V ≥V +1.62V I <I T <125°C IN OUT(nom) DO IN EN EN(high) BIAS OUT OUT CL J Dropoutmode V <V +V (V ) V >V V <V +1.62V — T <125°C IN OUT(nom) DO IN EN EN(high) BIAS OUT J Disabledmode (anytrueconditiondisables V <V V <V V <V — T >155°C IN IN(min) EN EN(low) BIAS BIAS(min) J thedevice) 7.5 Programming 7.5.1 ProgrammableSoft-Start The TPS74401 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor(C ).Thisfeatureisimportantformanyapplicationstoeliminatepower-upinitializationproblemswhen SS poweringFPGAs,DSPs,orotherprocessors.Thecontrolledvoltagerampoftheoutputalsoreducespeakinrush currentduringstart-up,minimizingstart-uptransientstotheinputpowerbus. To achieve a linear and monotonic soft-start, the TPS74401 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start charging current (I ), the soft-start capacitance (C ), and the internal reference voltage (V ), SS SS REF andcanbecalculatedusingEquation1: (cid:11)V uC (cid:12) t REF SS SS I SS (1) If large output capacitors are used, the device current limit (I ) and the output capacitor can set the start-up CL time.Inthiscase,thestart-uptimeisgivenbyEquation2: (V ´C ) t = OUT(nom) OUT SSCL I CL(min) where • V isthenominalsetoutputvoltageassetbytheuser, OUT(nom) • C istheoutputcapacitance, OUT • andI istheminimumcurrentlimitforthedevice. (2) CL(min) In applications where monotonic startup is required, the soft-start time given by Equation 1 must be set to be greaterthanEquation2. 16 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Programming (continued) Themaximumrecommendedsoft-startcapacitoris0.015μF.Largersoft-startcapacitorscanbeusedanddonot damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft- start capacitor when re-enabled. Soft-start capacitors larger than 0.015 μF can be a problem in applications where the user must rapidly pulse the enable pin and also require the device to soft-start from ground. C must SS be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Table 2 lists suggested soft-start capacitor values. Table2.StandardCapacitorValuesforProgrammingtheSoft-StartTime(1) C SOFT-STARTTIME SS Open 0.1ms 470pF 0.5ms 1000pF 1ms 4700pF 5ms 0.01μF 10ms 0.015μF 16ms V ×C 0.8V×C (F) t (s) = REF SS = SS SS I 0.73mA (1) SS wheretSS(s)=soft-starttimeinseconds. 7.5.2 SequencingRequirements The device can have V , V , and V sequenced in any order without causing damage to the device. IN BIAS EN However, for the soft-start function to work as intended, certain sequencing rules must be applied. Enabling the device after V and V are present is preferred, and can be accomplished using a digital output from a IN BIAS processor or supply supervisor. An analog signal from an external RC circuit, as shown in Figure 26, can also be usedaslongasthedelaytimeislongenoughforV andV tobepresent. IN BIAS VIN IN OUT VOUT C1mINF R1 BIAS TPS74401 FB VBIAS R R2 CBIAS EN GND SS 1mF C CSS Figure26. Soft-StartDelayUsinganRCCircuitonEnable If a signal is not available to enable the device after IN and BIAS, simply connecting EN to IN is acceptable for most applications as long as V is greater than 1.1 V and the ramp rate of V and V is faster the set soft- IN IN BIAS start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply less the dropout voltage until the set output voltage is reached. If EN is connected to BIAS, the device soft-starts as programmed, provided that V is present before V . If V and V are present before IN BIAS BIAS EN V isappliedandthesetsoft-starttimehasexpired,thenV tracksV . IN OUT IN Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS74401 belongs to a family of ultra-low dropout regulators that feature soft-start. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very lowoutputvoltageswithlowV toV headroom. IN OUT TheuseofanNMOS-passFEToffersseveralcriticaladvantagesformanyapplications.UnlikeaPMOStopology device, the output capacitor has little affect on loop stability. This architecture allows the TPS74401 to be stable withanyorevennooutputcapacitor.TransientresponseisalsosuperiortoPMOStopologies,particularlyforlow V applications. IN The TPS74401 features a programmable, voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that can be caused by large capacitive loads. A power-good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresisandde-glitchallowsslow-rampingsignalstobeusedforsequencingthedevice.ThelowV andV IN OUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltagesoftenpresentinprocessorintensivesystems. 8.1.1 Input,Output,andBiasCapacitorRequirements The TPS74401 does not require any output capacitor for stability. If an output capacitor is needed, the device is designed to be stable for all available types and values of output capacitance. The device is also stable with multiple capacitors in parallel, of any type or value. This flexibility is a result of an innovative control loop that ensuresthedeviceisstableindependentoftheoutputcapacitance. The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for V and V is 1 μF. If V and IN BIAS IN V are connected to the same supply, the recommended minimum capacitor for V is 4.7 μF. Use good BIAS BIAS quality, low-ESR capacitors on the input; ceramic X5R and X7R capacitors are preferred. Place these capacitors asclosetothepinsaspossibleforoptimumperformanceandtohelpensurestability. 8.1.2 TransientResponse The TPS74401 is designed to have transient response within 5% for most applications without an output capacitor. In some cases, the transient response can be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient at the expense of a slightly longer V recovery time; see OUT Figure 20 in the Typical Characteristics section. Because the TPS74401 is stable without an output capacitor, many applications can allow for little or no capacitance at the LDO output. For these applications, local bypass capacitance for the device under power can be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDOoutput. 18 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Application Information (continued) 8.1.3 DropoutVoltage The TPS74401 offers industry-leading dropout performance, making the device well-suited for high-current, low V and low V applications. The extremely low dropout of the TPS74401 also allows the device to be used in IN OUT place of a dc/dc converter and also achieve good efficiencies. Equation 3 provides a quick estimate of the efficiencies. V ´I OUT OUT V Efficiency» » OUT atI >>I V ´(I + I ) V OUT Q IN IN Q IN (3) This efficiency allows users to redesign the power architecture for their applications to achieve the smallest, simplest,andlowestcostsolution. There are two different specifications for dropout voltage with the TPS74401. The first specification (see Figure 38) is referred to as V Dropout and is for users who wish to apply an external bias voltage to achieve IN low dropout. This specification assumes that V is at least 1.62 V above V ; for example, when V is BIAS OUT BIAS powered by a 3.3-V rail with 5% tolerance and with V = 1.5 V. If V is higher than (3.3 V × 0.95) or V is OUT BIAS OUT lessthan1.5V,V dropoutislessthanspecified. IN The second specification (see Figure 39) is referred to as V Dropout and is for users who wish to have V BIAS BIAS < V + 1.62 V. This option allows the device to be used in applications where an auxiliary bias voltage is not IN available or low dropout is not required. Dropout is limited by BIAS in these applications because V provides BIAS the gate drive to the pass FET and therefore must be greater than V + V (V ). Because of this usage, IN OUT DO BIAS and BIAS tied together easily consume excessive power. Pay attention and do not exceed the power rating of theICpackage. 8.1.4 OutputNoise The TPS74401 provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-μF soft-start capacitor, the output noise is reduced by half and is typically 19 μV for a 1.2-V output (100 Hz to RMS 100 kHz). Noise is a function of the set output voltage because most of the output noise is generated by the internalreference.TheRMSnoisewitha0.001-μFsoft-startcapacitorisgiveninEquation4. §µV • VN(cid:11)µVRMS(cid:12) 16¤ RMS ‚u VOUT(V) ' V „ (4) ThelowoutputnoiseoftheTPS74401makesthedeviceagoodchoiceforpoweringtransceivers,PLLs,orother noise-sensitivecircuitry. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 8.2 Typical Applications 8.2.1 SettingtheTPS74401 Figure27showsatypicalapplicationcircuitfortheTPS74401. R and R can be calculated for any output voltage using the formula shown in Figure 27. Table 3 lists sample 1 2 resistorvaluesofcommonoutputvoltages.Inordertoachievethemaximumaccuracyspecifications,R mustbe 2 ≤4.99kΩ. VIN IN PG VPG C R IN EN PULLUP 1mF BIAS TPS74401 OUT VOUT VBIAS SS R1 COUT CBIAS GND FB Optional 1mF CSS R2 V R1= VOUT -1 ´R2 REF Figure27. TypicalApplicationCircuitfortheTPS74401 Table3.Standard1%ResistorValuesforProgrammingtheOutputVoltage(1) R (kΩ) R (kΩ) V (V) 1 2 OUT Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 (1) V =0.8×(1+R /R ). OUT 1 2 NOTE WhenV andV arepresentandV isnotsupplied,thisdeviceoutputsapproximately BIAS EN IN 50 μA of current from OUT. Although this condition does not cause any damage to the device, the output current can charge up the OUT node if total resistance between OUT andGND(includingexternalfeedbackresistors)isgreaterthan10kΩ. 20 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 8.2.1.1 DesignRequirements The design goals are V = 1.8 V, V = 1.5 V, and I = 2 A max. The design optimizes transient response IN OUT OUT while meeting a 1-ms startup time with a startup dominated by the soft-start feature. The input supply comes fromasupplyonthesamecircuitboard.TheavailablesystemrailsforV are2.7V,3.3V,and5V. BIAS ThedesignspaceconsistsofC ,C ,C ,C ,V ,R ,R ,andR ,andthecircuitisfromFigure27. IN OUT BIAS SS BIAS 1 2 3 ThisexampleusesaV of1.8V,withaV of2.5V. IN BIAS 8.2.1.2 DetailedDesignProcedure The first step for this design is to examine the maximum load current along with the input and output voltage requirements, to determine if the device thermal and dropout voltage requirements can be met. At 3 A, the input dropout voltage of the TPS74401 family is a maximum of 240 mV over temperature. As a result, the dropout headroomissufficientforoperationoverbothinputandoutputvoltageaccuracy. The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element from the input to the output multiplied by the maximum load current. In this example, the maximum voltage drop across in the pass element is (1.8 V – 1.5 V), giving a V = 300 mV. The power dissipated can than be DROP estimated by the equation P = I × V = ~600 mW. This calculation gives an efficiency of nearly DISS L(max) DROP 83.3%byusingEquation3. When the power dissipated in the linear regulator is known, the corresponding junction temperature increase can be calculated. To estimate the junction temperature increase above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. For thermal resistance information, refer to the Thermal Information table. For this example, using the KTW package, the junction temperature rise is calculated to be 21.2°C. The maximum junction temperature increase is calculated by adding the junction temperature rise to the maximum ambient temperature. In this example, the maximum junction temperature is 46.2°C. Keep in mind that the junction temperature must be less than 125°C for reliable operation. Additional ground planes, added thermal vias,andairflowallhelptoimprovethethermaltransfercharacteristicsofthesystem. Thenextstepistodeterminethebiasvoltageorifaseparatesourceisneededforthebiasvoltage.BecauseV IN is less than V plus the V dropout, V must be an independent supply. V = V + 1.62 V = 3.12 V; OUT BIAS BIAS BIAS OUT the system has a 3.3-V rail to use for this supply and also to provide some limited headroom for V . The 5-V BIAS railisabetterchoicetoimprovetheperformanceoftheLDO,sothe5-Vrailisused. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 8.2.1.3 ApplicationCurves C = 0mF SS V OUT C = 0.001mF SS 500mV/div CSS= 0.0047mF VIN= VBIAS= VEN V (500mV/div) v PG di V/ 1 1.1V V EN 1V/div 0V VOUT Time (1ms/div) Time (20ms/div) Figure28.Turn-OnResponse Figure29.Power-Up,Power-Down 50mV/div COUT=2 x 470mF (OSCON) 10mV/div COUT= 2 x 47(0OmSFCON) VOUT= 1.2V COUT=100mFCer. COUT= 100mF (Cer.) 50mV/div 10mV/div 50mV/div COUT=10mFCer. 10mV/div COUT= 10mF(Cer.) C =0mF C = 0mF 50mV/div OUT 10mV/div OUT 2.5V 3.0A 1V/ms 1A/ms 2A/div 500mV/div 100mA 1.5V Time (50ms/div) Time (50ms/div) Figure30.LoadTransientResponse Figure31.V LineTransient(3A) IN 10mV/div COUT= 2 x 470mF (OSCON) VOUT= 0.8V C = 100mF (Cer.) OUT 10mV/div C = 10mF (Cer.) OUT 10mV/div Output Shorted VOUT 10mV/div COUT= 0mF IOUT 50mV/div 1A/div 4.3V 1V/ms 500mV/div Output Open 3.3V Time (50ms/div) Time (20ms/div) Figure32.V LineTransient(3A) Figure33.OutputShort-CircuitRecovery BIAS 22 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 200 300 I = 3.0A OUT 250 V) 150 V) +125°C e (m +125°C e (m 200 ag ag +25°C olt 100 olt 150 V V ut ut o o p p 100 o o Dr 50 Dr -40°C +25°C 50 -40°C 0 0 0 500 1000 1500 2000 2500 3000 0.9 1.4 1.9 2.4 2.9 3.4 3.9 Output Current (mA) VBIAS-VOUT(V) Figure34.V DropoutVoltagevsI andTemperature Figure35.V DropoutVoltagevsV –V and IN OUT IN BIAS OUT (T ) Temperature(T ) J J 200 1400 180 IOUT= 1.5A 1300 VIN= VBIAS +125°C +25°C 160 1200 V) V) age (m 114200 +125°C age (m 11100000 ut Volt 10800 +25°C ut Volt 900 -40°C o o p p 800 o 60 o Dr Dr 40 700 -40°C 20 600 0 500 0.9 1.4 1.9 2.4 2.9 3.4 3.9 0 500 1000 1500 2000 2500 3000 VBIAS-VOUT(V) Output Current (mA) Figure36.V DropoutVoltagevsV –V and Figure37.V DropoutVoltagevsI andTemperature IN BIAS OUT BIAS OUT Temperature(T ) (T ) J J 8.2.2 UsinganAuxiliaryBiasRail Figure 38 shows a typical application of the TPS74401 using an auxiliary bias rail. The auxiliary bias rail allows for the designer to specify the system to have a low V . The bias rail supplies the error amplifier with a higher DO supplyvoltage,increasingthevoltagethatcanbeappliedtothegateofthepassdevice. V mustbeatleastV +1.62V. BIAS OUT BIAS IN V = 5V±5% BIAS V = 1.8V IN V = 1.5V OUT I = 1.5A OUT Reference Efficiency = 83% OUT V OUT FB Simplified BlockDiagram Figure38. TypicalApplicationoftheTPS74401UsinganAuxiliaryBiasRail Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 8.2.3 WithoutanAuxiliaryBias The TPS74401 family is capable of operating without a bias rail if V ≥ V + V (V ). Additional IN OUT DO BIAS capacitanceisadvisedforthisscenario,withatleast4.7µFofcapacitanceneartheinputpin.Figure39 showsa typicalapplicationoftheTPS74401withoutanauxiliarybias. IfusingtheTPS74401inthissituationandunderhighloadconditions,ensurethattheprintedcircuitboard(PCB) provides adequate thermal handling capabilities to keep the device in its recommended operating range. See the PowerSupplyRecommendationssectionformoreinformation. V IN V = 3.3V±5% BIAS IN BIAS V = 3.3V±5% IN V = 1.5V OUT I = 1.5A OUT Reference Efficiency = 45% OUT V OUT FB Simplified BlockDiagram Figure39. TypicalApplicationoftheTPS74401WithoutanAuxiliaryBias 9 Power Supply Recommendations The TPS74401 is designed to operate from an input voltage between 1.1 V to 5.5 V, provided the bias rail is at least 1.62 V higher than the input supply. The bias rail and the input supply must both provide adequate headroomandcurrentforthedevicetooperatenormally. Connect a low output impedance power supply directly to the IN pin of the TPS74401. This supply must have at least 1 µF of capacitance near the IN pin for stability. A supply with similar requirements must also be connected directlytothebiasrailwithaseparate1µForlargercapacitor. IftheINpinistiedtothebiaspin,aminimum4.7 µFofcapacitanceisneededforstability. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead before the input capacitor. 24 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 10 Layout 10.1 Layout Guidelines An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop ontheinputofthedeviceduringloadtransients,connectthecapacitanceonINandBIASascloseaspossibleto the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source andcanthereforeimprovestability.Toachieveoptimaltransientperformanceandaccuracy,connectthetopside of R in Figure 27 as close as possible to the load. This connection minimizes the voltage droop on BIAS during 1 transientconditionsandcanimprovetheturn-onresponse. 10.2 Layout Example Input GND Plane Cin IN NC NC NC OUT Vin Plane 5 4 3 2 1 Vout Plane IN 6 20 OUT IN 7 19 OUT R(pull-up) IN 8 Thermal Pad 18 OUT PG 9 17 NC Cout R1 FB/ BIAS 10 16 SNS R1 & R2 should be Cbias 11 12 13 1144 15 connected close to the load, EN GND NC NC SS Cotuhte s hLoDuOld a bse p aoss snibelaer to R2 Css Keep the ground planes on the same side of the PCB if possible to improve thermal Output GND Plane disappation Figure40. LayoutSchematic(VQFNPackages) 10.3 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad iscriticaltoavoidingthermalshutdownandensuringreliableoperation. Power dissipation of the device depends on input voltage and load conditions, and can be calculated using Equation5: P =(V -V )´I D IN OUT OUT (5) Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Power Dissipation (continued) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltagenecessarytoachievetherequiredoutputvoltageregulation. On the VQFN (RGW, RGR) packages, the primary conduction path for heat is through the exposed pad to the PCB. The pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On the DDPAK (KTW) package, the primary conduction path for heat is through the tab to the PCB. Connect that tab to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature,andpowerdissipationofthedeviceandcanbeestimatedusingEquation6: (+125°C-T ) R = A qJA P D (6) Knowing the maximum R , the minimum amount of PCB copper area needed for appropriate heatsinking can θJA beestimatedusingFigure41. 120 100 80 W) °(C/ 60 A qJ 40 qJA(RGW) 20 q (KTW) JA 0 0 1 2 3 4 5 6 7 8 9 10 2 Board Copper Area (in) Note: θ valueatboardsizeof9in2(thatis,3in×3in)isaJEDECstandard. JA Figure41. θ versusBoardSize JA Figure 41 shows the variation of θ as a function of ground plane copper area in the board. Figure 41 is JA intended only as a guideline to demonstrate the affects of heat spreading in the ground plane; do not use Figure41toestimateactualthermalperformanceinrealapplicationenvironments. NOTE When the device is mounted on an application PCB, TI strongly recommends using Ψ JT andΨ ,asexplainedinthesection. JB 10.4 Thermal Considerations A better method of estimating the thermal measure comes from using the thermal metrics Ψ and Ψ , as shown JT JB in Thermal Information . These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than R . The junction temperature can be estimated with the corresponding formulas θJA giveninEquation7. Y : T = T +Y ·P JT J T JT D Y : T = T +Y ·P JB J B JB D where • P isthepowerdissipationshownbyEquation5, D • T isthetemperatureatthecenter-topoftheICpackage,and T • T isthePCBtemperaturemeasured1mmawayfromtheICpackageonthePCBsurface(seeFigure42). B (7) 26 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 Thermal Considerations (continued) NOTE Both T and T can be measured on actual application boards using a thermo-gun (an T B infraredthermometer). For more information about measuring T and T , see the application note Using New Thermal Metrics T B (SBVA025),availablefordownloadatwww.ti.com. TBon PCB TTontopof IC TTontopof IC(1) 1mm T on PCB B (2) surface 1mm (a) Example RGW (QFN) Package Measurement (b) Example KTW (DDPAK) Package Measurement (1) T ismeasuredatthecenterofboththeX-andY-dimensionalaxes. T (2) T ismeasuredbelowthepackageleadonthePCBsurface. B Figure42. MeasuringPointsforT andT T B Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com Compared with θ , the thermal metrics Ψ and Ψ are less independent of board size, but do have a small JA JT JB dependency on board size and layout. Figure 43 shows characteristic performance of Ψ and Ψ versus board JT JB size. Referring to Figure 43, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point symmetric to an IC center. In the KTW package, for example (see Figure 42), silicon is not beneath the measuring point of T which is the center of the X and Y dimension, so that Ψ has a T JT dependency. Also, because of that non-point symmetry, device heat distribution on the PCB is not point symmetriceither,sothatΨ hasagreaterdependencyonboardsizeandlayout. JB 12 10 Y (RGW) W) JB C/ 8 Y (KTW) °( JB B YJ 6 d n a T 4 YJ Y (KTW) JT 2 Y (RGW) JT 0 0 2 4 6 8 10 2 Board Copper Area (in) Figure43. Ψ andΨ versusBoardSize JT JB For a more detailed discussion of why TI does not recommend using θ to determine thermal characteristics, JC(top) refer to the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Also, refer to the application note IC Package Thermal Metrics (SPRA953) (also available on the TI website) for further information. 28 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

TPS74401 www.ti.com SBVS066R–DECEMBER2005–REVISEDAPRIL2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 DevelopmentSupport 11.1.1.1 EvaluationModules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS74401. The TPS74401EVM-118 evaluation module (and related user guide) can be requested at the Texas InstrumentswebsitethroughtheproductfoldersorpurchaseddirectlyfromtheTIeStore. 11.1.1.2 SpiceModels Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS74401 is available through the product folders under Tools& Software. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • 6ACurrent-SharingDualLDOreferencedesign • UsingNewThermalMetricsapplicationreport • ICPackageThermalMetrics applicationreport • TPS74401EVM-118EvaluationModuleUserGuide 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2005–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS74401

TPS74401 SBVS066R–DECEMBER2005–REVISEDAPRIL2017 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 30 SubmitDocumentationFeedback Copyright©2005–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS74401

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS74401KTWR ACTIVE DDPAK/ KTW 7 500 Green (RoHS Call TI | SN Level-3-245C-168 HR -40 to 125 TPS74401 TO-263 & no Sb/Br) TPS74401KTWRG3 ACTIVE DDPAK/ KTW 7 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 TPS74401 TO-263 & no Sb/Br) TPS74401RGRR ACTIVE VQFN RGR 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 12KA & no Sb/Br) TPS74401RGRT ACTIVE VQFN RGR 20 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 12KA & no Sb/Br) TPS74401RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74401 TPS74401RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74401 TPS74401RGWT ACTIVE VQFN RGW 20 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74401 TPS74401RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS & no Sb/Br) 74401 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS74401 : •Enhanced Product: TPS74401-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS74401KTWR DDPAK/ KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TO-263 TPS74401RGRR VQFN RGR 20 3000 330.0 12.4 3.8 3.8 1.1 8.0 12.0 Q1 TPS74401RGRT VQFN RGR 20 250 180.0 12.5 3.8 3.8 1.1 8.0 12.0 Q1 TPS74401RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TPS74401RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS74401KTWR DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 TPS74401RGRR VQFN RGR 20 3000 338.0 355.0 50.0 TPS74401RGRT VQFN RGR 20 250 338.0 355.0 50.0 TPS74401RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74401RGWT VQFN RGW 20 250 210.0 185.0 35.0 PackMaterials-Page2

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MECHANICAL DATA MPSF015 – AUGUST 2001 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.304 (7,72) 0.410 (10,41) –A– 0.385 (9,78) 0.006 0.296 (7,52) –B– 0.303 (7,70) 0.300 (7,62) 0.0625 (1,587) H 0.297 (7,54) 0.055 (1,40) 0.252 (6,40) 0.064 (1,63) 0.0585 (1,485) 0.045 (1,14) 0.056 (1,42) 0.370 (9,40) 0.187 (4,75) 0.330 (8,38) 0.179 (4,55) H A 0.605 (15,37) 0.595 (15,11) 0.012 (0,305) C 0.000 (0,00) 0.104 (2,64) 0.019 (0,48) 0.096 (2,44) H 0.017 (0,43) 0.050 (1,27) 0.026 (0,66) C 0.034 (0,86) 0.014 (0,36) 0°~3° C F 0.022 (0,57) 0.010 (0,25) M B AM C M 0.183 (4,65) 0.170 (4,32) 4201284/A 08/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead width and height dimensions apply to the plated lead. D. Leads are not allowed above the Datum B. E. Stand–off height is measured from lead tip with reference to Datum B. F. Lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum dimension by more than 0.003”. G. Cross–hatch indicates exposed metal surface. H. Falls within JEDEC MO–169 with the exception of the dimensions indicated. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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