TPS734xx www.ti.com........................................................................................................................................ SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009 250mA, Low Quiescent Current, Ultra-Low Noise, High PSRR Low-Dropout Linear Regulator FEATURES DESCRIPTION 1 • 250mALowDropoutRegulatorwithEN The TPS734xx family of low-dropout (LDO), 2 • LowI :44m A low-power linear regulators offers excellent ac Q • MultipleOutputVoltageVersionsAvailable: performance with very low ground current. High power-supply rejection ratio (PSRR), low noise, fast – FixedOutputsof1.0Vto4.3VUsing start-up, and excellent line and load transient InnovativeFactoryEEPROMProgramming response are provided while consuming a very low – AdjustableOutputsfrom1.25Vto6.2V 44m A (typical) ground current. The TPS734xx is • HighPSRR:60dBat1kHz stable with ceramic capacitors and uses an advanced BiCMOS fabrication process to yield a typical dropout • Ultra-lowNoise:28m V RMS voltage of 125mV at 250mA output. The TPS734xx • FastStart-UpTime:45m s uses a precision voltage reference and feedback loop • StablewithaLow-ESR,2.0m FTypicalOutput to achieve overall accuracy of 2% over all load, line, process, and temperature variations. It is fully Capacitance specified from T = –40°C to +125°C and is offered in • ExcellentLoad/LineTransientResponse low-profile ThinSJOT-23, 2mm × 2mm SON, and 3mm • 2%OverallAccuracy(Load/Line/Temp) x 3mm SON packages that are ideal for wireless • VeryLowDropout:125mVat250mA handsets,printers,andWLANcards. • ThinSOT-23,2mm×2mmSON-6,and3mmx 3mmSON-8Packages APPLICATIONS • WiFi,WiMax • Printers • CellularPhones,SmartPhones • HandheldOrganizers,PDAs TPS734xxDDC TPS73401DDC TPS734xxDRV TPS73401DRV TSOT23-5 TSOT23-5 2mm x 2mm SON-6 2mm x 2mm SON-6 (TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW) IN 1 5 OUT IN 1 5 OUT OUT 1 6 IN OUT 1 6 IN NR 2 GND 5 N/C FB 2 GND 5 N/C GND 2 GND 2 GND 3 4 EN GND 3 4 EN EN 3 4 NR EN 3 4 FB 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS734xx SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) PRODUCT V (2) OUT TPS734xxyyyz XXisnominaloutputvoltage(forexample,28=2.8V,285=2.85V,01=Adjustable). YYYispackagedesignator. Zispackagequantity. (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Outputvoltagesfrom1.0Vto3.6Vin50mVincrementsareavailablethroughtheuseofinnovativefactoryEEPROMprogramming; minimumorderquantitiesmayapply.Contactfactoryfordetailsandavailability. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingtemperaturerange(unlessotherwisenoted). PARAMETER TPS734xx UNIT V range –0.3to+7.0 V IN V range –0.3toV +0.3 V EN IN V range –0.3toV +0.3 V OUT IN V range –0.3toV (TYP)+0.3 V FB FB Peakoutputcurrent Internallylimited Continuoustotalpowerdissipation SeeDissipationRatingsTable Junctiontemperaturerange,T –55to+150 °C J Storagejunctiontemperaturerange,T –55to+150 °C STG ESDrating,HBM 2 kV ESDrating,CDM 500 V (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. DISSIPATION RATINGS DERATINGFACTOR BOARD PACKAGE Rq JC Rq JA ABOVETA=+25°C TA<+25°C TA=+70°C TA=+85°C Low-K(1) DDC 90°C/W 280°C/W 3.6mW/°C 360mW 200mW 145mW High-K(2) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW Low-K(1) DRV 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mW High-K(2) DRV 20°C/W 65°C/W 15.4mW/°C 1.54W 845mW 615mW (1) TheJEDEClow-K(1s)boardusedtoderivethisdatawasa3in×3in(7,62cm×7,62cm),two-layerboardwith2-ounce(56,699g) coppertracesontopoftheboard. (2) TheJEDEChigh-K(2s2p)boardusedtoderivethisdatawasa3in×3in(7,62cm×7,62cm),multilayerboardwith1-ounce(28,35g) internalpowerandgroundplanesand2-ounce(56,699g)coppertracesontopandbottomoftheboard 2 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated

TPS734xx www.ti.com........................................................................................................................................ SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009 ELECTRICAL CHARACTERISTICS Overoperatingtemperaturerange(T =–40°Cto+125°C),V =V +0.3Vor2.7V,whicheverisgreater;I =1mA, J IN OUT(TYP) OUT V =V ,C =2.2m F,C =0.01m F,unlessotherwisenoted.ForTPS73401,V =3.0V. EN IN OUT NR OUT TypicalvaluesareatT =+25°C. J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Inputvoltagerange(1) 2.7 6.5 V IN V Internalreference(TPS73401) 1.184 1.208 1.232 V FB V Outputvoltagerange(TPS73401) V 6.3 V OUT FB V Outputaccuracy Nominal T =+25°C –1.0 +1.0 % OUT J V Outputaccuracy(1) OverVIN, VOUT+0.3V≤VIN≤6.5V –2.0 ±1.0 +2.0 % OUT I ,Temp 1mA≤I ≤250mA OUT OUT ΔV %/ΔV Lineregulation(1) V +0.3V≤V ≤6.5V 0.02 %/V OUT IN OUT(NOM) IN ΔV %/ΔI Loadregulation 500m A≤I ≤250mA 0.005 %/mA OUT OUT OUT Dropoutvoltage(2) V I =250mA 125 219 mV DO (V =V –0.1V) OUT IN OUT(NOM) I Outputcurrentlimit V =0.9×V 300 580 900 mA CL OUT OUT(NOM) I Groundpincurrent 500m A≤I ≤250mA 45 65 m A GND OUT I Shutdowncurrent(I ) V ≤0.4V 0.15 1.0 m A SHDN GND EN I Feedbackpincurrent(TPS73401) –0.5 0.5 m A FB f=100Hz 60 dB Power-supplyrejectionratio f=1kHz 56 dB PSRR V =3.85V,V =2.85V, IN OUT C =0.01m F,I =100mA f=10kHz 41 dB NR OUT f=100kHz 28 dB Outputnoisevoltage CNR=0.01m F 11xVOUT m VRMS V N BW=10Hzto100kHz,VOUT=2.8V CNR=none 95xVOUT m VRMS C =none 45 m s NR Startuptime, T VOUT=0~90%, CNR=0.001m F 45 m s STR VROU=T1=4Ω2.,8C5V, =2.2m F CNR=0.01m F 50 m s L OUT C =0.047m F 50 m s NR V Enablehigh(enabled) 1.2 V V EN(HI) IN V Enablelow(shutdown) 0 0.4 V EN(LO) I Enablepincurrent,enabled V =V =6.5V 0.03 1.0 m A EN(HI) EN IN Shutdown,temperatureincreasing 165 °C T Thermalshutdowntemperature SD Reset,temperaturedecreasing 145 °C T Operatingjunctiontemperature –40 +125 °C J Undervoltagelock-out V rising 1.90 2.20 2.65 V IN UVLO Hysteresis V falling 70 mV IN (1) MinimumV =V +V or2.7V,whicheverisgreater. IN OUT DO (2) V isnotmeasuredfordeviceswithV <2.8VbecauseminimumV =2.7V. DO OUT(NOM) IN Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3

TPS734xx SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009........................................................................................................................................ www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAMS IN OUT IN OUT 400W 400W Current 2mA Current 3.3MW Limit Limit EN Thermal Overshoot EN Thermal Overshoot Shutdown Detect Shutdown Detect UVLO UVLO Quickstart 1.208V 1.208V Bandgap(1) NR Bandgap FB 500kW 500kW GND GND NOTE (1):Fixed voltage versions between 1.0V to 1.2V have a 1.0V bandgap circuit instead of a 1.208V bandgap circuit. Figure1.FixedVoltageVersions Figure2.AdjustableVoltageVersions PIN CONFIGURATIONS TPS734xxDDC TPS73401DDC TPS734xxDRV TPS73401DRV TSOT23-5 TSOT23-5 2mm x 2mm SON-6 2mm x 2mm SON-6 (TOP VIEW) (TOP VIEW) (TOP VIEW) (TOP VIEW) IN 1 5 OUT IN 1 5 OUT OUT 1 6 IN OUT 1 6 IN NR 2 GND 5 N/C FB 2 GND 5 N/C GND 2 GND 2 GND 3 4 EN GND 3 4 EN EN 3 4 NR EN 3 4 FB PINDESCRIPTIONS TPS734xx NAME DDC DRV DRB DESCRIPTION IN 1 6 8 Inputsupply. GND 2 3,Pad 4 Ground.ThepadmustbetiedtoGND. Drivingtheenablepin(EN)highturnsontheregulator.Drivingthispinlowputsthe EN 3 4 5 regulatorintoshutdownmode.ENcanbeconnectedtoINifnotused. Fixedvoltageversionsonly;connectinganexternalcapacitortothispinbypassesnoise NR 4 2 3 generatedbytheinternalbandgap.Thisallowsoutputnoisetobereducedtoverylow levels. Adjustableversiononly;thisistheinputtothecontrollooperroramplifier,andisusedtoset FB 4 2 3 theoutputvoltageofthedevice. Outputoftheregulator.Asmallcapacitor(totaltypicalcapacitance≥2.0m Fceramic)is OUT 5 1 1 neededfromthispintogroundtoassurestability. N/C — 5 2,6,7 Notinternallyconnected.Thispinmusteitherbeleftopen,ortiedtoGND. 4 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated

TPS734xx www.ti.com........................................................................................................................................ SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009 TYPICAL CHARACTERISTICS Overoperatingtemperaturerange(T =–40°Cto+125°C);V =V +0.3Vor2.7V,whicheverisgreater;I =1mA, J IN OUT(TYP) OUT V =V ,C =2.2m F,C =0.01m F,unlessotherwisenoted.ForTPS73401,V =3.0V.TypicalvaluesareatT = EN IN OUT NR OUT J +25°C. TPS73401LINEREGULATION TPS73425LINEREGULATION 0.5 0.5 IOUT= 100mA IOUT= 100mA 0.4 0.4 0.3 0.3 T =-40°C (%) 0.2 TJ= 0°C J (%) 0.2 TJ=-40°C TJ= 0°C UT 0.1 UT 0.1 O O V V n 0 n 0 ge i -0.1 ge i -0.1 Chan -0.2 T =T +J8=5 °+C25°C Chan -0.2 TJ= +85°CTJ= +25°C -0.3 J -0.3 -0.4 TJ= +125°C -0.4 TJ= +125°C -0.5 -0.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VIN(V) VIN(V) Figure3. Figure4. TPS73401LOADREGULATION TPS73425LOADREGULATION 2.86 2.55 Y-axis range is±2% of 2.8V Y-axis range is±2% of 2.5V 2.85 2.54 2.84 2.53 2.83 2.52 V) 22..8821 TJ=-40°C V) 2.51 TJ= 0°C T =-40°C ( ( J T 2.80 T 2.50 U U O O V 2.79 V 2.49 2.78 TJ= +85°C 2.48 222...777765 TJ= +125°C 22..4476 TJ= +125T°CJ= +25°TCJ= +85°C 2.74 2.45 0 50 100 150 200 250 0 50 100 150 200 250 Load (mA) Load (mA) Figure5. Figure6. TPS73425GROUNDPINCURRENTvs TPS73425GROUNDPINCURRENT(DISABLE) OUTPUTCURRENT vsTEMPERATURE 60 500 TJ= +25°C TJ= +125°C 450 VEN= 0.4V T = +85°C 50 J 400 350 40 A) T =-40°C a) 300 m J n ( 30 ( 250 IGND TJ= 0°C IGND 200 VIN= 3.3V 20 150 VIN= 5.0V V = 6.5V 100 IN 10 50 0 0 0 50 100 150 200 250 -40 -25 -10 5 20 35 50 65 80 95 110 125 IOUT(mA) TJ(°C) Figure7. Figure8. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5

TPS734xx SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Overoperatingtemperaturerange(T =–40°Cto+125°C);V =V +0.3Vor2.7V,whicheverisgreater;I =1mA, J IN OUT(TYP) OUT V =V ,C =2.2m F,C =0.01m F,unlessotherwisenoted.ForTPS73401,V =3.0V.TypicalvaluesareatT = EN IN OUT NR OUT J +25°C. TPS73401DROPOUTVOLTAGEvs POWER-SUPPLYRIPPLEREJECTIONvsFREQUENCY OUTPUTCURRENT (V –V =1.0V) IN OUT 400 90 350 80 I = 1mA OUT 70 300 I = 250mA (mV) 225000 TJ= +8T5J°C= +125°C R (dB) 6500 OUT 1IO0U0Tm=A VDO 150 TJ= +25°C PSR 40 30 100 20 T = 0°C 50 TJ=-J40°C 10 CCONRUT== 0 1.001mmFF IOUT= 200mA 0 0 0 50 100 150 200 250 10 100 1k 10k 100k 1M 10M I (mA) Frequency (Hz) OUT Figure9. Figure10. POWER-SUPPLYRIPPLEREJECTIONvsFREQUENCY POWER-SUPPLYRIPPLEREJECTIONvsFREQUENCY (V –V =0.5V) (V –V =0.3V) IN OUT IN OUT 90 90 80 80 IOUT= 1mA IOUT= 1mA 70 70 IOUT= 200mA IOUT= 200mA 60 60 B) IOUT= B) IOUT= R (d 50 100mA R (d 50 100mA R 40 R 40 S S P P 30 30 20 20 I = OUT 10 COUT= 2.2mF 10 COUT= 2.2mF 200mA C = 0.01mF I = 250mA C = 0.01mF NR OUT NR 0 0 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure11. Figure12. TPS73425 TPS73425 TOTALNOISEvsC TOTALNOISEvsC NR OUT 140 30 I = 1mA OUT 120 COUT= 2.2mF 25 )S 100 )S M M 20 R R V V m 80 m se ( se ( 15 Noi 60 Noi al al 10 Tot 40 Tot 20 5 I = 1mA OUT C = 0.01mF NR 0 0 0.01 0.1 1 10 0 5 10 15 20 25 CNR(nF) COUT(mF) Figure13. Figure14. 6 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated

TPS734xx www.ti.com........................................................................................................................................ SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009 TYPICAL CHARACTERISTICS (continued) Overoperatingtemperaturerange(T =–40°Cto+125°C);V =V +0.3Vor2.7V,whicheverisgreater;I =1mA, J IN OUT(TYP) OUT V =V ,C =2.2m F,C =0.01m F,unlessotherwisenoted.ForTPS73401,V =3.0V.TypicalvaluesareatT = EN IN OUT NR OUT J +25°C. TPS73425 TURN-ONRESPONSE TPS73425 (V =V ) ENABLERESPONSEOVERSTABLEV IN EN IN 3.5 3.5 3.0 VEN 3.0 VEN 2.5 COUT= 2.2mF VOUT 2.5 COUT= 2.2mF VOUT V) 2.0 V) 2.0 e ( e ( g 1.5 g 1.5 a a olt COUT= 10mF olt V 1.0 V 1.0 C = 10mF OUT 0.5 0.5 0 0 -0.5 -0.5 10ms/div 10ms/div Figure15. Figure16. TPS73410 TPS73410 POWER-UP/POWER-DOWN LOADTRANSIENTRESPONSE 7 6 IOUT= 250mA 100mV/div VIN= 2.7V COUT= 1.0mF VOUT V IN 5 COUT= 2.2mF 4 100mV/div VOUT s olt 3 V V OUT 2 250mA 1 0 100mA/div 1mA -1 IOUT 50ms/div 20ms/div Figure17. Figure18. TPS73410 LINETRANSIENTRESPONSE I =250mA OUT COUT= 2.2mF 20mV/div V OUT C =1.0mF OUT 20mV/div V OUT 3.7V dV IN = 1V/ms dt 2.7V 1V/div V IN 20ms/div Figure19. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7

TPS734xx SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009........................................................................................................................................ www.ti.com APPLICATION INFORMATION Input and Output Capacitor Requirements The TPS734xx family of LDO regulators combines the high performance required of many RF and Although an input capacitor is not required for precision analog applications with ultra-low current stability, it is good analog design practice to connect consumption. High PSRR is provided by a high gain, a 0.1m F to 1m F low equivalent series resistance high bandwidth error loop with good supply rejection (ESR) capacitor across the input supply near the at very low headroom (V – V ). Fixed voltage regulator. The ground of this capacitor should be IN OUT versions provide a noise reduction pin to bypass connected as close as the ground of output capacitor; noise generated by the bandgap reference and to a capacitor value of 0.1m F is enough in this condition. improve PSRR while a quick-start circuit fast-charges When it is difficult to place these two ground points this capacitor at startup. The combination of high close together, a 1m F capacitor is recommended. performance and low ground current also make the This capacitor counteracts reactive input sources and TPS734xx an excellent choice for portable improves transient response, noise rejection, and applications. All versions have thermal and ripple rejection. A higher-value capacitor may be over-current protection and are fully specified from necessary if large, fast rise-time load transients are –40°Cto+125°C. anticipated, or if the device is located several inches from the power source. If source impedance is not Figure 20 shows the basic circuit connections for sufficiently low, a 0.1m F input capacitor may be fixedvoltagemodels. Figure 21gives the connections necessarytoensurestability. for the adjustable output version (TPS73401). R and 1 R can be calculated for any output voltage using the The TPS734xx is designed to be stable with standard 2 formulainFigure21. ceramic output capacitors of values 2.2m F or larger. X5R and X7R type capacitors are best because they have minimal variation in value and ESR over Optional input capacitor. May improve source temperature. Maximum ESR of the output capacitor impedance, noise, or PSRR. should be < 1.0Ω, so output capacitor type should be eitherceramicorconductivepolymerelectrolytic. VIN IN OUT VOUT TPS734xx Feedback Capacitor Requirements 2.2mF EN GND NR Ceramic (TPS73401 only) The feedback capacitor, C , shown in Figure 21 is FB VEN Optional bypass capacitor required for stability. For a parallel combination of R1 to reduce output noise and R equal to 250kΩ, any value from 3pF to 1nF 2 and increase PSRR. can be used. Fixed voltage versions have an internal 30pF feedback capacitor that is quick-charged at Figure20.TypicalApplicationCircuitfor start-up. The adjustable version does not have this FIxedVoltageVersions quick-charge circuit, so values below 5pF should be used to ensure fast startup; values above 47pF can be used to implement an output voltage soft-start. imOpepMdtiaaoynn caimel ,ip nnrpoouviste ec s,a oopura rPcciSetoRr.R. VOUT=(R1R+2 R2) ´1.208 LTahregeTrPvSa7lu3e40c1apisacsittoarbslealisnouimnitpyr-ogvaeinncooisnefigsulirgahtitolyn. (OUTtiedtoFB)withoutC . FB VIN IN OUT VOUT TPS73401 R1 CFB Output Noise 2.2mF EN GND FB Ceramic In most LDOs, the bandgap is the dominant noise R2 source. If a noise reduction capacitor (CNR) is used with the TPS734xx, the bandgap does not contribute V EN significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier Figure21.TypicalApplicationCircuitfor input. To minimize noise in a given application, use a AdjustableVoltageVersions 0.01m F noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that space gives 2m A of divider current has the same noise space performance as a fixed voltage version. To further 8 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated

TPS734xx www.ti.com........................................................................................................................................ SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009 optimize noise, equivalent series resistance of the As with any linear regulator, PSRR and transient output capacitor can be set to approximately 0.2Ω. response are degraded as (V – V ) approaches IN OUT This configuration maximizes phase margin in the dropout. This effect is shown in the Typical control loop, reducing total output noise by up to Characteristicssection. 10%. Startup and Noise Reduction Capacitor Noise can be referred to the feedback point (FB pin) such that with C = 0.01m F, total noise is given Fixed voltage versions of the TPS734xx use a NR approximatelybyEquation1: quick-start circuit to fast-charge the noise reduction 11mV capacitor, C , if present (see the Functional Block V = R M S x V NR N V OUT Diagrams). This architecture allows the combination (1) of very low output noise and fast start-up times. The The TPS73401 adjustable version does not have the NR pin is high impedance so a low leakage C NR noise-reduction pin available, so ultra-low noise capacitor must be used; most ceramic capacitors are operation is not possible. Noise can be minimized appropriateinthisconfiguration. accordingtotheaboverecommendations. Note that for fastest startup, V should be applied IN first, then the enable pin (EN) driven high. If EN is Board Layout Recommendations to Improve tied to IN, startup is somewhat slower. Refer to the PSRR and Noise Performance Typical Characteristics section. The quick-start switch To improve ac performance such as PSRR, output is closed for approximately 135m s. To ensure that noise,andtransient response, it is recommended that C is fully charged during the quick-start time, a NR the board be designed with separate ground planes 0.01m Forsmallercapacitorshouldbeused. for V and V , with each ground plane connected IN OUT only at the GND pin of the device. In addition, the Transient Response ground connection for the bypass capacitor should As with any regulator, increasing the size of the connectdirectlytotheGNDpinofthedevice. output capacitor reduces over/undershoot magnitude but increases duration of the transient response. In Internal Current Limit the adjustable version, adding C between OUT and FB The TPS734xx internal current limit helps protect the FB improves stability and transient response. The regulator during fault conditions. During current limit, transient response of the TPS734xx is enhanced by the output sources a fixed amount of current that is an active pull-down that engages when the output largely independent of output voltage. For reliable overshoots by approximately 5% or more when the operation, the device should not be operated in device is enabled. When enabled, the pull-down currentlimitforextendedperiodsoftime. devicebehaveslikea400Ωresistortoground. The PMOS pass element in the TPS734xx has a Undervoltage Lock-Out (UVLO) built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This The TPS734xx utilizes an undervoltage lock-out current is not limited, so if extended reverse voltage circuit to keep the output shut off until internal operation is anticipated, external limiting may be circuitry is operating properly. The UVLO circuit has a appropriate. de-glitch feature so that it typically ignores undershoot transients on the input if they are less Shutdown than50m sduration. The enable pin (EN) is active high and is compatible Minimum Load with standard and low voltage TTL-CMOS levels. When shutdown capability is not required, EN can be The TPS734xx is stable and well-behaved with no connectedtoIN. output load. To meet the specified accuracy, a minimum load of 1mA is required. Below 1mA at Dropout Voltage junction temperatures near +125°C, the output can drift up enough to cause the output pull-down to turn The TPS734xx uses a PMOS pass transistor to on. The output pull-down limits voltage drift to 5% achieve low dropout. When (V – V ) is less than IN OUT typically but ground current could increase by the dropout voltage (VDO), the PMOS pass device is approximately 50m A. In typical applications, the in its linear region of operation and the input-to-output junction cannot reach high temperatures at light loads resistance is the R of the PMOS pass element. DS, ON because there is no appreciable dissipated power. Because the PMOS device behaves like a resistor in The specified ground current would then be valid at dropout, V approximately scales with output DO noloadconditionsinmostapplications. current. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9

TPS734xx SBVS089F–DECEMBER2007–REVISEDFEBRUARY2009........................................................................................................................................ www.ti.com Thermal Information Thermal Protection Power Dissipation Thermal protection disables the output when the The ability to remove heat from the die is different for junction temperature rises to approximately +165°C, each package type, presenting different allowing the device to cool. When the junction considerations in the PCB layout. The PCB area temperature cools to approximately +145°C the around the device that is free of other components outputcircuitryisagainenabled.Dependingonpower moves the heat from the device to the ambient air. dissipation, thermal resistance, and ambient Performance data for JEDEC low- and high-K boards temperature, the thermal protection circuit may cycle are given in the Dissipation Ratings table. Using on and off. This cycling limits the dissipation of the heavier copper increases the effectiveness in regulator, protecting it from damage as a result of removing heat from the device. The addition of plated overheating. through-holes to heat-dissipating layers also improvestheheatsinkeffectiveness. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an Power dissipation depends on input voltage and load inadequate heatsink. For reliable operation, junction conditions. Power dissipation is equal to the product temperature should be limited to +125°C maximum. of the output current time the voltage drop across the Toestimatethemargin of safety in a complete design outputpasselement,asshowninEquation2: (including heatsink), increase the ambient temperature until the thermal protection is triggered; PD(cid:2)(cid:4)VIN(cid:1)VOUT(cid:5)(cid:3)IOUT (2) use worst-case loads and signal conditions. For good Package Mounting reliability, thermal protection should trigger at least +35°C above the maximum expected ambient Solder pad footprint recommendations for the condition of your particular application. This TPS734xx are available from the Texas Instruments configuration produces a worst-case junction websiteatwww.ti.com. temperature of +125°C at the highest expected ambienttemperatureandworst-caseload. The internal protection circuitry of the TPS734xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS734xx into thermal shutdowndegradesdevicereliability. 10 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 4-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) TPS73401DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OCW & no Sb/Br) TPS73401DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OCW & no Sb/Br) TPS73401DRVR ACTIVE WSON DRV 6 3000 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBG & no Sb/Br) TPS73401DRVT ACTIVE WSON DRV 6 250 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBG & no Sb/Br) TPS73418DRVR ACTIVE WSON DRV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CBI & no Sb/Br) TPS73418DRVT ACTIVE WSON DRV 6 250 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CBI & no Sb/Br) TPS73430DRVR ACTIVE WSON DRV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CVW & no Sb/Br) TPS73430DRVT ACTIVE WSON DRV 6 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 CVW & no Sb/Br) TPS73433DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OEV & no Sb/Br) TPS73433DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OEV & no Sb/Br) TPS73433DRVR ACTIVE WSON DRV 6 3000 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CVX & no Sb/Br) TPS73433DRVT ACTIVE WSON DRV 6 250 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 CVX & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 4-Jul-2020 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS73401DDCR SOT- DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 23-THIN TPS73401DDCT SOT- DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 23-THIN TPS73401DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73401DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73418DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73418DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73430DRVR WSON DRV 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73430DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73430DRVT WSON DRV 6 250 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73430DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73433DDCR SOT- DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 23-THIN TPS73433DDCT SOT- DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 23-THIN TPS73433DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73433DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS73401DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TPS73401DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TPS73401DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73401DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73418DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73418DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73430DRVR WSON DRV 6 3000 205.0 200.0 33.0 TPS73430DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73430DRVT WSON DRV 6 250 205.0 200.0 33.0 TPS73430DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73433DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0 TPS73433DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0 TPS73433DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73433DRVT WSON DRV 6 250 203.0 203.0 35.0 PackMaterials-Page2

None

GENERIC PACKAGE VIEW DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4206925/F

PACKAGE OUTLINE DRV0006A WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD B 2.1 A 1.9 PIN 1 INDEX AREA 2.1 1.9 0.8 C 0.7 SEATING PLANE 0.08 C (0.2) TYP 1 0.1 0.05 EXPOSED 0.00 THERMAL PAD 3 4 2X 7 1.3 1.6 0.1 6 1 4X 0.65 0.35 6X PIN 1 ID 0.3 0.25 6X (OPTIONAL) 0.2 0.1 C A B 0.05 C 4222173/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) (1) 1 7 6X (0.3) 6 SYMM (1.6) (1.1) 4X (0.65) 4 3 (R0.05) TYP SYMM ( 0.2) VIA (1.95) TYP LAND PATTERN EXAMPLE SCALE:25X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS 4222173/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. www.ti.com

EXAMPLE STENCIL DESIGN DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM 6X (0.45) METAL 1 7 6X (0.3) 6 (0.45) SYMM 4X (0.65) (0.7) 4 3 (R0.05) TYP (1) (1.95) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X 4222173/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE DRV0006D WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD B 2.1 A 1.9 PIN 1 INDEX AREA 2.1 1.9 0.8 C 0.7 SEATING PLANE 0.08 C (0.2) TYP 1 0.1 0.05 EXPOSED 0.00 THERMAL PAD 3 4 2X 7 1.3 1.6 0.1 6 1 4X 0.65 0.35 6X PIN 1 ID 0.3 0.25 6X (OPTIONAL) 0.2 0.1 C A B 0.05 C 4225563/A 12/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRV0006D WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) (1) 1 7 6X (0.3) 6 SYMM (1.6) (1.1) 4X (0.65) 4 3 (R0.05) TYP SYMM ( 0.2) VIA (1.95) TYP LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK (PREFERRED) DEFINED SOLDER MASK DETAILS 4225563/A 12/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. www.ti.com

EXAMPLE STENCIL DESIGN DRV0006D WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM 6X (0.45) METAL 1 7 6X (0.3) 6 (0.45) SYMM 4X (0.65) (0.7) 4 3 (R0.05) TYP (1) (1.95) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X 4225563/A 12/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated