TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 CAP-FREE NMOS 250-mA LOW DROPOUT REGULATOR WITH REVERSE CURRENT PROTECTION FEATURES APPLICATIONS • ControlledBaseline • Portable/Battery-PoweredEquipment – OneAssembly/TestSite,OneFabrication • Post-RegulationforSwitchingSupplies Site • Noise-SensitiveCircuitrysuchasVCOs • ExtendedTemperaturePerformanceof • PointofLoadRegulationforDSPs,FPGAs, –55(cid:176) Cto125(cid:176) C ASICs,andMicroprocessors • EnhancedDiminishingManufacturing Sources(DMS)Support Optional Optional • EnhancedProduct-ChangeNotification VIN IN OUT VOUT • QualificationPedigree (1) TPS732xx • StablewithNoOutputCapacitororAnyValue EN GND NR orTypeofCapacitor • InputVoltageRange:1.7Vto5.5V • UltralowDropoutVoltage: Optional 40mVTypat250mA Typical Application Circuit for Fixed-Voltage Versions • ExcellentLoadTransientResponse—withor withoutOptionalOutputCapacitor DESCRIPTION • NewNMOSTopologyProvidesLowReverse The TPS732xx family of low-dropout (LDO) voltage LeakageCurrent regulators uses a new topology: an NMOS pass • LowNoise:30m V Typ(10kHzto100kHz) element in a voltage-follower configuration. This RMS • 0.5%InitialAccuracy topology is stable using output capacitors with low ESR and even allows operation without a capacitor. • 1%OverallAccuracy(Line,Load,and It also provides high reverse blockage (low reverse Temperature) current) and ground pin current that is nearly • LessThan1m AMaxI inShutdownMode constantoverallvaluesofoutputcurrent. Q • ThermalShutdownandSpecifiedMin/Max The TPS732xx uses an advanced BiCMOS process CurrentLimitProtection to yield high precision while delivering low dropout • AvailableinMultipleOutputVoltageVersions voltages and low ground pin current. Current consumption, when not enabled, is under 1 m A and – FixedOutputsof1.2Vto5V ideal for portable applications. The low output noise – AdjustableOutputsfrom1.2Vto5.5V (30 m V with 0.1 m F C ) is ideal for powering RMS NR – CustomOutputsAvailable VCOs. These devices are protected by thermal shutdownandfoldbackcurrentlimit. DCQ PACKAGE SOT223 DBV PACKAGE (TOP VIEW) SOT23 DRBPACKAGE (TOP VIEW) TAB IS GND 3m(mTOxP3mVImEWS)ON (1) ComponentqualificationinaccordancewithJEDECand OUT 1 8 IN industrystandardstoensurereliableoperationoveran IN 1 5 OUT N/C 2 7 N/C GND 2 1 2 3 4 5 NR/FB 3 6 N/C extendedtemperaturerange.Thisincludes,butisnotlimited EN 3 4 NR/FB GND 4 5 EN to,HighlyAcceleratedStressTest(HAST)orbiased85/85, temperaturecycle,autoclaveorunbiasedHAST, IN GND EN OUT NR/FB electromigration,bondintermetalliclife,andmoldcompound life.Suchqualificationtestingshouldnotbeviewedas justifyinguseofthiscomponentbeyondspecified performanceandenvironmentallimits. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERINGINFORMATION(1) PRODUCT V (2) OUT XXisthenominaloutputvoltage(forexample,25=2.5V,01=Adjustable(3)). TPS732xxyyyz YYYisthepackagedesignator. Zisthepackagequantity. (1) Forthemostcurrentspecificationandpackageinformation,seethePackageOptionAddendumlocatedattheendofthisdatasheetor seetheTIwebsiteatwww.ti.com. (2) Outputvoltagesfrom1.2Vto4.5Vin50-mVincrementsareavailablethroughtheuseofinnovativefactoryEEPROMprogramming; minimumorderquantitiesmayapply.Contactfactoryfordetailsandavailability. (3) Forfixed1.2Voperation,tieFBtoOUT. ABSOLUTE MAXIMUM RATINGS overoperatingjunctiontemperaturerangeunlessotherwisenoted(1) V range –0.3Vto6V IN V range –0.3Vto6V EN V range –0.3Vto5.5V OUT Peakoutputcurrent Internallylimited Outputshort-circuitduration Indefinite Continuoustotalpowerdissipation SeeDissipationRatingsTable Ambienttemperaturerange,T –55(cid:176) Cto150(cid:176) C A Storagetemperaturerange –65(cid:176) Cto150(cid:176) C ESDrating,HBM 2kV ESDrating,CDM 500V (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedundertheElectricalCharacteristics isnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability. POWER DISSIPATION RATINGS(1) T £ 25(cid:176) C T =70(cid:176) C T =85(cid:176) C T =125(cid:176) C DERATINGFACTOR A A A A BOARD PACKAGE RQ JC RQ JA ABOVET =25(cid:176) C POWER POWER POWER POWER A RATING RATING RATING RATING Low-K(2) DBV 64(cid:176) C/W 255(cid:176) C/W 3.9mW/(cid:176) C 450mW 275mW 215mW 58mW High-K(3) DBV 64(cid:176) /W 180(cid:176) C/W 5.6mW/(cid:176) C 638mW 388mW 305mW 83mW (1) SeePowerDissipationintheApplicationssectionformoreinformationrelatedtothermaldesign. (2) TheJEDECLow-K(1s)boarddesignusedtoderivethisdatawasa3inch· 3inch,two-layerboardwith2-ouncecoppertracesontop oftheboard. (3) TheJEDECHigh-K(2s2p)boarddesignusedtoderivethisdatawasa3inch· 3inch,multilayerboardwith1-ounceinternalpowerand groundplanesand2-ouncecoppertracesonthetopandbottomoftheboard. 2 SubmitDocumentationFeedback

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 ELECTRICAL CHARACTERISTICS Overoperatingtemperaturerange(T =–55(cid:176) Cto+125(cid:176) C),V =V +0.5V(1),I =10mA,V =1.7V,and A IN OUT(nom) OUT EN C =0.1m F,unlessotherwisenoted.TypicalvaluesareatT =25(cid:176) C OUT A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Inputvoltagerange(1) 1.7 5.5 V IN V Internalreference(TPS73201) T =25(cid:176) C 1.198 1.2 1.21 V FB A Outputvoltagerange(TPS73201)(2) V 5.5–V V FB DO Nominal T =25(cid:176) C – 0.5% V A OUT Accuracy(1) VIN,IOUT,andT V10OUmTA+£0.I5V££ V2I5N0£m5A.5V; –1% – 0.5% +1% OUT D V %/D V Lineregulation(1) V +0.5V£ V £ 5.5V 0.01 %/V OUT IN OUT(nom) IN 1mA£ I £ 250mA 0.002 D V %/D I Loadregulation OUT %/mA OUT OUT 10mA£ I £ 250mA 0.0005 OUT Dropoutvoltage(3) V I =250mA 40 150 mV DO (V =V (nom)–0.1V) OUT IN OUT Z (DO) Outputimpedanceindropout 1.7V£ V £ V +V 0.25 W O IN OUT DO I Outputcurrentlimit V =0.9· V 250 425 600 mA CL OUT OUT(nom) I Short-circuitcurrent V =0V 300 mA SC OUT I Reverseleakagecurrent(4)(–I ) V £ 0.5V,0V£ V £ V 0.1 15 m A REV IN EN IN OUT I =10mA(I ) 400 550 I Groundpincurrent OUT Q m A GND I =250mA 650 950 OUT I Shutdowncurrent(I ) V £ 0.5V,V £ V £ 5.5 0.02 1 m A SHDN GND EN OUT IN I FBpincurrent(TPS73201) .1 .45 m A FB Power-supplyrejectionratio f=100Hz,IOUT=250mA 58 PSRR dB (ripplerejection) f=10kHz,I =250mA 37 OUT V Outputnoisevoltage COUT=10m F,NoCNR 27· VOUT m V N BW=10Hzto100kHz C =10m F,C =0.01m F 8.5· V RMS OUT NR OUT tSTR Startuptime VCOUT==31Vm F,,RCL=3=00W.01m F 600 m s OUT NR V (HI) Enablehigh(enabled) 1.7 V V EN IN V (LO) Enablelow(shutdown) 0 0.5 V EN I (HI) Enablepincurrent(enabled) V =5.5V 0.02 0.1 m A EN EN Shutdown,Temperatureincreasing 160 T Thermalshutdowntemperature (cid:176) C SD Reset,Temperaturedecreasing 140 T Operatingambienttemperature –55 125 (cid:176) C A (1) MinimumV =V +V or1.7V,whicheverisgreater. IN OUT DO (2) TPS73201istestedatV =2.5V. OUT (3) V isnotmeasuredfortheTPS73214,TPS73215,orTPS73216,sinceminimumV =1.7V. DO IN (4) Fixed-voltageversionsonly;seetheApplicationssectionformoreinformation. SubmitDocumentationFeedback 3

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 6 5 4 e Lif d e mat 3 sti E s ar e Y 2 1 0 100 110 120 130 140 150 160 ContinuousT (°C) j A. T =q · W+T (atstandardJESD51conditions) j JA A Figure1.EstimatedDeviceLifeatElevatedTemperaturesElectromigrationFailMode 4 SubmitDocumentationFeedback

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 FUNCTIONALBLOCKDIAGRAMS IN Charge Pump EN Thermal Protection Ref Servo 27kW Bandgap Error Amp Current Limit OUT 8kW GND R 1 R1+R2=80kW R2 NR Figure2.FixedVoltageVersion IN Table 1. Standard 1% Resistor Values for Common Output Voltages VOUT R1 R2 Charge 1.2V Short Open Pump 1.5V 23.2kW 95.3kW EN Thermal 1.8V 28.0kW 56.2kW Protection 2.5V 39.2kW 36.5kW Ref Servo 2.8V 44.2kW 33.2kW 27kW 3.0V 46.4kW 30.9kW Bandgap Error 3.3V 52.3kW 30.1kW Amp 5.0V 78.7kW 24.9kW OUT Current Limit NOTE: VOUT = (R1 + R2)/R2 × 1.204; GND 8kW 80kW R1R2 @ 19kW for best R accuracy. 1 FB R 2 Figure3.AdjustableVoltageVersion SubmitDocumentationFeedback 5

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 PIN ASSIGNMENTS DBV PACKAGE DCQ PACKAGE DRBPACKAGE SOT23 SOT223 3mmx3mmSON (TOP VIEW) (TOP VIEW) (TOPVIEW) OUT 1 8 IN IN 1 5 OUT TAB IS GND N/C 2 7 N/C NR/FB 3 6 N/C GND 2 GND 4 5 EN EN 3 4 NR/FB 1 2 3 4 5 IN GND EN OUT NR/FB TERMINALFUNCTIONS TERMINAL SOT23 SOT223 3· 3SON DESCRIPTION NAME (DBV) (DCQ) (DRB) PINNO. PINNO. PINNO. IN 1 1 8 Unregulatedinputsupply GND 2 3 4,Pad Ground Drivingtheenablepin(EN)highturnsontheregulator.Drivingthispinlowputs EN 3 5 5 theregulatorintoshutdownmode.SeetheShutdownsectionunderApplications Informationformoredetails.ENcanbeconnectedtoINifnotused. Fixedvoltageversionsonly—connectinganexternalcapacitortothispinbypasses NR 4 4 3 noisegeneratedbytheinternalbandgap,reducingoutputnoisetoverylowlevels. Adjustablevoltageversiononly—thisistheinputtothecontrollooperroramplifier, FB 4 4 3 andisusedtosettheoutputvoltageofthedevice. OUT 5 2 1 OutputoftheRegulator.Therearenooutputcapacitorrequirementsforstability. 6 SubmitDocumentationFeedback

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 TYPICAL CHARACTERISTICS ForallvoltageversionsatT =25(cid:176) C,V =V +0.5V,I =10mA,V =1.7V,andC =0.1m F,unlessotherwise J IN OUT(nom) OUT EN OUT noted. LOADREGULATION LINEREGULATION 0.5 0.20 0.4 ReferredtoIOUT=10mA ReferredtoVIN=VOUT+0.5VatIOUT=10mA 0.15 0.3 - 40(cid:1)C +25(cid:1)C 0.10 (%)UT 00..21 +125(cid:1)C (%)UT 0.05 +125(cid:1)C +25(cid:1)C O O V V n 0 n 0 i i nge - 0.1 nge - 0.05 ha - 0.2 ha - 40(cid:1)C C C - 0.10 - 0.3 - 0.4 - 0.15 - 0.5 - 0.20 0 50 100 150 200 250 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IOUT(mA) VIN- VOUT(V) Figure4. Figure5. DROPOUTVOLTAGEvsOUTPUTCURRENT DROPOUTVOLTAGEvsTEMPERATURE 100 100 TPS73225DBV TPS73225DBV I =250mA OUT 80 80 +125(cid:1)C V) 60 V) 60 m m ( ( VDO 40 +25(cid:1)C VDO 40 20 20 - 40(cid:1)C 0 0 0 50 100 150 200 250 - 50 - 25 0 25 50 75 100 125 IOUT(mA) Temperature((cid:1)C) Figure6. Figure7. OUTPUTVOLTAGEACCURACYHISTOGRAM OUTPUTVOLTAGEDRIFTHISTOGRAM 30 18 I =10mA I =10mA OUT OUT 16 AllVoltageVersions 25 14 %) %) ( 20 ( 12 s s nit nit 10 U U of 15 of 8 nt nt e e c 10 c 6 er er P P 4 5 2 0 0 098765432101234567890 000000000000000000000 1.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.1. 10987654321 12345678910 --------V--Error(%) -----W-o-rst-Ca-se-dV /dT(ppm/(cid:1)C) OUT OUT Figure8. Figure9. SubmitDocumentationFeedback 7

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 TYPICAL CHARACTERISTICS (continued) ForallvoltageversionsatT =25(cid:176) C,V =V +0.5V,I =10mA,V =1.7V,andC =0.1m F,unlessotherwise J IN OUT(nom) OUT EN OUT noted. GROUNDPINCURRENTvsOUTPUTCURRENT GROUNDPINCURRENTvsTEMPERATURE 1000 800 I =250mA 900 700 OUT 800 600 700 500 A) 600 A) m( 500 m( 400 D D N N G400 G I I 300 300 V =5.5V 200 VIN=5.5V 200 VIINN=4V VIN=4V 100 VIN=2V 100 V =2V IN 0 0 0 50 100 150 200 250 - 50 - 25 0 25 50 75 100 125 IOUT(mA) Temperature((cid:1)C) Figure10. Figure11. CURRENTLIMITvsV GROUNDPINCURRENTinSHUTDOWN OUT (FOLDBACK) vsTEMPERATURE 500 1 450 VENABLE=0.5V I V =V +0.5V 400 CL IN OUT A) 350 m mit( 300 ISC A) Li 250 m(D0.1 Current 210500 IGN 100 50 TPS73233 0 0.01 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 - 50 - 25 0 25 50 75 100 125 V (V) Temperature((cid:1)C) OUT Figure12. Figure13. CURRENTLIMITvsV CURRENTLIMITvsTEMPERATURE IN 600 600 550 550 A) 500 A) 500 m m mit( 450 mit( 450 Li Li nt 400 nt 400 e e urr urr C 350 C 350 300 300 250 250 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - 50 - 25 0 25 50 75 100 125 V (V) Temperature((cid:1)C) IN Figure14. Figure15. 8 SubmitDocumentationFeedback

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 TYPICAL CHARACTERISTICS (continued) ForallvoltageversionsatT =25(cid:176) C,V =V +0.5V,I =10mA,V =1.7V,andC =0.1m F,unlessotherwise J IN OUT(nom) OUT EN OUT noted. PSRR(RIPPLEREJECTION)vsFREQUENCY PSRR(RIPPLEREJECTION)vsV –V IN OUT 90 40 I =100mA I =1mA 80 COOUUTT=Any COOUUTT=1m F 35 70 B) IOUT=1mA 30 Rejection(d 654000 ICOOUUTT==1AmnAy COUT=10m F IOC=O10=01mm AF SRR(dB) 2250 e P 15 pl 30 p Ri 20 IOUT=100mA 10 Frequency = 100kHz 10 IOUT=Any COUT=10m F 5 COUT = 10m F 0 VIN=VOUT+1V COUT=0m F 0 CNR = 0.01m F 10 100 1k 10k 100k 1M 10M 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Frequency(Hz) VIN- VOUT(V) Figure16. Figure17. NOISESPECTRALDENSITY NOISESPECTRALDENSITY C =0m F C =0.01m F NR NR 1 1 C =1m F OUT √Hz) COUT=0m F √Hz) COUT=1m F V/ 0.1 V/ 0.1 C =10m F m( OUT m( N N e e C =0m F OUT C =10m F OUT IOUT=150mA IOUT=150mA 0.01 0.01 10 100 1k 10k 100k 10 100 1k 10k 100k Frequency(Hz) Frequency(Hz) Figure18. Figure19. RMSNOISEVOLTAGEvsC RMSNOISEVOLTAGEvsC OUT NR 60 140 V =5.0V OUT 50 120 V =5.0V OUT 100 40 MS) MS) 80 VOUT=3.3V (RN 30 VOUT=3.3V (RN 60 V V 20 40 V =1.5V V =1.5V OUT OUT 10 CNR=0.01m F 20 COUT=0m F 10Hz<Frequency<100kHz 10Hz<Frequency<100kHz 0 0 0.1 1 10 1p 10p 100p 1n 10n C (m F) C (F) OUT NR Figure20. Figure21. SubmitDocumentationFeedback 9

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 TYPICAL CHARACTERISTICS (continued) ForallvoltageversionsatT =25(cid:176) C,V =V +0.5V,I =10mA,V =1.7V,andC =0.1m F,unlessotherwise J IN OUT(nom) OUT EN OUT noted. TPS73233 TPS73233 LOADTRANSIENTRESPONSE LINETRANSIENTRESPONSE VIN=3.8V COUT=0m F IOUT=250mA 50mV/tick V OUT C =0m F OUT 50mV/div V C =1m F OUT OUT 50mV/tick V OUT 50mV/tick COUT=10m F VOUT 50mV/div COUT=100m F VOUT dV 250mA 5.5V IN=0.5V/m s dt 50mA/tick 4.5V 10mA I 1V/div VIN OUT 10m s/div 10m s/div Figure22. Figure23. TPS73233 TPS73233 TURN-ONRESPONSE TURN-OFFRESPONSE RCLOU=T1=kW0m F VOUT RCLOU=T2=0W10m F 1V/div RCLOU=T2=0W1m F 1V/div RCLOU=T2=0W1m F R =1kW RCL=2=0W10m F CLOUT=0m F OUT V OUT 2V 2V V EN 1V/div 1V/div 0V 0V V EN 100m s/div 100m s/div Figure24. Figure25. TPS73233 POWERUP/POWERDOWN I vsTEMPERATURE ENABLE 6 10 5 V IN 4 V OUT 1 3 A) n s ( Volt 2 BLE A 1 EN I 0.1 0 - 1 - 2 0.01 50ms/div - 50 - 25 0 25 50 75 100 125 Temperature (°C) Figure26. Figure27. 10 SubmitDocumentationFeedback

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 TYPICAL CHARACTERISTICS (continued) ForallvoltageversionsatT =25(cid:176) C,V =V +0.5V,I =10mA,V =1.7V,andC =0.1m F,unlessotherwise J IN OUT(nom) OUT EN OUT noted. TPS73201 TPS73201 RMSNOISEVOLTAGEvsC I vsTEMPERATURE ADJ FB 60 160 55 140 50 120 45 100 V(rms)N 4305 I(nA)FB 8600 V =2.5V 30 COUT=0m F 40 OUT 25 R1=39.2kW 20 10Hz<Frequency<100kHz 20 0 10p 100p 1n 10n - 50 - 25 0 25 50 75 100 125 CFB(F) Temperature((cid:1)C) Figure28. Figure29. TPS73201 TPS73201 LOADTRANSIENT,ADJUSTABLEVERSION LINETRANSIENT,ADJUSTABLEVERSION C =10nF V =2.5V FB OUT R =39.2kW C =10nF 100mV/div 1 COUT=0m F VOUT 100mV/div COUT=0m F FB VOUT C =10m F C =10m F OUT OUT 100mV/div VOUT 100mV/div VOUT 4.5V 250mA 3.5V V IN 10mA I OUT 10m s/div 5m s/div Figure30. Figure31. SubmitDocumentationFeedback 11

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 APPLICATION INFORMATION The TPS732xx belongs to a family of new generation INPUT AND OUTPUT CAPACITOR LDO regulators that use an NMOS pass transistor to REQUIREMENTS achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor Although an input capacitor is not required for constraints. These features, combined with low noise stability, it is good analog design practice to connect and an enable input, make the TPS732xx ideal for a 0.1 m F to 1 m F low ESR capacitor across the input portable applications. This regulator family offers a supply near the regulator. This counteracts reactive wide selection of fixed output voltage versions and input sources and improves transient response, an adjustable output version. All versions have noise rejection, and ripple rejection. A higher-value thermal and over-current protection, including capacitor may be necessary if large, fast rise-time foldbackcurrentlimit. load transients are anticipated or the device is locatedseveralinchesfromthepowersource. Figure 32 shows the basic circuit connections for the fixed voltage models. Figure 33 gives the The TPS732xx does not require an output capacitor connections for the adjustable output version for stability and has maximum phase margin with no (TPS73201). capacitor. It is designed to be stable for all available types and values of capacitors. In applications where Optionalinputcapacitor. Optionaloutputcapacitor. V – V < 0.5 V and multiple low ESR capacitors IN OUT Mayimprovesource Mayimproveloadtransient, areinparallel,ringingmayoccurwhen the product of impedance,noise,orPSRR. noise,orPSRR. C and total ESR drops below 50 nW F. Total ESR OUT VIN IN OUT VOUT includes all parasitic resistances, including capacitor TPS732xx ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and EN GND NR traceresistancewillmeetthisrequirement. OUTPUT NOISE Optionalbypass capacitortoreduce A precision band-gap reference is used to generate outputnoise. theinternal reference voltage, V . This reference is REF Figure32.TypicalApplicationCircuitfor the dominant noise source within the TPS732xx and Fixed-VoltageVersions it generates approximately 32 m VRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the samegainasthereferencevoltage,sothat the noise Optionalinputcapacitor. Optionaloutputcapacitor. voltageoftheregulatorisapproximatelygivenby: Mayimprovesource Mayimproveloadtransient, impedance,noise,orPSRR. noise,orPSRR. V (cid:3)32(cid:1)V (cid:1)(R1(cid:2)R2)(cid:3)32(cid:1)V (cid:1)VOUT N RMS R RMS V VIN IN OUT VOUT 2 REF (1) TPS732xx R C Since the value of V is 1.2V, this relationship 1 FB REF reducesto: EN GND FB (cid:3) (cid:4) (cid:1)V R2 V ((cid:1)V )(cid:2)27 RMS (cid:1)V (V) N RMS V OUT (R +R) Optionalcapacitor (2) VOUT= 1R1 2 ×1.204 reduacnedsiomuptrpouvtensoise forthecaseofnoCNR. transientresponse. An internal 27 kW resistor in series with the noise reduction pin (NR) forms a low-pass filter for the Figure33.TypicalApplicationCircuitfor voltage reference when an external noise reduction Adjustable-VoltageVersions capacitor, C , is connected from NR to ground. For NR C = 10 nF, the total noise in the 10 Hz to 100 kHz NR R and R can be calculated for any output voltage 1 2 bandwidth is reduced by a factor of ~3.2, giving the using the formula shown in Figure 33. Sample approximaterelationship: resistor values for common output voltages are (cid:3) (cid:4) shown in Figure 3. For the best accuracy, make the V ((cid:1)V )(cid:2)8.5 (cid:1)VRMS (cid:1)V (V) parallel combination of R and R approximately 19 N RMS V OUT 1 2 (3) kW . forC =10nF. NR 12 SubmitDocumentationFeedback

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 This noise reduction effect is shown as RMS Noise For large step changes in load current, the VoltagevsC intheTypicalCharacteristicssection. TPS732xx requires a larger voltage drop from V to NR IN V to avoid degraded transient response. The The TPS73201 adjustable version does not have the OUT boundary of this transient dropout region is noise-reduction pin available. However, connecting a approximately twice the dc dropout. Values of V feedback capacitor, C , from the output to the FB IN FB – V above this line insure normal transient pin reduces output noise and improve load transient OUT response. performance. Operating in the transient dropout region can cause The TPS732xx uses an internal charge pump to an increase in recovery time. The time required to develop an internal supply voltage sufficient to drive recover from a load transient is a function of the the gate of the NMOS pass element above V . OUT magnitude of the change in load current rate, the The charge pump generates ~250 m V of switching rate of change in load current, and the available noise at ~2 MHz; however, charge-pump noise headroom (V to V voltage drop). Under contributionisnegligibleat the output of the regulator IN OUT worst-case conditions [full-scale instantaneous load formostvaluesofI andC . OUT OUT change with (V – V ) close to dc dropout levels], IN OUT the TPS732xx can take a couple of hundred BOARD LAYOUT RECOMMENDATION TO microseconds to return to the specified regulation IMPROVE PSRR AND NOISE accuracy. PERFORMANCE To improve ac performance such as PSRR, output TRANSIENT RESPONSE noise, and transient response, it is recommended Thelowopen-loopoutputimpedanceprovidedby the that the PCB be designed with separate ground NMOS pass element in a voltage follower planes for V and V , with each ground plane IN OUT configuration allows operation without an output connected only at the GND pin of the device. In capacitor for many applications. As with any addition, the ground connection for the bypass regulator, the addition of a capacitor (nominal value capacitor should connect directly to the GND pin of 1 m F) from the output pin to ground reduces thedevice. undershoot magnitude but increase duration. In the adjustable version, the addition of a capacitor, C , INTERNAL CURRENT LIMIT FB from the output to the adjust pin also improves the The TPS732xx internal current limit helps protect the transientresponse. regulator during fault conditions. Foldback helps to The TPS732xx does not have active pulldown when protect the regulator from damage during output the output is overvoltage. This allows applications short-circuit conditions by reducing current limit when that connect higher voltage sources, such as V dropsbelow 0.5 V. See Figure 12in the Typical OUT alternate power supplies, to the output. This also CharacteristicssectionforagraphofI vsV . OUT OUT results in an output overshoot of several percent if the load current quickly drops to zero when a SHUTDOWN capacitor is connected to the output. The duration of The Enable pin is active high and is compatible with overshoot can be reduced by adding a load resistor. standard TTL-CMOS levels. V below 0.5 V (max) The overshoot decays at a rate determined by output EN turns the regulator off and drops the ground pin capacitor COUT and the internal/external load current to approximately 10 nA. When shutdown resistance.Therateofdecayisgivenby: capability is not required, the Enable pin can be (Fixedvoltageversion) connected to V . When a pullup resistor is used, IN V and operation down to 1.8 V is required, use pullup dV(cid:4)dt(cid:2) OUT resistorvaluesbelow50kW . COUT(cid:1)80k(cid:1)(cid:3)RLOAD (4) DROPOUT VOLTAGE The TPS732xx uses an NMOS pass transistor to achieveextremelylowdropout.When(V – V ) is IN OUT less than the dropout voltage (V ), the NMOS pass DO device is in its linear region of operation and the input-to-output resistance is the R of the NMOS DS-ON passelement. SubmitDocumentationFeedback 13

TPS73201-EP,, TPS73215-EP TPS73216-EP, TPS73218-EP, TPS73225-EP TPS73230-EP, TPS73233-EP, TPS73250-EP www.ti.com SGLS346–JUNE2006 (Adjustablevoltageversion) 35(cid:176) C above the maximum expected ambient V condition of your application. This produces a dV(cid:5)dt(cid:3)C (cid:1)80k(cid:1)(cid:4)(ORUT(cid:2)R )(cid:4)R worst-case junction temperature of 125(cid:176) C at the OUT 1 2 LOAD (5) highest expected ambient temperature and worst-caseload. REVERSE CURRENT The internal protection circuitry of the TPS732xx has The NMOS pass element of the TPS732xx provides been designed to protect against overload inherent protection against current flow from the conditions. It was not intended to replace proper output of the regulator to the input when the gate of heatsinking. Continuously running the TPS732xx into the pass device is pulled low. To ensure that all thermalshutdownwilldegradedevicereliability. charge is removed from the gate of the pass element, the enable pin must be driven low before POWER DISSIPATION the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on The ability to remove heat from the die is different for thegate. each package type, presenting different considerations in the PCB layout. The PCB area After the enable pin is driven low, no bias voltage is around the device that is free of other components needed on any pin for reverse current blocking. Note moves the heat from the device to the ambient air. that reverse current is specified as the current Performance data for JEDEC low-K and high-K flowing out of the IN pin due to voltage applied on boards are shown in the Power Dissipation Ratings the OUT pin. There will be additional current flowing table. Using heavier copper increases the into the OUT pin due to the 80-kW internal resistor effectiveness in removing heat from the device. The dividertoground(seeFigure2andFigure3). addition of plated through-holes to heat-dissipating For the TPS73201, reverse current may flow when layersalsoimprovestheheat-sinkeffectiveness. V ismorethan1VaboveV . FB IN Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product THERMAL PROTECTION of the output current times the voltage drop across theoutputpasselement(V toV ): Thermal protection disables the output when the IN OUT junction temperature rises to approximately 160(cid:176) C, PD(cid:3)(VIN(cid:2)VOUT)(cid:1)IOUT (6) allowing the device to cool. When the junction temperature cools to approximately 140(cid:176) C, the Power dissipation can be minimized by using the output circuitry is again enabled. Depending on lowest possible input voltage necessary to assure power dissipation, thermal resistance, and ambient therequiredoutputvoltage. temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, Package Mounting protectingitfromdamageduetooverheating. Solder pad footprint recommendations for the Any tendency to activate the thermal protection TPS732xx are presented in Application Bulletin circuit indicates excessive power dissipation or an Solder Pad Recommendations for Surface-Mount inadequate heatsink. For reliable operation, junction Devices (AB-132), available from the Texas temperature should be limited to 125(cid:176) C maximum. Instrumentswebsiteatwww.ti.com. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; useworst-caseloadsandsignalconditions. For good reliability, thermal protection should trigger at least 14 SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS73201MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKJM & no Sb/Br) TPS73215MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKKM & no Sb/Br) TPS73216MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKLM & no Sb/Br) TPS73218MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKMM & no Sb/Br) TPS73225MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKNM & no Sb/Br) TPS73230MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKOM & no Sb/Br) TPS73233MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKPM & no Sb/Br) TPS73250MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKQM & no Sb/Br) V62/06644-01XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKJM & no Sb/Br) V62/06644-02XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKKM & no Sb/Br) V62/06644-03XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKLM & no Sb/Br) V62/06644-04XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKMM & no Sb/Br) V62/06644-05XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKNM & no Sb/Br) V62/06644-06XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKOM & no Sb/Br) V62/06644-07XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKPM & no Sb/Br) V62/06644-08XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 PKQM & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS73201MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73215MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73216MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73218MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73225MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73230MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73233MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73250MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS73201MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73215MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73216MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73218MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73225MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73230MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73233MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS73250MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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