TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 (cid:0) Available in 5-V, 4.85-V, and 3.3-V D OR P PACKAGE Fixed-Output and Adjustable Versions (TOP VIEW) (cid:0) Very Low-Dropout Voltage...Maximum of GND 1 8 PG 32 mV at I = 100 mA (TPS7150) O EN 2 7 SENSE†/FB‡ (cid:0) Very Low Quiescent Current – Independent IN 3 6 OUT of Load...285 µA Typ IN 4 5 OUT (cid:0) Extremely Low Sleep-State Current 0.5 µA Max (cid:0) PW PACKAGE 2% Tolerance Over Specified Conditions (TOP VIEW) For Fixed-Output Versions (cid:0) GND 1 20 PG Output Current Range of 0 mA to 500 mA (cid:0) GND 2 19 NC TSSOP Package Option Offers Reduced GND 3 18 NC Component Height for Space-Critical NC 4 17 FB‡ Applications NC 5 16 NC (cid:0) Power-Good (PG) Status Output EN 6 15 SENSE† NC 7 14 OUT description IN 8 13 OUT IN 9 12 NC The TPS71xx integrated circuits are a family of micropower low-dropout (LDO) voltage IN 10 11 NC regulators. An order of magnitude reduction in NC – No internal connection dropout voltage and quiescent current over †SENSE – Fixed voltage options only conventional LDO performance is achieved by (TPS7133, TPS7148, and TPS7150) replacing the typical pnp pass transistor with a ‡FB – Adjustable version only (TPS7101) PMOS device. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32 mV at an output current of 100 mA for the TPS7150) and is directly proportional to the output current (see Figure1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to 500mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 µA maximum at T = 25°C. J Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 description (continued) 0.25 TA = 25°C 0.2 V – e 0.15 TPS7133 g a olt TPS7148 V ut 0.1 o TPS7150 p o r D 0.05 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 IO – Output Current – A Figure 1. Dropout Voltage Versus Output Current Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery indicator. The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in PDIP (8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of 1,2 mm. AVAILABLE OPTIONS OUTPUT VOLTAGE PACKAGED DEVICES (V) CHIP FORM TTJJ SMALL OUTLINE PLASTIC DIP TSSOP (Y) MIN TYP MAX (D) (P) (PW) 4.9 5 5.1 TPS7150QD TPS7150QP TPS7150QPW TPS7150Y 4.75 4.85 4.95 TPS7148QD TPS7148QP TPS7148QPW TPS7148Y –40°C to 125°C 3.23 3.3 3.37 TPS7133QD TPS7133QP TPS7133QPW TPS7133Y Adjustable† TPS7101QD TPS7101QP TPS7101QPW TPS7101Y 1.2 V to 9.75 V †The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS7150QDR). The TPS7101Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TPS71xx† 8 20 VI IN PG PG 9 15 IN SENSE 10 14 IN OUT VO 0.1 µF 6 13 EN OUT CO‡ + 10 µF GND 1 2 3 CSR †TPS7133, TPS7148, TPS7150 (fixed-voltage options) ‡Capacitor selection is nontrivial. See application information section for details. Figure 2. Typical Application Configuration TPS71xx chip information These chips, when properly assembled, display characteristics similar to the TPS71xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (5) SENSE§ (3) (6) (5) (4) IN FB¶ (6) (2) TPS71xx (4) EN OUT (7) PG (1) (7) GND CHIP THICKNESS: 15 MILS TYPICAL 80 BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. §SENSE – Fixed voltage options only (TPS7133, TPS7148, (1) (2) (3) and TPS7150) ¶FB – Adjustable version only (TPS7101) 92 NOTE A: For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the Applications Information section of this data sheet. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 functional block diagram IN RESISTOR DIVIDER OPTIONS † DEVICE R1 R2 UNIT EN † † TPS7101 0 ∞ Ω TPS7133 420 233 kΩ PG TPS7148 726 233 kΩ _ TPS7150 756 233 kΩ NOTE A: Resistors are nominal values only. + OUT COMPONENT COUNT 1.12 V SENSE‡/FB MOS transistors 464 + Bilpolar transistors 41 _ Vref = 1.178 V R1 Diodes 4 Capacitors 17 Resistors 76 R2 GND †Switch positions are shown with EN low (active). ‡For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in Applications Information section. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§ Input voltage range¶, V, PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 11 V I Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A O Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2 Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C §Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ¶All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Figure 3)# PPAACCKKAAGGEE TAA ≤ 25°C DERATING FACTOR TAA = 70°C TAA = 125°C POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING DD 772255 mmWW 55..88 mmWW//°CC 446644 mmWW 114455 mmWW P 1175 mW 9.4 mW/°C 752 mW 235 mW PW|||| 700 mW 5.6 mW/°C 448 mW 140 mW DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Figure 4)# PPAACCKKAAGGEE TCC ≤ 25°C DERATING FACTOR TCC = 70°C TCC = 125°C POWER RATING ABOVE TC = 25°C POWER RATING POWER RATING D 2188 mW 17.5 mW/°C 1400 mW 438 mW PP 22773388 mmWW 2211.99 mmWW//°°CC 11775522 mmWW 554488 mmWW PW|| 4025 mW 32.2 mW/°C 2576 mW 805 mW #Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. ||Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 DISSIPATION DERATING CURVE† DISSIPATION DERATING CURVE† vs vs FREE-AIR TEMPERATURE CASE TEMPERATURE 1400 4800 W W m m 4400 Dissipation – 11200000 PR θPJaAc k=a 1g0e6°C/W Dissipation – 343206000000 PRWθJ CP a=c 3k1a°gCePR/W θPJaCc k=a 4g6e°C/W Continuous 860000 DR θPJaAc k=a 1g7e2°C/W Continuous 222480000000 m m 1600 – MaximuPD 420000 PPRWaθcJ kAaan =gd e1 P7W8°PC/W – MaximuPD 1842000000 RθJCD =P 5a7c°kCa/gWe 0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA – Free-Air Temperature – °C TC – Case Temperature – °C Figure 3 Figure 4 †Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. recommended operating conditions MIN MAX UNIT TPS7101Q 2.5 10 TPS7133Q 3.77 10 IInnppuutt vvoollttaaggee, VVII‡‡‡ VV TPS7148Q 5.2 10 TPS7150Q 5.33 10 High-level input voltage at EN, VIH 2 V Low-level input voltage at EN, VIL 0.5 V Output current range, IO 0 500 mA Operating virtual junction temperature range, TJ –40 125 °C ‡Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load) Because the TPS7101 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rDS(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the recommended input voltage range for the TPS7101. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR† = 1 Ω, SENSE/FB shorted to OUT O O (unless otherwise noted) TPS7101Q, TPS7133Q PARAMETER TEST CONDITIONS‡ TJJ TPS7148Q, TPS7150Q UNIT MIN TYP MAX GGrroouunndd ccuurrrreenntt ((aaccttiivvee mmooddee)) EENN ≤≤ 00..55 VV,, VVII = VVOO ++ 11 VV,, 25°C 285 350 µµAA 0 mA ≤ IO ≤ 500 mA –40°C to 125°C 460 25°C 0.5 IInnppuutt ccuurrrreenntt ((ssttaannddbbyy mmooddee)) EENN = VVI, 22.77 VV ≤≤ VVI ≤≤ 1100 VV –40°C to 125°C 2 µµAA 25°C 1.2 2 OOuuttppuutt ccuurrrreenntt lliimmiitt VVOO == 00, VVII == 1100 VV AA –40°C to 125°C 2 Pass-element leakagge current in standbyy 25°C 0.5 mode EENN = VVI, 22.77 VV ≤≤ VVI ≤≤ 1100 VV –40°C to 125°C 1 µµAA 25°C 0.02 0.5 PPGG lleeaakkaaggee ccuurrrreenntt NNoorrmmaall ooppeerraattiioonn, VVPPGG == 1100 VV µµAA –40°C to 125°C 0.5 Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C Thermal shutdown junction temperature 165 °C 2.5 V ≤ VI ≤ 6 V 2 EENN llooggiicc hhiigghh ((ssttaannddbbyy mmooddee)) –4400°°CC ttoo 112255°°CC VV 6 V ≤ VI ≤ 10 V 2.7 25°C 0.5 EENN llooggiicc llooww ((aaccttiivvee mmooddee)) 22.77 VV ≤≤ VVII ≤≤ 1100 VV VV –40°C to 125°C 0.5 EN hysteresis voltage 25°C 50 mV 25°C –0.5 0.5 EENN iinnppuutt ccuurrrreenntt 00 VV ≤≤ VVII ≤≤ 1100 VV 00 VV ≤≤ VVII ≤≤ 1100 VV µµAA –40°C to 125°C –0.5 0.5 25°C 2.05 2.5 MMiinniimmuumm VVII ffoorr aaccttiivvee ppaassss eelleemmeenntt VV –40°C to 125°C 2.5 25°C 1.06 1.5 MMiinniimmuumm VVII ffoorr vvaalliidd PPGG IIPPGG == 330000 µµAA IIPPGG == 330000 µµAA –40°C to 125°C 1.9 VV †CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TPS7101 electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, FB shorted to OUT at device leads (unless otherwise noted) TPS7101Q PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ TTJJ UUNNIITT MIN TYP MAX VI = 3.5 V, IO = 10 mA 25°C 1.178 V RReeffeerreennccee vvoollttaaggee ((mmeeaassuurreedd aatt FFBB with OUT connected to FB) 2.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA, –40°C to 125°C 1.143 1.213 V See Note 1 Reference voltage temperature –40°C to 125°C 61 75 ppm/°C coefficient 25°C 0.7 1 VVII == 22.44 VV, 5500 µµAA ≤≤ IIOO ≤≤ 115500 mmAA –40°C to 125°C 1 VVII == 22.44 VV, 150 mA ≤ IOO ≤ 500 25°C 0.83 1.3 Pass-element series resistance mA –40°C to 125°C 1.3 ΩΩ (see Note 2) 25°C 0.52 0.85 VVII == 22.99 VV, 5500 µµAA ≤≤ IIOO ≤≤ 550000 mmAA –40°C to 125°C 0.85 VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.32 VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.23 IInnppuutt rreegguullaattiioonn VII = 2.5 V to 10 V,, 50 µµA ≤ IOO ≤ 500 mA,, 25°C 18 mmVV See Note 1 –40°C to 125°C 25 IOO = 5 mA to 500 mA,, 2.5 V ≤ VII ≤ 10 V,, 25°C 14 mmVV See Note 1 –40°C to 125°C 25 OOuuttppuutt rreegguullaattiioonn IOO = 50 µµA to 500 mA,, 2.5 V ≤ VII ≤ 10 V,, 25°C 22 mmVV See Note 1 –40°C to 125°C 54 25°C 48 59 IIOO == 5500 µµAA –40°C to 125°C 44 RRiippppllee rreejjeeccttiioonn ff == 112200 HHzz ddBB IOO = 500 mA,, 25°C 45 54 See Note 1 –40°C to 125°C 44 Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz CO = 4.7 µF 25°C 95 1100 HHz ≤≤ ff ≤≤ 110000 kkHHz, Output noise voltage CCSSRR†† == 11 ΩΩ CO = 10 µF 25°C 89 µVrms CO = 100 µF 25°C 74 PG trip-threshold voltage§ VFB voltage decreasing from above VPG –40°C to 125°C 1.101 1.145 V PG hysteresis voltage§ Measured at VFB 25°C 12 mV 25°C 0.1 0.4 PPGG oouuttppuutt llooww vvoollttaaggee§§ IIPPGG == 440000 µµAA, VVII == 22.1133 VV VV –40°C to 125°C 0.4 25°C –10 0.1 10 FFBB iinnppuutt ccuurrrreenntt nnAA –40°C to 125°C –20 20 †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. §Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TPS7133 electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TPS7133Q PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ TTJJ UUNNIITT MIN TYP MAX VI = 4.3 V, IO = 10 mA 25°C 3.3 OOuuttppuutt vvoollttaaggee VV 4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37 25°C 4.5 7 IIOO == 1100 mmAA, VVII == 33.2233 VV –40°C to 125°C 8 25°C 47 60 DDrrooppoouutt vvoollttaaggee IIOO == 110000 mmAA, VVII == 33.2233 VV mmVV –40°C to 125°C 80 25°C 235 300 IIOO == 550000 mmAA, VVII == 33.2233 VV –40°C to 125°C 400 PPaassss-eelleemmeenntt sseerriieess rreessiissttaannccee ((3.23 V – VOO))/IOO,, VII = 3.23 V,, 25°C 0.47 0.6 ΩΩ IO = 500 mA –40°C to 125°C 0.8 25°C 20 IInnppuutt rreegguullaattiioonn VVII == 44.33 VV ttoo 1100 VV, 5500 µµAA ≤≤ IIOO ≤≤ 550000 mmAA mmVV –40°C to 125°C 27 25°C 21 38 IIOO == 55 mmAA ttoo 550000 mmAA, 44.33 VV ≤≤ VVII ≤≤ 1100 VV mmVV –40°C to 125°C 75 OOuuttppuutt rreegguullaattiioonn 25°C 30 60 IIOO == 5500 µµAA ttoo 550000 mmAA, 44.33 VV ≤≤ VVII ≤≤ 1100 VV mmVV –40°C to 125°C 120 25°C 43 54 IIOO == 5500 µµAA –40°C to 125°C 40 RRiippppllee rreejjeeccttiioonn ff == 112200 HHzz ddBB 25°C 39 49 IIOO == 550000 mmAA –40°C to 125°C 36 Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz CO = 4.7 µF 25°C 274 1100 HHz ≤≤ ff ≤≤ 110000 kkHHz, Output noise voltage CCSSRR†† == 11 ΩΩ CO = 10 µF 25°C 228 µVrms CO = 100 µF 25°C 159 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 2.868 3 V PG hysteresis voltage 25°C 35 mV 25°C 0.22 0.4 PPGG oouuttppuutt llooww vvoollttaaggee IIPPGG == 11 mmAA, VVII == 22.88 VV –40°C to 125°C 0.4 VV †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TPS7148 electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TPS7148Q PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ TTJJ UUNNIITT MIN TYP MAX VI = 5.85 V, IO = 10 mA 25°C 4.85 OOuuttppuutt vvoollttaaggee VV 5.85 V≤VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95 25°C 2.9 6 IIOO == 1100 mmAA, VVII == 44.7755 VV –40°C to 125°C 8 25°C 30 37 DDrrooppoouutt vvoollttaaggee IIOO == 110000 mmAA, VVII == 44.7755 VV mmVV –40°C to 125°C 54 25°C 150 180 IIOO == 550000 mmAA, VVII == 44.7755 VV –40°C to 125°C 250 PPaassss-eelleemmeenntt sseerriieess rreessiissttaannccee ((4.75 V – VOO))/IOO,, VII = 4.75 V,, 25°C 0.32 0.35 ΩΩ IO = 500 mA –40°C to 125°C 0.52 25°C 27 IInnppuutt rreegguullaattiioonn VVII == 55.8855 VV ttoo 1100 VV, 5500 µµAA ≤≤ IIOO ≤≤ 550000 mmAA mmVV –40°C to 125°C 37 25°C 12 42 IIOO == 55 mmAA ttoo 550000 mmAA, 55.8855 VV ≤≤ VVII ≤≤ 1100 VV mmVV –40°C to 125°C 80 OOuuttppuutt rreegguullaattiioonn 25°C 42 60 IIOO == 5500 µµAA ttoo 550000 mmAA, 55.8855 VV ≤≤ VVII ≤≤ 1100 VV mmVV –40°C to 125°C 130 25°C 42 53 IIOO == 5500 µµAA –40°C to 125°C 39 RRiippppllee rreejjeeccttiioonn ff == 112200 HHzz ddBB 25°C 39 50 IIOO == 550000 mmAA –40°C to 125°C 35 Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz CO = 4.7 µF 25°C 410 1100 HHz ≤≤ ff ≤≤ 110000 kkHHz, Output noise voltage CCSSRR†† == 11 ΩΩ CO = 10 µF 25°C 328 µVrms CO = 100 µF 25°C 212 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 4.5 4.7 V PG hysteresis voltage 25°C 50 mV 25°C 0.2 0.4 PPGG oouuttppuutt llooww vvoollttaaggee IIPPGG == 11.22 mmAA, VVII == 44.1122 VV VV –40°C to 125°C 0.4 †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TPS7150 electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TPS7150Q PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ TTJJ UUNNIITT MIN TYP MAX VI = 6 V, IO = 10 mA 25°C 5 OOuuttppuutt vvoollttaaggee VV 6 V≤VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1 25°C 2.9 6 IIOO == 1100 mmAA, VVII == 44.8888 VV –40°C to 125°C 8 25°C 27 32 DDrrooppoouutt vvoollttaaggee IIOO == 110000 mmAA, VVII == 44.8888 VV mmVV –40°C to 125°C 47 25°C 146 170 IIOO == 550000 mmAA, VVII == 44.8888 VV –40°C to 125°C 230 PPaassss-eelleemmeenntt sseerriieess rreessiissttaannccee ((4.88 V – VOO))/IOO,, VII = 4.88 V,, 25°C 0.29 0.32 ΩΩ IO = 500 mA –40°C to 125°C 0.47 25°C 25 IInnppuutt rreegguullaattiioonn VVII == 66 VV ttoo 1100 VV, 5500 µµAA ≤≤ IIOO ≤≤ 550000 mmAA mmVV –40°C to 125°C 32 25°C 30 45 IIOO == 55 mmAA ttoo 550000 mmAA, 66 VV ≤≤ VVII ≤≤ 1100 VV mmVV –40°C to 125°C 86 OOuuttppuutt rreegguullaattiioonn 25°C 45 65 IIOO == 5500 µµAA ttoo 550000 mmAA, 66 VV ≤≤ VVII ≤≤ 1100 VV mmVV –40°C to 125°C 140 25°C 45 55 IIOO == 5500 µµAA –40°C to 125°C 40 RRiippppllee rreejjeeccttiioonn ff == 112200 HHzz ddBB 25°C 42 52 IIOO == 550000 mmAA –40°C to 125°C 36 Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz CO = 4.7 µF 25°C 430 1100 HHz ≤≤ ff ≤≤ 110000 kkHHz, Output noise voltage CCSSRR†† == 11 ΩΩ CO = 10 µF 25°C 345 µVrms CO = 100 µF 25°C 220 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 4.55 4.75 V PG hysteresis voltage 25°C 53 mV 25°C 0.2 0.4 PPGG oouuttppuutt llooww vvoollttaaggee IIPPGG == 11.22 mmAA, VVII == 44.2255 VV –40°C to 125°C 0.4 VV †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR† = 1 Ω, T = 25°C, SENSE/FB O O J shorted to OUT (unless otherwise noted) TPS7101Y, TPS7133Y PARAMETER TEST CONDITIONS‡ TPS7148Y, TPS7150Y UNIT MIN TYP MAX Ground current (active mode) EN ≤ 0.5 V, VI = VO + 1 V, 285 µA 0 mA ≤ IO ≤ 500 mA Output current limit VO = 0, VI = 10 V 1.2 A PG leakage current Normal operation, VPG = 10 V 0.02 µA Thermal shutdown junction temperature 165 °C EN hysteresis voltage 50 mV Minimum VI for active pass element 2.05 V Minimum VI for valid PG IPG = 300 µA 1.06 V TPS7101Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ UUNNIITT MIN TYP MAX Reference voltage (measured at FB with OUT connected to FB) VI = 3.5 V, IO = 10 mA 1.178 V VI = 2.4 V, 50 µA ≤ IO ≤ 150 mA 0.7 VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 0.83 Pass-element series resistance (see Note 2) VI = 2.9 V, 50 µA ≤ IO ≤ 500 mA 0.52 Ω VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 0.32 VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 0.23 VI = 2.5 V to 10 V, 50 µA ≤ IO ≤ 500 mA, Input regulation 18 mV See Note 1 2.5 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA, 14 mV See Note 1 OOuuttppuutt rreegguullaattiioonn 2.5 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA, 22 mV See Note 1 VI = 3.5 V, f = 120 Hz, Ripple rejection 59 dB IO = 50 µA Output noise-spectral density VI = 3.5 V, f = 120 Hz 2 µV/√Hz VVII == 33..55 VV,, CO = 4.7 µF 95 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CO = 10 µF 89 µVrms CSR†† = 1 Ω CO = 100 µF 74 PG hysteresis voltage§ VI = 3.5 V, Measured at VFB 12 mV PG output low voltage§ VI = 2.13 V, IPG = 400 µA 0.1 V FB input current VI = 3.5 V VI = 3.5 V 0.1 nA †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. §Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR† = 1 Ω, T = 25°C, SENSE shorted O O J to OUT (unless otherwise noted) (continued) TPS7133Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ UUNNIITT MIN TYP MAX Output voltage VI = 4.3 V, IO = 10 mA 3.3 V VI = 3.23 V, IO = 10 mA 0.02 Dropout voltage VI = 3.23 V, IO = 100 mA 47 mV VI = 3.23 V, IO = 500 mA 235 Pass-element series resistance (3.23 V – VO)/IO, VI = 3.23 V, 0.47 Ω IO = 500 mA 4.3 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 21 mV OOuuttppuutt rreegguullaattiioonn 4.3 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 30 mV RRiippppllee rreejjeeccttiioonn VII = 4.3 V,, IO = 50 µA 54 ddBB f = 120 Hz IO = 500 mA 49 Output noise-spectral density VI = 4.3 V, f = 120 Hz 2 µV/√Hz VVII == 44..33 VV,, CO = 4.7 µF 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CO = 10 µF 228 µVrms CCSSRR†† = 1 Ω CO = 100 µF 159 PG hysteresis voltage VI = 4.3 V 35 mV PG output low voltage VI = 2.8 V, IPG = 1 mA 0.22 V TPS7148Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ UUNNIITT MIN TYP MAX Output voltage VI = 5.85 V, IO = 10 mA 4.85 V VI = 4.75 V, IO = 10 mA 0.08 Dropout voltage VI = 4.75 V, IO = 100 mA 30 mV VI = 4.75 V, IO = 500 mA 150 Pass-element series resistance (4.75 V – VO)/IO, VI = 4.75 V, 0.32 Ω IO = 500 mA 5.85 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 12 mV OOuuttppuutt rreegguullaattiioonn 5.85 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 42 mV RRiippppllee rreejjeeccttiioonn VII = 5.85 V,, IO = 50 µA 53 ddBB f = 120 Hz IO = 500 mA 50 Output noise-spectral density VI = 5.85 V, f = 120 Hz 2 µV/√Hz VVII == 55..8855 VV,, CO = 4.7 µF 410 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CO = 10 µF 328 µVrms CCSSRR†† = 1 Ω CO = 100 µF 212 PG hysteresis voltage VI = 5.85 V 50 mV PG output low voltage VI = 4.12 V, IPG = 1.2 mA 0.2 0.4 V †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF/CSR† = 1 Ω, T = 25°C, SENSE shorted O O J to OUT (unless otherwise noted) (continued) TPS7150Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ UUNNIITT MIN TYP MAX Output voltage VI = 6 V, IO = 10 mA 5 V VI = 4.88 V, IO = 10 mA 0.13 Dropout voltage VI = 4.88 V, IO = 100 mA 27 mV VI = 4.88 V, IO = 500 µA 146 Pass-element series resistance (4.88 V – VO)/IO, VI = 4.88 V, 0.29 Ω IO = 500 mA 6 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA 30 mV OOuuttppuutt rreegguullaattiioonn 6 V ≤ VI ≤ 10 V, IO = 50 µA to 500 mA 45 mV RRiippppllee rreejjeeccttiioonn VII = 6 V,, IO = 50 µA 55 ddBB f = 120 Hz IO = 500 mA 52 Output noise-spectral density VI = 6 V, f = 120 Hz 2 µV/√Hz VVII == 66 VV,, CO = 4.7 µF 430 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CO = 10 µF 345 µVrms CCSSRR†† = 1 Ω CO = 100 µF 220 PG hysteresis voltage VI = 6 V 53 mV PG output low voltage VI = 4.25 V, PG = 1.2 mA 0.2 V †CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 5 IQ Quiescent current vs Input voltage 6 vs Free-air temperature 7 VDO Dropout voltage vs Output current 8 ∆VDO Change in dropout voltage vs Free-air temperature 9 ∆VO Change in output voltage vs Free-air temperature 10 VO Output voltage vs Input voltage 11 ∆VO Change in output voltage vs Input voltage 12 13 14 VVOO OOuuttppuutt vvoollttaaggee vvss OOuuttppuutt ccuurrrreenntt 15 16 17 18 RRiippppllee rreejjeeccttiioonn vvss FFrreeqquueennccyy 19 20 21 22 OOuuttppuutt ssppeeccttrraall nnooiissee ddeennssiittyy vvss FFrreeqquueennccyy 23 24 rDS(on) Pass-element resistance vs Input voltage 25 R Divider resistance vs Free-air temperature 26 II(SENSE) SENSE pin current vs Free-air temperature 27 FB leakage current vs Free-air temperature 28 Minimum input voltage for active-pass element vs Free-air temperature 29 VVII Minimum input voltage for valid PG vs Free-air temperature 30 II(EN) Input current (EN) vs Free-air temperature 31 Output voltage response from Enable (EN) 32 VPG Power-good (PG) voltage vs Output voltage 33 34 CCSSRR CCoommppeennssaattiioonn sseerriieess rreessiissttaannccee vvss OOuuttppuutt ccuurrrreenntt 35 36 CCSSRR CCoommppeennssaattiioonn sseerriieess rreessiissttaannccee vvss AAddddeedd cceerraammiicc ccaappaacciittaannccee 37 38 CCSSRR CCoommppeennssaattiioonn sseerriieess rreessiissttaannccee vvss OOuuttppuutt ccuurrrreenntt 39 40 CCSSRR CCoommppeennssaattiioonn sseerriieess rreessiissttaannccee vvss AAddddeedd cceerraammiicc ccaappaacciittaannccee 41 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS QUIESCENT CURRENT QUIESCENT CURRENT vs vs OUTPUT CURRENT INPUT VOLTAGE 355 400 TA = 25°C TA = 25°C 345 350 RL = 10 Ω µA 335 TPS71xx, VI = 10 V µA 300 TPS7133 Current – 331255 Current – 250 TPS7150TPS7148 – Quiescent 239055 TPS7150, VI = 6 V – Quiescent 210500 TPProSg7r1a0m1m Weidth t oV O2.5 V Q Q 100 I 285 I TPS7148, VI = 5.85 V 275 50 TPS7133, VI = 4.3 V 265 0 0 50 100 150 200 250 300 350 400 450 500 0 1 2 3 4 5 6 7 8 9 10 IO – Output Current – mA VI – Input Voltage – V Figure 5 Figure 6 TPS7148Q QUIESCENT CURRENT DROPOUT VOLTAGE vs vs FREE-AIR TEMPERATURE OUTPUT CURRENT 400 0.3 VI = VO(nom) + 1 V TA = 25°C IO = 10 mA 0.25 350 A TPS7133 µnt – e – V 0.2 re 300 ag uiesent Cur 250 ropout Volt 0.15 TPS7148 Q D 0.1 – Q TPS7150 I 200 0.05 150 0 –50 –25 0 25 50 75 100 125 0 50 100 150 200 250 300 350 400 450 500 TA – Free-Air Temperature – °C IO – Output Current – mA Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS CHANGE IN DROPOUT VOLTAGE CHANGE IN OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 10 20 IO = 100 mA VI = VO(nom) + 1 V 8 IO = 10 mA 15 V V 6 m m – – e 10 e 4 g g a olta 2 Volt 5 ut V put po 0 Out 0 o n Dr –2 e in –5 ge i –4 ang n h a C –10 Ch –6 – O V –8 ∆ –15 –10 –20 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 9 Figure 10 OUTPUT VOLTAGE CHANGE IN OUTPUT VOLTAGE vs vs INPUT VOLTAGE INPUT VOLTAGE 6 20 TA = 25°C TA = 25°C RL = 10 Ω TPS7150 15 RL = 10 Ω 5 V m – TPS7148 e 10 V g ge – 4 Volta 5 TPS7150 ut Volta 3 TPS7133 Output 0 TPS7148 Outp e In –5 – 2 TPS7101 With VO ng TPS7133 O Programmed to 2.5 V ha V C –10 – 1 O V ∆ –15 0 –20 0 1 2 3 4 5 6 7 8 9 10 4 5 6 7 8 9 10 VI – Input Voltage – V VI – Input Voltage – V Figure 11 Figure 12 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS TPS7101Q TPS7133Q OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT 2.52 3.34 TVAO =P r2o5g°Crammed to 2.5 V TA = 25°C 2.515 3.33 2.51 3.32 V V e – e – ag 2.505 ag 3.31 Volt Volt VI = 10 V ut 2.5 VI = 3.5 V ut 3.3 p p – Out 2.495 VI = 10 V – Out 3.29 VI = 4.3 V O O V V 2.49 3.28 2.485 3.27 2.48 3.26 0 100 200 300 400 500 0 100 200 300 400 500 IO – Output Current – mA IO – Output Current – mA Figure 13 Figure 14 TPS7148Q TPS7150Q OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT 4.92 5.06 4.91 TA = 25°C 5.05 TA = 25°C 4.9 5.04 4.89 5.03 V V ge – 4.88 ge – 5.02 ut Volta 44..8876 VI = 5.85 V ut Volta 5.051 VI = 6 V p p – Out 44..8854 VI = 10 V – Out 44..9998 VI = 10 V O O V 4.83 V 4.97 4.82 4.96 4.81 4.95 4.8 4.94 0 100 200 300 400 500 0 100 200 300 400 500 IO – Output Current – mA IO – Output Current – mA Figure 15 Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS TPS7101Q TPS7133Q RIPPLE REJECTION RIPPLE REJECTION vs vs FREQUENCY FREQUENCY 70 70 60 60 RL = 100 kΩ 50 RL = 100 kΩ 50 B B d d n – n – 40 o 40 o cti cti e e 30 ej ej RL = 500 Ω R 30 R ple TA = 25°C RL = 500 Ω ple 20 Rip 20 CVIO = = 3 .45. 7V µF (CSR = 1 Ω) Rip 10 TA = 25°C RL = 10 Ω No Input Capacitance VI = 3.5 V 10 VO Programmed to 2.5 V 0 CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance RL = 10 Ω 0 –10 10 100 1K 10K 100K 1M 10M 10 100 1 k 10 k 100 k 1 M 10 M f – Frequency – Hz f – Frequency – Hz Figure 17 Figure 18 TPS7148Q TPS7150Q RIPPLE REJECTION RIPPLE REJECTION vs vs FREQUENCY FREQUENCY 70 70 60 60 B 50 RL = 100 kΩ B 50 RL = 100 kΩ Ripple Rejection – d 432000 RL = 10 Ω RL = 500 Ω Ripple Rejection – d 432000 RL = 10 Ω RL = 500 Ω 10 TA = 25°C TA = 25°C VI = 3.5 V VI = 3.5 V 0 CO = 4.7 µF (CSR = 1 Ω) 10 CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance No Input Capacitance –10 0 10 100 1 k 10 k 100 k 1 M 10 M 10 100 1 k 10 k 100 k 1 M 10 M f – Frequency – Hz f – Frequency – Hz Figure 19 Figure 20 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS TPS7101Q TPS7133Q OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY 10 10 TA = 25°C TA = 25°C No Input Capacitance No Input Capacitance z z H VI = 3.5 V H VI = 4.3 V V/ VO Programmed to 2.5 V V/ µ µ y – CO = 4.7 µF (CSR = 1 Ω) y – CO = 10 µF (CSR = 1 Ω) ensit 1 CO = 10 µF (CSR = 1 Ω) ensit 1 CO = 4.7 µF (CSR = 1 Ω) D D e e CO = 100 µF (CSR = 1 Ω) s s oi oi N N al al r r ct 0.1 ct 0.1 e e p p S S ut ut p p ut ut O O CO = 100 µF (CSR = 1 Ω) 0.01 0.01 10 102 103 104 105 10 102 103 104 105 f – Frequency – Hz f – Frequency – Hz Figure 21 Figure 22 TPS7148Q TPS7150Q OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY 10 10 TA = 25°C z No Input Capacitance z CO = 10 µF (CSR = 1 Ω) H H VI = 5.85 V V/ V/ CO = 4.7 µF (CSR = 1 Ω) µ– CO = 10 µF (CSR = 1 Ω) µ– y y nsit 1 CO = 4.7 µF (CSR = 1 Ω) nsit 1 TA = 25°C e e D D No Input Capacitance se se VI = 6 V oi oi N N al al r r ct 0.1 ct 0.1 e e p p S S ut ut utp CO = 100 µF (CSR = 1 Ω) utp O O CO = 100 µF (CSR = 1 Ω) 0.01 0.01 10 100 1 k 10 k 100 k 10 100 1 k 10 k 100 k f – Frequency – Hz f – Frequency – Hz Figure 23 Figure 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS PASS-ELEMENT RESISTANCE DIVIDER RESISTANCE vs vs INPUT VOLTAGE FREE-AIR TEMPERATURE 1.1 1.2 TA = 25°C VI = VO(nom) + 1 V Ω 1 VI(FB) = 1.12 V VI(sense) = VO(nom) 1.1 – e 0.9 TPS7150 c Ω an M 1 st 0.8 – si e TPS7148 Re 0.7 IO = 500 mA nc 0.9 nt sta eme 0.6 Resi 0.8 El r ass- 0.5 IO = 100 mA vide 0.7 – P 0.4 – Di n) R 0.6 TPS7133 o 0.3 S( D r 0.2 0.5 0.1 0.4 2 3 4 5 6 7 8 9 10 –50 –25 0 25 50 75 100 125 VI – Input Voltage – V TA – Free-Air Temperature – °C Figure 25 Figure 26 FIXED-OUTPUT VERSIONS ADJUSTABLE VERSION SENSE PIN CURRENT FB LEAKAGE CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 6 0.6 VI = VO(nom) + 1 V 5.8 VI(sense) = VO(nom) VFB = 2.5 V A 0.5 µ – 5.6 nt A e n Curr 5.4 nt – 0.4 n re Pi ur e 5.2 C 0.3 s e n g e a S 5 k – ea 0.2 se) B L n 4.8 F e s II( 4.6 0.1 4.4 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 27 Figure 28 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS MINIMUM INPUT VOLTAGE FOR ACTIVE MINIMUM INPUT VOLTAGE FOR VALID PASS ELEMENT POWER GOOD (PG) vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 2.1 1.1 RL = 500 Ω 2.09 V 2.08 V 1.09 – – e e g 2.07 g a a olt olt V 2.06 V 1.08 ut ut np 2.05 np m I m I mu 2.04 mu 1.07 ni ni ÁMiÁ2.03 ÁMiÁ – – ÁVIÁ2.02 ÁVIÁ1.06 2.01 2 1.05 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 29 Figure 30 EN INPUT CURRENT vs FREE-AIR TEMPERATURE 100 90 VI = VI(EN) = 10 V 80 A – n 70 nt e 60 r r u ut C 50 p n 40 – I N) 30 E II( 20 10 0 –40 –20 0 20 40 60 80 100 120 140 TA – Free-Air Temperature – °C Figure 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN) – V VO(nom) e g a olt V ut p ut O – VO TA = 25°C RL = 500 Ω 6 CO = 4.7 µF (ESR = 1Ω) V No Input Capacitance 4 – e g a 2 olt V N 0 E –2 0 20 40 60 80 100 120 140 Time – µs Figure 32 POWER-GOOD (PG) VOLTAGE vs OUTPUT VOLTAGE 6 TA = 25°C PG Pulled Up to 5 V With 5 kΩ V 5 – e g a olt 4 V G) P d ( 3 o o G r- e w 2 o P Á– Á G P 1 ÁVÁ 0 93 94 95 96 97 98 VO – Output Voltage (VO as a percent of VO(nom)) – % Figure 33 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE COMPENSATION SERIES RESISTANCE vs vs OUTPUT CURRENT OUTPUT CURRENT 100 100 Ω VI = VO(nom) + 1 V Ω VI = VO(nom) + 1 V No Input Capacitance Resistance – 10 NTCAoO =A= d 24d5.7°eC dµ FCeramic CapRaecgitiaonnc oef Instability Resistance – 10 CTNCAeoO r =Ia=n m 2p45ui.c7°tC CµCFaap p+aa 0cc.ii5ttaa µnnFcc eeof Series Series Region of Instability mpensation 1 mpensation 1 Co Co – – R R CS Region of Instability CS Region of Instability 0.1 0.1 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 IO – Output Current – mA IO – Output Current – mA Figure 34 Figure 35 TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE COMPENSATION SERIES RESISTANCE vs vs ADDED CERAMIC CAPACITANCE ADDED CERAMIC CAPACITANCE 100 100 Ω VI = VO(nom) + 1 V Ω VI = VO(nom) + 1 V – No Input Capacitance – No Input Capacitance ce IO= 100 mA ce IO= 500 mA an CO = 4.7 µF an CO = 4.7 µF sist TA = 25°C sist TA = 25°C Re 10 Re 10 s Region of Instability s Region of Instability e e eri eri S S n n o o ati ati s s en 1 en 1 p p m m o o C C – – R R S Region of Instability S Region of Instability C C 0.1 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Ceramic Capacitance – µF Ceramic Capacitance – µF Figure 36 Figure 37 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS TYPICAL REGIONS OF STABILITY† TYPICAL REGIONS OF STABILITY† COMPENSATION SERIES RESISTANCE COMPENSATION SERIES RESISTANCE vs vs OUTPUT CURRENT OUTPUT CURRENT 100 100 Region of Instability VI = VO(nom) + 1 V VI = VO(nom) + 1 V Ω No Input Capacitance Ω No Input Capacitance e – CO = 10 µF e – CO = 10 µF + 0.5 µF of nc No Ceramic Capacitance nc Added Ceramic Capacitance sta TA = 25°C sta TA = 25°C si si Re 10 Re 10 s s erie erie Region of Instability S S n n o o ati ati s s en 1 en 1 p p m m o o C C – – R R CS 0.2 CS 0.2 0.1 0.1 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 IO – Output Current – mA IO – Output Current – mA Figure 38 Figure 39 TYPICAL REGIONS OF STABILITY† TYPICAL REGIONS OF STABILITY† COMPENSATION SERIES RESISTANCE COMPENSATION SERIES RESISTANCE vs vs ADDED CERAMIC CAPACITANCE ADDED CERAMIC CAPACITANCE 100 100 VI = VO(nom) + 1 V VI = VO(nom) + 1 V Ω No Input Capacitance Ω No Input Capacitance – ce CO = 10 µF e – CO = 10 µF an IO = 100 mA nc IO = 500 mA esist TA = 25°C sista TA = 25°C R 10 e 10 es s R eri Region of Instability rie Region of Instability S e on n S sati atio n s e 1 n 1 p e m p m o C o C SR – R – C 0.2 S 0.2 C 0.1 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Ceramic Capacitance – µF Ceramic Capacitance – µF Figure 40 Figure 41 †CSR values below 0.1 Ω are not recommended. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS To Load VI IN OUT + SENSE EN CO Ccer† RL GND CSR †Ceramic capacitor Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 41) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 APPLICATION INFORMATION The TPS71xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good indicator. The TPS71xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the TPS7148 (4.85 V), and the TPS7150 (5 V). The family also offers an adjustable device, the TPS7101 (adjustable from 1.2 V to 9.75 V). device operation The TPS71xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (I = I /β). Close examination of the data sheets reveals B C that those devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves. The TPS71xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS71xx specifications reflect actual performance under load. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates B to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS71xx quiescent current remains low even when the regulator drops out, eliminating both problems. Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges. The TPS71xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is reestablished in typically 120 µs. minimum load requirements The TPS71xx family is stable even at zero load; no minimum load is required for operation. SENSE-pin connection The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate. external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load transient response and noise rejection if the TPS71xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 APPLICATION INFORMATION external capacitor requirements (continued) As with most LDO regulators, the TPS71xx family requires an output capacitor for stability. A 10-µF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 Ω over temperature. Where component height and/or mounting area is a problem, physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance. In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be reduced to 4.7 µF, provided ESR is maintained between the values shown in figures 34 through 41. Because minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit ESR to 1.5 Ω maximum. TPS71xx† 8 20 VI IN PG PG 9 15 IN SENSE 250 kΩ 10 14 IN OUT VO C1 0.1 µF 6 EN OUT 13 + CO 50 V 10 µF GND ESR 1 2 3 †TPS7133, TPS7148, TPS7150 (fixed-voltage options) Figure 43. Typical Application Circuit programming the TPS7101 adjustable LDO regulator Programming the adjustable regulators is accomplished using an external resistor divider as shown in Figure44. The equation governing the output voltage is: VO(cid:1)Vref(cid:2)(cid:3)1(cid:0)RR12(cid:4) where V = reference voltage, 1.178 V typ ref POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27

TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003 APPLICATION INFORMATION programming the TPS7101 adjustable LDO regulator (continued) Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2 is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at FB introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate resistance: (cid:3)V (cid:4) O R1(cid:1) (cid:0)1 (cid:2)R2 V ref OUTPUT VOLTAGE TPS7101 PROGRAMMING GUIDE OUTPUT R1 R2 UNIT VI IN PG Power-Good VOLTAGE 0.1 µF Indicator 2.5 V 191 169 kΩ 250 kΩ >2.7 V 3.3 V 309 169 kΩ EN OUT VO 3.6 V 348 169 kΩ <0.5V + R1 4 V 402 169 kΩ FB 5 V 549 169 kΩ GND 6.4 V 750 169 kΩ R2 Figure 44. TPS7101 Adjustable LDO Regulator Programming power-good indicator The TPS71xx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low, relative to its nominal regulated value. regulator protection The TPS71xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS71xx also features internal current limiting and thermal protection. During normal operation, the TPS71xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS7101QD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7101Q & no Sb/Br) TPS7101QDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7101Q & no Sb/Br) TPS7101QP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 125 TPS7101QP & no Sb/Br) TPS7101QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7101 & no Sb/Br) TPS7133QD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7133Q & no Sb/Br) TPS7133QDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7133Q & no Sb/Br) TPS7133QDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7133Q & no Sb/Br) TPS7133QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7133Q & no Sb/Br) TPS7133QP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 125 TPS7133QP & no Sb/Br) TPS7148QD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7148Q & no Sb/Br) TPS7148QP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 125 TPS7148QP & no Sb/Br) TPS7150QD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7150Q & no Sb/Br) TPS7150QDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7150Q & no Sb/Br) TPS7150QDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 7150Q & no Sb/Br) TPS7150QP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 125 TPS7150QP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2018 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS7101QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS7101QPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS7133QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS7150QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS7101QDR SOIC D 8 2500 367.0 367.0 35.0 TPS7101QPWR TSSOP PW 20 2000 367.0 367.0 38.0 TPS7133QDR SOIC D 8 2500 350.0 350.0 43.0 TPS7150QDR SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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