Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 TPS6128x Low-, Wide- Voltage Battery Front-End DC/DC Converter Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications 1 Features 3 Description • 95%Efficiencyat2.3MHzOperation The TPS6128x device provides a power supply 1 solution for products powered by either by a Li-Ion, • 2µAQuiescentCurrentinLowI Pass-Through Q Nickel-Rich, Silicon Anode, Li-Ion or LiFePO4 battery. Mode The voltage range is optimized for single-cell portable • WideV RangeFrom2.3Vto4.8V applicationslikeinsmart-phonesortabletPCs. IN • I ≥4A(Peak)atV =3.35V,V ≥ 2.65V OUT OUT IN Used as a high-power pre-regulator, the TPS6128x • IntegratedPass-ThroughMode(35mΩ) extends the battery run-time and overcomes input current- and voltage limitations of the powered • ProgrammableValleyInductorCurrentLimitand system. OutputVoltage • ProgrammableAverageInputCurrentLimitand While in shutdown, the TPS6128x operates in a true OutputVoltage pass-through mode with only 2µA quiescent consumptionforlongestbatteryshelflife. • TruePass-ThroughModeDuringShutdown • Best-in-ClassLineandLoadTransient During operation, when the battery is at a good state- of-charge, a low-ohmic, high-efficient integrated pass- • Low-RippleLight-LoadPFMMode through path connects the battery to the powered • In-SituCustomizationwithOn-ChipE2PROM system. (WriteProtect) If the battery gets to a lower state of charge and its • TwoInterfaceOptions: voltage becomes lower than the desired minimum – I2CCompatibleI/Fupto3.4Mbps(TPS61280) system voltage, the device seamlessly transits into boostmodetoutilizethefullbatterycapacity. – SimpleI/OLogicControlInterface(TPS6128x) • ThermalShutdownandOverloadProtection DeviceInformation(1) • TotalSolutionSize <20mm2,Sub1-mmProfile PARTNUMBER PACKAGE BODYSIZE(NOM) TPS61280 2 Applications TPS61281 DSBGA(16) 1.66mmx1.66mm • Single-CellNi-Rich,Si-Anode,Li-Ion,LiFePO4 TPS61282 Smart-PhonesorTabletPCs (1) For all available packages, see the orderable addendum at • 2.5G/3G/4GMini-ModuleDataCards theendofthedatasheet. • CurrentLimitedApplicationsFeaturingHighPeak PowerLoads 4 Simplified Schematic TPS61280 SW VOUT VBAT’ L SW VOUT 0.47μH VIN C10Oµ(Fx2 X)5R 6.3V (0603) Battery VIN 2.5V .. 4.35V 1.5µF X5R 6.3V (0402C)I Voltage Select VSEL Enable EN Forced Bypass /Auto BYP 1.8V SCL I2C Bus SDA GPIO Interrupt PGND PGND PGND AGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 10.3 FeatureDescription...............................................16 2 Applications........................................................... 1 10.4 DeviceFunctionalModes......................................18 3 Description............................................................. 1 10.5 Programming.........................................................23 10.6 RegisterMaps.......................................................26 4 SimplifiedSchematic............................................. 1 11 ApplicationandImplementation........................ 34 5 RevisionHistory..................................................... 2 11.1 ApplicationInformation..........................................34 6 Description(continued)......................................... 3 11.2 TypicalApplication................................................34 7 DeviceComparisonTable..................................... 3 12 PowerSupplyRecommendations..................... 46 8 PinConfigurationandFunctions......................... 4 13 Layout................................................................... 46 9 Specifications......................................................... 6 13.1 LayoutGuidelines.................................................46 9.1 AbsoluteMaximumRatings .....................................6 13.2 LayoutExample....................................................46 9.2 HandlingRatings.......................................................6 13.3 ThermalConsideration..........................................47 9.3 RecommendedOperatingConditions.......................6 14 DeviceandDocumentationSupport................. 48 9.4 ThermalInformation..................................................7 14.1 DeviceSupport......................................................48 9.5 ElectricalCharacteristics...........................................7 14.2 RelatedLinks........................................................48 9.6 TimingRequirements................................................9 14.3 Trademarks...........................................................48 9.7 I2CInterfaceTimingCharacteristics ........................9 14.4 ElectrostaticDischargeCaution............................48 9.8 TypicalCharacteristics............................................12 14.5 Glossary................................................................48 10 DetailedDescription........................................... 14 15 Mechanical,Packaging,andOrderable 10.1 Overview...............................................................14 Information........................................................... 49 10.2 FunctionalBlockDiagram.....................................15 15.1 PackageSummary................................................49 5 Revision History ChangesfromOriginal(October2013)toRevisionA Page • AddedHandlingRatingtable,FeatureDescriptionsection,DeviceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation Supportsection,andMechanical,Packaging,andOrderableInformationsection. .............................................................. 1 • AddedtheDeviceInformationtable....................................................................................................................................... 1 • DeletedthePackageMarkingChipCodecolumnfromtheDeviceComparisonTable.Theinformationisfoundin thePOAattheendofthedatasheet ..................................................................................................................................... 4 • Added"VoltageatVIN"totheAbsoluteMaximumRatingstable.......................................................................................... 6 • ChangedtheTypicalCharacteristicssectiongraphs .......................................................................................................... 12 • ChangedthesecondparagraphintheStart-UpandShutdownModesection.................................................................... 21 2 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 6 Description (continued) TPS6128x device supports more than 4A pulsed load current even from a deeply discharged battery. In this mode of operation, the TPS6128x enables the utilization of the full battery capacity: A high battery-cut-off voltage originated by powered components with a high minimum input voltage is overcome; new battery chemistries can be fully discharged; high current pulses forcing the system into shutdown are buffered by the device seamlessly transitioningbetweenboostandby-passmodebackandforth. This has significant impact on the battery on-time and translates into either a longer use-time and better user- experienceatanequalbatterycapacityorintoreducedbatterycostsatsimilaruse-times. The TPS6128x operates in synchronous, 2.3MHz boost mode and enters power-save mode operation (PFM) at lightloadcurrentstomaintainhighefficiencyovertheentireloadcurrentrange. The TPS6128x offers a small solution size (<20mm2) due to minimum amount of external components, enabling theuseofsmallinductorsandinputcapacitors,availableasa16-pinchip-scalepackage(CSP). 7 Device Comparison Table DEVICE PARTNUMBER SPECIFICFEATURES DC/DCboost/bypassthreshold=3.15V(Vsel=L) I2CControlInterface TPS61280 UserProg.E2PROMSettings DC/DCboost/bypassthreshold=3.35V(Vsel=H) Valleyinductorcurrentlimit=3A DC/DCboost/bypassthreshold=3.15V(Vsel=L) TPS61281 SimpleLogicControlInterface DC/DCboost/bypassthreshold=3.35V(Vsel=H) Valleyinductorcurrentlimit=3A DC/DCboost/bypassthreshold=3.3V(Vsel=L) TPS61282 SimpleLogicControlInterface DC/DCboost/bypassthreshold=3.5V(Vsel=H) Valleyinductorcurrentlimit=4A Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 8 Pin Configuration and Functions TPS61280 EN GPIO VIN VIN VIN VIN GPIO EN A4 A3 A2 A1 VSEL SCL VOUT VOUT VOUT VOUT SCL VSEL B4 B3 B2 B1 nBYP SDA SW SW SW SW SDA nBYP C4 C3 C2 C1 AGND PGND PGND PGND PGND PGND PGND AGND D4 D3 D2 D1 TOP VIEW BOTTOM VIEW PinFunctions-TPS61280 PIN I/O DESCRIPTION NAME NO. VIN A3,A4 I Powersupplyinput. VOUT B3,B4 O Boostconverteroutput. Thisistheenablepinofthedevice.Ontherisingedgeoftheenablepin,alltheregistersareresetwiththeirdefault values.Thisinputmustnotbeleftfloatingandmustbeterminated. EN=Low:ThedeviceisforcedintoshutdownmodeandtheI2Ccontrolinterfaceisdisabled.Dependingonthe logiclevelappliedtothenBYPinput,theconvertercaneitherbeforcedinpass-throughmodeorit'soutputcanbe EN A1 I regulatedtoaminimumlevelsoastolimittheinput-to-outputvoltagedifferencetolessthan3.6V(typ).Thecurrent consumptionisreducedtoafewµA.Formoredetails,refertoTable2. EN=High:Thedeviceisoperatingnormallyfeaturingautomaticdc/dcboost,pass-throughmodetransition.For moredetails,refertoTable2. Thispincaneitherbeconfiguredasainput(modeselection)orasdualroleinput/open-drainoutput(nRST/nFAULT) pin.Perdefault,thepinisconfiguredasnRST/nFAULTinput/output.Theinputmustnotbeleftfloatingandmustbe terminated. ManualResetInput:DrivenRST/nFAULTlowtoinitiatearesetoftheconverter'soutput.nRST/nFAULTcontrolsa fallingedge-triggeredsequenceconsistingofadischargephaseofthecapacitancelocatedattheconverter'soutput followedbyastart-upphase. GPIO A2 I/O FaultOutput(open-draininterruptsignaltohost):Indicatesthatafaulthasoccurred(e.g.thermalshutdown,output voltageoutoflimits,currentlimittriggered,andsoon).Tosignalsuchanevent,thedevicegeneratesafallingedge- triggeredinterruptbydrivinganegativepulseontotheGPIOlineandthenreleasesthelinetoitsinactivestate. Modeselectioninput=Low:Thedeviceisoperatinginregulatedfrequencypulsewidthmodulationmode(PWM)at high-loadcurrentsandinpulsefrequencymodulationmode(PFM)atlightloadcurrents. Modeselectioninput=High:Low-noisemodeenabled,regulatedfrequencyPWMoperationforced. VSELsignalisprimarilyusedtosettheoutputvoltagedc/dcboost,pass-throughthreshold.Thispinmustnotbeleft VSEL B1 I floatingandmustbeterminated. AlogiclowlevelonthenBYPinputforcesthedeviceinpass-throughmode.Formoredetails,refertoTable2.This nBYP C1 I pinmustnotbeleftfloatingandmustbeterminated. SCL B2 I Serialinterfaceclockline.Thispinmustnotbeleftfloatingandmustbeterminated. SDA C2 I/O Serialinterfaceaddress/dataline.Thispinmustnotbeleftfloatingandmustbeterminated. SW C3,C4 I/O Inductorconnection.DrainoftheinternalpowerMOSFET.Connecttotheswitchedsideoftheinductor. PGND D2,D3,D4 Powergroundpin. AGND D1 Analoggroundpin.ThisisthesignalgroundreferencefortheIC. 4 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 TPS6128x EN PG VIN VIN VIN VIN PG EN A4 A3 A2 A1 VSEL MODE VOUT VOUT VOUT VOUT MODE VSEL B4 B3 B2 B1 nBYP AGND SW SW SW SW AGND nBYP C4 C3 C2 C1 AGND PGND PGND PGND PGND PGND PGND AGND D4 D3 D2 D1 TOP VIEW BOTTOM VIEW PinFunctions-TPS6128x PIN I/O DESCRIPTION NAME NO. VIN A3,A4 I Powersupplyinput. VOUT B3,B4 O Boostconverteroutput. Thisistheenablepinofthedevice.Ontherisingedgeoftheenablepin,alltheregistersarereset withtheirdefaultvalues.Thisinputmustnotbeleftfloatingandmustbeterminated. EN=Low:Thedeviceisforcedintoshutdownmode.Dependingonthelogiclevelappliedtothe nBYPinput,theconvertercaneitherbeforcedinpass-throughmodeorit'soutputcanberegulatedto EN A1 I aminimumlevelsoastolimittheinput-to-outputvoltagedifferencetolessthan3.6V(typ).The currentconsumptionisreducedtoafewµA.Formoredetails,refertoTable2. EN=High:Thedeviceisoperatingnormallyfeaturingautomaticdc/dcboost,pass-throughmode transition.Formoredetails,refertoTable2. Power-GoodOutput(open-drainoutputtohost):AlogichighonthePGoutputindicatesthatthe converter'soutputvoltageiswithinitsregulationlimits.Alogiclowindicatesafaulthasoccurred(e.g. PG A2 O thermalshutdown,outputvoltageoutoflimits,currentlimittriggeredetc...).ThePGsignalisde- assertedautomaticallyoncetheICresumesproperoperation. VSELsignalisprimarilyusedtosettheoutputvoltagedc/dcboost,pass-throughthreshold.Thispin VSEL B1 I mustnotbeleftfloatingandmustbeterminated. AlogiclowlevelonthenBYPinputforcesthedeviceinpass-throughmode.Formoredetails,referto nBYP C1 I Table2.Thispinmustnotbeleftfloatingandmustbeterminated. Thisisthemodeselectionpinofthedevice.Thispinmustnotbeleftfloating,mustbeterminatedand canbeconnectedtoAGND.Duringstart-upthispinmustbeheldlow.Oncetheoutputvoltagesettled andPGpinindicatesthattheconverter'soutputvoltageiswithinitsregulationlimitsthedevicecanbe forcedinPWMmodeoperationbyapplyingahighlevelonthispin. MODE B2 I MODE=Low:Thedeviceisoperatinginregulatedfrequencypulsewidthmodulationmode(PWM)at high-loadcurrentsandinpulsefrequencymodulationmode(PFM)atlightloadcurrents.Thispin mustbeheldlowduringdevicestart-up. MODE=High:Low-noisemodeenabled,regulatedfrequencyPWMoperationforced. Inductorconnection.DrainoftheinternalpowerMOSFET.Connecttotheswitchedsideofthe SW C3,C4 I/O inductor. PGND D2,D3,D4 Powergroundpin. AGND C2,D1 Analoggroundpin.ThisisthesignalgroundreferencefortheIC. Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 9 Specifications 9.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MAX MIN UNIT VoltageatVOUT(2) DC –0.3 4.7 V VoltageatVIN(2),EN(2),VSEL(2),nBYP(2),PG(2), GPIO(2) DC –0.3 5.2 V VoltageatVIN(2) Transient:0.01%dutycycle -0.3 5.5 V operation Inputvoltage VoltageatSCL(2),SDA(2)MODE(2) DC –0.3 3.6 V DC –0.3 4.7 V VoltageatSW(2) Transient:2ns,2.3MHz –0.3 5.5 V DifferentialvoltagebetweenVINandVOUT DC –0.3 4 V ContinuousaveragecurrentintoSW (3) 1.8 A A Inputcurrent PeakcurrentintoSW (4) 5.5 A A Powerdissipation Internallylimited Operatingtemperaturerange,T (5) –40 85 °C A Temperaturerange Operatingvirtualjunction,T –40 150 °C J (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmyaffectdevicereliability. (2) Allvoltagesarewithrespecttonetworkgroundterminal. (3) Limitthejunctiontemperatureto105°Cforcontinuousoperationatmaximumoutputpower. (4) Limitthejunctiontemperatureto105°Cfor15%dutycycleoperation. (5) Inapplicationswherehighpowerdissipationand/orpoorpackagethermalresistanceispresent,themaximumambienttemperaturemay havetobederated.Maximumambienttemperature(T )isdependentonthemaximumoperatingjunctiontemperature(T ),the A(max) J(max) maximumpowerdissipationofthedeviceintheapplication(P ),andthejunction-to-ambientthermalresistanceofthepart/package D(max) intheapplication(θ ),asgivenbythefollowingequation:T =T –(θ XP ).Toachieveoptimumperformance,itis JA A(max) J(max) JA D(max) recommendedtooperatethedevicewithamaximumjunctiontemperatureof105°C. 9.2 Handling Ratings MIN MAX UNIT T Storagetemperature –65 150 °C stg range Humanbodymodel(HBM),perANSI/ESDA/JEDEC JS-001,allpins(1) –2000 2000 V V Electrostaticdischarge Chargeddevicemodel(CDM),perJEDEC ESD specificationJESD22-C101,allpins(2) –1000 1000 V MachineModel(MM) –200 200 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 9.3 Recommended Operating Conditions MIN NOM MAX UNIT Inputvoltagerange 2.30 4.85 V V I Inputvoltagerangeforin-situcustomizationbyE2PROMwriteoperation 3.4 3.5 3.6 V L Inductance 200 470 800 nH C Outputcapacitance 9 13 100 µF O I Maximumloadcurrentduringstart-up 250 mA L T Ambienttemperature –40 85 °C A T Operatingjunctiontemperature –40 125 °C J 6 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 9.4 Thermal Information TPS6128x THERMALMETRIC(1) UNIT YFF(16PINS) R Junction-to-ambientthermalresistance 78 θJA R Junction-to-case(top)thermalresistance 0.6 θJCtop R Junction-to-boardthermalresistance 13 θJB °C/W ψ Junction-to-topcharacterizationparameter 2.4 JT ψ Junction-to-boardcharacterizationparameter 13 JB R Junction-to-case(bottom)thermalresistance n/a θJCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 9.5 Electrical Characteristics MinimumandmaximumvaluesareatV =2.3Vto4.85V,V =3.4V(orV ,whicheverishigher),EN=1.8V,VSEL= IN OUT IN 1.8V,nBYP=1.8V,–40°C≤T ≤125°C;CircuitofParameterMeasurementInformationsection(unlessotherwisenoted). J TypicalvaluesareatV =3.2V,V =3.4V,EN=1.8V,T =25°C(unlessotherwisenoted). IN OUT J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT DC/DCboostmode.Devicenot switching,IOUT=0mA,VIN=3.2V, 47 65 µA VOUT=3.4V Pass-throughmode(auto) Operatingquiescentcurrent EN=1.8V,nBYP=1.8V, 27 42 µA intoVIN VIN=3.6V IQ TPS6128x PEaNs=s-t1h.r8oVu,gnhBmYoPd=eA(fGorNceDd,) –8450°C°C≤TJ≤ 15 25 µA VOUT=3.6V DC/DCboostmode.Devicenot Operatingquiescentcurrent intoVOUT sVwOUitcTh=in3g.,4IVOUT=0mA,VIN=3.2V, 8.5 19 µA EN=0V,nBYP=0V,VIN=3.6V 2.6 6 μA ISD Shutdowncurrent TPS6128x EN=0V,nBYP=1.8V,VIN=3.6V 8.5 20 μA Falling 2.0 2.1 V VUVLO Under-voltagelockoutthreshold TPS6128x Hysteresis 0.1 V EN,VSEL,nBYP,MODE,SDA,SCL,GPIO,PG VIL Low-levelinputvoltage 0.4 V TPS6128x VIH High-levelinputvoltage 1.2 V Low-leveloutputvoltage(SDA) IOL=8mA 0.3 V TPS61280 VOL Low-leveloutputvoltage(GPIO) IOL=8mA,GPIOCFG=0 0.3 V Low-leveloutputvoltage(PG) TPS6128x IOL=8mA 0.3 V EN,VSEL,nBYP, RPD pull-downresistance TPS6128x Input≤0.4V 300 kΩ EN,VSEL,nBYP,MODE,PG TPS6128x 9 pF CIN inputcapacitance InputconnectedtoAGNDorVIN SDA,SCL,GPIOinputcapacitance TPS61280 9 pF 0.95x RisingVOUT VOUT VTHPG Powergoodthreshold TPS6128x 0.9x FallingVOUT VOUT Ilkg Inputleakagecurrent TPS6128x InputconnectedtoAGND –40°C≤TJ≤ 0 µA InputconnectedVIN 85°C 0.5 µA Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com Electrical Characteristics (continued) MinimumandmaximumvaluesareatV =2.3Vto4.85V,V =3.4V(orV ,whicheverishigher),EN=1.8V,VSEL= IN OUT IN 1.8V,nBYP=1.8V,–40°C≤T ≤125°C;CircuitofParameterMeasurementInformationsection(unlessotherwisenoted). J TypicalvaluesareatV =3.2V,V =3.4V,EN=1.8V,T =25°C(unlessotherwisenoted). IN OUT J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OUTPUT VOUT(TH) ThresholdDCvoltageaccuracy TPS6128x Noload.Openloop -1.5% +1.5% 2.65V≤VIN≤VOUT_TH-150mV IOUT=0mA -2% +2% PWMoperation. VOUT RegulatedDCvoltageaccuracy TPS6128x 2.65V≤VIN≤VOUT_TH-150mV IOUT=0mA -2% +4% PFM/PWMoperation Power-savemode ΔVOUT outputripplevoltage TPS6128x PFMoperation,IOUT=1mA 30 mVpk PWMmodeoutputripplevoltage PWMoperation,IOUT=500mA 15 mVpk POWERSWITCH Low-sideswitchMOSFET onresistance VIN=3.2,VOUT=3.5V 45 80 mΩ High-siderectifierMOSFET rDS(on) onresistance TPS6128x VIN=3.2V,VOUT=3.5V 40 70 mΩ High-sidepass-throughMOSFET onresistance VIN=3.2V,VOUT=3.5V 35 60 mΩ ReverseleakagecurrentintoSW EN=AGND,VIN=VOUT=SW=3.5V 0.1 2 µA –40°C≤TJ≤85°C Ilkg TPS6128x EN=nBYP=VIN,VIN=2.9V,VOUT=4.4V,VSW=0V ReverseleakagecurrentintoVOUT devicenotswitching 0.11 2 µA –40°C≤TJ≤85°C ISINK VOUTsinkcapability TPS6128x EN=AGND,VOUT≤3.6V,IOUT=-10mA 0.3 V Valleyinductorcurrentlimit TPS61280 VIN=2.9V,VOUT=3.5V,–40°C≤TJ≤125°C,auto 2475 3000 3525 mA TPS61281 PFM/PWM Valleyinductorcurrentlimit TPS61282 VIN=2.9V,VOUT=3.5V,–40°C≤TJ≤125°C,auto 3300 4000 4700 mA PFM/PWM EN=nBYP=GND,VIN=3.2V 5000 mA Passthroughmodecurrentlimit TPS6128x EN=VIN,nBYP=don'tcare,VIN=3.2V 5600 7400 9100 mA Pre-chargemodecurrentlimit 500 650 mA (linearmode,phase1) TPS6128x VIN-VOUT≥300mV Pre-chargemodecurrentlimit 2000 mA (linearmode,phase2) OSCILLATOR fOSC Oscillatorfrequency TPS6128x VIN=2.7V,VOUT=3.5 2.3 MHz THERMALSHUTDOWN,HOTDIEDETECTOR Thermalshutdown(1) TPS6128x 140 160 °C Hotdiedetectoraccuracy(1) TPS61280 -10 105 +10 °C (1) Verifiedbycharacterization.Nottestedinproduction. 8 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 9.6 Timing Requirements MIN TYP MAX UNIT V =3.2V,VOUT_TH=01011 IN (3.4V),R =50Ω Start-uptime TPS6128x LOAD 500 µs TimefromactiveV toV IN OUT settled GPIOrisetime(1) TPS61280 200 ns (1) Specifiedbycharacterization.Nottestedinproduction. 9.7 I2C Interface Timing Characteristics(1) PARAMETER TESTCONDITIONS MIN MAX UNIT Standardmode 100 kHz Fastmode 400 kHz Fastmodeplus 1 MHz f SCLClockFrequency High-speedmode(writeoperation),C –100pFmax 3.4 MHz (SCL) B High-speedmode(readoperation),C –100pFmax 3.4 MHz B High-speedmode(writeoperation),C –400pFmax 1.7 MHz B High-speedmode(readoperation),C –400pFmax 1.7 MHz B Standardmode 4.7 μs BusFreeTimeBetweenaSTOPand t Fastmode 1.3 μs BUF STARTCondition Fastmodeplus 0.5 μs Standardmode 4 μs HoldTime(Repeated)START Fastmode 600 ns t ,t HD STA Condition Fastmodeplus 260 ns High-speedmode 160 ns Standardmode 4.7 μs Fastmode 1.3 μs t LOWPeriodoftheSCLClock Fastmodeplus 0.5 μs LOW High-speedmode,C –100pFmax 160 ns B High-speedmode,C –400pFmax 320 ns B Standardmode 4 μs Fastmode 600 ns t HIGHPeriodoftheSCLClock Fastmodeplus 260 ns HIGH High-speedmode,C –100pFmax 60 ns B High-speedmode,C –400pFmax 120 ns B Standardmode 4.7 μs SetupTimeforaRepeatedSTART Fastmode 600 ns t ,t SU STA Condition Fastmodeplus 260 ns High-speedmode 160 ns Standardmode 250 ns Fastmode 100 ns t ,t DataSetupTime SU DAT Fastmodeplus 50 ns High-speedmode 10 ns Standardmode 0 3.45 μs Fastmode 0 0.9 μs t ,t DataHoldTime Fastmodeplus 0 μs HD DAT High-speedmode,C –100pFmax 0 70 ns B High-speedmode,C –400pFmax 0 150 ns B (1) Specifiedbydesign.Nottestedinproduction. Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com I2C Interface Timing Characteristics(1) (continued) PARAMETER TESTCONDITIONS MIN MAX UNIT Standardmode 1000 ns Fastmode 20+0.1C 300 ns B t RiseTimeofSCLSignal Fastmodeplus 120 ns RCL High-speedmode,C –100pFmax 10 40 ns B High-speedmode,C –400pFmax 20 80 ns B Standardmode 20+0.1C 1000 ns B Fastmode 20+0.1C 300 ns RiseTimeofSCLSignalAftera B t RepeatedSTARTConditionandAfter Fastmodeplus 120 ns RCL1 anAcknowledgeBIT High-speedmode,C –100pFmax 10 80 ns B High-speedmode,C –400pFmax 20 160 ns B Standardmode 20+0.1C 300 ns B Fastmode 300 ns t FallTimeofSCLSignal Fastmodeplus 120 ns FCL High-speedmode,C –100pFmax 10 40 ns B High-speedmode,C –400pFmax 20 80 ns B Standardmode 1000 ns Fastmode 20+0.1C 300 ns B t RiseTimeofSDASignal Fastmodeplus 120 ns RDA High-speedmode,C –100pFmax 10 80 ns B High-speedmode,C –400pFmax 20 160 ns B Standardmode 300 ns Fastmode 20+0.1C 300 ns B t FallTimeofSDASignal Fastmodeplus 120 ns FDA High-speedmode,C –100pFmax 10 80 ns B High-speedmode,C –400pFmax 20 160 ns B Standardmode 4 μs Fastmode 600 ns t t SetupTimeofSTOPCondition SU, STO Fastmodeplus 260 ns High-Speedmode 160 ns Standardmode 400 pF Fastmode 400 pF C CapacitiveLoadforSDAandSCL B Fastmodeplus 550 pF High-Speedmode 400 pF 10 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 SDA tf tLOW tr tsu;DAT tf thd;STA tr tBUF SCL thd;STA tsu;STA tsu;STO S thd;DAT HIGH Sr P S Figure1. SerialInterfaceTimingDiagramforStandard-,Fast-,Fast-ModePlus Sr Sr P tfDA trDA SDAH thd;DAT tsu;STO tsu;STA thd;STA tsu;DAT SCLH tfCL trCL1 trCL trCL1 See Note A tHIGH tLOW tLOW tHIGH See Note A = MCS Current Source Pull-Up = R(P) Resistor Pull-Up Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit. Figure2. SerialInterfaceTimingDiagramforH/S-Mode Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 9.8 Typical Characteristics 50 70 48 65 (cid:13) (cid:12)46 (cid:13) (cid:12) m m60 e (44 e ( anc42 anc55 esist40 esist50 R R On 38 On 45 ET 36 ET F F40 S 34 S H L 35 32 30 30 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Junction Temperature (ƒC) C001 Junction Temperature (ƒC) C002 V =3.2V V =3.5V T =–40to125°C V =3.2V V =3.5V T =–40to125°C IN OUT J IN OUT J Figure3.HighsideR vsJunctionTemperature Figure4.LowsideR vsJunctionTemperature ds(on) ds(on) 50 60 48 (cid:13) (cid:12)46 A) nce (m44 oost (µ50 a42 B n Resist3480 Current_ FET O36 scent 40 TJ =T 3j=02°C5C LS 34 Quie TJ =T -j=4-04°C0 32 TJ =T 8j=58°C5C 30 30 -40 -20 0 20 40 60 80 100 120 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 Junction Temperature (ƒC) C003 Input Voltage (V) C004 V =3.2V Bypass T =–40to125°C V =2.3-3.4V V =3.4V I =0mA IN J IN OUT OUT EN=High Bypass=High Figure5.BypassFETR vsJunctionTemperature Figure6.QuiescentCurrentatBoostModevsInputVoltage ds(on) 20 35 Bypass (µA) 18 Bypass (µA) 233913 Quiescent Current_Force 111246 TTTJJJ = ==TTT jjj-83===45028-04°°55C°CC0CC Quiescent Current_Auto 112222791357 TTTJJJ TTT ===jjj ===-83428-504055°°C0C°CCC 10 15 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 Input Voltage (V) C005 Input Voltage (V) C006 V =2.3-4.8V V =3.4V I =0mA V =3.4-4.8V V =3.4V I =0mA IN OUT OUT IN OUT OUT EN=High Bypass=Low EN=High Bypass=High Figure7.QuiescentCurrentatForcedBypassModevs Figure8.QuiescentCurrentatAutoBypassModevsInput InputVoltage Voltage 12 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 Typical Characteristics (continued) 5 13 12 µA) 4 µA) 11 w Iq ( w Iq ( 10 Lo 3 Lo 9 _ _ nt nt 8 e e Curr 2 Curr 7 kage TJ =T j3=02°C5C kage 6 TJ =T j3=02°5CC a 1 a 5 Le TJ =T j-=4-04°C0 Le TJ =T j-=4-04°0C 4 TJ =T j8=58°C5C TJ =T j8=58°5CC 0 3 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V) C007 Input Voltage (V) C008 V =2.3-4.8V V =4.4V V =0V V =2.3-4.8V V =4.4V V =0V IN OUT SW IN OUT SW EN=Low Bypass=Low EN=Low Bypass=High Figure9.ShutdownCurrentatLowI ModevsInputVoltage Figure10.ShutdownCurrentvsInputVoltage Q 4.5 2.20 A) ent Limit (34..50 shold (V) Curr Thre2.00 alley 3.0 VLO V U h n Switc2.5 TPS61281 Vi VViINn RRiissiinngg TPS61282 VVin FFaalllliinngg IN 2.0 1.80 -40 10 60 110 -40 -20 0 20 40 60 80 100 120 Temperature (ƒC) C009 Junction Temperature (ƒC) C010 V =3.2V V =3.5V T =–40to125°C V =3.2V V =3.5V T =–40to125°C IN OUT J IN OUT J EN=High Bypass=High Figure11.SwitchValleyCurrentLimit:TPS61281,TPS61282 Figure12.V UVLOThresholdRising/FallingvsJunction IN vsInputVoltage Temperature 1.10 1.10 EN Rising nBYP Rising 1.00 EN Falling 1.00 nBYP Falling V) V) d (0.90 d (0.90 ol ol h h s s e e hr0.80 hr0.80 T T c c gi gi o0.70 o0.70 L L N N E E 0.60 0.60 0.50 0.50 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Junction Temperature (ƒC) C011 Junction Temperature (ƒC) C012 V =3.2V V =3.5V T =–40to125°C V =3.2V T =–40to125°C IN OUT J IN J Figure13.ENLogicHighThresholdRising/Fallingvs Figure14.BYPLogicHighThresholdRising/Fallingvs JunctionTemperature JunctionTemperature Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10 Detailed Description 10.1 Overview TheTPS6128xisahigh-efficiencystep-upconverterfeaturingpass-throughmodeoptimizedtoprovidelow-noise voltage supply for 2G RF power amplifiers (PAs) in mobile phones and/or to pre-regulate voltage for supplying subsystem like eMMC memory, audio codec, LCD bias, antenna switches, RF engine PMIC etc. It is designed to allow the system to operate at maximum efficiency for a wide range of power consumption levels from a low-, wide-voltagebatterycell. The capability of the TPS6128x to step-up the voltage as well as to pass-through the input battery voltage when itslevelishighenoughallowsystemstooperateatmaximumperformanceoverawiderangeofbatteryvoltages, thereby extending the battery life between charging. The device also addresses brownouts caused by the peak currents drawn by the APU and GPU which can cause the battery rail to droop momentarily. Using the TPS6128x device as a pre-regulator eliminates system brownout condition while maintaining a stable supply rail forcriticalsub-systemtofunctionproperly. The TPS6128x synchronous step-up converter typically operates at a quasi-constant 2.3-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6128x converter operatesinpower-savemodewithpulsefrequencymodulation(PFM). In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain amount above the input voltage. The TPS6128x device operates differently as it can smoothly transition in and out of zero duty cycle operation. Depending upon the input voltage, output voltage threshold and load current, the integrated bypass switch automatically transitions the converter into pass-through mode to maintain low- dropout and high-efficiency. The device exits pass-through mode (0% duty cycle operation) if the total dropout resistance in bypass mode is insufficient to maintain the output voltage at it's nominal level. Refer to the typical characteristicssection(DCOutputVoltagevs.InputVoltage)forfurtherdetails. DuringPWMoperation,theconverterusesanovelquasi-constanton-timevalleycurrentmodecontrolschemeto achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on the V /V ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low- IN OUT side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on- time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on timeragainandactivatingthelow-sideN-MOSswitch. The current mode architecture provides excellent transient load response, requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while minimizing the number of external components. The TPS6128x directly and accurately controls the average input current through intelligent adjustment of the valley current limit, allowing an accuracy of ±17.5%. Together with an external bulk capacitor, the TPS6268x allows an application to be interfaced directly to its load, without overloading the input source due to appropriate set average input current limit. An open-drain output (PG or GPIO/nFAULT) provides a signal to issue an interrupt to the system if any fault is detected on the device (thermal shutdown, output voltage out-of limits etc...). The output voltage can be dynamically adjusted between two values (floor and roof voltages) by toggling a logic control input (VSEL) without the need for external feedback resistors. This features can either be used to raise the output voltage in anticipation of a positive load transient or to dynamically change the PA supply voltage dependingonitsmodeofoperationand/ortransmittingpower. The TPS61280 integrates an I2C compatible interface allowing transfers up to 3.4Mbps. This communication interface can be used to set the output voltage threshold at which the converter transitions between boost and pass-through mode, for reprogramming the mode of operation (PFM/PWM or forced PWM), for settings the averageinputcurrentlimitorresettingtheoutputvoltageforinstance. Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the E2PROMCTRL Register, it is possible to store the active configuration in non-volatile E2PROM; during power-up, thecontentsoftheE2PROMarecopiedintotheI2Cregistersandusedtoconfigurethedevice. 14 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 10.2 Functional Block Diagram SW SW VIN VIN Band-gap VIN Bias Supply UnTLdhoeecrrvkmoolautaltge CVoMnAtrXol revirDetaG NMOS ControlVMAX VOUT Shutdown NMOS PMOS VOUT Gate Valley Driver Current Sense VIN VOUT Averaging Error Pulse Width Amplifier Modulator Control Logic gm Start-Up V Control REF SCL MODE ol I/F Control GPIO: RESET(I) / FAULT(O) ntr Logic PG o SDA C EN nBYP VSEL PGND PGND PGND AGND Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.3 Feature Description 10.3.1 VoltageScalingManagement(VSEL) In order to maintain a certain minimum output voltage under heavy load transients, the output voltage set point can be dynamically increased by asserting the VSEL input. The functionality also helps to mitigate undershoot during severe line transients, while minimizing the output voltage during more benign operating conditions to savepower. Theoutputvoltagerampsup(floortorooftransition)atpre-definedratedefinedbytheaverageinputcurrentlimit setting. The required time to ramp down the voltage (roof to floor transition) largely depends on the amount of capacitance present at the converter's output as well as on the load current. Table 1 shows the ramp rate control whentransitioningtoalowervoltage. Table1.RampDownRatevs.TargetMode ModeAssociatedwithFloorVoltage OutputVoltageRampRate ForcedPWM Outputcapacitanceisbeingdischargedatarateofapprox.50mA(orhigher)constantcurrent inadditiontotheloadcurrentdrawn PFM Outputcapacitanceisbeingdischarged(solely)bytheloadcurrentdrawn 10.3.2 SpreadSpectrum,PWMFrequencydithering ThegoalistospreadouttheemittedRFenergyoveralargerfrequencyrangesothattheresultingEMIissimilar to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that isfocusedonspecificfrequencies. Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or regulated, based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency(harmonics). Thespreadspectrumarchitecturevariestheswitchingfrequencybyca. ±15%ofthenominalswitchingfrequency thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The frequencyditheringschemeismodulatedwithatriangleprofileandamodulationfrequencyf . m 0 dBV FENV,PEAK Dfc Dfc Non-modulated harmonic F1 Side-band harmonics window after modulation 0 dBVref B=2×f ×(1+m )=2×(Df +f ) m f c m B=2×f ×(1+m )=2×(Df +f ) B =2×f ×(1+m ×h) m f c m h m f Figure15.SpectrumofaFrequencyModulated Figure16.SpreadBandsofHarmonicsin Sin.WavewithSinusoidalVariationinTime ModulatedSquareSignals (1) The above figures show that after modulation the sideband harmonic is attenuated compared to the non- modulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the modulationindex(mf)thelargertheattenuation. (1) Spectrumillustrationsandformulae(Figure15andFigure16)copyrightIEEETRANSACTIONSONELECTROMAGNETIC COMPATIBILITY,VOL.47,NO.3,AUGUST2005. 16 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 δ ´ ƒ m = c ƒ ƒ m where • f isthecarrierfrequency(approx.2.3MHz) c • f isthemodulatingfrequency(approx.40kHz) m • δisthemodulationratio(approx0.15) (1) Dƒ d= c ƒ c (2) The maximum switching frequency f is limited by the process and finally the parameter modulation ratio (δ), c together with f , which is the side-band harmonics bandwidth around the carrier frequency f . The bandwidth of m c afrequencymodulatedwaveformisapproximatelygivenbytheCarson’sruleandcanbesummarizedas: B=2 ´ ¦m ´(1+ m¦)=2 ´ (D¦c + ¦m) (3) f < RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are m addedintheinputfilterandthemeasuredvalueishigherthanexpectedintheoreticalcalculations. f > RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the m measurementsmatchwiththetheoreticalcalculations. Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.4 Device Functional Modes 10.4.1 Power-SaveMode The TPS6128x integrates a power-save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFMmode. Figure17. Power-SaveModeRipple 10.4.2 Pass-ThroughMode The TPS6128xA contains an internal switch for bypassing the dc/dc boost converter during pass-through mode. When the input voltage is larger than the preset output voltage, the converter seamlessly transitions into 0% duty cycle operation and the bypass FET is fully enhanced. Entry in pass-through mode is triggered by condition whereVOUT >VOUT_NORMandnoswitchinghasoccurredduringpast16μs. In this mode of operation, the load (2G RF PA for instance) is directly supplied from the battery for maximum RF output power, highest efficiency and lowest possible input-to-output voltage difference. The device consumes only a standby current of 15µA (typ). In pass-through mode, the device is short-circuit protected by a very fast currentlimitdetectionscheme. During this operation, the output voltage follows the input voltage and will not fall below the programmed output voltagethresholdastheinputvoltagedecreases.Theoutputvoltagedropduringpass-throughmodedependson theloadcurrentandinputvoltage,theresultingoutputvoltageiscalculatedas: V = V -(R x I ) OUT IN DSON(BP) OUT (4) Conversely,theefficiencyinpass-throughmodeisdefinedas: I η=1-R OUT DSON(BP) V IN (5) inwhichR isthetypicalon-resistanceofthebypassFET DSON(BP) 18 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 Device Functional Modes (continued) 4.5 4.4 4.3 4.2 4.1 4 V) Output Voltage ( 3333....6789 3.5 3.4 3.3 Vout_nom = 3.15V 3.2 Vout_nom = 3.35V Vout_nom = 3.3V 3.1 Vout_nom = 3.5V 3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V) G000 Figure18. DCOutputVoltagevs.InputVoltage Pass-throughmodeexitistriggeredwhentheoutputvoltagereachesthepre-definedthreshold(e.g.3.4V). During pass-through mode, the TPS6128x device is short-circuit protected by a very fast current limit detection scheme. If the current in the pass-through FET exceeds approximately 7.3Amps a fault is declared and the devicecyclesthroughastart-upprocedure. 10.4.3 ModeSelection Depending on the settings of CONFIG Register the device can be operated at a quasi-constant 2.3-MHz frequency PWM mode or in automatic PFM/PWM mode. In this mode, the converter operates in pseudo-fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiencyoverawideloadcurrentrange.Formoredetails,seetheCONFIGRegister description. The quasi-constant frequency PWM mode has the tightest regulation and the best line/load transient performance. In forced PWM mode, the device features a unique R management function to maintain high DS(ON) broadbandefficiencyaswellaslowresistanceinpass-throughmode. In the TPS61280 device, the GPIO pin can be configured (via the CONFIG Register) to select the operating mode of the device. In the other TPS6128x devices, the MODE pin is used to select the operating mode. Pulling this pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the converter modulates its switching frequency according to a spread spectrum PWM modulation technique allowingsimplefilteringoftheswitchingharmonicsinnoise-sensitiveapplications. For additional flexibility, it is possible to switch from power-save mode (GPIO or MODE input = L) to PWM mode (GPIO or MODE input = H) during operation. This allows efficient power management by adjusting the operation oftheconvertertothespecificsystemrequirements(e.g.2GRFPARx/Txoperation). NOTE During start-up (conventionally or when recovering from thermal shutdown) the device must be set to operate with auto PFM/PWM mode. Consequently, the device determines automaticallyPFMorPWMmodedependingontheoutput'sload.Oncetheoutputvoltage settled and PG pin indicates that the converter's output voltage is within its regulation limits,thedevicecanbeforcedinPWMmodeoperation,ifdesired. Entry to forced pass-through mode (nBYP = L) initiates with a current limited transition followed by a true bypass state. To prevent reverse current to the battery, the devices waits until the output discharges below the input voltage level before entering forced pass-through mode. Care should be taken to prohibit the output voltage from collapsing whilst transitioning into forced pass-through mode under heavy load conditions and/or limited output capacitance. This can be easily done by adding capacitance to the output of the converter. In forced pass- throughmode,theoutputfollowstheinputbelowthepresetoutputthresholdvoltage(VOUT_TH). Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com Device Functional Modes (continued) 10.4.4 CurrentLimitOperation TheTPS6128xdevicefeaturesavalleyinductorcurrentlimitscheme. In dc/dc boost mode, the TPS6128x device employs a current limit detection scheme in which the voltage drop across the synchronous rectifier is sensed during the off-time. In the TPS61280 the current limit threshold can be set via an I2C register. TPS6128x devices have a fixed current limit threshold. See the Device Comparison Table fordetailedinformation. The output voltage is reduced as the power stage of the device operates in a constant current mode. The maximum continuous output current (I ), before entering current limit (CL) operation, can be defined by OUT(MAX) Equation6. V I = I ´ IN ´ h O U T(M A X _D C) LIM IT V O U T (6) Whereη istheefficiency Theinductorpeak-to-peakcurrentripple(ΔI )iscalculatedbyEquation7 L V D DI = IN ´ L L f (7) The output current, I , is the average of the rectifier ripple current waveform. When the load current is OUT(DC) increasedsuchthatthetroughisabovethecurrentlimitthreshold,theoff-timeisincreasedtoallowthecurrentto decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When the currentlimitisreachedtheoutputvoltagedecreasesduringfurtherloadincrease. Figure19illustratestheinductorandrectifiercurrentwaveformsduringcurrentlimitoperation. IPEAK IL CTuhrrreensth Loilmdit IVALLEY Rectifier Current DIL IOUT IOUT(DC) Increased Load Current IIN(DC) f Inductor Current IIN(DC) DIL ΔIL=VIN×D L f Figure19. Inductor/RectifierCurrentsinCurrentLimitOperation(DC/DCBoostMode) During pass-through mode, the TPS6128x device is short-circuit protected by a very fast current limit detection scheme. If the current in the bypass FET exceeds approximately 7.5Amps a fault is declared and the device cyclesthroughastart-upprocedure. 10.4.5 Start-UpandShutdownMode The TPS6128x automatically powers-up as soon as the input voltage is applied. The device has an internal soft- start circuit that limits the inrush current during start-up. The first phase in the start-up procedure is to bias the outputnodeclosetotheinputlevel(socalledpre-chargephase). 20 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 Device Functional Modes (continued) In this operating mode, the device limits its output current to ca. 500mA. Should the output voltage not have reached the input level within a maximum duration of 750µs, the device automatically increases its pre-charge current to ca. 2000mA. If the output voltage still fails to reach its target after 1.5ms, a fault condition is declared. Afterwaiting1ms,arestartisattempted. Duringstart-up,itisrecommendedtokeepDCloadcurrentdrawbelow250mA. TheTPS6128xdevicecontainsathermalregulationloopthatmonitorsthedietemperatureduringthepre-charge phase. If the die temperature rises to high values of about 110°C, the device automatically reduces the current to prevent the die temperature from increasing further. Once the die temperature drops about 10°C below the threshold, the device will automatically increase the current to the target value. This function also reduces the currentduringashort-circuitcondition. When the EN and nBYP pins are set high, the device enters normal operation (i.e. automatic dc/dc boost, pass- throughmode)andensuresthattheoutputvoltageremainsaboveapre-definedthreshold(e.g.3.3V). Setting the EN pin low (nBYP = 1) forces the TPS6128x device in shutdown mode with a current consumption of <8.5µA typ. In this mode, the output of the converter is regulated to a minimum level so as to limit the input-to- output voltage difference to less than 3.6V (typ). The device is capable of sinking up to 10mA output current and prohibits reverse current flow from the output to the input. For proper operation, the EN pin must be terminated andmustnotbeleftfloating. Changing operating mode from auto mode (EN = nBYP = 1) to low I Pass-through mode (EN = nBYP = 0) with Q device pins EN and nBYP can either be done controlling EN and nBYP pins from same control signal (delay between signal < 60ns) or first switching in forced pass-through mode (EN = 1, nBYP = 0) followed by switching tolowI Pass-throughmode(EN=nBYP=0). Q The TPS6128x device also features the possibility of shutting the converter's output for a short period of time, either via the nRST/nFAULT (GPIO). Pulling this input low initiates a reset of the converter's output. The sequence is falling edge-triggered and consists of a discharge phase (down to ca. 600mV or lower) of the capacitancelocatedattheconverter'soutputfollowedbyastart-upphase. Table2.ModeofOperation ENInput nBYPInput DeviceState Thedeviceisshutdowninpass-throughmodefeaturingashutdowncurrentdowntoca.2µAtyp. 0 0 Theloadcurrentcapabilityislimited(uptoca.250mA). Thedeviceisshutdownandtheoutputvoltageisreducedtoaminimumvalue(VIN-VOUT≤3.6V). 0 1 Thedeviceshutdowncurrentisapproximately8.5µAtyp. Thedeviceisactiveinforcedpass-throughmode. 1 0 Thedevicesupplycurrentisapproximately15µAtyp.fromthebattery.Thedeviceisshortcircuitprotected byacurrentlimitofca.7300mA. Thedeviceisactiveinautomode(dc/dcboost,pass-through). 1 1 Thedevicesupplycurrentisapproximately50µAtyp.fromthebattery. 10.4.6 UndervoltageLockout The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery from excessive discharge. The I2C control interface and the output stage of the converter are disabled once the falling V trips the under-voltage lockout threshold V (2.0V typ). The device starts operation once the rising IN UVLO V tripsV thresholdplusitshysteresisof100mVattyp.2.1V. IN UVLO 10.4.7 ThermalShutdown As soon as the junction temperature, T , exceeds 150°C (typ.) the device goes into thermal shutdown. In this J mode the bypass, high-side and low-side MOSFETs are turned-off. When the junction temperature falls below thethermalshutdownminusitshysteresis,thedevicecontinuoustheoperation. Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.4.8 FaultStateandPower-Good TheTPS6128xentersthefaultstateunderanyofthefollowingsconditions: • Theoutputvoltagefailstoachievetherequiredlevelduringastart-upphase. • Theoutputvoltagefallsoutofregulation(inpre-chargemode). • Thedevicehasenteredthermalshutdown. Once a fault is triggered, the regulator stops operating and disconnects the load. After waiting 1ms, the device attempts to restart. The TPS61280 device can be configured to signal a fault condition by pulling the open-drain GPIO pin (nFAULT) low for a short period of time. The nFAULT output provides a falling edge triggered interrupt signal to the host. To ensure proper operation, the GPIO port needs to be pull high quick enough, i.e. faster than ca.200ns.Todoso,itisrecommendedtouseaGPIOpull-upresistorintherangeof1kΩ to10kΩ. The TPS6128x (simple logic I/F version) device only provide a power-good output (PG) for signaling the system when the regulator has successfully completed start-up and no faults have occurred. Power-good also functions asanearlywarningflagforexcessivedietemperatureandoverloadconditions. • PGisassertedhighwhenthestart-upsequenceissuccessfullycompleted. • PG is pulled low when the output voltage falls approx. 10% below its regulation level or the die temperature exceeds115°C.PGisre-assertedhighwhenthedevicecoolsbelowca.100°C. • AnyfaultconditioncausesPGtobede-asserted. • PGispulledhighwhenthedeviceisoperatinginforcedpass-throughmode(i.e.nBYP=L). • PGispulledhighwhenthedeviceisinshutdownmode. 22 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 10.5 Programming 10.5.1 SerialInterfaceDescription(TPS61280) I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull- up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slavedevicereceivesand/ortransmitsdataonthebusundercontrolofthemasterdevice. The TPS6128x device works as a slave and supports the following data transfer modes, as defined in the I2C- BusSpecification:standardmode(100kbps)andfastmode(400kbps),fastmodeplus(1Mbps)andhigh-speed mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intactaslongassupplyvoltageremainsabove2.1V. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-mode. The TPS6128xA device supports 7-bit addressing; 10-bit addressing and general call address are not supported.Thedevice7bitaddressisdefinedas‘1110101’. It is recommended that the I2C masters initiates a STOP condition on the I2C bus after the initial power up of SDAandSCLpull-upvoltagestoensureresetoftheTPS6128xI2Cengine. 10.5.2 Standard-,Fast-,Fast-ModePlusProtocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 20. All I2C-compatible devices should recognizeastartcondition. DATA CLK S P STARTCondition STOPCondition Figure20. STARTandSTOPConditions The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 21). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 22) by pulling the SDA line low during the entire high periodoftheninthSCLcycle.Upondetectingthisacknowledge,themasterknowsthatcommunicationlinkwitha slavehasbeenestablished. DATA CLK Data line Change stable; of data data valid allowed Figure21. BitTransferontheSerialInterface Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com Programming (continued) The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 20). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. Attemptingtoreaddatafromregisteraddressesnotlistedinthissectionwillresultin00hbeingreadout. Figure22. AcknowledgeontheI2CBus Figure23. BusProtocol 24 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 Programming (continued) 10.5.3 HS-ModeProtocol The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS mastercode,butalldevicesmustrecognizeitandswitchtheirinternalsettingtosupport3.4Mbpsoperation. Themasterthengeneratesarepeatedstartcondition(arepeatedstartconditionhasthesametimingasthestart condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be usedtosecurethebusinHS-mode. Attemptingtoreaddatafromregisteraddressesnotlistedinthissectionwillresultin00hbeingreadout. 10.5.4 TPS6128xI2CUpdateSequence The TPS6128xA requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS6128x device acknowledges by pulling the SDA line low during thehighperiodofasingleclockpulse.AvalidI2CaddressselectstheTPS6128x.TPS6128xperformsanupdate onthefallingedgeoftheacknowledgesignalthatfollowstheLSBbyte. 1 7 1 1 8 1 8 1 1 S SlaveAddress R/W A RegisterAddress A Data A/A P “0”Write A =Acknowledge (SDAlow) From Master toTPS6128x A =Not acknowledge (SDAhigh) S =STARTcondition Sr =REPEATED STARTcondition FromTPS6128x to Master P =STOPcondition Figure24. :“Write”DataTransferFormatinStandard-,Fast,Fast-PlusModes 1 7 1 1 8 1 1 7 1 1 8 1 1 S SlaveAddress R/W A RegisterAddress A Sr SlaveAddress R/W A Data A/A P “0”Write “1”Read A =Acknowledge (SDAlow) From Master toTPS6128x A =Not acknowledge (SDAhigh) S =STARTcondition FromTPS6128x to Master Sr =REPEATED STARTcondition P =STOPcondition Figure25. “Read”DataTransferFormatinStandard-,Fast,Fast-PlusModes F/S Mode HS Mode F/S Mode 1 8 1 1 7 1 1 8 1 8 1 1 S HS-Master Code A Sr SlaveAddress R/W A RegisterAddress A Data A/A P DataTransferred (n x Bytes+Acknowledge) HS Mode Continues Sr SlaveAddress A =Acknowledge (SDAlow) From Master toTPS6128x A =Not acknowledge (SDAhigh) S =STARTcondition FromTPS6128x to Master Sr =REPEATED STARTcondition P =STOPcondition Figure26. DataTransferFormatinH/S-Mode Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.6 Register Maps 10.6.1 SlaveAddressByte MSB LSB 1 1 1 0 1 A1 A0 TheslaveaddressbyteisthefirstbytereceivedfollowingtheSTARTconditionfromthemasterdevice. 10.6.2 RegisterAddressByte MSB LSB 0 0 0 0 0 D2 D1 D0 Following the successful acknowledgment of the slave address, the bus master will send a byte to the TPS6128xA,whichwillcontaintheaddressoftheregistertobeaccessed. 10.6.3 I2CRegisters,E2PROM,WriteProtect Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the E2PROMCTRL Register, it is possible to store the active configuration in non-volatile E2PROM; during power-up, thecontentsoftheE2PROMarecopiedintotheI2Cregistersandusedtoconfigurethedevice. NOTE An active high Write Protect (WP) bit prevents the configuration parameters from being changed by accident. Once the E2PROM memory has been programmed with Write Protect(WP)bitset,itscontentwillbelockedandcannotbereprogrammedanymore. Configuration parameters can be read from the I2C register(s) or E2PROM registers at any time (the WP bit has noeffectonreadoperations). 10.6.4 E2PROMConfigurationParameters Table3showsthememorymapoftheconfigurationparameters. Table3.ConfigurationMemoryMap Register Factory RegisterName Description Address Default 01h CONFIGRegister xxh Setsmiscellaneousconfigurationbits Setstheflooroutputvoltagethresholdboost/pass-throughmodechange 02h VOUTFLOORSETRegister xxh (VSEL=L) Setstheroofoutputvoltagethresholdboost/pass-throughmodechange 03h VOUTROOFSETRegister xxh (VSEL=H) 04h ILIMSETRegister xxh Setstheaverageinputcurrentlimitindc/dcboostmode 05h StatusRegister xxh Returnsstatusflags Controlswhetherreadandwriteoperationsaccess FFh E2PROMCTRLRegister 00h I2CorE2PROMregisters 26 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 The following procedure details how to save the content of all I2C registers to the E2PROM non-volatile configurationmemory. 1. BusmastersendsSTARTcondition 2. Busmastersends7-bitslaveaddresspluslowR/Wbit(forexampleEAh) 3. TPS6128xacknowledges(SDAlow) 4. BusmastersendsaddressofE2PROMCTRLRegister(FFh) 5. TPS6128xacknowledges(SDAlow) 6. BusmastersendsdatatobewrittentotheControlRegister(C0h) 7. TPS6128xacknowledges(SDAlow) 8. BusmastersendsSTOPcondition S 7-Bit SlaveAddress 0 A Control RegisterAddress A Control Register Data A P EAh FFh C0h Figure27. SavingContentsofallI2CRegisterstoE2PROM Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.6.5 CONFIGRegister Memorylocation:0x01 Description RESET ENABLE RESERVED GPIOCFG SSFM MODE_CTRL Bits D7 D6 D5 D4 D3 D2 D1 D0 Memorytype R/W R/W R/W R/W R/W R/W R/W R/W Defaultvalue 0 0 0 0 0 0 0 1 Storedin E2PROM? N Y Y N Y Y Y Y Bit Description RESET Deviceresetbit. 0:Normaloperation. 1:Defaultvaluesaresettoallinternalregisters.Thedeviceoperationiscycled(ON-OFF-ON),thatis,theconverter isdisabledforashortperiodoftimeandtheoutputisreset. ENABLE[1:0] Deviceenablebits. 00:Deviceoperationfollowshardwarecontrolsignal(refertoTable2). 01:Deviceoperatesinautotransitionmode(dc/dcboost,bypass)regardlessofthenBYPcontrolsignal(EN=1). 10:Deviceisforcedinpass-throughmoderegardlessofthenBYPcontrolsignal(EN=1). 11:Deviceisinshutdownmode.Theoutputvoltageisreducedtoaminimumvalue(VIN-VOUT≤3.6V) regardlessofthenBYPcontrolsignal(EN=1). RESERVED Reservedbit. Thisbitsisreservedforfutureuse.Duringwriteoperationsdataintendedforthisbitisignored,andduringread operations0isreturned. GPIOCFG GPIOportconfigurationbit. 0:GPIOportisconfiguredtosupportmanualresetinput(nRST)andinterruptgenerationoutput(nFAULT). 1:GPIOportisconfiguredasadevicemodeselectioninput. SSFM Spreadmodulationcontrol. 0:Spreadspectrummodulationisdisabled. 1:SpreadspectrummodulationisenabledinPWMmode. MODE_CTRL[1:0] Devicemodeofoperationbits. 00:Deviceoperationfollowshardwarecontrolsignal(GPIOmustbeconfiguredasmodeselectioninput). 01:PFMwithautomatictransitionintoPWMoperation. 10:ForcedPWMoperation. 11:PFMwithautomatictransitionintoPWMoperation(VSEL=L),forcedPWMoperation(VSEL=H). 28 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 10.6.6 VOUTFLOORSETRegister Memorylocation:0x02 Description RESERVED RESERVED RESERVED VOUTFLOOR_TH Bits D7 D6 D5 D4 D3 D2 D1 D0 Memorytype R/W R/W R/W R/W R/W R/W R/W R/W Defaultvalue 0 0 0 0 0 1 1 0 Storedin E2PROM? N N N Y Y Y Y Y Bit Description RESERVED Reservedbit. Thisbitsisreservedforfutureuse.Duringwriteoperationsdataintendedforthisbitisignored,andduring readoperations0isreturned. VOUTFLOOR_TH[4:0] Outputvoltagethreshold,dc/dcboost/pass-throughmodechange. 00000:2.850V 00001:2.900V 00010:2.950V 00011:3.000V 00100:3.050V 00101:3.100V 00110:3.150V 00111:3.200V 01000:3.250V 01001:3.300V 01010:3.350V 01011:3.400V 01100:3.450V 01101:3.500V 01110:3.550V 01111:3.600V 10000:3.650V 10001:3.700V 10010:3.750V 10011:3.800V 10100:3.850V 10101:3.900V 10110:3.950V 10111:4.000V 11000:4.050V 11001:4.100V 11010:4.150V 11011:4.200V 11100:4.250V 11101:4.300V 11110:4.350V 11111:4.400V Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.6.7 VOUTROOFSETRegister Memorylocation:0x03 Description RESERVED RESERVED RESERVED VOUTROOF_TH Bits D7 D6 D5 D4 D3 D2 D1 D0 Memorytype R/W R/W R/W R/W R/W R/W R/W R/W Defaultvalue 0 0 0 0 1 0 1 0 Storedin E2PROM? N N N Y Y Y Y Y Bit Description RESERVED Reservedbit. Thisbitsisreservedforfutureuse.Duringwriteoperationsdataintendedforthisbitisignored,andduring readoperations0isreturned. VOUTROOF_TH[4:0] Outputvoltagethreshold,dc/dcboost/pass-throughmodechange. 00000:2.850V 00001:2.900V 00010:2.950V 00011:3.000V 00100:3.050V 00101:3.100V 00110:3.150V 00111:3.200V 01000:3.250V 01001:3.300V 01010:3.350V 01011:3.400V 01100:3.450V 01101:3.500V 01110:3.550V 01111:3.600V 10000:3.650V 10001:3.700V 10010:3.750V 10011:3.800V 10100:3.850V 10101:3.900V 10110:3.950V 10111:4.000V 11000:4.050V 11001:4.100V 11010:4.150V 11011:4.200V 11100:4.250V 11101:4.300V 11110:4.350V 11111:4.400V 30 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 10.6.8 ILIMSETRegister Memorylocation:0x04 Description RESERVED RESERVED ILIMOFF Soft-start ILIM Bits D7 D6 D5 D4 D3 D2 D1 D0 Memorytype R/W R/W R/W R/W R/W R/W R/W R/W Defaultvalue 0 0 0 1 1 0 1 1 Storedin E2PROM? N N N Y Y Y Y Y Bit Description RESERVED Reservedbit. Thisbitsisreservedforfutureuse.Duringwriteoperationsdataintendedforthisbitisignored,andduringread operations0isreturned. ILIM[3:0] Inductorvalleycurrentlimitindc/dcboostmode(COUTRNGbit=0)(1). 1000:1500mA 1001:2000mA 1010:2500mA 1011:3000mA 1100:3500mA 1101:4000mA 1110:4500mA 1111:5000mA Soft-Start Soft-startselectionbit. 0:DC/DCboostsoft-startcurrentislimitedperILIMbitsettings 1:DC/DCboostsoft-startcurrentislimitedtoca.1250mAinductorvalleycurrent ILIMOFF Enable/DisableCurrentLimit 0:CurrentLimitEnabled 1:CurrentLimitDisabled (1) RefertotheStart-UpandShutdownModesectionforadditionalinformation. Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 10.6.9 StatusRegister Memorylocation:0x05 Description TSD HOTDIE DCDCMODE OPMODE ILIMPT ILIMBST FAULT PGOOD Bits D7 D6 D5 D4 D3 D2 D1 D0 Memorytype R R R R R R R R Defaultvalue 0 0 0 0 0 0 0 0 Storedin E2PROM? N N N N N N N N Bit Description TSD Thermalshutdownstatusbit. 0:Normaloperation. 1:Thermalshutdowntripped.Thisflagisresetafterreadout. HOTDIE Instantaneousdietemperaturebit. 0:T <115ºC. J 1:T >115ºC. J DCDCMODE DC/DCmodeofoperationstatusbit. 1:DeviceoperatesinPFMmode. 0:DeviceoperatesinPWMmode. OPMODE Devicemodeofoperationstatusbit. 0:Deviceoperatesinpass-throughmode. 1:Deviceoperatesindc/dcmode. ILIMPT Currentlimitstatusbit(pass-throughmode). 0:Normaloperation. 1:IndicatesthatthebypassFETcurrentlimithastriggered.Thisflagisresetafterreadout. ILIMBST Currentlimitstatusbit(dc/dcboostmode). 0:Normaloperation. 1:Indicatesthattheaverageinputcurrentlimithastriggeredfor1.5msindc/dcboostmode.Thisflagisresetafter readout. FAULT FAULTstatusbit. 0:Normaloperation. 1:Indicatesthatafaultconditionhasoccurred.Thisflagisresetafterreadout. PGOOD PowerGoodstatusbit. 0:Indicatestheoutputvoltageisoutofregulation. 1:Indicatestheoutputvoltageiswithinitsnominalrange.Thisbitissetiftheconverterisforcedinpass-through mode. 32 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 10.6.10 E2PROMCTRLRegister Memorylocation:0xFF Description WEN WP ISE2PROMWP RESERVED RESERVED RESERVED RESERVED RESERVED Bits D7 D6 D5 D4 D3 D2 D1 D0 Memorytype R/W R/W R R/W R/W R/W R/W R/W Defaultvalue 0 0 0 0 0 0 0 0 StoredinE2PROM? N Y N N N N N N Bit Description WEN E2PROMWriteEnablebit. 0:Nooperation. 1:ForcesthecontentsofselectedI2CregisterbitstobecopiedintoE2PROM,therebymakingthemthedefault valuesduringpower-up.WhenthecontentsofalltheI2CregisterbitshavebeenwrittentotheE2PROM,thedevice automaticallyresetsthisbit. WP E2PROMWriteProtectbit. 0:Normaloperation. 1:ForcestheE2PROMcontenttobelockedfollowingawritesequence(WEN=1).ThisprotectstheE2PROM contentfromundesirablewriteactionsmakingitvirussafe.Thisprocessisnonreversible. ISE2PROMWP E2PROMWriteProtectStatusbit. 0:E2PROMcontentisnotwriteprotected.E2PROMcontentcanstillbeupdated. 1:E2PROMcontentiswriteprotected.E2PROMcontentispermanentlylocked. RESERVED Reservedbit. Thisbitsisreservedforfutureuse.Duringwriteoperationsdataintendedforthisbitisignored,andduringread operations0isreturned. Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 11.1 Application Information The devices are step up dc/dc converters with true bypass function integrated. They are typically used as pre- regulators with input voltage ranges from 2.3V to 4.8V, extend the battery run time and overcome input current andinputvoltagelimitationsofthesystembeingpowered. While in input voltage higher than boost/bypass threshold, the high-efficient integrated pass-through path connectsthebatterytothepoweredsystemdirectly. If the input voltage becomes lower than boost/bypass threshold, the device seamlessly transitions into boost modeoperationwithamaximumavailableoutputcurrentof3A. The following design procedure can be used to select component values for the TPS61280, TPS61281 and TPS61282. 11.2 Typical Application 11.2.1 TPS61281with2.5V-4.35V ,1500mAOutputCurrent(TPS61280withI2CProgrammable) IN TPS61281 SW VOUT VBAT’ L SW VOUT 0.47μH VIN C (x2) O 10µF X5R 6.3V (0603) Battery VIN C I 1.5µF X5R 6.3V (0402) Voltage Select VSEL Enable EN 1.8V Forced Bypass /Auto BYP PFM/FPWM MODE PG Interrupt PGND PGND AGND PGND AGND Figure28. TPS61280TypicalApplication 11.2.1.1 DesignRequirement Table4.DesignParameters REFERENCE DESCRIPTION PARAMETER V Inputvoltagerange 2.5V-4.35V IN V OutputvoltagerangeatV =Low V =3.15VifV ≤3.15V,V =V ifV >3.15V OUT SEL OUT IN OUT IN IN V OutputvoltagerangeV =High V =3.35VifV ≤3.35V,V =V ifV >3.35V OUT SEL OUT IN OUT IN IN I Outputcurrent 1500mA OUT 34 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 11.2.1.2 DetailedDesignParameters 11.2.1.2.1 InductorSelection A boost converter normally requires two main passive components for storing energy during the conversion, an inductor and an output capacitor are required. It is advisable to select an inductor with a saturation current rating higherthanthepossiblepeakcurrentflowingthroughthepowerswitches. The inductor peak current varies as a function of the load, the input and output voltages and can be estimated usingEquation8. V xD I V I = IN + OUT with D =1- IN L(PEAK) 2x fx L (1-D)xh V OUT (8) Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the converter.Thiscouldeventuallyharmthedeviceandreduceit'sreliability. When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating, series resistance, and operating temperature. The inductor DC current rating should be greater than the maximuminputaveragecurrent,refertoEquation9andtheCurrentLimitOperationsectionformoredetails. V 1 I = OUT x xI L(DC) V h OUT IN (9) The TPS6128xA series of step-up converters have been optimized to operate with a effective inductance in the range of 200nH to 800nH. Larger or smaller inductor values can be used to optimize the performance of the deviceforspecificoperatingconditions.Formoredetails,seetheCheckingLoopStability section. In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (that is, quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size,increasedinductanceusuallyresultsinaninductorwithlowersaturationcurrent. The total losses of the coil consist of both the losses in the DC resistance, R , and the following frequency- (DC) dependentcomponents: • Thelossesinthecorematerial(magnetichysteresisloss,especiallyathighswitchingfrequencies) • Additionallossesintheconductorfromtheskineffect(currentdisplacementathighfrequencies) • Magneticfieldlossesoftheneighboringwindings(proximityeffect) • Radiationlosses For good efficiency, the inductor’s DC resistance should be less than 30mΩ. The following inductor series from differentsuppliershavebeenusedwiththeTPS6128xAconverters. Table5.ListofInductors SERIES DIMENSIONS(inmm) DCINPUTCURRENTLIMITSETTING DFE252010C 2.5x2.0x1.0max.height ≤3000mA DFE252012C 2.5x2.0x1.2max.height ≤3500mA DFR252010C 2.5x2.0x1.0max.height ≤3000mA DFE252012C 2.5x2.0x1.2max.height ≤3500mA DFE252012P 2.5x2.0x1.2max.height ≤3500mA DFE201610C 2.0x1.6x1.0max.height ≤2000mA DFE201612C 2.0x1.6x1.2max.height ≤3000mA DFE201612P 2.0x1.6x1.2max.height ≤3000mA Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 11.2.1.2.2 OutputCapacitor For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly recommended. This small capacitor should be placed as close as possible to the V and GND pins of the IC. OUT Togetanestimateoftherecommendedminimumoutputcapacitance,Equation10 canbeused. I x (V -V ) C = OUT OUT IN MIN fx DVx V OUT (10) Wherefistheswitchingfrequencywhichis2.3MHz(typ.)and ΔVisthemaximumallowedoutputripple. With a chosen ripple voltage of 20mV, a minimum effective capacitance of 10μF is needed. The total ripple is larger due to the ESR and ESL of the output capacitor. This additional component of the ripple can be calculated usingEquation11 æ I ΔI ö ΔV = ESR x ç OUT + L ÷ OUT(ESR) è1 -D 2 ø (11) æ I ΔI ö 1 ΔV = ESLx ç OUT + L -I ÷ x OUT(ESL) è1 -D 2 OUTø t SW(RISE) (12) æ I ΔI ö 1 ΔV =ESLx ç OUT - L -I ÷ x OUT(ESL) è1-D 2 OUTø t SW(FALL) (13) with: • I =outputcurrentoftheapplication OUT • D=dutycycle • ΔI =inductorripplecurrent L • t =switchnoderisetime SW(RISE) • t =switchnodefalltime SW(FALL) • ESR=equivalentseriesresistanceoftheusedoutputcapacitor • ESL=equivalentseriesinductanceoftheusedoutputcapacitor An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause loweroutputvoltagerippleaswellasloweroutputvoltagedropduringloadtransients. In applications featuring high (pulsed) load currents (e.g. ≥2Amps), it is recommended to run the converter with a reasonable amount of effective output capacitance and low-ESL device, for instance x2 22µF X5R 6.3V (0603) MLCCcapacitorsconnectedinparallelwitha1µFX5R6.3V(0306-2T)MLCCLLcapacitor. DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the device's effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with material are responsible for differences between the rated capacitor value and it's effective capacitance. For instance, a 10µF X5R 6.3V (0603) MLCC capacitor would typically show an effectivecapacitanceoflessthan5µF(under3.5Vbiascondition,hightemperature). For RF Power Amplifier applications, the output capacitor loading is combined between the dc/dc converter and theRFPowerAmplifier(x210µFX5R6.3V(0603)+PAinputcap4.7µFX5R6.3V(0402))arerecommended. 36 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and; therefore, theregulationcircuithasnovoltagedroponwhichitcanreact. 11.2.1.2.3 InputCapacitor Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible to the device. While a 4.7μF input capacitor is sufficient for most applications, larger values may be used to reduceinputcurrentripplewithoutlimitations. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed between C and the power source lead to reduce ringing than can occur between the inductance of the power I sourceleadsandC. I 11.2.1.2.4 CheckingLoopStability Thefirststepofcircuitandstabilityevaluationistolookfromasteady-stateperspectiveatthefollowingsignals: • Switchingnode,SW • Inductorcurrent,I L • Outputripplevoltage,V OUT(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulationloopmaybeunstable.Thisisoftenaresultofboardlayoutand/orL-Ccombination. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. V immediately shifts by an amount equal to ΔI x ESR, where ESR OUT (LOAD) is the effective series resistance of C . ΔI begins to charge or discharge C generating a feedback OUT (LOAD) OUT error signal used by the regulator to return V to its steady-state value. The results are most easily interpreted OUT whenthedeviceoperatesinPWMmode. During this recovery time, V can be monitored for settling time, overshoot or ringing that helps judge the OUT converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (that is, MOSFET r ) that are DS(on) temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range,andtemperaturerange. The TPS6128xA series of step-up converters have been optimized to operate with a effective inductance in the range of 200nH to 800nH and with output capacitors in the range of 8uF to 100µF. The internal compensation is optimizedforanoutputfilterofL=0.5µHandC =15µF. O Table6.ComponentList REFERENCE DESCRIPTION PARTNUMBER,MANUFACTURER C 1.5μF,6.3V,0402,X5Rceramic GRM155R60J155ME80D IN C 2x10μF,6.3V,0603,X5Rceramic 2xGRM188R60J106ME84 OUT L 470nH,47mΩ,2.5mmx2.0mmx1.2mm DFE252012CR470 Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 11.2.1.3 ApplicationPerformanceCurves 100.0 100.0 90.0 95.0 %) %) Efficiency ( 80.0 Efficiency ( 90.0 70.0 VIN= 2.5V VIN= 3.6V VIN= 2.5V VIN= 3.6V VIN= 2.7V VIN= 4.3V VIN= 2.7V VIN= 4.3V VIN= 3.0V VIN= 3.0V 60.0 85.0 0.0001 0.001 0.01 0.1 1 2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 Current (A) Current (A) V =3.15V VSEL=Low Mode=Low V =3.15V VSEL=Low Mode=Low OUT OUT Figure29.TPS61281EfficiencyvsOutputCurrent Figure30.TPS61281EfficiencyvsOutputCurrent 100.0 100.0 90.0 95.0 %) %) y ( y ( nc 80.0 nc e e ci ci Effi Effi 90.0 70.0 V = 2.5V V = 3.6V V = 2.5V V = 3.6V IN IN IN IN V = 2.7V V = 4.3V V = 2.7V V = 4.3V IN IN IN IN V = 3.0V V = 3.0V IN IN 60.0 85.0 0.0001 0.001 0.01 0.1 1 2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 Current (A) Current (A) V =3.35V VSEL=High Mode=Low V =3.35V VSEL=High Mode=Low OUT OUT Figure31.TPS61281EfficiencyvsOutputCurrent Figure32.TPS61281EfficiencyvsOutputCurrent 3.276 3.213 3.244 3.181 V) 3.213 V) age ( 3.181 age ( 3.15 olt olt V V ut 3.15 ut 3.118 p p ut ut O 3.118 O V = 2.5V V = 2.5V IN IN V = 2.7V 3.087 V = 2.7V IN IN 3.087 V = 2.9V V = 2.9V IN IN V = 3.1V V = 3.0V IN IN 3.055 3.055 0.0001 0.001 0.01 0.1 1 2 1.5 1.9 2.3 2.7 Current (A) Current (A) V =3.15V Mode=Low V =3.15V Mode=Low OUT OUT Figure34.TPS61281DCOutputVoltagevsOutputCurrent Figure33.TPS61281DCOutputVoltagevsOutputCurrent 38 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 3.484 3.417 V = 2.5V IN V = 2.7V 3.451 IN V = 2.9V 3.384 IN V = 3.1V IN V) 3.417 V) VIN= 3.2V e ( e ( 3.35 g 3.384 g a a olt olt V V ut 3.35 ut 3.317 p p ut ut O 3.317 O V = 2.5V IN V = 2.7V 3.284 3.284 VIN= 2.9V IN V = 3.1V IN 3.25 3.25 0.0001 0.001 0.01 0.1 1 2 1.6 2 2.4 2.8 Current (A) Current (A) VOUT=3.35V Mode=Low VOUT=3.35V Mode=Low Figure35.TPS61281DCOutputVoltagevsOutputCurrent Figure36.TPS61281DCOutputVoltagevsOutputCurrent 4.5 4.5 4.4 4.4 4.3 4.3 4.2 4.2 V) 4.1 V) 4.1 e ( 4 e ( 4 ag 3.9 ag 3.9 olt 3.8 olt 3.8 V V ut 3.7 ut 3.7 Outp 33..56 Outp 33..56 3.4 I = 1mA 3.4 I = 1mA OUT OUT 3.3 I = 100mA 3.3 I = 100mA 3.2 IOUT= 1000mA 3.2 IOUT= 1000mA OUT OUT 3.1 I = 1500mA 3.1 I = 1500mA OUT OUT 3 3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V) Input Voltage (V) VOUT=3.15V VSEL=Low VOUT=3.35V VSEL=High Mode=Low Figure37.TPS61281DCOutputVoltagevsInputVoltage Figure38.TPS61281DCOutputVoltagevsInputVoltage 3.1 3 2.9 nt (A) 2.8 e 2.7 urr C 2.6 ut utp 2.5 O 2.4 2.3 2.2 2.1 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 Input Voltage (V) V =3.35V T =85°C Mode=Low OUT A Figure39.TPS61281MaximumOutputCurrentvsInput Figure40.BoosttoPass-ThroughModeExit/Entry Voltage Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com Figure41.TPS61281DynamicVoltageManagement Figure42.TPS61281DynamicVoltageManagement (VSEL)LoadCurrent50mA (VSEL)LoadCurrent500mA Figure43.TPS61281ForcedPass-ThroughtoBoostMode Figure44.TPS61280,81ALoadTransientResponseIn Transition PFM/PWMOperation Figure45.TPS61280,81ALoadTransientResponseIn Figure46.Start-UpatNoLoad PFM/PWMOperation 40 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 Figure47.Start-Upat30OhmLoad Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 11.2.2 TPS61282with2.5V-4.35VIN,2000mAOutputCurrent(TPS61280withI2CProgrammable) SuPA BUCK/BYPASS C IN 10µF 4G PA 3G PA C IN 4.7µF 2G PA TPS61280 SW VOUT VBAT’(4.0V) L SW VOUT 0.47μH C (x2) O VIN 10µF X5R 6.3V (0603) 3.3V ±10% VIN PMIC C Low ESLcapacitor 1.5µF X5R 6.3V (0402)I 1µF X5R 6.3V (0306-2T) SMPS Vcore Note: VBAT’rail may need additional bulk capacitance (ca 750µF) C 1- SANYO POSCAPTM: 220µF, 6mWESR, (7.3x4.3x1.1mm) 10µFIN Voltage Select VSEL 2- SANYO POSCAPTM: 330µF, 35mWESR, (3.5x2.8x1.4mm) SMPS VIO Enable EN LDO Forced Bypass /Auto BYP LDO SCL I2C Bus Mode Selection, PFM/PWM or FPWM SDA GPIO 2G PATx Enable BB PROCESSOR PGND Enable PGND PGND AGND I2C Bus Figure48. TPS6128x,DeviceOverview 11.2.2.1 DesignRequirements Table7.DesignParameters REFERENCE DESCRIPTION PARTNUMBER,MANUFACTURER V Inputvoltagerange 2.5V-4.35V IN V OutputvoltagerangeatV =Low V =3.3VifV ≤3.3V,V =V ifV >3.3V OUT SEL OUT IN OUT IN IN V OutputvoltagerangeV =High V =3.5VifV ≤3.5V,V =V ifV >3.5V OUT SEL OUT IN OUT IN IN I OutputCurrent 2000mA OUT Table8.ComponentList REFERENCE DESCRIPTION PARTNUMBER,MANUFACTURER C 1.5μF,6.3V,0402,X5Rceramic GRM155R60J155ME80D I C 4x10μF,6.3V,0603,X5Rceramic 4xGRM188R60J106ME84 O L 470nH,47mΩ,2.5mmx2.0mmx1.2mm DFE252012CR470 11.2.2.2 DetailedDesignProcedures See TPS61281 with 2.5V-4.35 V , 1500 mA Output Current (TPS61280 with I2C Programmable) for all Detailed IN DesignProcedures. 42 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 11.2.2.3 ApplicationPerformanceCurves 100.0 100.0 90.0 %) %) 95.0 Efficiency ( 80.0 Efficiency ( 90.0 70.0 VIN= 2.5V VIN= 3.6V VIN= 2.5V VIN= 3.3V VIN= 2.7V VIN= 4.3V VIN= 2.7V VIN= 4.3V VIN= 3.0V VIN= 3.0V 60.0 85.0 0.0001 0.001 0.01 0.1 1 2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 Current (A) Current (A) VOUT=3.3V VSEL=Low Mode=Low VOUT=3.3V VSEL=Low Mode=Low Figure49.TPS61282EfficiencyvsOutputCurrent Figure50.TPS61282EfficiencyvsOutputCurrent 100.0 100.0 90.0 %) %) 95.0 Efficiency ( 80.0 Efficiency ( 90.0 70.0 VIN= 2.5V VIN= 3.3V VIN= 2.5V VIN= 3.3V VIN= 2.7V VIN= 4.3V VIN= 2.7V VIN= 4.3V VIN= 3.0V VIN= 3.0V 60.0 85.0 0.0001 0.001 0.01 0.1 1 2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 Current (A) Current (A) V =3.5V VSEL=High Mode=Low V =3.5V VSEL=High Mode=Low OUT OUT Figure51.TPS61282EfficiencyvsOutputCurrent Figure52.TPS61282EfficiencyvsOutputCurrent 3.432 3.333 3.399 3.366 3.3 Output Voltage (V) 333...2233363.4733 VVVIIINNN=== 222...579VVV Output Voltage (V) 33..223647 VVVVIIIINNNN==== 2223....5791VVVV VIN= 3.1V VIN= 3.2V 3.201 3.201 0.0001 0.001 0.01 0.1 1 2 2 2.4 2.8 3.2 3.6 4 Current (A) Current (A) VOUT=3.3V Mode=Low VOUT=3.3V Mode=Low Figure53.TPS61282DCOutputVoltagevsOutputCurrent Figure54.TPS61282DCOutputVoltagevsOutputCurrent Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 3.64 3.57 3.605 3.535 V) 3.57 V) Voltage ( 3.535 Voltage ( 3.5 Output 33.4.346.535 VVVIIINNN=== 222...579VVV Output 33.4.4635 VVVVVIIIIINNNNN===== 22233.....57912VVVVV VIN= 3.1V VIN= 3.4V 3.395 3.395 0.0001 0.001 0.01 0.1 1 2 1.8 2.2 2.6 3 3.4 3.8 Current (A) Current (A) VOUT=3.5V Mode=Low VOUT=3.5V Mode=Low Figure55.TPS61282DCOutputVoltagevsOutputCurrent Figure56.TPS61282DCOutputVoltagevsOutputCurrent 4.5 4.5 4.4 4.4 4.3 4.3 4.2 4.2 ge (V) 34..941 ge(V) 344...901 a a olt 3.8 olt 3.8 Output V 333...567 Output V 333...567 IOIUoTu =t= 11mmAA 3.4 I = 1mA 3.4 IOIUoTu =t= 110000mmAA 3.3 IOOUUTT= 100mA 33..23 IOUIoT u=t =11000000mmAA 3.2 I = 1000mA 3.1 IOUT= 2000mA 3.1 IOUIoTu =t= 22000000mmAA OUT 3.0 3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V) Input Voltage(V) C013 VOUT=3.3V VSEL=Low Mode=Low VOUT=3.5V VSEL=High Mode=Low Figure57.TPS61282DCOutputVoltagevsInputVoltage Figure58.TPS61282DCOutputVoltagevsInputVoltage Figure59.BoosttoPass-ThroughModeExit/Entry Figure60.TPS61282DynamicVoltageManagement (VSEL)LoadCurrent50mA 44 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 Figure61.TPS61282DynamicVoltageManagement Figure62.TPS61282LineTransient (VSEL)LoadCurrent500mA Figure63.TPS61282LoadTransientResponseInPWM Figure64.TPS61282LoadTransientResponseIn Operation PFM/PWMOperation Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 12 Power Supply Recommendations The devices are designed to operate from an input voltage supply range between 2.3 V and 4.8 V. This input supply should be well regulated. If the input supply is located more than a few inches from the TPS61280, TPS61281orTPS61282converteradditionalbulkcapacitancemayberequiredinadditiontotheceramicbypass capacitors.Anelectrolyticortantalumcapacitorwithavalueof47 μFisatypicalchoice. 13 Layout 13.1 Layout Guidelines • For all switching power supplies, the layout is an important step in the design, especially at high peak currentsandhighswitchingfrequencies. • Ifthelayoutisnotcarefullydone,theregulatorcouldshowstabilityproblemsaswellasEMIproblems. • Therefore,usewideandshorttracesforthemaincurrentpathandforthepowergroundtracks. • Tominimizevoltagespikesattheconverter'soutput: – Placetheoutputcapacitor(s)ascloseaspossibletoGNDandV ,asshowninFigure65. OUT – TheinputcapacitorandinductorshouldalsobeplacedascloseaspossibletotheIC. – Use a common ground node for power ground and a different one for control ground to minimize the effectsofgroundnoise. – ConnectthesegroundnodesatanyplaceclosetothegroundpinsoftheIC. – Junction-to-ambientthermalresistanceishighlyapplicationandboard-layoutdependent. – It is suggested to maximize the pour area for all planes other than SW. Especially the ground pour should besettofillavailablePWBsurfaceareaandtiedtointernallayerswithaclusterofthermalvias. 13.2 Layout Example L Vin Vout n t t u u i C o o C C GND Figure65. SuggestedLayout(Top) 46 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 13.3 Thermal Consideration Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipationlimitsofagivencomponent. Threebasicapproachesforenhancingthermalperformancearelistedbelow: • ImprovingthepowerdissipationcapabilityofthePCBdesign • ImprovingthethermalcouplingofthecomponenttothePCB • Introducingairflowinthesystem As power demand in portable designs is more and more important, designers must figure the best trade-off between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction temperature can increase significantly which could lead to bad application behaviors (i.e. premature thermal shutdownorworstcasereducedevicereliability). Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Thedeviceoperatingjunctiontemperature(T )shouldbekeptbelow125°C. J Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 www.ti.com 14 Device and Documentation Support 14.1 Device Support 14.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 14.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table9.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY TPS61280 Clickhere Clickhere Clickhere Clickhere Clickhere TPS61281 Clickhere Clickhere Clickhere Clickhere Clickhere TPS61282 Clickhere Clickhere Clickhere Clickhere Clickhere 14.3 Trademarks NanoFreeisatrademarkofTexasInstruments. I2CisatrademarkofNXPSemiconductors. 14.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 14.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 48 SubmitDocumentationFeedback Copyright©2013–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS61280 TPS61281 TPS61282

TPS61280,TPS61281,TPS61282 www.ti.com SLVSBI1A–OCTOBER2013–REVISEDSEPTEMBER2014 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 15.1 Package Summary CHIPSCALEPACKAGE CHIPSCALEPACKAGE (BOTTOMVIEW) (TOPVIEW) A4 A3 A2 A1 B4 B3 B2 B1 TIYMLLLLS D TPS6128x C4 C3 C2 C1 D4 D3 D2 D1 A1 E Code: • YM —YearMonthdatecode • LLLL—Lottracecode • S—Assemblysitecode 15.1.1 ChipScalePackageDimensions The TPS6128x device is available in a 16-bump chip scale package (YFF, NanoFree™). The package dimensionsaregivenas: • D=ca.1666±30μm • E=ca.1666±30 μm Copyright©2013–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLinks:TPS61280 TPS61281 TPS61282

PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS61280YFFR ACTIVE DSBGA YFF 16 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS & no Sb/Br) 61280 TPS61280YFFT ACTIVE DSBGA YFF 16 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS & no Sb/Br) 61280 TPS61281YFFR ACTIVE DSBGA YFF 16 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS & no Sb/Br) 61281 TPS61281YFFT ACTIVE DSBGA YFF 16 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS & no Sb/Br) 61281 TPS61282YFFR ACTIVE DSBGA YFF 16 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS & no Sb/Br) 61282 TPS61282YFFT ACTIVE DSBGA YFF 16 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS & no Sb/Br) 61282 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 11-Feb-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS61280YFFR DSBGA YFF 16 3000 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1 TPS61280YFFT DSBGA YFF 16 250 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1 TPS61281YFFR DSBGA YFF 16 3000 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1 TPS61281YFFT DSBGA YFF 16 250 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1 TPS61282YFFR DSBGA YFF 16 3000 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1 TPS61282YFFT DSBGA YFF 16 250 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS61280YFFR DSBGA YFF 16 3000 182.0 182.0 20.0 TPS61280YFFT DSBGA YFF 16 250 182.0 182.0 20.0 TPS61281YFFR DSBGA YFF 16 3000 182.0 182.0 20.0 TPS61281YFFT DSBGA YFF 16 250 182.0 182.0 20.0 TPS61282YFFR DSBGA YFF 16 3000 182.0 182.0 20.0 TPS61282YFFT DSBGA YFF 16 250 182.0 182.0 20.0 PackMaterials-Page2

PACKAGE OUTLINE YFF0016 DSBGA - 0.625 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D 0.625 MAX C SEATING PLANE 0.30 0.12 BALL TYP 0.05 C 1.2 TYP D C SYMM 1.2 TYP B D: Max = 1.696 mm, Min =1 .636 mm 0.4 TYP E: Max = 1.696 mm, Min =1 .636 mm A 1 2 3 4 0.3 16X 0.2 SYMM 0.015 C A B 0.4 TYP 4219386/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YFF0016 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 16X ( 0.23) 1 2 3 4 A (0.4) TYP B SYMM C D SYMM LAND PATTERN EXAMPLE SCALE:30X 0.05 MAX ( 0.23) 0.05 MIN METAL UNDER METAL SOLDER MASK SOLDER MASK ( 0.23) OPENING SOLDER MASK OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219386/A 05/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YFF0016 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 16X ( 0.25) 1 2 3 4 A (0.4) TYP B SYMM METAL TYP C D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X 4219386/A 05/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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