Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 TPS6112x Synchronous Boost Converter With 1.1-A Switch and Integrated LDO 1 Features 3 Description • Synchronous,95%Efficient,BoostConverterWith The TPS6112x devices provide a complete power 1 supply solution for products powered by either a one- 500-mAOutputCurrentFrom1.8-VInput cell Li-Ion or Li-Polymer by either a one-cell Li-Ion or • Integrated200-mAReverseVoltageProtected Li-Polymer battery, or a two- to four-cell Alkaline, LDOforDC-DCOutputVoltagePostRegulation NiCd, or NiMH battery. The devices can generate two orSecondOutputVoltage stable output voltages that are either adjusted by an • 40-µA(Typical)TotalDeviceQuiescentCurrent external resistor divider or are fixed internally on the chip. The device also provides a simple solution for • InputVoltageRange:1.8Vto5.5V generating3.3Voutofaone-cellLi-IonorLi-Polymer • FixedandAdjustableOutputVoltageOptionsup battery at a maximum output current of at least 200 to5.5V mA with supply voltages down to 1.8 V. The • PowerSaveModeforImprovedEfficiencyatLow implemented boost converter is based on a fixed OutputPower frequency, pulse-width-modulation (PWM) controller using a synchronous rectifier to obtain maximum • LowBatteryComparator efficiency. The maximum peak current in the boost • PowerGoodOutput switchislimitedtoavalueof1600mA. • LowEMI-Converter(IntegratedAntiringingSwitch) The converter can be disabled to minimize battery • LoadDisconnectDuringShutdown drain. During shutdown, the load is completely • OvertemperatureProtection disconnected from the battery. A low-EMI mode is implemented to reduce ringing and, in effect, lower • AvailableinaSmall4-mm× 4-mmVQFN-16orin radiated electromagnetic energy when the converter aTSSOP-16Package enters discontinuous conduction mode. A power good output at the boost stage simplifies control of any 2 Applications connected circuits like cascaded power supply stages • AllSingleCellLiorDualCellBatteryorUSB ormicroprocessors. PoweredProductsasMP-3Player,PDAs,and The built-in LDO can be used for a second output OtherPortableEquipment voltage derived either from the boost output or • DualInputorDualOutputMode directly from the battery. The LDO can be enabled separately that is, using the power good of the boost • SimpleLi-Ionto3.3-VConversion stage. The device is packaged in a 16-pin VQFN (RSA) package measuring 4 mm x 4 mm or in a 16- TypicalApplicationSchematic pinTSSOP(PW)package. 10 (cid:2)H DeviceInformation(1) VBAT SWN SWP PARTNUMBER PACKAGE BODYSIZE(NOM) Battery 10 (cid:2)F LBI VOUT Vout1 TSSOP(16) 5.00mm×4.40mm TPS61120 TPS61120 FB 100 (cid:2)F VQFN(16) 4.00mm×4.00mm TPS61121 OFF ON SKIPEN PGOOD Control TPS61122 TSSOP(16) 5.00mm×4.40mm Control OFF ON EN LBO Outputs Inputs (1) For all available packages, see the orderable addendum at LDOIN OFF ON LDOEN LDOOUT Vout2 theendofthedatasheet. 2.2 (cid:2)F LDOSENSE GND PGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9.3 FeatureDescription.................................................12 2 Applications........................................................... 1 9.4 DeviceFunctionalModes........................................14 3 Description............................................................. 1 10 ApplicationandImplementation........................ 15 4 RevisionHistory..................................................... 2 10.1 ApplicationInformation..........................................15 10.2 TypicalApplications..............................................15 5 DeviceOptions....................................................... 3 11 PowerSupplyRecommendations..................... 24 6 PinConfigurationandFunctions......................... 3 12 Layout................................................................... 24 7 Specifications......................................................... 4 12.1 LayoutGuidelines.................................................24 7.1 AbsoluteMaximumRatings......................................4 12.2 LayoutExample....................................................24 7.2 ESDRatings..............................................................4 12.3 ThermalConsiderations........................................25 7.3 RecommendedOperatingConditions.......................4 13 DeviceandDocumentationSupport................. 26 7.4 ThermalInformation..................................................4 7.5 ElectricalCharacteristics...........................................5 13.1 DeviceSupport......................................................26 7.6 TypicalCharacteristics..............................................6 13.2 CommunityResources..........................................26 13.3 Trademarks...........................................................26 8 ParameterMeasurementInformation................10 13.4 ElectrostaticDischargeCaution............................26 9 DetailedDescription............................................ 11 13.5 Glossary................................................................26 9.1 Overview.................................................................11 14 Mechanical,Packaging,andOrderable 9.2 FunctionalBlockDiagram.......................................12 Information........................................................... 26 4 Revision History ChangesfromRevisionC(April2004)toRevisionD Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 2 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 5 Device Options Table1.AvailableOutputVoltageOptions(1) PARTNUMBER(2) OUTPUTVOLTAGEDC-DC OUTPUTVOLTAGELDO TPS61120PW Adjustable Adjustable TPS61121PW 3.3V 1.5V TPS61122PW 3.6V 3.3V TPS61120RSA Adjustable Adjustable TPS61121RSA 3.3V 1.5V (1) Contactthefactorytocheckavailabilityofotherfixedoutputvoltageversions. (2) Thepackagesareavailabletapedandreeled.AddRsuffixtodevicetype(forexampleTPS61120PWRorTPS61120RSAR)toorder quantitiesof2000devicesperreelfortheTSSOP(PW)packageand3000devicesperreelfortheQFN(RSA)package. 6 Pin Configuration and Functions PWPackage 16-PinTSSOP RSAPackage TopView 16-PinVQFNWithThermalPad TopView SWP 1 16 VOUT T NPU SWN 2 15 FB WWOB PGND 3 14 PGOOD SSVF VBAT 4 13 LBO PGND PGOOD LBI 5 12 GND VBAT LBO Thermal SKIPEN 6 11 LDOSENSE LBI Pad GND EN 7 10 LDOOUT SKIPEN LDOSENSE LDOEN 8 9 LDOIN NN NT EOE OIOU D LDO L D L PinFunctions PIN NO. I/O DESCRIPTION NAME TSSOP VQFN EN 7 5 I DC-DC-enableinput.(1:VBATenabled,0:GNDdisabled) FB 15 13 I DC-DCvoltagefeedbackofadjustableversions GND 12 10 I/O Control/logicground LBI 5 3 I Lowbatterycomparatorinput(comparatorenabledwithEN) LBO 13 11 O Lowbatterycomparatoroutput(opendrain) LDOEN 8 6 I LDO-enableinput(1:LDOINenabled,0:GNDdisabled) LDOOUT 10 8 O LDOoutput LDOIN 9 7 I LDOinput LDOSENSE 11 9 I LDOfeedbackforvoltageadjustment,mustbeconnectedtoLDOOUTatfixed outputvoltageversions SWP 1 15 I DC-DCrectifyingswitchinput PGND 3 1 I/O Powerground PGOOD 14 12 O DC-DCoutputpowergood(1:good,0:failure)(opendrain) SKIPEN 6 4 I Enable/disablepowersavemode(1:VBATenabled,0:GNDdisabled) SWN 2 16 I DC-DCswitchinput VBAT 4 2 I Supplypin VOUT 16 14 O DC-DCoutput Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerangeunlessotherwisenoted(1) MIN MAX UNIT FB –0.3 3.6 V SWN,SWP –0.3 10 V Inputvoltage VOUT,LDOIN,LDOOUT,LDOEN,LDOSENSE,PGOOD,LBO,VBAT, –0.3 7 V LBI,SKIPEN,EN MaximumjunctiontemperatureT –40 150 °C J StoragetemperatureT –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±750 V C101(2) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions MIN NOM MAX UNIT SupplyvoltageatVBAT,V 1.8 5.5 V I Operatingambienttemperaturerange,T –40 85 °C A Operatingvirtualjunctiontemperaturerange,T –40 125 °C J 7.4 Thermal Information TPS61120,TPS61121, TPS61120 TPS61122 THERMALMETRIC(1) UNIT PW(TSSOP) RSA(VQFN) 16PINS 16PINS R Junction-to-ambientthermalresistance 100.5 33.9 °C/W θJA R Junction-to-case(top)thermalresistance 35.8 36.3 °C/W θJC(top) R Junction-to-boardthermalresistance 45.4 11 °C/W θJB ψ Junction-to-topcharacterizationparameter 2.6 0.5 °C/W JT ψ Junction-to-boardcharacterizationparameter 44.8 11 °C/W JB R Junction-to-case(bottom)thermalresistance n/a 2.2 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 4 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 7.5 Electrical Characteristics overrecommendedfree-airtemperaturerangeandoverrecommendedinputvoltagerange(typicalatanambienttemperature rangeof25°C)(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DC-DCSTAGE V Inputvoltagerange 1.8 5.5 V I Adjustableoutputvoltagerange V 2.5 5.5 V O (TPS61120) Reference V 485 500 515 mV ref voltage Oscillator f 400 500 600 kHz frequency I Switchcurrentlimit VOUT=3.3V 1100 1300 1600 mA SW Startupcurrent 0.4*I mA limit SW SWNswitchonresistance VOUT=3.3V 200 350 mΩ SWPswitchonresistance VOUT=3.3V 250 500 mΩ Totalaccuracy(includinglineand -3% ±3% loadregulation) I =0mA,V =VBAT=1.8V, DC-DC intoVBAT VOOUT=3.3EVN,ENLDO=0 10 25 µA quiescent current intoVOUT IO=0mA,VEN=VBAT=1.8V, 10 25 µA VOUT=3.3V,ENLDO=0 DC-DCshutdowncurrent V =0V 0.2 1 µA EN LDOSTAGE V Inputvoltagerange 1.8 7 V I(LDO) Adjustableoutputvoltagerange V 0.9 5.5 V O(LDO) (TPS61120) I Outputcurrent 200 320 mA O(max) LDOshortcircuitcurrentlimit 500 mA Minimumvoltagedrop I =200mA 300 mV O Totalaccuracy(includinglineand I ≥1mA ±3% loadregulation) O LDOINchangefrom1.8Vto2.6V Lineregulation 0.6% at100mA,LDOOUT=1.5V Loadchangefrom10%to90%, Loadregulation 0.6% LDOIN=3.3V LDOIN=7V,VBAT=1.8V,EN= LDOquiescentcurrent 20 30 µA VBAT LDOshutdowncurrent LDOEN=0V,LDOIN=7V 0.1 1 µA CONTROLSTAGE V LBIvoltagethreshold V voltagedecreasing 490 500 510 mV IL LBI LBIinputhysteresis 10 mV LBIinputcurrent EN=VBATorGND 0.01 0.1 µA LBOoutputlowvoltage V =3.3V,I =100µA 0.04 0.4 V O OI LBOoutputlowcurrent 100 µA LBOoutputleakagecurrent V =7V 0.01 0.1 µA LBO V EN,SKIPENinputlowvoltage 0.2×VBAT V IL V EN,SKIPENinputhighvoltage 0.8×VBAT V IH V LDOENinputlowvoltage 0.2×V V IL LDOIN 0.8× V LDOENinputhighvoltage V IH V LDOIN EN,SKIPENinputcurrent ClampedonGNDorVBAT 0.01 0.1 µA Power-Goodthreshold V =3.3V 0.9*V 0.92*V 0.95*V V O O O O Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com Electrical Characteristics (continued) overrecommendedfree-airtemperaturerangeandoverrecommendedinputvoltagerange(typicalatanambienttemperature rangeof25°C)(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Power-Gooddelay 30 µs Power-Goodoutputlowvoltage V =3.3V,I =100µA 0.04 0.4 V O OI Power-Goodoutputlowcurrent 100 µA Power-Goodoutputleakage V =7V 0.01 0.1 µA PG current Overtemperatureprotection 140 °C Overtemperaturehysteresis 20 °C 7.6 Typical Characteristics Table2.TableofGraphs FIGURE BOOSTCONVERTER Figure1, Maximumoutputcurrent vsInputvoltage Figure2 vsOutputcurrent(TPS61120)(V =2.5V,V =1.8V) Figure3 O I vsOutputcurrent(TPS61121)(V =3.3V,V =1.8V,2.4V) Figure4 O I Efficiency vsOutputcurrent(TPS61120)(V =5.0V,V =2.4V,3.3V) Figure5 O I vsInputvoltage(TPS61121) Figure6 Outputvoltage vsOutputcurrent(TPS61121) Figure7 No-loadsupplycurrentintoVBAT vsInputvoltage(TPS61121) Figure8 No-loadsupplycurrentintoVOUT vsInputvoltage(TPS61121) Figure9 LDO vsInputvoltage(V =2.5V,3.3V) Figure10 O Maximumoutputcurrent vsInputvoltage(V =1.5V,1.8V) Figure11 O Outputvoltage vsOutputcurrent(TPS61122) Figure12 Dropoutvoltage vsOutputcurrent(TPS61121,TPS61122) Figure13 SupplycurrentintoLDOIN vsLDOINinputvoltage(TPS61121) Figure14 PSRR vsFrequency(TPS61121) Figure15 1.4 1 0.90 1.2 A A 0.80 m Output Current - 00..681 VO = 5 V m Output Current - 0000....45670000 VO = 2.5 V mu mu Maxi 0.4 Maxi 0.30 0.20 0.2 0.10 0 0 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 VI- Input Voltage - V VI- Input Voltage - V Figure1.TPS61120MaximumBoostConverterOutput Figure2.TPS61120MaximumBoostConverterOutput CurrentvsInputVoltage CurrentvsInputVoltage 6 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 100 100 VI = 2.4 V 90 90 VI = 1.8 V 80 80 70 70 % Efficiency - % 456000 Efficiency - 456000 30 30 20 20 VO = 2.5 V, 10 VI = 1.8 V 10 VO = 3.3 V 0 0 0.1 1 10 100 1000 0.1 1 10 100 1000 IO - Output Current - mA IO - Output Current - mA Figure3.TPS61120BoostConverterEfficiencyvsOutput Figure4.TPS61121BoostConverterEfficiencyvsOutput Current Current 100 100 VI = 3.3 V IO = 10 mA IO = 200 mA 90 VI = 2.4 V 80 90 70 % IO = 100 mA Efficiency - 456000 Efficiency - % 80 30 70 20 10 VO = 5 V 0 60 0.1 1 10 100 1000 1.8 2 2.2 2.4 2.6 2.8 3 3.2 IO - Output Current - mA VI - Input Voltage - V Figure5.TPS61120BoostConverterEfficiencyvsOutput Figure6.TPS61121BoostConverterEfficiencyvsInput Current Voltage 3.40 14 VI = 2.4 V A 85°C 3.38 3.36 mAT - 12 25°C B - Output Voltage - V 3333....23338024 pply Current Into V 1068 -40°C O 3.26 u 4 V S d 3.24 a o L 2 3.22 o- N 3.20 0 0 200 400 600 800 1.8 2 2.2 2.4 2.6 2.8 3 3.2 IO - Output Current - mA VI - Input Voltage - V Figure7.TPS61121BoostConverterOutputVoltagevs Figure8.TPS61121No-LoadSupplyCurrentIntoVBATvs OutputCurrent InputVoltage Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 14 400 A 85°C VO = 3.3 V mVOUT - 1102 -2450°°CC nt - mA 330500 nt Into 8 ut Curre 250 VO = 2.5 V e p urr Out 200 pply C 6 m LDO 150 o-Load Su 24 Maximu 15000 N 0 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VI - Input Voltage - V LDO Input Voltage - V Figure9.TPS61121No-LoadSupplyCurrentIntoVOUTvs Figure10.TPS61120MaximumLDOOutputCurrentvs InputVoltage LDOInputVoltage 400 3.4 VO = 1.5 V 3.38 350 A m 3.36 Current - 235000 VO = 1.8 V age - V 33..3324 Output 200 put Volt 3.3 DO 150 Out 3.28 m L DO 3.26 u L m 100 xi 3.24 a M 50 3.22 0 3.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 0 50 100 150 200 250 300 350 400 LDO Input Voltage - V LDO Output Current - mA Figure11.TPS61120MaximumLDOOutputCurrentvs Figure12.TPS61122LDOOutputVoltagevsLDOOutput LDOInputVoltage Current 3.5 85°C 20 A 3 m N - 25°C oltage - V 2.52 VO(LLDTOAT GOPEUS 16T.1P51U 2VT1) nto LDOI 15 -40°C Dropout V 1.5 VO(LLDTOAT GOPEUS 36T.1P31U 2VT2) Current I 10 O y LD 1 ppl Su 5 0.5 0 0 10 60 110 160 210 260 310 1.8 2 2.2 2.4 2.6 2.8 3 3.2 LDO Output Current - mA LDOIN Input Voltage - V Figure13.LDODropoutVoltagevsLDOOutputCurrent Figure14.TPS61121SupplyCurrentIntoLDOINvsLDO InputVoltage 8 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 80 LDOIN = 3.3 V 70 LDO Output Current 10 mA 60 B 50 d RR - 40 S P 30 LDO Output Current 200 mA 20 10 0 1k 10k 100k 1M 10M f - Frequency - Hz Figure15.TPS61121PSRRvsFrequency Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 8 Parameter Measurement Information U1 L1 SWN 10 m H SWP VBAT VOUT Vout1 SPuopwpelyr 10 Cm F3 R1 LBI FB R3 2.C2 6m F 10C04 m F Boost Output R2 LDOIN R6 SKIPEN LDOOUT Vout2 R5 LDO Output C5 EN LDOSENSE 2.2 m F R7 List of Components: R4 R9 LDOEN U1 = TPS6112xPW LBO L1 = Sumida CDRH73−100 Control C3, C5, C6 = X7R/X5R Ceramic Outputs PGOOD C4 = Low ESR Tantalum GND PGND TPS6112xPW Figure16. TPS61120TypicalApplicationSchematic 10 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 9 Detailed Description 9.1 Overview The TPS6112x synchronous step-up converter typically operates at a 500-kHz frequency pulse width modulation (PWM) at moderate to heavy load currents. The converter enters Power Save mode at low load currents to maintain a high efficiency over a wide load. The Power Save mode can also be disabled, forcing the converter to operateatafixedswitchingfrequency. The TPS6112x family of devices is based on a fixed frequency with multiple feed forward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. Also, the peak current of the NMOS switch is sensed to limit the maximum current flowing through the switchandtheinductor. The device includes an additional built-in LDO which can be used to generate a second output voltage derived fromtheoutputoftheTPS6112xoranexternalpowersupply. Additionally, TPS6112x integrated the low-battery detector circuit is used to supervise the battery voltage and to generateanerrorflagwhenthebatteryvoltagedropsbelowauser-setthresholdvoltage. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 9.2 Functional Block Diagram SWN SWP Backgate Control Anti- VBAT Ringing VOUT VOUT 100 kW 20 pF Vmax Gate Control Control PGND PGND PGND Error Amplifier _ Regulator FB + + Vref = 0.5 V _ GND Control Logic Oscillator Temperature EN Control PGOOD LDOIN ENLDO Backgate SYNC Control GND LDOOUT Error LBO Amplifier _ LDOFB Low Battery Comparator + _ LBI + Vref = 0.5 V _ + + GND _ Vref = 0.5 V GND 9.3 Feature Description 9.3.1 ControllerCircuit The controller circuit of the device is based on a fixed-frequency multiple feedforward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect andslowwaythroughthecontrolloopandtheerroramplifier.Thecontrolloop,determinedbytheerroramplifier, only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to generateanaccurateandstableoutputvoltage. ThepeakcurrentoftheNMOSswitchisalsosensedtolimitthemaximumcurrentflowingthroughtheswitchand the inductor. The typical peak current limit is set to 1300 mA. An internal temperature sensor prevents the device fromgettingoverheatedincaseofexcessivepowerdissipation. 12 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 Feature Description (continued) 9.3.2 SynchronousRectifier The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier. Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power conversion efficiency reaches 95%. To avoid ground shift due to the high currents in the NMOS switch, two separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in shutdown and allows current flowing from the battery to the output. This device however uses a special circuit which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when theregulatorisnotenabled(EN=low). The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of the converter. No additional components have to be added to the design to make sure that the battery is disconnectedfromtheoutputoftheconverter. 9.3.3 LDO The built-in LDO can be used to generate a second output voltage derived from the DC-DC converter output, from the battery, or from another power source like an ac adapter or a USB power rail. The LDO is capable of being back biased. This allows the user to just connect the outputs of DC-DC converter and LDO. So the device is able to supply the load via DC-DC converter when the energy comes from the battery and efficiency is most important and from another external power source via the LDO when lower efficiency is not critical. The LDO must be disabled if the LDOIN voltage drops below LDOOUT to block reverse current flowing. The status of the DC-DCstage(enabledordisabled)doesnotmatter. 9.3.4 DeviceEnable The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is switchedoff,andtheloadisisolatedfromtheinput(asdescribedintheSynchronousRectifier section).Thisalso meansthattheoutputvoltagecandropbelowtheinputvoltageduringshutdown. 9.3.4.1 UndervoltageLockout An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than approximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters the shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is implementedinordertopreventthemalfunctioningoftheconverter. 9.3.4.2 Softstart During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the battery. When the boost section is enabled, the internal startup cycle starts with the first step, the precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is chargedtoavalueclosetotheinputvoltage.Therectifyingswitchcurrentislimitedinthatphase.Thisalsolimits the output current under short-circuit conditions at the output. After charging the output capacitor to the input voltage the device starts switching. Until the output voltage is reached, the boost switch current limit is set to 40% of its nominal value to avoid high peak currents at the battery during startup. When the output voltage is reached,theregulatortakescontrolandtheswitchcurrentlimitissetbackto100%. 9.3.5 LDOEnable The LDO can be separately enabled and disabled by using the LDOEN pin in the same way as the EN pin at the DC-DC converter stage described above. This is completely independent of the status of the EN pin. The voltage levelsofthelogicsignalswhichneedtobeappliedatLDOENarerelatedtoLDOIN. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com Feature Description (continued) 9.3.6 PowerGood The PGOOD pin stays high impedance when the DC-DC converter delivers an output voltage within a defined voltage window. So it can be used to enable any connected circuitry such as cascaded converters (LDO) or to resetmicroprocessorcircuits. 9.3.7 LowBatteryDetectorCircuit—LBI/LBO The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI. During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold. ItisactivelowwhenthevoltageatLBIgoesbelow500mV. The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV, which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the Programming the LBI/LBO Threshold Voltage section for more details about the programming of the LBI threshold. If the low-battery detection circuit is not used, the LBI pin should be connected to GND (or to VBAT) andtheLBOpincanbeleftunconnected.DonotlettheLBIpinfloat. 9.3.8 Low-EMISwitch The device integrates a circuit that removes the ringing that typically appears on the SW node when the converterentersdiscontinuouscurrentmode.Inthiscase,thecurrentthroughtheinductorrampstozeroandthe rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and thereforedampensringing. 9.4 Device Functional Modes 9.4.1 PowerSaveMode The SKIPEN pin can be used to select different operation modes. To enable the Power save mode, SKIPEN must be set high. Power save mode is used to improve efficiency at light loads. In power save mode, the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses, and goes again into power save mode once the output voltage exceeds the set thresholdvoltage.TheskipmodecanbedisabledbysettingtheSKIPENtoGND. 14 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information TheTPS6112xDC-DCconvertersareintendedforsystemspoweredbyadualortriplecellNiCdorNiMHbattery with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary alkalinebatterycellscanbethepowersourceinsystemswheretheTPS6112xisused. The built-in LDO can be used to generate a second output voltage derived from the DC-DC converter output, from the battery, or from another power source like an ac adapter or a USB power rail. The maximum programmableoutputvoltageattheLDOis5.5V. 10.2 Typical Applications 10.2.1 SolutionforMaximumOutputPower U1 L1 SWN 10 m H SWP VBAT VOUT 3.3 V, C3 R1 C6 C4 >250 mA 10 m F LBI 2.2 m F 100 m F R2 LDOIN SKIPEN LDOOUT 1.5 V, C5 >120 mA EN LDOSENSE 2.2 m F R7 R9 List of Components: LDOEN LBO LBO U1 = TPS61121PW L1 = Sumida CDRH73–100 C3, C5, C6 = X7R/X5R Ceramic PGOOD PGOOD C4 = Low ESR Tantalum GND PGND TPS61121PW Figure17. SolutionforMaximumOutputPower 10.2.1.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable3. Table3.TPS6112x5VOutputDesignParameters DESIGNPARAMETERS EXAMPLEVALUES Inputvoltagerange 1.8Vto3.3V Outputvoltageboost 3.3V OutputvoltageLDO 1.5V Outputvoltageripple ±3%V O Transientresponse ±10%V O Inputvoltageripple ±200mV Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 10.2.1.2 DetailedDesignProcedure TheTPS6112xDC-DCconvertersareintendedforsystemspoweredbyadualortriplecellNiCdorNiMHbattery with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary alkalinebatterycellscanbethepowersourceinsystemswheretheTPS6112xisused. 10.2.1.2.1 ProgrammingtheOutputVoltage 10.2.1.2.1.1 DC-DCConverter The output voltage of the TPS61120 DC-DC converter section can be adjusted with an external resistor divider. The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Based on those two values, the recommended value for R6 should be lower than 500 kΩ, in order to set the divider current at 1 µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200 kΩ. From that, the value of resistor R3, depending on the needed output voltage (V ), can be calculated using O Equation1: (cid:3)V (cid:4) (cid:3) V (cid:4) R3(cid:2)R6(cid:1) O –1 (cid:2)180k(cid:1)(cid:1) O –1 V 500mV FB (1) If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. If for any reason the value for R6 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is recommended.TherequiredcapacitancevaluecanbeeasilycalculatedusingEquation2. (cid:4)200k(cid:1) (cid:5) CparR3(cid:3)20pF(cid:1) R6 (cid:2)1 (2) U1 L1 SWN 10 m H SWP VBAT VOUT VCC1 SPuopwpelyr 10 Cm F3 R1 LBI FB R3 2.C2 6m F 10C04 m F Boost Output R2 LDOIN R6 SKIPEN LDOOUT VCC2 R5 C5 LDO Output LDOSENSE 2.2 m F EN R7 R9 R4 LDOEN LBO Control Outputs PGOOD GND PGND TPS6112xPW Figure18. TypicalApplicationCircuitforAdjustableOutputVoltageOption 10.2.1.2.1.2 LDO Programming the output voltage at the LDO follows almost the same rules as in the DC-DC converter section. The maximum programmable output voltage at the LDO is 5.5 V. Since reference and internal feedback circuitry are similar, as they are at the boost converter section, R4 also should be in the 200-kΩ range. The calculation of thevalueofR5canbedoneusingthefollowingEquation3: 16 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 (cid:3)V (cid:4) (cid:3) V (cid:4) R5(cid:2)R4(cid:1) O –1 (cid:2)180k(cid:1)(cid:1) O –1 V 500mV FB (3) Ifasanexample,anoutputvoltageof1.5Visneeded,a360kΩ-resistorshouldbechosenforR5. 10.2.1.2.2 ProgrammingtheLBI/LBOThresholdVoltage The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is generated on-chip, which has a value of 500 mV. The recommended value for R2is therefore in the range of 500 kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage V can be BAT, calculatedusingEquation4. (cid:4) V (cid:5) (cid:4) V (cid:5) R1(cid:3)R2(cid:1) BAT (cid:2)1 (cid:3)390k(cid:1)(cid:1) BAT (cid:2)1 V 500mV LBI(cid:2)threshold (4) The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not exceedtheoutputvoltageoftheDC-DCconverter.Ifnotused,theLBOpincanbeleftfloatingortiedtoGND. 10.2.1.2.3 InductorSelection A boost converter normally requires two main passive components for storing energy during the conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is recommended to keep the possible peak inductor current below the current limit threshold of the power switch in the chosen configuration. For example, the current limit threshold of the TPS6112x's switch is 1600 mA at an output voltage of 3.3 V. The highest peak current through the inductor and the switch depends on the output load, the input (V ), and the output voltage (V ). Estimation of the maximum average inductor current can be BAT OUT doneusingEquation5: V I (cid:2)I (cid:1) OUT L OUT V (cid:1)0.8 BAT (5) For example, for an output current of 250 mA at 3.3 V, at least 575 mA of current flows through the inductor at a minimuminputvoltageof1.8V. The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is advisable to work with a ripple in the range of 20% of the average inductor current. A smaller ripple reduces the magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way, regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those parameters,itispossibletocalculatethevaluefortheinductorbyusingEquation6: VBAT(cid:1)(cid:3)VOUT–VBAT(cid:4) L(cid:2) (cid:1)IL(cid:1)ƒ(cid:1)VOUT (6) Parameter f is the switching frequency and Δ I is the ripple current in the inductor, that is, 20% × I . In this L L example, the desired inductor value is in the range of 14 µH. In typical applications a 10 µH inductor is recommended. The minimum possible inductor value is 4.7 µH. With the calculated inductance value and current, it is possible to choose a suitable inductor. Care must be taken that load transients and losses in the circuit can lead to higher currents as estimated in Equation 5. Also, the losses in the inductor caused by magnetichysteresislossesandcopperlossesareamajorparameterfortotalcircuitefficiency. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com ThefollowinginductorseriesfromdifferentsuppliershavebeenusedwiththeTPS6112xconverters: Table4.ListofInductors VENDOR RECOMMENDEDINDUCTORSERIES CDRH5D18 Sumida CDRH6D28 WurthElectronik 7447789___ 7447779___ DR73 Coiltronics DR74 TDK SLF7032 EPCOS B82462G 10.2.1.2.4 CapacitorSelection 10.2.1.2.4.1 InputCapacitor An input capacitor with a value of at least a 10 µF is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramiccapacitorinparallel,placedclosetotheIC,isrecommended. 10.2.1.2.4.2 OutputCapacitorDC-DCConverter The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. Calclating the minimum capacitance required to define the ripple is possible, supposing that the ESR is zero, by usingEquation7: IOUT(cid:1)(cid:4)VOUT(cid:2)VBAT(cid:5) Cmin(cid:3) ƒ(cid:1)(cid:1)V(cid:1)VOUT (7) Parameterƒ istheswitchingfrequencyandΔVisthemaximumallowedripple. With a chosen ripple voltage of 10 mV, a minimum capacitance of 22 µF is needed. The total ripple is larger due totheESRoftheoutputcapacitor.ThisadditionalcomponentoftheripplecanbecalculatedusingEquation8: (cid:1)V (cid:2)I (cid:1)R ESR OUT ESR (8) Anadditionalrippleof20mVistheresultofusingatantalumcapacitorwithalowESRof80mΩ.Thetotalripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this example, the total ripple is 30 mV. Additional ripple is caused by load transients. This means that the output capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor has to completely supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. In typical applications a 100 µF capacitance is recommended. For economical reasons this usually is a tantalum capacitor. Because of this the control loop has been optimized for using output capacitors with an ESR of above 30 mΩ. Theminimumvaluefortheoutputcapacitoris22µF. 10.2.1.2.4.2.1 SmallSignalStability When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the range of 10 pF in parallel with R3 helps to obtain small signal stability, with the lowest ESR output capacitors. For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in Equation9,canbeused. A (cid:3) d (cid:3) 10(cid:1)(R3(cid:2)R6) REG V R6(cid:1)(1(cid:2)i(cid:1)(cid:2)(cid:1)1.6(cid:1)s) FB (9) 18 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 10.2.1.2.4.3 OutputCapacitorLDO To ensure stable output regulation, it is required to use an output capacitor at the LDO output. Ceramic capacitors in the range from 1 µF up to 4.7 µF is recommended. Using the standard ESR tantalum is recommendedatcapacitanceof4.7µFandabove.Thereisnomaximumcapacitancevalue. 10.2.1.3 ApplicationCurves Figure19.TPS61121BoostConverterOutputVoltagein Figure20.TPS61121BoostConverterOutputVoltagein ContinuousMode PowerSaveMode Figure21. TPS61121BoostConverterLoadTransient Figure22.TPS61121BoostConverterLineTransient Response Response Figure23.TPS61121BoostConverterStart-upAfter Figure24.TPS61121LDOLoadTransientResponse Enable Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com Figure25.TPS61121LDOLineTransientResponse Figure26.TPS61121LDOStart-upAfterEnable 10.2.2 LowProfileSolution,MaximumHeight1.8mm The TPS6112x boost converter with LDO features two independent output voltages. An efficient synchronous boost converter provides a 3.3-V V with output currents up to 500 mA. A 200-mA LDO regulator generates a OUT1 1.5-V V . The two outputs can be used independently from each other. TPS6112x supports the lower profile OUT2 ofinductorwithmaximumheight1.8mm. U1 L1 SWN 10 m H SWP VBAT VOUT 3.3 V C3 R1 C6 C4 10 m F 2.2 m F 100 m F LBI R2 LDOIN SKIPEN LDOOUT 1.5 V C5 EN LDOSENSE 2.2 m F R7 R9 List of Components: LDOEN U1 = TPS61121PW LBO LBO L1 = Sumida 5D18−100 C3, C5, C6 = X7R/X5R Ceramic PGOOD PGOOD C4 = Low ESR, Low Profile Tantalum GND PGND TPS61121PW Figure27. LowProfileSolution,MaximumHeight1.8mm 20 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 10.2.3 DualPowerSupplyWithAuxiliaryPositiveOutputVoltage The TPS6112x boost converter with LDO features multiple output voltages. An efficient synchronous boost converter provides Vout1 3.3 V with output currents up to 500mA. A 200-mA LDO regulator generates Vout2 1.5 V.Anotherrailprovides6Vwithdiscretechargepumpadded. 6 V C7 DS1 U1 0.1 m F C8 L1 1 m F SWN 10 m H SWP VBAT VOUT 3.3 V C3 R1 C6 C4 10 m F 2.2 m F 100 m F LBI R2 LDOIN SKIPEN LDOOUT 1.5 V C5 EN LDOSENSE 2.2 m F List of Components: R7 R9 U1 = TPS61121PW LDOEN L1 = Sumida CDRH73−100 LBO LBO C3, C5, C6, C7, C8 = X7R/X5R Ceramic PGOOD PGOOD C4 = Low ESR Tantalum GND PGND DS1 = BAT54S TPS61121PW Figure28. DualPowerSupplyWithAuxiliaryPositiveOutputVoltage Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 10.2.4 DualPowerSupplyWithAuxiliaryNegativeOutputVoltage The TPS6112x boost converter with LDO features multiple output voltages. An efficient synchronous boost converter provides Vout1 3.3 V with output currents up to 500 mA. A 200-mA LDO regulator generates Vout2 1.5 V.Anotherrailprovides–3Vwithdiscretechargepumpadded. −3 V C7 DS1 C8 U1 0.1 m F 1 m F L1 SWN 10 m H SWP VBAT VOUT 3.3 V C3 R1 C6 C4 10 m F 2.2 m F 100 m F LBI R2 LDOIN SKIPEN LDOOUT 1.5 V C5 EN LDOSENSE 2.2 m F List of Components: R7 R9 U1 = TPS61121PW LDOEN L1 = Sumida CDRH73−100 LBO LBO C3, C5, C6, C7, C8 = X7R/X5R Ceramic PGOOD PGOOD C4 = Low ESR Tantalum GND PGND DS1 = BAT54S TPS61121PW Figure29. DualPowerSupplyWithAuxiliaryNegativeOutputVoltage 22 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 10.2.5 SingleOutputUsingLDOasFilter The TPS6112x could provide a linear output of 3.3 V with the input from the output of the boost converter, and deliver200-mAoutputcurrent. U1 L1 SWN 10 m H SWP VBAT VOUT 10 Cm F3 R1 FB R3 22C m6F LBI R2 R6 LDOIN SKIPEN LDOOUT 3.3 V R5 LDOSENSE C5 EN 2.2 m F R7 R9 R4 LDOEN List of Components: LBO LBO U1 = TPS61121PW L1 = Sumida CDRH73−100 PGOOD PGOOD C3, C5 = X7R/X5R Ceramic GND PGND C6 = X7R/X5R Ceramic or Low ESR Tantalum TPS61121PW Figure30. SingleOutputUsingLDOasFilter 10.2.6 DualInputPowerSupplySolution The TPS6112x boost converter can support dual input power supply, one input for boost converter to generate a 3.3 Vout with 500-mA output current, while the other input for LDO to generate the second 3.3 Vout with 200-mA outputcurrent. USB Input 4.2 V...5.5 V D1 U1 L1 SWN 10 m H SWP VBAT VOUT VCC R3 3.3 V System Supply 10 Cm F3 R1 LBI FB 1 MW 2.C2 6m F 10C04 m F R2 LDOIN R6 180 kW SYNC LDOOUT R5 LDOSENSE EN 1.022 MW R7 R8 List of Components: R4 LDOEN 180 kW U1 = TPS61120PW L1 = Sumida CDRH73–100 LBO Control C3, C5, C6 = X7R/X5R Ceramic Outputs PGOOD C4 = Low ESR Tantalum D1 = On-Semiconductor MBR0520 GND PGND TPS61120PW Figure31. DualInputPowerSupplySolution Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 11 Power Supply Recommendations Thedeviceisdesignedtooperatefromaninputvoltagesupplyrangebetween1.8Vand5.5V.Thisinputsupply must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor withavalueof47 μFisatypicalchoice. 12 Layout 12.1 Layout Guidelines As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of groundnoise.ConnectthesegroundnodesatanyplaceclosetooneofthegroundpinsoftheIC. The feedback divider should be placed as close as possible to the control ground pin of the device. To lay out the control ground, using short traces is also recommended, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control groundcurrent. 12.2 Layout Example VIN VIA to Ground Plane RLBI1 VIA to Vin/Vout/PGood/LBO Plane Input Capacitor Inductor RLBI2 GND N GND Low High LInopguict SKIPE LBI VBAT PGND GND EN SWN Boost Output LDOEN SWP Capacitor Exposed PAD LDOIN VOUT LDO Output Capacitor LDOOUT FB RPG RLBO LDO GND LBO PGO S O GND NS D RLDO1 RLDO2 RFB2 RFB1 GND Figure32. LayoutExample 24 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 www.ti.com SLVS427D–JUNE2002–REVISEDMAY2015 12.3 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipationlimitsofagivencomponent. Threebasicapproachesforenhancingthermalperformancearelistedbelow. • ImprovingthepowerdissipationcapabilityofthePCBdesign • ImprovingthethermalcouplingofthecomponenttothePCB • Introducingairflowinthesystem Themaximumjunctiontemperature(T )oftheTPS6112xdevicesis150°C.Thethermalresistanceofthe16-pin J TSSOP package (PW) is R = 100.5°C/W. The 16-pin QFN (RSA) has a thermal resistance of R = ΘJA ΘJA 33.9°C/W, if the thermal pad is soldered and the board layout is optimized. Specified regulator operation is assured to a maximum ambient temperature T of 85°C. Therefore, the maximum power dissipation is about 647 A mW for the TSSOP (PW) package and 1917 mW for the QFN (RSA) package; see Equation 10. More power can bedissipatedifthemaximumambienttemperatureoftheapplicationislower. T -T P = J(MAX) A D(MAX) R qJA (10) If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is lower. Using the above Equation 10 results in 1180 mW power dissipation for the RSA package and 400 mW for thePWpackage. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS61120 TPS61121 TPS61122

TPS61120,TPS61121,TPS61122 SLVS427D–JUNE2002–REVISEDMAY2015 www.ti.com 13 Device and Documentation Support 13.1 Device Support 13.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 13.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 26 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61120 TPS61121 TPS61122

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS61120PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS61120RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS61120PWR TSSOP PW 16 2000 350.0 350.0 43.0 TPS61120RSAR QFN RSA 16 3000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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