(cid:10)(cid:8)(cid:9)(cid:4)(cid:1)(cid:2)(cid:3)(cid:26) (cid:5)(cid:15)(cid:11)(cid:22)(cid:14)(cid:13) (cid:8)(cid:24)(cid:18)(cid:21) (cid:6)(cid:25)(cid:11)(cid:17)(cid:24)(cid:11)(cid:23)(cid:16)(cid:20)(cid:19) (cid:7)(cid:20)(cid:12)(cid:24)(cid:17)(cid:13) User’s Guide March 2000 Mixed-Signal Products SLVU023

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  2000, Texas Instruments Incorporated

Preface Related Documentation From Texas Instruments (cid:0) TPS60140, TPS60141 Low Power DC-DC Converter Regulated 5 V, 100-mA Charge Pump Voltage Tripler (TI Literature Number SLVS273) provides detailed information on the TPS60140 and TPS60141 devices. (cid:0) Erich Bayer, Alexander Müller, Hans Schmeller, and Günter Sporer: Charge Pump Technology Optimized for Battery Operated Systems, EE–Times Special Seminar Series, Analog and Mixed Signal Technology, San Jose, October 1999 FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks TI and PowerPAD are trademarks of Texas Instruments Incorporated. Chapter Title—Attribute Reference iii

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Running Title—Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Basic Operation of a Voltage Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Description of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Physical Data of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Schematic of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Layout of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 Setup of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 3 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Low Battery Detection Resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Figures 1–1 Charge Pump Voltage Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2–1 Schematic of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2–2 Placement of the Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2–3 Top Layer of the EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 3–1 Resistive Divider at LBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Tables 2–1 Bill of Materials of the TPS60120 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3–1 Recommended Values for the LBI Resistive Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3–2 Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Contents v

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Chapter 1 Introduction The evaluation module (EVM) for the new Texas Instruments (TI) charge pump device TPS60140 (TPS60140EVM–144) helps designers to evaluate the device. The TPS6014x charge pumps (also called switched capacitor dc/ dc converters) are regulated voltage triplers. The TPS6014x devices generate an output voltage of 5 V from two NiCd, NiMH or alkaline battery cells. With this EVM it is possible to evaluate the performance of the device. For op- eration, you only need either a battery pack or a dc source in the appropriate voltage range. The board layout of charge pumps is critical, similar to the layout of inductive dc/dc converters. Therefore, the layout given in this EVM user’s guide can be used as a reference design and should provide a good tool to reduce evalua- tion time for the designer. Topic Page 1.1 Basic Operation of a Voltage Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1.2 Description of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Introduction 1-1

Basic Operation of a Voltage Tripler 1.1 Basic Operation of a Voltage Tripler The TPS6014x charge pumps operate as a regulated voltage tripler, therefore the functionality of an unregulated voltage tripler is described with a short de- scription of the used regulation scheme. A description of the EVM follows. Figure 1–1 shows the basic block diagram of a charge pump that operates as a voltage tripler. Everything that is shaded is part of the TPS6014x devices. All the capacitors are external, therefore a minimum of four capacitors is re- quired. Figure 1–1.Charge Pump Voltage Tripler S5 S1 S3 VIN CIN C1F S6 C2F S2 S4 S7 OSC Control VOUT COUT In a charge pump, the oscillator is running with a duty cycle of 50%. One oscil- lator cycle can be divided in two phases: phase 1 where the flying capacitors are charged and phase two in which the flying capacitors are discharged into the output capacitor. In phase 1 the flying capacitors are charged with the input voltage up to a maximum of V , and the switches S to S are closed. Both IN 1 4 flying capacitors C and C are charged in parallel and therefore both are 1F 2F charged to V . In phase 2 the flying capacitors are placed in series to the input IN voltage, and the switches S to S are closed. The output capacitor C can 5 7 OUT be charged up to 3 times the input voltage V as long as there are no losses IN in the system. Hence the name of this charge pump topology: voltage tripler. The TPS6014x charge pumps are regulated charge pumps, therefore a con- trol circuit is part of the device. This control circuit controls the output voltage. The output voltage is divided with an internal resistive divider. The divided por- tion of the output voltage is compared to the internal reference voltage and this control signal controls the oscillator and the switches. Only a short description of the regulation scheme is given, for more detailed information refer to the re- lated documents section in the preface of this user’s guide. 1-2 Introduction

Description of the EVM The regulation is done with an improved pulse-skip mode. This mode skips pulses or cycles, as long as the output voltage is above 5 V. Then it activates the switches again and switches as long as the output voltage is below 5 V. With high loads an additional regulation is used to improve the voltage ripple performance of the device. The output resistance is used to regulate the cur- rent given to the output. Only the minimum necessary current to sustain a regu- lated output voltage is given through the device. The TPS6014x delivers an output voltage of 5.0 V. For an input voltage of 2.0 V to 3.6 V, the maximum continuous output current is 100 mA and for an input of 1.8 V to 2.0 V, the maximum is 50 mA. The devices can be disabled with the ENABLE pin. This limits the supply current to 0.1 m A and disconnects the input from the output. The TPS60140 additionally has a low battery detector (LBI input and LBO out- put) on-chip that can be programmed externally with a resistive divider. The resistive divider has to be connected to the LBI pin. The LBO pin then gives a digital low signal if the voltage on the LBI pin is below 1.21 V ±5%. If the volt- age on the LBI pin is above 1.21 V ±5%, then the LBO pin is high-impedance. Therefore a 100 kW to 1 MW resistor has to be connected between the LBO pin and the output voltage. The TPS60141 has a power good detector (PG out- put) instead of the low-battery detector. The PG output is high-impedance if the output voltage is above 5 V – 10%. For more details please refer to the datasheet (literature number SLVS273). 1.2 Description of the EVM The EVM is built up using the TPS60140 with all necessary external parts for optimized operation. The minimum number of external charge pump capacitors is four. The EVM is built up with six external capacitors for optimized performance. To reduce the spikes during turnover from the transfer phase (charging of the output ca- pacitor) to the charging phase (charging of the transfer or flying capacitors) and vice versa, a small ceramic capacitor (100 nF) is in parallel to the bigger ones at the input and output. Additional resistors and a capacitor at LBI and LBO are added. The capacitors have to be ceramic capacitors. The ESR of all other capacitor types is too high. For the flying capacitors, the criterion is to use ceramic capacitors. For high frequencies, all other capacitors do not remain at their capacitance value. The TPS60140 EVM can also be used to evaluate the other device of this fami- ly (TPS60141). For that purpose replace the integrated circuit. The LBI resis- tors can be removed, but it is not necessary. The LBO pullup resistor works as PG pullup, LBO pad gives the PG signal. Introduction 1-3

1-4 Introduction

Chapter 2 Physical Data of the EVM This chapter shows the schematic and the layout of the EVM. The layout of a charge pump is critical. The given layout can be used as a reference and helps the designer to reduce evaluation time. Topic Page 2.1 Schematic of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Layout of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 2.3 Setup of the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Physical Data of the EVM 2-1

Schematic of the EVM 2.1 Schematic of the EVM Figure 2–1 shows the schematic of the EVM. For this EVM only ceramic capac- itors are used. Capacitors C5 and C6 are bypass capacitors that filter the spikes during turnover from transfer to charging phase and vice versa. Figure 2–1.Schematic of the EVM R1 IN LBI 357 kW R2 619 kW IC1 ENABLE 1 20 C7 GND GND 100 nF IN 1 2 GND GND 19 R3 3 18 ENABLE LBI 1 MW 4 17 OUT FB LBO LBO 1 5 16 IN OUT OUT OUT IN TPS60140 6 15 1 C1+ C2+ C2 C1 2.2 m F 7 IN IN 14 2.2 m F OUT 16 V 8 13 16 V C1– D C2– C4 9 PGND erPA PGND 12 10C05 nF 160.3 m VF w 10 PGND Po PGND 11 IN C3 C6 4.7 m F 100 nF 10 V Table 2–1.Bill of Material of the TPS60140 EVM Component Value Part Number Manufacturer Description C1, C2 2.2 m F, 16V EMK316BJ225KL–T Taiyo Yuden Ceramic flying capacitors C3 4.7 m F, 10V LMK316BJ475KL–T Taiyo Yuden Ceramic input capacitor C4 10 m F, 6.3V JMK316BJ106ML–T Taiyo Yuden Ceramic output capacitor C5, C6 100 nF Ceramic bypass capacitors at input and output C7 100 nF Filter capacitor for the LBI input signal R1 357 kW E96–Series LBI input voltage adjustment R2 619 kW E96–Series LBI input voltage adjustment R3 1 MW Pull up for the open drain output LBO Table 2–1 contains the bill of material of the TPS60140EVM–144. The follow- ing paragraph describes the use of some of the parts. 2-2 Physical Data of the EVM

Schematic of the EVM R1/R2 adjust the input voltage of the LBI input for low battery detection. For the sum of these two resistors, a value of 100 kW to 1 MW is recommended. The resistive divider on the EVM is connected to the input voltage V . For the IN given resistor values, the LBO signal will go active (high) if the input voltage is below 2 V. C7 works as a filter capacitor for the LBI input voltage. This capac- itor is recommended if line or load transients occur, because at the switching point of the LBI comparator, noise at the input can trigger the LBO and this can lead to oscillations at the LBO pin. Since the LBO output, which signalizes a low battery state, is an open drain output, it requires an external pull up resistor (R3). For R3 a value between 100kW and 1MW is recommended. In case your application does not require low battery detection these four parts can be omitted. For the input and output of the voltage there are two six-pin connectors on the board. The first three pins of each are the supply pins (In or Out) and the last three pins of each are the ground (GND) pins. The three-pin connector can be used to connect the ENABLE pin of the device. The connector has the supply (In) signal at the first pin, the logic signal (con- nection to the ENABLE pin) at the second pin and the ground (GND) signal at the third pin. This way it is possible to use jumpers to connect the pin either to input (supply voltage) to enable the device, or to ground to disable the de- vice. It is also possible to connect any other signal by using an external signal source and connecting it to the second pin. The ENABLE pin is a logic level CMOS input, for specifications of the levels please refer to the datasheet. The value of the signal connected to the logic pins can be higher than the supply voltage, but must not exceed the maximum ratings (see the TPS60140 and TPS60141 datasheet for the maximum ratings). Applying a logic low level to the ENABLE input turns off the device and disconnects the output from the input. The output capacitor is not discharged via the device. In this state the supply current decreases to 0.1m A. For normal operation connect the ENABLE signal to the input voltage or a logic high level respectively. Physical Data of the EVM 2-3

Layout of the EVM 2.2 Layout of the EVM Figure 2–2 and 2–3 show the placement of the components and the layout of the EVM. The components and all signals are exclusively placed on the top layer of the PC board. To provide optimal performance the bottom layer is a solid plane (only interrupted by some vias) connected to GND. Figure 2–2.Placement of the Components (cid:6)(cid:4)(cid:5)(cid:3)(cid:0)(cid:1)(cid:2)(cid:0) Figure 2–3.Top Layer of the EVM (cid:6)(cid:4)(cid:5)(cid:3)(cid:0)(cid:1)(cid:2)(cid:0) 2-4 Physical Data of the EVM

Setup of the EVM The device has the PowerPAD on the bottom (an exposed leadframe that can be soldered with the board to reduce the thermal resistance RQ CA from case to ambient). On the EVM, the PowerPAD is not soldered to make it easier to replace the soldered TPS60140 with a TPS60141. On the EVM and below the PowerPAD is an open copper plate connected to GND. Measurements have shown that this thermal connection of the IC is suf- ficient, as long as the device is not operated at extreme points, e.g., high ambi- ent temperature (50°C and above) or constantly at the absolute maximum con- tinuous output current. Nevertheless, it is recommended that the PowerPAD be soldered if possible. Table 2–1 contains the values and description of all 7 capacitors and 3 resis- tors that are placed on the EVM. The required space for the IC and all external parts on the EVM is approximate- ly 15 mm × 25 mm = 375 mm2. The EVM is not optimized for space, the pads for the capacitors can be reduced and they can be placed narrower to the IC. This EVM was not designed to make it easy to solder other (bigger) capacitors for evaluation purposes. 2.3 Setup of the EVM For proper operation of the EVM, please follow these few steps: 1) Make sure that the enable (EN) input is either properly jumpered or con- nected to an external source. 2) Connect a load to the output (between GND and Out). > 50 W or 0 mA to 100 mA for 2 V ≤ V ≤ 3.6 V IN > 100 W or 0 mA to 50 mA for 1.8 V ≤ V < 2 V IN 3) Connect a dc power supply (or a battery pack) with an appropriate voltage between input (In), and ground (GND). 1.8 V ≤ V ≤ 3.6 V IN Physical Data of the EVM 2-5

2-6 Physical Data of the EVM

Chapter 3 Component Selection This chapter provides details on selecting the external components for a power supply built with the TPS6014x device. Topic Page 3.1 Low Battery Detection Resistor Selection . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Capacitor Selection and Accompanying Measurements . . . . . . . . . . 3-3 Component Selection 3-1

Low Battery Detection Resistor Selection 3.1 Low Battery Detection Resistor Selection The resistive divider of the low battery detector (LBI) on the EVM is connected between the input voltage V and GND. With the given resistive values, the IN threshold on the EVM is set to 2 V. With the formulas below and Table 3–1 given in this section, other threshold values can be set. There is additionally a capacitor with 100 nF in parallel to the resistor R . Line 2 or load transients can lead to changes in the input voltage and when these changes are bigger than the hysteresis of the LBI comparator (multiplied with the factor of the resistive divider) the LBO output will toggle. The capacitor is used to eliminate this toggling. Figure 3–1.Resistive Divider at LBI VIN R1 LBI C7 R2 The following two formulas can be used to calculate the resistive divider for low battery detection. First the sum of the resistors has to be fixed. It is recommended to use a value between 100 kW and 1 MW for this sum. With these values, the current flowing into the LBI pin can be neglected. Nevertheless, the lower the sum of the two resistor values, the lower is the influence in input current changes of the LBI pin. Lower values can also be used, but the current drawn from the input voltage (e.g. the battery) increases with decreasing resistor values. V trip R2 (cid:3) (cid:4)R1(cid:1)R2(cid:5)(cid:0) V IN R1 (cid:3) (cid:4)R1(cid:1)R2(cid:5)(cid:2)R2 The tolerance of the LBI threshold is given in the datasheet with 1.15 V ≤ V ≤ 1.27V. (LBI) Now the tolerance of the input trip voltage with a given tolerance of the resis- tors of the resistive divider can be calculated with the following two formulas: R1,min(cid:1)R2,max Vtrip(min) (cid:3) VLBI,min(cid:0) R 2,max R1,max(cid:1)R2,min Vtrip(max) (cid:3) VLBI,max(cid:0) R 2,min 3-2 Component Selection

Capacitor Selection Table 3–1 shows possible values for the resistors of the resistive divider. The resistors are taken from the E96-series and have therefore a tolerance of 1%. The sum of the resistors was chosen to around 1 MW . Table 3–1.Recommended Values for the LBI Resistive Divider V /V R /kW R /kW V /V V /V Bat 1 2 trip(min) trip(max) 1.8 357 732 1.700 (–5.56%) 1.902 (+5.67%) 1.9 365 634 1.799 (–5.32%) 2.016 (+6.11%) 2.0 412 634 1.883 (–5.85%) 2.112 (+5.6%) 2.1 432 590 1.975 (–5.95%) 2.219 (+5.67%) 2.2 442 536 2.080 (–5.45%) 2.338 (+6.27%) 3.2 Capacitor Selection For the maximum output current and best performance, the capacitors placed on the EVM are recommended ones to use. For lower currents or higher al- lowed output voltage ripple, smaller ceramic capacitors can also be used (see Table 3–2). Table 3–2.Capacitor Selection Load Current, Flying Capacitors, Input Capacitor, Output Capacitor, Output Voltage Ripple, I /mA C /m F C /m F C /m F V /mV LOAD xF IN OUT P–P 0–100 2.2 4.7 10 40 0–100 2.2 4.7 22 18 0–100 2.2 2.2 10 130 0–50 2.2 4.7 4.7 40 All capacitors used in Table 3–2 are ceramic capacitors with X7R or X5R mate- rial. With other types of capacitors, especially at the outputs, the output voltage ripple will increase. Component Selection 3-3

3-4 Component Selection