TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 (cid:0) Independent Dual Channels DBT PACKAGE (cid:0) (TOP VIEW) Hysteretic Control for Fast Transient Response INV1 1 30 LH1 (cid:0) 4.5-V to 25-V Input Voltage Range NC 2 29 OUT1_u (cid:0) Adjustable Output Voltage Down to 1.2 V SOFTSTART1 3 28 LL1 (cid:0) NC 4 27 OUT1_d Synchronous Rectifier Enables Efficiencies C 5 26 OUTGND1 T of >95% NC 6 25 TRIP1 (cid:0) Minimized External Component Count GND 7 24 V SENSE CC (cid:0) Separate Standby Control and Over Current REF 8 23 TRIP2 Protection STBY1 9 22 Vref5 (cid:0) STBY2 10 21 REG5V_IN Low Supply Current...0.8 mA Typ (cid:0) VCC 11 20 OUTGND2 30-Pin TSSOP COMP 12 19 OUT2_d (cid:0) Low Standby Current (1-µA maximum) SOFTSTART2 13 18 LL2 (cid:0) NC 14 17 OUT2_u EVM Available (TPS5602EVM-121) INV2 15 16 LH2 description NC – No internal connection The TPS5602 is a dual-channel synchronous buck switch-mode power supply controller featuring very fast feedback control and minimized component count. By using the hysteretic control method, it is ideal for high-transient current applications, such as ’C6000 and multiple ’C54x DSPs. The TPS5602 is designed specifically for DSP applications that require high efficiency. Since both channels are independent, the up and down power sequencing can be easily achieved by properly setting the standby pins. The wide input voltage and adjustable output voltage make the TPS5602 suitable for many applications. typical design 5 V + C3 GND D1 R3 R2 C4 OUT1 L1 1.8 V C1 C7 R5 C2 R6 C8 R1 L2 OUT2 C5 R4 3.3 V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 AVAILABLE OPTIONS PACKAGE TA TSSOP EVM (DBT) TPS5602IDBT –4400°°CC ttoo 8855°°CC TTPPSS55660022EEVVMM-112211 TPS5602IDBTR functional block diagram SFT1 SOFT START1 LH1 INV1 Hysteretic Comp. OUT1_u DLY LL1 1.185 V OUT1_d Setup trigger DLY OUTGND1 Current Comp. TRIP1 OSC on CT OSC VccSENSE Current Protection Fixed off–time reset Trigger Trigger on 1.1 V Comp TRIP2 GND Setup trigger Current Comp. OUTGND2 UVLO OUT2_d DLY INV2 3.8 V LL2 Out2_u Hysteretic Comp. DLY LH2 1.185 V VREF5 SFT2 SOFT START2 Vcc STBY1 Vref STBY2 REF 1.185 V 4.5 V REG5Vin 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. COMP 12 I/O Voltage monitor comparator input CT 5 I/O The oscillator frequency external capacitor connection GND 7 Control GND INV1 1 I CH1 hysteretic comparator inverting input INV2 15 I CH2 hysteretic comparator inverting input LH1 30 I/O CH2 high-side gate drive boost capacitor input LH2 16 I/O CH1 high-side gate drive boost capacitor input LL1 28 I/O CH1 high-side drive and current protection LL2 18 I/O CH2 high-side drive and current protection NC 2, 4, 6, 14 OUT1_d 27 I/O CH1 low-side gate drive output OUT2_d 19 O CH2 low-side gate drive output OUT1_u 29 O CH1 high-side switch output OUT2_u 17 O CH2 high-side switch output OUTGND1 26 Output GND 1 OUTGND2 20 Output GND 2 REF 8 O 1.185-V reference voltage output REG5V_IN 21 I External 5-V input SOFTSTART1 3 I/O CH1 soft start control external capacitor connection SOFTSTART2 13 I/O CH2 soft start control external capacitor connection STBY1 9 I CH1 standby control STBY2 10 I CH2 standby control TRIP1 25 I CH1 output current control input TRIP2 23 I CH2 output current control input VCC 11 I Supply voltage input Vref5 22 O 5-V internal regulator output VCCSENSE 24 I Supply voltage sense input detailed description vref (1.185 V) The reference voltage is used for the output voltage setting and the voltage protection (COMP). vref (5 V) An internal linear voltage regulator offers a fixed 5-V voltage as the bootstrap voltage so that the design for the bootstrap is much easier. The tolerance is 6%. The extra current capability can also be used to power external circuitry. 5-V switch If the internal 5-V switch senses a 5-V input from REG5V pin, the internal 5-V linear regulator will be disconnected from the MOSFET drivers. The external 5-V will be used for the low-side driver and the high-side bootstrap, thus increasing the efficiency. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 detailed description (continued) hysteretic comparator Each channel has a hysteretic comparator to regulate the output voltage of the synchronous-buck converter. The hysteresis is set internally and is typically 8.5 mV. The total delay from the comparator input to the driver output is typically 500 ns from low to high and 350 ns from high to low. low-side driver The low-side driver is designed to driver low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5V from Vref5. The current rating of the driver is typically 1 A, source and sink. high-side driver The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from the Vref5, limiting the maximum drive voltage between OUTxU and LLx to 5 V. The maximum voltage that can be applied between LHx and OUTGNDx is 30 V. deadtime control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turnon time of the MOSFETs drivers. The typical deadtime from low-side-driver-off to high-side-driver-on is 75 ns and 164 ns from high-side-driver-off to low-side-driver-on. current protection The current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during on-time through V Sense and LLx pins. An external resistor between Vin and TRIPx pin with the internal CC current source connected to the current comparator negative input adjusts the current limit. The typical internal current source current is 15 µA. When the voltage on the positive pin is lower than the negative pin, the current comparator turns on the trigger, and then activates the oscillator. This oscillator repeatedly resets the trigger until the overcurrent condition is removed. The equation for the external resistor selection is: Rds(on)(cid:0)(Itrip(cid:1)Iind(p-p)(cid:3)2) Rclmt(cid:2) 0.000015 Where Rds(on) is the MOSFET turnon resistance; Itrip is the required trip current; Iind(p-p) is the peak-to-peak inductor ripple current. Itrip must be greater than 0.5×Iind(p-p). The tolerance is ±30%. COMP COMP is an internal comparator used for any voltage protection such as the output under-voltage protection for DSP power applications. If the core voltage is lower than the setpoint, the comparator turns off both channels to prevent the DSP from damage. SOFT1, SOFT2 Separate soft-start terminals make it possible to set the sequencing of each output for any possibility. The capacitor value for a start-up time can be calculated by the following equation: C = 2 × T (µF) Where C is the external capacitor value, T is the required start-up time in (ms). STBY1, STBY2 Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current is less than 1 µA. The STBY pins can be used for sequencing. UVLO When the input voltage rises to about 3.8 V, the IC is turned on, ready to function. When the input voltage falls below the turnon value, the IC is turned off. The typical hysteresis is 149 mV. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V CC Input voltage, V, INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V I Softstart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V REG5V_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V TRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V Maximum Driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Output voltage, LLx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V Output voltage, OUTx_u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 32 V Output voltage, OUTx_d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Power dissipation (T = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Table A Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C A Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND terminal. DISSIPATION RATING TABLE TA = 25°C TA ≥ 25°C TA = 85°C PACKAGE POWER DISSIPATION DERATING FACTOR POWER DISSIPATION DBT 874 mW 6.993 mW/°C 454 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 25 V INV1/2 6 COMP 6 SOFTSTART1/2 6 Input voltage, VI REG5V_IN 5.5 V STBY1/STBY2 12 TRIP1/2 2255 VCC_SENCE Operation junction temperature range, TA –40 85 °C electrical characteristics over recommended T = –40°C to 85°C temperature range, V = 7 V A CC (unless otherwise noted) reference voltage PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C, Ivref = 50 µA 1.167 1.185 1.203 VVreff RReeffeerreennccee vvoollttaaggee VV VI = 4.5 V to 25 V, I = 1 µA to 1 mA 1.155 1.215 VI(Regin) Line regulation VCC = 5.5 V to 25 V, I = 50 µA 0.2 12 mV VI(Regl) Load regulation I = 1 µA to 1 mA, 0.5 10 mV POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 quiescent current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Operating current without switching Both STBY >2.5 V, No switching 0.8 1.5 mA VI = 4.5 V to 25 V I(CCS) Stand-by current Both STBY <0.5 V, VI = 4.5 V to 25 V 1 1000 nA hysteretic comparator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vhys† Hysteresis window 5.5 8.5 11.5 mV VH(off) Offset voltage 2 mV IH(bias) Bias current 10 pA t(HLT), t(LHT) TTL input signal 230 t(LH) Propagation delay from INV to OUTxU‡‡ 500 650 ns 1100 mmVV oovveerrddrriivvee oonn hhyysstteerreettiicc bbaanndd ssiiggnnaall t(HI) 350 500 †Vhys is assured by design. ‡The delay time in the table includes the driver. driver deadtime PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(DRVLH) Low side to high side 90 nnss t(DRVHL) High side to low side 160 standby PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IH High-level input voltage 2.5 V SSTTBBYY11, SSTTBBYY22 IL Low-level input voltage 0.5 V Tturn-on 7.2 PPrroopaaggaattiioonn ddeellaayy SSttaabbyy ttoo ddrriivveerr oouuttpuutt µµss Tturn-off 4.8 5 V regulator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage I = 10 mA 4.7 5.3 V VI(Regin) VCC = 5.5 V to 25 V, I = 10 mA 20 LLooaadd rreegguullaattiioonn mmVV VI(Regl) I = 1 mA to 10 mA, VCC = 5.5 V 40 IOS Short-circuit output current Vref = 0 V 80 mA 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 electrical characteristics over recommended free-air temperature range, V = 7 V (unless CC otherwise noted) (continued) 5-V internal switch PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VTLH 4.2 4.9 TThhrreesshhoolldd vvoollttaaggee VV VTHL 4.1 4.7 Rson On-time resistance 2.5 8 Ω Vhys Hysteresis 50 250 mV current limit PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal current source 10 15 20 µA Input offset voltage 2.5 mV UVLO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(TLH) 3.6 4.2 TThhrreesshhoolldd vvoollttaaggee VV V(THL) 3.5 4.1 Hysteresis 50 250 mV driver output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUT_u sink current VO = 3 V 0.5 1.2 AA OUT_u source current VO = 2 V –1 –1.7 OUT_d sink current VO = 3 V 0.5 1.2 AA OUT_d source current VO = 2 V –1 –1.7 High side driver is GND referenced, CL = 2200 pF 25.6 RRiissee ttiimmee IInnpuutt:: IINNVV == 00 VV –– 33 VV, nnss tr/tf = 10 ns, Frequency = 200 kHz, CL = 3300 pF 30.8 High side driver is GND referenced, CL = 2200 pF 23.2 FFaallll ttiimmee IInnpuutt:: IINNVV == 00 VV –– 33 VV, nnss tr/tf = 10 ns, Frequency = 200 kHz, CL = 3300 pF 25.2 Softstart PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(CTRL) Softstart current 1.8 2.5 3 µA Maximum discharge current 0.92 mA COMP† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Threshold voltage 1 1.1 1.25 V Turn on Propaggation delayy 50% dutyy cyycle,, 452 FFrreeqquueennccyy == 220000 kkHHzz nnss No capacitor on COMP or OUT_u pin, Turn off 384 †The delay time in the table includes the drivers. oscillator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency without Ct 202.4 kHz Frequency with Ct Ct = 100 pF 67.5 kHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 TYPICAL CHARACTERISTICS QUIESCENT CURRENT (BOTH CHANNELS ON) QUIESCENT CURRENT (BOTH CHANNEL STANDBY) vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 950 160.0 140.0 900 TJ = 125°C µnt –A 850 TJ = 25°C nt – nA 120.0 rre rre 100.0 TJ = 125°C u u ent C 800 TJ = –40°C ent C 80.0 c c es 750 es Qui Qui 60.0 – – on) 700 off) 40.0 q ( I( I 650 20.0 TJ = 25°C TJ = –40°C 600 0.0 4.5 7.0 25.0 4.5 7.0 10.0 15.0 20.0 25.0 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 1 Figure 2 DRIVE OUTPUT VOLTAGE DRIVE VOLTAGE vs vs DRIVE CURRENT (SOURCE) DRIVE CURRENT (SINK) 6 3.5 TJ = –40°C 3 5 V ge – V age – 2.5 Output Volta 34 TJ = 25°C TJ = 125°C Output Volt 2 TJ = 25°C r er 1.5 e v – Drivc) 2 – Drink) 1 TJ = 125°C V(sr 1 V(s 0.5 TJ = –40°C 0 0 0.1 0.5 1 0.1 0.5 1 I(src) – Driver Source Current – A I(sink) – Driver Sink Current – A Figure 3 Figure 4 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 TYPICAL CHARACTERISTICS SOFTSTART CAPACITANCE CURRENT-PROTECTION SOURCE CURRENT vs vs SOFTSTART TIMING SUPPLY VOLTAGE 1 14.0 A µ F – µce – rrent 13.8 TJ = 125°C n u a C pacit 0.1 urce 13.6 art Ca on So 13.4 TJ = 25°C Softst otecti 13.2 – Pr start) 0.01 urrent- 13.0 TJ = –40°C C( C – 12.8 p) I(tri 0.001 12.6 1 10 100 4.5 7.0 10.0 15.0 20.0 25.0 T(start) – Softstart Timing – ms VCC(trip) – Supply Voltage – V Figure 5 Figure 6 STANDBY THRESHOLD VOLTAGE (H–L) UVLO HYSTERESIS VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 2.5 0.20 0.18 V age – 2.0 V 0.16 eshold Volt 1.5 s Voltage – 00..1124 hr si 0.10 T e y 1.0 er db yst 0.08 n H Sta OL 0.06 – V y) 0.5 U 0.04 b st V( 0.02 0.0 –40 –20 0 25 50 70 95 125 0.00 –40 –20 0 25 50 70 95 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 TYPICAL CHARACTERISTICS UVLO THRESHOLD VOLTAGE STANDBY THRESHOLD (L–H) vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 3.80 2.5 3.78 V – 3.76 ge 2.0 V a – olt e 3.74 V g d olta 3.72 hol 1.5 V s d re shol 3.70 – Th re 3.68 y) 1.0 h b O T 3.66 V(st L V U 3.64 0.5 3.62 3.60 0.0 –40 –20 0 25 50 70 95 125 –40 –20 0 25 50 70 95 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 9 Figure 10 SOFT START CHARGE CURRENT VREF5 VOLTAGE vs vs JUNCTION TEMPERATURE VREF5 CURRENT 5.1 –3.0 –2.5 5.0 TJ = 125°C µA TJ = 25°C – V ent –2.0 e – 4.9 r g e Cur Volta 4.8 TJ = –40°C g –1.5 – ar 5 h F C E art –1.0 VR 4.7 st oft S 4.6 –0.5 4.5 0.0 0 –10 –20 –30 –40 –50 –40 –20 0 25 50 70 95 125 TJ – Junction Temperature – °C Vref5 – Current – mA Figure 11 Figure 12 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION 1.8 V 3.3 V V 3 A 3. 3 O V V 8 A 1. 4 V VI 5–9 5 A m a r g a Di c 15 ti a R8 R9 15 em h c S M INV1LH1 NCOUT1LLL1SOFTSTART1OUT1DNC CtOUTGND1 NCTRIP1GNDVCCSENSEREFTRIP2 VREF5STBY15VinSTBY2VCCOUTGND2 OUT2DCOMPSOFTSTART2LL2 NCOUT2UINV2LH2 ure 13. EV g Fi Open POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION application for DSP power The design shown in this data sheet is a reference design for a DSP application. An evaluation module (EVM), TPS5602EVM-121 (SLVP121), is available for customer testing and evaluation. The intent is to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. The input voltage for this EVM is from 4.5 V to 9 V. The outputs are 1.8 V at 4 A and 3.3 V at 3 A. By changing few components this EVM can be used for different operating specifications such as high-input voltage. This application provides the following power supply sequence: the core power goes up before the I/O supply, and if the core power is brought down by abnormal condition, the I/O power will be brought down with it. To help the customers to design the power supply using the TPS5602, key design procedures are shown below: switching frequency With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and the turn on resistance of high side and low side MOSFET. It is a very complex equation if everything is included. To make it more useful to the designers, a simplified equation only considers the most influential factors. The tolerance of this equation is about 30%: Vout(cid:0)(Vin(cid:2)Vout)(cid:0)(cid:5)ESR(cid:2)(cid:5)10(cid:0)10(cid:2)7(cid:1)Td(cid:6)(cid:4)Cout(cid:6) ƒ s(cid:3) Vin(cid:0)(cid:5)Vin(cid:0)ESR(cid:0)(cid:5)10(cid:0)10–7(cid:1)Td(cid:6)(cid:1)0.007(cid:0)Lout(cid:2)ESL(cid:0)Vin(cid:6) Where ƒs is the switching frequency (Hz); Vout is the output voltage (V); Vin is the input voltage (V); Cout is the output capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent series inductance in the output capacitor (H); Lout is the output inductance (H); and Td is the output feedback filter time constant (S). Example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF: ESR = 40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs Then, the frequency fs = 122 kHz. output inductor ripple current The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the output capacitor selection. The equation is exhibited below: Vin(cid:2)Vout(cid:2)Iout(cid:0)(cid:5)Rdson(cid:1)RL(cid:6) Iripple(cid:3) (cid:0)D(cid:0)Ts Lout Where Iripple is the peak-to-peak ripple current through the inductor (A); Vin is the input voltage (V); Vout is the output voltage (V); Iout is the output current; Rdson is the on-time resistance of MOSFET (Ω); D is the duty cycle; and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value. Example: Vin = 5 V, Vout = 1.8 V, Iout = 5 A: Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 mS; Lout = 6 µH Then, the ripple current Iripple = 2 A. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION application for DSP power (continued) output capacitor RMS current Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the output capacitor can be calculated as: (cid:0)I Io(rms)(cid:3) (cid:7)12 Where Io(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak–to–peak inductor ripple current (A). Example: ∆I = 2 A, so Io(rms) = 0.58 A input capacitor RMS current Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as: Ii(rms)(cid:3)Io(cid:0)(cid:5)D(cid:0)(cid:7)(1(cid:2)D)(cid:1)(1(cid:2)D)(cid:0)(cid:7)D(cid:6) Where Ii(rms) is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle. From the equation, it can be seen that the highest input RMS current usually occurs at lowest input voltage. Example: Io = 5 A; D = 0.36 Then, Ii(rms) = 3.36 A softstart The softstart timing can be adjusted by selecting the softstart capacitor value. The equation is C = 2 × T soft soft Where Csoft is the softstart capacitance (µF); Tsoft is the start-up time pin (S). Example: Tsoft = 5 ms, so Csoft = 0.01 µF. current protection The current protection in TPS5602 is set using an internal current source and an external resistor to set up the current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point; if the voltage drop exceeds the limit, the internal oscillator is activated, and continuously resets the current limit until the over-current condition is removed. The equation below should be used for calculating the external resistor value for current protection: Rds(on)(cid:0)(Itrip(cid:1)Iind(p-p)(cid:4)2) Rclmt(cid:3) 0.000015 Where Rclmt is the external current limit resistor (R10, R11); Rds(on) is the high side MOSFET on resistance; Itrip is the required current limit; lind(p-p) is the peak-to-peak output inductor current. Example: Rds(on) = 10 mΩ, Itrip = 5 A, Lind = 2 A, so Rclmt = 4 kΩ. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION application for DSP power (continued) sequencing and under voltage protection The EVM design uses the standby pins to implement power sequencing. There are two ways to achieve the protection: one uses a voltage supervisory circuit such as the TI TPS3305-18, the other uses a low cost comparator, such as the TI TLV1391. The standby pin for the second channel is pulled low by either the supervisory circuit or the external protection comparator until the first channel output voltage is above the start-up threshold voltage. With the protection hysteresis, during the power down, if the core voltage is lower than, for example, 1.3 V, the 3.3 output will be pulled down together. During the normal operation, if the core voltage is lost, the I/O voltage will be pulled down at the same time. This protection circuit prevents the DSPs from any damage caused by the malfunctioning power supply. The equation displayed below uses the comparator for the protection setpoint: Assuming R16 is much larger than R17, and R19 is 10 kΩ, and the R13 value is adjusted for the turnon setpoint: (Von(cid:2)1.2)(cid:0)(cid:5)R16(cid:4)R19(cid:6) R13(cid:3) 1.2 Where Von is the required turn on setpoint. For the turn-off setpoint, R16 is adjusted, R13(cid:0)R19(cid:0)(1.2(cid:2)Vin) R16(cid:3) R19(cid:0)(Voff(cid:2)1.2)(cid:2)1.2(cid:0)R13 By solving these equations together, or using a spreadsheet to iterate, the setpoints can be easily derived. The two equations are used for the verification: Von(cid:3)1.2(cid:0)(R13(cid:1)(cid:5)R16(cid:4)R19(cid:6) and Voff(cid:3)R13(cid:0)(cid:5)1.2(cid:2)Vin(cid:1) 1.2 (cid:1) 1.2(cid:6) (cid:5)R16(cid:4)R19(cid:6) R16 R19 R13 Where Von and Voff are the turnon and turnoff setpoints respectively Example can be found by using the numbers in the bill of materials. layout considerations Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult than most general PCB designs. The general design should proceed from the switching node to the output, then back to the driver section and, finally, placing the low-level components. Below are several specific points to consider before layout of a TPS5602 design begins. (cid:0) All sensitive analog components should be referenced to ANAGND. These include components connected to Vref5, Vref, INV, LH, and COMP. (cid:0) Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect to the ground side of the bulk storage capacitors on V , and drive ground will connect to the main ground O plane close to the source of the low-side FET. (cid:0) Connections from the drivers to the gate of the power FETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used. (cid:0) The bypass capacitor for V should be placed close to the TPS5602. CC 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION layout considerations (continued) (cid:0) When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should be as short and as wide as possible. (cid:0) When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5602. (cid:0) When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND. (cid:0) The bulk storage capacitors across V should be placed close to the power FETs. High-frequency bypass IN capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side FET and to the source of the low-side FET. (cid:0) High-frequency bypass capacitors should be placed across the bulk storage capacitors on V . O (cid:0) LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH and LL should be routed very close to each other to minimize differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to where HISENSE connects to V , to IN reduce high-frequency noise coupling on HISENSE. (cid:0) The output voltage sensing trace should be isolated from the switching node and/or inductor pulses by the use of a ground trace or plane. test results The tests are conducted at T = 25°C, the input voltage is 5 V (if not specifically noted). A 3.3-V OUTPUT EFFICIENCY 1.8-V OUTPUT EFFICIENCY 98 95 96 90 94 92 85 % 90 % – – 80 y 88 y c c n n cie 86 cie 75 Effi 84 Effi 82 70 80 65 78 76 60 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IO – Output Current – A IO – Output Current – A Figure 14 Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION COMBINED SYSTEM EFFICIENCY 3.3-V OUTPUT LOAD REGULATION 94 3.32 I(1.8) = 4 A 93 I(3.3) = 3 A 92 3.315 V – % 91 e ag Efficiency 8990 Output Volt 3.31 – O 88 V 3.305 87 86 3.3 10 20 30 40 50 60 70 80 90 100 0 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Percentage of Output Current on Both Channels – % IO – Output Current – A Figure 16 Figure 17 1.8-V OUTPUT LOAD REGULATION 3.3-V LINE REGULATION 1.8 3.35 3.34 1.795 V V e – e – 3.33 g g a a olt olt V V ut 1.79 ut 3.32 p p ut ut O O – – 3.31 O O V 1.785 V 3.3 1.78 3.29 0 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 4.5 5 7 9 11 13 15 17 19 21 23 25 IO – Output Current – A VI – Input Voltage – V Figure 18 Figure 19 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION 1.8-V OUTPUT LINE REGULATION OUTPUT VOLTAGE RIPPLE 1.805 1.8 V – 1.795 50 mV/div e g a ∆V = 48 mV olt V ut 1.79 p ut O – 1.785 O V 1.78 VI = 5 V 5 µs/div 1.775 4.5 5 7 9 11 13 15 17 19 21 23 25 VI – Input Voltage – V Figure 20 Figure 21 POWER-UP SEQUENCING POWER-DOWN SEQUENCING 3.3 V 200 ms 3.3 V 1 V/div 1 V/div 1.8 V 1.8 V VI = 5 V 100 ms/div 1 ms/div Figure 22 Figure 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION TRANSIENT RESPONSE (OVERSHOOT) 90 A/µs 1 A/div ∆ = 100 mV 100 mV/div 5 µs/div Figure 24 TRANSIENT RESPONSE (UNDERSHOOT) 6.5 A/µs 1 A/div ∆V = 75 mV 100 mV/div 5 µs/div Figure 25 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION Table 1. SLVP121 Bill of Materials REF. PART NUMBER MFR. DESCRIPTION SIZE C1† Open C2 Std Capacitor, ceramic, 470 pF,16 V, X7R, 20% 805 C3 Std Capacitor, ceramic, 2200 pF,16 V, X7R, 20% 805 C4 GRM235Y5V106Z016A muRata Capacitor, ceramic, 10 µF, 16 V, Y5V 1210 C5† Open 805 C6 Std Capacitor, ceramic, 1 µF, 16 V, X7R, 20% 1206 C7 Std Capacitor, ceramic, 2200 pF, 16 V, X7R, 20% 805 C8 Std Capacitor, ceramic, 2200 pF, 16 V, X7R, 20% 805 C9 GRK316F225ZG Taiyo Yuden Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20% 1206 C11 GRK316F225ZG Taiyo Yuden Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20% 1206 C12 GRK316F225ZG Taiyo Yuden Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20% 1206 C13† Std Open 805 C14† Std Open 805 C15 10TPB220M SANYO Capacitor, electrolytic, 220 µF, 10 V, 20% 10×10 mm C16 2R5TPB680M SANYO Capacitor, POSCAP, 680 µF, 2.5 V, 20% 7.3×4.3 mm C17 4TPB470M SANYO Capacitor, POSCAP, 470 µF, 4 V, 20% 7.3×4.3 mm C18 GMK325F106ZH Taiyo Yuden Capacitor, ceramic, 10 µF, 35 V 1210 C21 GMK325F106ZH Taiyo Yuden Capacitor, ceramic, 10 µF, 35 V 1210 D1 SD103-AWDICT-ND Digikey Diode, Schottky, 40 mA, 200 mA, 400 mW 3.5×1.5 mm D2 SD103-AWDICT-ND Digikey Diode, Schottky, 40 mA, 200 mA, 400 mW 3.5×1.5 mm J1 S1132-12-ND Sullins Header, right angle, 12-pin, 0.1 ctrs, 0.3” pins Digikey, S1132–12–ND L2 DO3316P-682 Coilcraft Inductor, 6.8 µH, 4.4 A 0.5x0.37 in L3 DO3316P-103 Coilcraft Inductor 10 µH, 3.9 A 0.5x0.37 in Q1–Q4 Si441DY Rev. A Siliconix MOSFET, N-Ch, 30 V, 10-A, 0.013 Ω SO–8 R1 Std Resistor, SMD, MF, 1.74 kΩ, 1/8W, 1% 805 R4 Std Resistor, SMD, MF, 680 Ω, 1/8W, 1% 805 R6 Std Resistor, SMD, MF, 910 Ω, 1/8W, 1% 805 R7 Std Resistor, SMD, MF, 1.21 kΩ, 1/8W, 1% 805 R8 Std Resistor, SMD, MF, 15 Ω, 1/8W, 5% 805 R9 Std Resistor, SMD, MF, 15 Ω, 1/8W, 5% 805 R10 Std Resistor, SMD, MF, 5.1 kΩ, 1/8W, 5% 805 R11 Std Resistor, SMD, MF, 5.1 kΩ, 1/8W, 5% 805 R13† Std Open, resistor, SMD, MF, 3.3 kΩ, 1/8W, 5% 805 R14 Std Open, resistor, SMD, MF, kΩ, 1/8W, 5% 805 R15† Std Open, resistor, SMD, MF, 1 kΩ, 1/8W, 5% 805 R16† Std Open, resistor, SMD, MF, 200 kΩ, 1/8W, 5% 805 R17† Std Open, resistor, SMD, MF, 10 kΩ, 1/8W, 5% 805 R18† Std Open, resistor, SMD, MF, 1 kΩ, 1/8W, 5% 805 R19† Std Open, resistor, SMD, MF, 10 kΩ, 1/8W, 5% 805 R20† Std Open, resistor, SMD, MF, 0 kΩ 805 U1 TPS5602DBT TI Dual channel controller TSSOP 30-pin U2† TLV1391 TI Open, single Comparator SOT-23 U3 TPS3305-18D TI Supervisor D NOTE: This table is for 5–9 V input voltage and 3.3 V/1.8 V only. †Any components with † are for optional test purpose only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION To change the EVM operating specifications, several suggestions are shown in the following table. HIGH INPUT VOLTAGE LOW-COST POWER 2.5 V OUTPUT VOLTAGE COMPONENT SECOND SOURCE (TO 25 V) SEQUENCING Change R1 to 1 kΩ Remove U3 Q1–4 IR7811 for higher efficiency Add R15 (1 kΩ) Change Rt to 1.2 kΩ Add U2 Change C15 to ELNA Change U3 to TPS3305-25D Add R13, R16, R17, R19 RV-35V221MH10-R (35 V, 220 µF) TOP SIDE BOTTOM SIDE 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION BOARD ASSEMBLY POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 APPLICATION INFORMATION Power Supply Load 5–V, 5–A Supply 0 – 5 A – + Load 0 – 5 A NOTE: All wire pairs should be twisted. Figure 26. Test Setup 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5602 DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER SLVS217 – JUNE 1999 MECHANICAL DATA DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 30 PINS SHOWN 0,27 0,50 0,08 M 0,17 30 16 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 1 15 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 28 30 38 44 50 DIM A MAX 7,90 7,90 9,80 11,10 12,60 A MIN 7,70 7,70 9,60 10,90 12,40 4073252/D 09/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-153 except for pin count and body length POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2008 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty TPS5602IDBT ACTIVE TSSOP DBT 30 60 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) TPS5602IDBTG4 ACTIVE TSSOP DBT 30 60 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) TPS5602IDBTR ACTIVE TSSOP DBT 30 2000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) TPS5602IDBTRG4 ACTIVE TSSOP DBT 30 2000 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2009 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) TPS5602IDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2009 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS5602IDBTR TSSOP DBT 30 2000 346.0 346.0 33.0 PackMaterials-Page2

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