Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 TPS560200 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With Advanced Eco-Mode™ 1 Features 3 Description • IntegratedMonolithic0.95-Ω High-Sideand0.33- The TPS560200 is an 17-V, 500-mA, low-Iq, adaptive 1 on-time D-CAP2 mode synchronous monolithic buck ΩLow-SideMOSFETs converter with integrated MOSFETs in easy-to-use 5- • 500-mAContinuousOutputCurrent pinSOT-23package. • OutputVoltageRange:0.8Vto6.5V The TPS560200 lets system designers complete the • 0.8-VVoltageReferenceWith ±1.3%Accuracy suite of various end-equipment power bus regulators OverTemperature with a cost-effective, low component count and low • Auto-SkipAdvanced Eco-Mode™forHigh standby current solution. The main control loop for EfficiencyatLightLoads the device uses the D-CAP2 mode control that provides a fast transient response with no external • D-CAP2™ModeEnablesFastTransient compensation components. The adaptive on-time Responses control supports seamless transition between PWM • NoExternalCompensationNeeded mode at higher load conditions and advanced Eco- • 600-kHzSwitchingFrequency Modeoperationatlightloads. • 2-msInternalSoft-Start The TPS560200 also has a proprietary circuit that • SafeStart-UpintoPrebiasedVOUT enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as • ThermalShutdown POSCAP or SP-CAP, and ultra-low ESR ceramic • –40°Cto125°COperatingJunctionTemperature capacitors. The device operates from 4.5-V to 17-V Range VIN input. The output voltage can be programmed • Availablein5-PinSOT-23Package between 0.8 V and 6.5 V. The device also features a fixed 2-ms soft-start time. The device is available in 2 Applications the 5-pinSOT-23package. • SetTopBoxes DeviceInformation(1) • Modems PARTNUMBER PACKAGE BODYSIZE(NOM) • DTBs TPS560200 SOT(5) 2.90mm×1.60mm • ASDLs (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic VIN Lo VOUT VIN PH Cin Co R1 EN VSENSE R2 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription...................................................7 2 Applications........................................................... 1 7.4 DeviceFunctionalModes..........................................9 3 Description............................................................. 1 8 ApplicationandImplementation........................ 10 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................10 8.2 TypicalApplication .................................................10 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 14 6 Specifications......................................................... 4 10 Layout................................................................... 14 6.1 AbsoluteMaximumRatings .....................................4 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................14 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................14 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 15 6.5 ElectricalCharacteristics...........................................4 11.1 DeviceSupport......................................................15 6.6 TypicalCharacteristics..............................................6 11.2 Trademarks...........................................................15 7 DetailedDescription.............................................. 7 11.3 ElectrostaticDischargeCaution............................15 7.1 Overview...................................................................7 11.4 Glossary................................................................15 7.2 FunctionalBlockDiagram.........................................7 12 Mechanical,Packaging,andOrderable Information........................................................... 15 4 Revision History ChangesfromRevisionB(February2015)toRevisionC Page • DeletedSWIFT™fromthedatasheettitle ........................................................................................................................... 1 ChangesfromRevisionA(Janurary2015)toRevisionB Page • RemovednotefromENABLE(ENPIN)toindicatethattheparametersareproductiontested ........................................... 5 ChangesfromOriginal(September2013)toRevisionA Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection. ................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 5 Pin Configuration and Functions DBVPackage 5-PinSOT-23 (TopView) EN 1 5 VSENSE GND 2 PH 3 4 VIN PinFunctions PIN I/O DESCRIPTION NAME NO. EN 1 I Enablepin.Floattoenable GND 2 — Returnforcontrolcircuitryandlow-sidepowerMOSFET PH 3 O Theswitchnode VIN 4 I Suppliesthecontrolcircuitryofthepowerconverter VSENSE 5 I Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS560200

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) MIN MAX UNIT VIN –0.3 20 Inputvoltage EN –0.3 7 VSENSE –0.3 3 V PH –0.6 20 Outputvoltage PH10-nstransient –2 20 EN ±100 µA Sourcecurrent PH Currentlimit A Sinkcurrent PH Currentlimit A Operatingjunctiontemperature –40 125 °C Storagetemperature,T –65 150 stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Inputvoltagerange 4.5 17 V I T Operatingjunctiontemperature –40 125 °C J 6.4 Thermal Information TPS560200 THERMALMETRIC(1) DBV UNIT 5Pins R Junction-to-ambientthermalresistance 166.8 θJA R Junction-to-case(top)thermalresistance 100 θJC(top) R Junction-to-boardthermalresistance 75.5 θJB °C/W ψ Junction-to-topcharacterizationparameter 29.2 JT ψ Junction-to-boardcharacterizationparameter 3.7 JB R Junction-to-case(bottom)thermalresistance 28.7 θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics T =–40°Cto125°C,VIN=4.5Vto17V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) VINOperatinginputvoltage 4.5 17 V VINInternalUVLOthreshold VINRising 3.9 4.35 4.5 V VINInternalUVLOhysteresis 200 mV 4 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 Electrical Characteristics (continued) T =–40°Cto125°C,VIN=4.5Vto17V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VINShutdownsupplycurrent EN=0V,VIN=12V 2.0 3.7 9 µA VINOperating–nonswitchingsupplycurrent VSENSE=850mV,VIN=12V 35 60 95 µA ENABLE(ENPIN) Rising 1.16 1.29 V Enablethreshold Falling 1.05 1.13 V InternalSoft-Start VSENSErampsfrom0Vto0.8V 2 ms OUTPUTVOLTAGE 25°C,VIN=12V,VOUT=1.05V,IOUT=5 0.796 0.804 0.812 V mA,Pulse-Skipping 25°C,VIN=12V,VOUT=1.05V,IOUT= 0.792 0.800 0.808 V Voltagereference 100mA,Continuouscurrentmode VIN=12V,VOUT=1.05V,IOUT=100 0.789 0.800 0.811 V mA,Continuouscurrentmode MOSFET High-sideswitchresistance(1)(2) VIN=12V 0.50 0.95 1.50 Ω Low-sideswitchresistance(1) VIN=12V 0.20 0.33 0.55 Ω CURRENTLIMIT LOUT=10µH,Valleycurrent,VOUT=1.05 Low-sideswitchsourcingcurrentlimit 550 650 775 mA V THERMALSHUTDOWN Thermalshutdown 170 °C Thermalshutdownhysteresis 10 °C ON-TIMETIMERCONTROL Ontime VIN=12V 130 165 200 ns Minimumofftime 25°C,VSENSE=0.5V 250 400 ns OUTPUTUNDERVOLTAGEPROTECTION OutputUVPthreshold Falling 56 63 69 %VREF Hiccuptime 15 ms (1) Notproductiontested (2) Measuredatpins Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS560200

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com 6.6 Typical Characteristics V =12V,T =25°C(unlessotherwisenoted). IN A 100 6 EN = 0 V nt (µA) 80 urrent (µA) 45 y Curre 60 down C3 I - SupplCC 2400 ccsdn - Shut12 v I 0 0 –50 0 50 100 150 –50 0 50 100 150 TJ Junction Temperature ((cid:131)C) C001 TJ Junction Temperature ((cid:131)C) C002 Figure1.SupplyCurrentvsJunctionTemperature Figure2.ShutdownCurrentvsJunctionTemperature 40 700 I = 500 mA 675 OUT A) 30 kHz) 650 Current (µ 20 equency ( 660205 put 10 g Fr 575 n n EN I 0 Switchi 550 VOUT = 3.3 V VOUT = 1.05 V VOUT = 1.8 V 525 –10 500 0 2 4 6 8 10 4 6 8 10 12 14 16 18 EN Input Voltage (V) C003 VIN - Input Voltage (V) C004 Figure3.ENInputCurrentvsENInputVoltage Figure4.SwitchingFrequencyvsInputVoltage 800 0.806 I = 100 mA O Hz) 700 0.804 ncy (k 600 e (V) 0.802 g Freque 450000 VOUT = 3.3 V SE Voltag0.800 n N hi 300 E0.798 witc VOUT = 1.05 V VS w - S 200 0.796 s 100 f VOUT = 1.8 V 0.794 0 –50 0 50 100 150 0.0 0.1 0.2 0.3 0.4 0.5 TJ Junction Temperature ((cid:131)C) C006 IO - Output Current (A) C005 Figure5.SwitchingFrequencyvsOutputCurrent Figure6.VSENSEVoltagevsJunctionTemperature 6 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 7 Detailed Description 7.1 Overview The TPS560200 is a 500-mA synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low- ESRoutputcapacitorsincludingceramicandspecialpolymertypes. 7.2 Functional Block Diagram VIN VREF VSENSE VSS HS Drive VREF Soft Start SSDONE EN START VIN XCON PH UVLO VREF Control VIN Logic LS Drive TON One-Shot PGND GND AGND PH Thermal MAL Shutdown ZCD ZCD VTHER Bandgap LS Reference VREF BGOK PVGRNEDF OCP 7.3 Feature Description 7.3.1 PWMOperation The main control loop of the TPS560200 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlow-ESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one-shottimerexpires.Thisoneshotissetbytheconverterinputvoltage,VIN,andtheoutputvoltage,VOUT,to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2modecontrol. Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS560200

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com Feature Description (continued) 7.3.2 PWMFrequencyandAdaptiveOn-TimeControl TPS560200 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS560200 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output voltage to set the on-time, one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the outputvoltage;therefore,whenthedutyratioisVOUT/VIN,thefrequencyisconstant. 7.3.3 AdvancedAuto-SkipEco-ModeControl The TPS560200 is designed with advanced auto-skip Eco-Mode to increase higher light-load efficiency. As the output current decreases from heavy-load condition, the inductor current is also reduced. If the output current is reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time increases as it takes more time to discharge the output capacitor to the level of the reference voltage with smaller load current. The transition point to the light load operation I current can be calculated in OUT(LL) Equation1. 1 (V -V )×V I = × IN OUT OUT OUT(LL) 2×L ×fsw V OUT IN (1) 7.3.4 Soft-StartandPrebiasedSoft-Start The TPS560200 has an internal 2-ms soft-start. When the EN pin becomes high, internal soft-start function beginsrampingupthereferencevoltagetothePWMcomparator. The TPS560200 contains a unique circuit to prevent current from being pulled from the output during start-up if the output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft-start becomes greater than feedback voltage V ), the controller slowly activates synchronous rectification by VSENSE starting the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (V ) starts and OUT ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normalmodeoperation. 7.3.5 CurrentProtection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the PH pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by V , IN V , the on-time and the output inductor value. During the on time of the low-side FET switch, this current OUT decreases linearly. The average value of the switch current is the load current Iout. The TPS560200 constantly monitorsthelow-sideFETswitchvoltage,whichisproportionaltotheswitchcurrent,duringthelow-sideon-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each switching cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in thesamemanner. There are some important considerations for this type of overcurrent protection. The peak current is the average load current plus one half of the peak-to-peak inductor current. The valley current is the average load current minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This protection is nonlatching. When the VSENSE voltage becomes lower than 63% of the target voltage, the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shuts down and re-starts afterhiccuptime. 8 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 Feature Description (continued) Whentheovercurrentconditionisremoved,theoutputvoltagereturnstotheregulatedvalue. 7.3.6 ThermalShutdown TPS560200 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C), thedeviceisshutoff.Thisisnonlatchprotection. 7.4 Device Functional Modes 7.4.1 NormalOperation When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS560200canoperateinitsnormalswitchingmodes.Normalcontinuousconductionmode(CCM)occurswhen the minimum switch current is above 0 A. In CCM, the TPS560200 operates at a quasi-fixed frequency of 600 kHz. 7.4.2 Eco-ModeOperation When the TPS560200 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS560200 begins operating in pulse-skipping Eco-Mode. Each switching cycle is followed by a period of energy-saving sleeptime.ThesleeptimeendswhentheVFBvoltagefallsbelowtheEco-Modethresholdvoltage.Astheoutput currentdecreasestheperceivedtimebetweenswitchingpulsesincreases. 7.4.3 StandbyOperation When the TPS560200 is operating in either normal CCM or Eco-Mode, it may be placed in standby by asserting theENpinlow. Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS560200

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS560200 is used as a step-down converter which converts a voltage of 4.5 V to 17 V to a lower voltage. WEBENCH®softwareisavailabletoaidinthedesignandanalysisofcircuits. 8.2 Typical Application U1 L1 10µH VIN 4.5-17V TPS560200 VOUT1.05V, 0.5A 4 VIN PH 3 C1 C2 C3 C4 R1 C5 10µF 0.1µF 1 EN 10µF 10µF 6.19k open R2 5 VSENSE GND 2 20.0k Figure7. TypicalApplicationSchematic 8.2.1 DesignRequirements Tobeginthedesignprocess,theusermustknowafewapplicationparameters: Table1.DesignParameters PARAMETER VALUES Inputvoltagerange 4.5Vto17V Outputvoltage 1.05V Outputcurrent 500mA Outputvoltageripple 10mV/pp 8.2.2 DetailedDesignProcedure 8.2.2.1 OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1% toleranceorbetterdividerresistors.StartbyusingEquation2tocalculateV . OUT To improve efficiency at light loads, consider using larger value resistors, high resistance is more susceptible to noise,andthevoltageerrorsfromtheVSENSEinputcurrentaremorenoticeable. R1´0.8V R2= V -0.8V OUT (2) 8.2.2.2 OutputFilterSelection TheoutputfilterusedwiththeTPS560200isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L xC OUT OUT (3) 10 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS560200. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable2. Table2.RecommendedComponentValues L1 OutputVoltage R1 R2 C5 C3+C4 (µH) (V) (kΩ) (kΩ) (pF) (µF) MIN TYP MAX 1.0 4.99 20.0 10 10+10 1.05 6.19 20.0 10 10+10 1.2 10.0 20.0 10 10+10 1.5 17.4 20.0 10 10+10 1.8 24.9 20.0 optional 10 10+10 2.5 42.2 20.0 optional 10 10+10 3.3 61.9 20.0 optional 10 10+10 5.0 105 20.0 optional 10 10+10 Because the DC gain is dependent on the output voltage, the required inductor value increases as the output voltage increases. Additional phase boost can be achieved by adding a feed-forward capacitor (C5) in parallel withR1.Thefeed-forwardcapacitorismosteffectiveforoutputvoltagesatorabove1.8V. The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 4, Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 600 kHz for f . SW Use 600 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS SW currentofEquation6. I = VOUT x VIN(max) -VOUT LPP V L x fsw IN(max) OUT (4) I I =I + LPP LPEAK OUT 2 (5) 1 I = I 2 + I 2 LOUT(RMS) OUT 12 LPP (6) For this design example, the calculated peak current is 0.582 A and the calculated RMS current is 0.502 A. The inductorusedisaWürth744777910withapeakcurrentratingof2.6AandanRMScurrentratingof2A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS560200 is intended for usewithceramicorotherlow-ESRcapacitors.TherecommendedvaluesaregiveninTable2.UseEquation7 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V x(V -V ) I = OUT IN OUT COUT(RMS) 12 xVIN xLOUT xfsw (7) For this design two MuRata GRM32DR61E106KA12L 10-µF output capacitors are used. The typical ESR is 2 mΩ each.ThecalculatedRMScurrentis0.047Aandeachoutputcapacitorisratedfor3A. Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS560200

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com 8.2.2.3 InputCapacitorSelection The TPS560200 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF capacitor(C2)from pin4togroundisoptionaltoprovideadditionalhighfrequencyfiltering.Thecapacitorvoltage ratingmustbegreaterthanthemaximuminputvoltage. 8.2.3 ApplicationCurves V =12V,V =1.05V,T =25°C(unlessotherwisenoted). IN OUT A 100 90 90 80 80 70 70 % V = 5 V % 60 ncy - 5600 IN VIN = 12 V ncy - 50 VIN = 5 V VIN = 12 V Efficie 40 Efficie 3400 30 20 20 10 10 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.001 0.01 0.1 1 Output Current - A C015 Output Current - A C016 Figure8.Efficiency Figure9.Light-LoadEfficiency 1.5 0.50 V = 5 V 0.40 IN 1.0 0.30 Regulation - % 00..05 VIN = 12 V Regulation - % –0000....10120000 IOUT = 0.25 A Load –0.5 Line –0.20 –1.0 –0.30 –0.40 –1.5 –0.50 0.0 0.1 0.2 0.3 0.4 0.5 4 6 8 10 12 14 16 18 Output Current - A C017 Input Voltage - V C018 Figure10.LoadRegulation Figure11.LineRegulation 60 180 VOUT= 50 mV/div (ac coupled) 40 Phase 120 20 60 es Gain - dB -200 Gain -06 0 hase - Degre IOUT= 200 mA/div P -40 -120 125 mAto 375 mAload step -60 -180 slew rate = 500 mA/ µsec 100 1000 10000 100000 1000000 Frequency - Hz C019 Time = 200 µs/div Figure12.LoopResponse,IOUT=0.25A Figure13.TransientResponse,25%to75%LoadStep 12 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 VIN= 5 V/div VOUT= 50 mV/div (ac coupled) EN = 5 V/div IOUT= 200 mA/div 10 mAto 250 mAload step slew rate = 500 mA/ µsec VOUT= 500 mV/div Time = 200 µs/div Time = 2 ms/div Figure14.TransientResponse,2%to50%LoadStep Figure15.Start-UpRelativetoEN VOUT= 20 mV/div (ac coupled) VOUT= 20 mV/div (ac coupled) PH = 5 V/div PH = 5 V/div Time = 1 µs/div Time = 5 µs/div Figure16.OutputRipple,I =500mA Figure17.OutputRipple,I =30mA OUT OUT VOUT= 20 mV/div (ac coupled) PH = 5 V/div Time = 2 ms/div Figure18.OutputRipple,I =0mA OUT Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS560200

TPS560200 SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 www.ti.com 9 Power Supply Recommendations The TPS560200 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters require the input voltage to be higher than the output voltage for proper operation. The maximum recommended operatingdutycycleis65%.Usingthatcriteria,theminimumrecommendedinputvoltageisVO/0.65. 10 Layout 10.1 Layout Guidelines The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Take care to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN and GND pins of the device. An additional high-frequency bypass capacitor may be added. See Figure 19 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. The PH pin should be routed to a small copper area directly adjacent to the pin. Make the circulating loop from PH to the output inductor, output capacitors and back to GND as tight as possible while preserving adequate etch width to reduce conduction losses in the copper. Connect the exposed thermal pad to bottom or internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top-side copper to the internal or bottom layer copper. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate layout schemes; however, this layoutproducedgoodresultsandisintendedasaguideline. 10.2 Layout Example VIN VIN GND HIGH FREQENCY OUTPUT BYPASS CAPACITOR INDUCTOR VIN PH VOUT VIN INPUT GND BYPASS CAPACITOR VSENSE EN TO ENABLE CONTROL OUTPUT GND FILTER CAPACITOR FEEDBACK GND RESISTORS OPTIONAL FEED FORWARD CAPACITOR VIA to Ground Plane Figure19. LayoutSchematic 14 SubmitDocumentationFeedback Copyright©2013–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS560200

TPS560200 www.ti.com SLVSC81C–SEPTEMBER2013–REVISEDFEBRUARY2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Trademarks Eco-Mode,D-CAP2aretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2013–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS560200

PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS560200DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 L562 & no Sb/Br) TPS560200DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 L562 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS560200 : •Automotive: TPS560200-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Feb-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS560200DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS560200DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Feb-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS560200DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS560200DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/D 11/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/D 11/2018 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/D 11/2018 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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