Typical Size 6,4 mm X 9,7 mm TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 3-V TO 4-V INPUT, 9-A OUTPUT SYNCHRONOUS BUCK PWM ™ SWITCHER WITH INTEGRATED FETs (SWIFT ) FEATURES DESCRIPTION (cid:1) 15-mΩ MOSFET Switches for High Efficiency As a member of the SWIFT™ family of dc/dc regulators, at 9-A Continuous Output the TPS54910 low-input voltage high-output current (cid:1) 0.9-V to 2.5-V Adjustable Output Voltage synchronous buck PWM converter integrates all (cid:1) Externally Compensated With 1% Accuracy required active components. Included on the substrate (cid:1) Fast Transient Response with the listed features are a true, high performance, (cid:1) voltage error amplifier that enables maximum Wide PWM Frequency: performance under transient conditions and flexibility in Fixed 350 kHz, 550 kHz or choosing the output filter L and C components; an Adjustable 280 kHz to 700 kHz (cid:1) under-voltage-lockout circuit to prevent start-up until Load Protected by Peak Current Limit and the input voltage reaches 3 V; an internally and Thermal Shutdown (cid:1) externally set slow-start circuit to limit in-rush currents; Integrated Solution Reduces Board Area and and a power good output useful for processor/logic Total Cost reset, fault signaling, and supply sequencing. APPLICATIONS The TPS54910 is available in a thermally enhanced (cid:1) Low-Voltage, High-Density Systems With 28-pin TSSOP (PWP) PowerPAD™ package, which Power Distributed at 3.3 V eliminates bulky heatsinks. TI provides evaluation (cid:1) Point of Load Regulation for High modules and the SWIFT™ designer software tool to aid Performance DSPs, FPGAs, ASICs and in quickly achieving high-performance power supply Microprocessors designs to meet aggressive equipment development (cid:1) Broadband, Networking and Optical cycles. Communications Infrastructure (cid:1) Portable Computing/Notebook PCs SIMPLIFIED SCHEMATIC EFFICIENCY AT 700 kHz SIMPLIFIED SCHEMATIC 100 95 Input VIN PH Output TPS54910 90 BOOT 85 % PGND y − 80 c VBIAS COMP en 75 ci Effi 70 65 AGND VSENSE 60 VI = 3.3 V, Compensation 55 VO = 2.5 V Network 50 0 1 2 3 4 5 6 7 8 9 10 11 12 IO − Output Current − A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products Copyright © 2002 − 2005, Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA OUTPUT VOLTAGE PACKAGE PART NUMBER −40°C to 85°C 0.9 V to 2.5 V Plastic HTSSOP (PWP)(1) TPS54910PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54910PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS54910 UNIT SS/ENA, SYNC −0.3 to 7 RT −0.3 to 6 IInnppuutt vvoollttaaggee rraannggee,, VVII VSENSE −0.3 to 4 VV VIN −0.3 to 4.5 BOOT −0.3 to 10 VBIAS, COMP, PWRGD −0.3 to 7 OOuuttppuutt vvoollttaaggee rraannggee, VVO PH −0.6 to 6 VV PH Internally Limited SSoouurrccee ccuurrrreenntt, IIO COMP, VBIAS 6 mA PH 16 A SSiinnkk ccuurrrreenntt,, IISS COMP 6 mmAA SS/ENA, PWRGD 10 Voltage differential AGND to PGND ±0.3 V Operating virtual junction temperature range, TJ −40 to 125 °C Storage temperature, Tstg −65 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Input voltage, VI 3 4 V Operating junction temperature, TJ −40 125 °C DISSIPATION RATINGS(1)(2) PACKAGE THERMAL IMPEDANCE TA =25°C TA = 70°C TA = 85°C JUNCTION-TO-AMBIENT POWER RATING POWER RATING POWER RATING 28 Pin PWP with solder 14.4°C/W 6.94 W(3) 3.81 W 2.77 W 28 Pin PWP without solder 27.9°C/W 3.58 W 1.97 W 1.43 W (1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. (2) Test board conditions: 1. 3” x 3”, 4 layers, thickness: 0.062” 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 0.5 oz. copper ground planes on the 2 internal layers 5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet) (3) Maximum power dissipation may be limited by over current protection. 2

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN 3.0 4.0 V fs = 350 kHz, SYNC≤ 0.8 V, RT open, 9.8 17.0 PH pin open I(Q) Quiescent current fs = 550 kHz, SYNC≥ 2.5 V, RT open, 14.0 23.0 mA PH pin open Shutdown, SS/ENA = 0 V 1 1.4 UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO 2.95 3.0 V Stop threshold voltage, UVLO 2.70 2.80 V Hysteresis voltage, UVLO 0.14 0.16 V Rising and falling edge deglitch, UVLO(1) 2.5 µs BIAS VOLTAGE Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 2.90 V Output current, VBIAS (2) 100 µA CUMULATIVE REFERENCE Vref Accuracy 0.882 0.891 0.900 V REGULATION IL = 4.5 A, fs = 350 kHz, TJ = 85°C 0.07 LLiinnee rreegguullaattiioonn((11))((33)) %%//VV IL = 4.5 A, fs = 550 kHz, TJ = 85°C 0.07 IL = 0 A to 9 A, fs = 350 kHz, TJ = 85°C 0.03 LLooaadd rreegguullaattiioonn((11))((33)) %%//AA IL = 0 A to 9 A, fs = 550 kHz, TJ = 85°C 0.03 OSCILLATOR SYNC ≤ 0.8 V, RT open 280 350 420 IInntteerrnnaallllyy sseett—ffrreeee rruunnnniinngg ffrreeqquueennccyy kkHHzz SYNC ≥ 2.5 V, RT open 440 550 660 RT = 180 kΩ (1% resistor to AGND) 252 280 308 EExxtteerrnnaallllyy sseett—ffrreeee rruunnnniinngg ffrreeqquueennccyy rraannggee RT = 100 kΩ (1% resistor to AGND) 460 500 540 kkHHzz RT = 68 kΩ (1% resistor to AGND) 663 700 762 High level threshold, SYNC 2.5 V Low level threshold, SYNC 0.8 V Pulse duration, external synchronization, 50 ns SYNC(1) Frequency range, SYNC(1) 330 700 kHz Ramp valley(1) 0.75 V Ramp amplitude (peak-to-peak)(1) 1 V Minimum controllable on time(1) 200 ns Maximum duty cycle(1) 90% (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 10 3

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1 kΩ COMP to AGND(1) 90 110 dB Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND(1) 3 5 MHz Error amplifier common mode input voltage Powered by internal LDO(1) 0 VBIAS V range Input bias current, VSENSE VSENSE = Vref 60 250 nA Output voltage slew rate (symmetric), COMP 1.0 1.4 V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin 10-mV overdrive(1) 70 85 ns (excluding deadtime) SLOW-START/ENABLE Enable threshold voltage, SS/ENA 0.82 1.2 1.4 V Enable hysteresis voltage, SS/ENA(1) 0.03 V Falling edge deglitch, SS/ENA(1) 2.5 µs Internal slow-start time 2.6 3.35 4.1 ms Charge current, SS/ENA SS/ENA = 0 V 3 5 8 µA Discharge current, SS/ENA SS/ENA = 1.3 V, VI = 1.5 V 1.5 2.3 4.0 mA POWER GOOD Power good threshold voltage VSENSE falling 90 %Vref Power good hysteresis voltage(1) 3 %Vref Power good falling edge deglitch(1) 35 µs Output saturation voltage, PWRGD I(sink) = 2.5 mA 0.18 0.3 V Leakage current, PWRGD VI = 5.5 V 1 µA CURRENT LIMIT Current limit VI = 3.3 V(1), Output shorted 11 15 A Current limit leading edge blanking time 100 ns Current limit total response time 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) 135 150 165 °C Thermal shutdown hysteresis(1) 10 °C OUTPUT POWER MOSFETS rDS(on) PPower MMOOSSFFEETT swiittchhes VVII == 33. 6V (V4)(4) 1154 3208 mΩΩ (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 10 (4) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) production tested. 4

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 PWP PACKAGE (TOP VIEW) AGND 1 28 RT VSENSE 2 27 SYNC COMP 3 26 SS/ENA PWRGD 4 25 VBIAS BOOT 5 24 VIN PH 6 23 VIN PH 7 THERMAL 22 VIN PH 8 PAD 21 VIN PH 9 20 VIN PH 10 19 PGND PH 11 18 PGND PH 12 17 PGND PH 13 16 PGND PH 14 15 PGND TERMINAL FUNCTIONS TERMINAL DDEESSCCRRIIPPTTIIOONN NAME NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD to AGND. BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6−14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or the internal shutdown signal is active. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. SYNC 27 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. VIN 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider. 5

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 INTERNAL BLOCK DIAGRAM AGND VBIAS VIN Enable Comparator SS/ENA VBIAS REG Falling SHUTDOWN 1.2 V Edge ILIM VIN Deglitch Thermal Comparator 3 − 6 V Hysteresis: 0.03 V 2.5 µs Shutdown Leading 150°C Edge VIN UVLO Blanking Comparator Falling 100 ns and VIN Rising BOOT 2.95 V Edge Hysteresis: 0.16 V Deglitch 15 mΩ 2.5 µs SS_DIS SHUTDOWN PH LOUT VO Internal/External Slow-start + (Internal Slow-start Time = 3.35 ms − R Q Adaptive Dead-Time CO and Error S Control Logic Amplifier PWM Reference Comparator VIN VREF = 0.891 V 15 mΩ OSC PGND Powergood Comparator PWRGD VSENSE Falling 0.90 Vref Edge TPS54910 Deglitch Hysteresis: 0.03 Vref SHUTDOWN 35 µs VSENSE COMP RT SYNC RELATED DC/DC PRODUCTS (cid:1) TPS40000—dc/dc controller (cid:1) TPS56300—dc/dc controller (cid:1) PT6600 series—9 A plugin modules 6

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS DRAIN-SOURCE DRAIN-SOURCE INTERNALLY SET ON-STATE RESISTANCE ON-STATE RESISTANCE OSCILLATOR FREQUENCY vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE 25 ΩDrain Source On-State Reststance − m 11205005−40VIOI N= =9 3A.00 V 25 85 125 ΩDrain Source On-State Reststance − m 1122050505−40VIOI N= =9 3A.06 V 25 85 125 f − Internally Set Oscillator Frequency − kHz 234567555555000000−40 SSYYNNCC 0 ≤≥ 02..85 VV 25 85 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 1 Figure 2 Figure 3 EXTERNALLY SET OSCILLATOR FREQUENCY VOLTAGE REFERENCE DEVICE POWER LOSSES vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE LOAD CURRENT Hz 800 0.895 8 y − k 7 VTJI == 31.235 V°C ernally Set Oscillator Frequenc 345670000000000 RRTT == 6180 0k ΩkΩ − Voltage Reference − VVref0000....888888997913 Device Power Losses − W 123456 Ext RT = 180 kΩ − 0.885 0 f 200−40 0 25 85 125 −40 0 25 85 125 0 2 4 6 8 10 12 14 16 TJ − Junction Temperature − °C TJ − Junction Temperature − °C IL − Load Current − A Figure 4 Figure 5 Figure 6 OUTPUT VOLTAGE REGULATION INTERNAL SLOW-START TIME vs ERROR AMPLIFIER vs INPUT VOLTAGE OPEN LOOP RESPONSE JUNCTION TEMPERATURE 0.895 140 0 3.80 put Voltage Regulation − V 000...888899913 Gain − dB110246800000 PhRCTaALLs =e== 211560°0 Ck ΩpF,, −−−−−−11864220000000hase − Degrees Slow-Start Time − ms 3333....23560505 − OutO0.887 20 Gain −−116400P nternal 3.05 V 0 −180 I 2.90 0.885 −20 −200 2.75 3 3.1 3.2 3.3 3.4 3.5 3.6 1 10 100 1 k 10 k 100 k 1 M 10 M −40 0 25 85 125 VI − Input Voltage − V f − Frequency − Hz TJ − Junction Temperature − °C Figure 7 Figure 8 Figure 9 7

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 APPLICATION INFORMATION Figure 10 shows the schematic diagram for a typical thermal PowerPAD underneath the integrated circuit, TPS54910 application. The TPS54910 (U1) can provide TPS54910, package must be soldered to the up to 9 A of output current at a nominal output voltage of printed-circuit board. 1.8 V. For proper thermal performance, the exposed VI C10 C12 U1 10 µF 10 µF TPS54910PWP R6 28 24 RT VIN 71.5 kΩ 23 VIN 27 22 R7 SYNC VIN 10 kΩ VIN 21 C6 26 20 SS/ENA VIN 0.047 µF PH 14 C3 25 13 VBIAS PH 1 µF PH 12 4 PWRGD PH 11 L1 10 0.65 µH C1 C4 PH R2 R3 3 9 1000 pF 301 Ω 10 kΩ 3300 pF COMP PPHH 8 C8 C7 C5 VO C2 7 22 µF 22 µF 22 µF PH R1 6 PH 10 Ω 150 pF 2 VSENSE BOOT 5 C9 PGND 19 0.047 µF 18 PGND R7 R4 17 2.4 Ω PGND 9.76 kΩ 1 16 AGND PGND 15 C11 PGND 3300 pF POWERPAD Analog and Power Grounds Are Tied at the Pad Under the Package of IC Figure 10. Application Circuit COMPONENT SELECTION FEEDBACK CIRCUIT The values for the components used in this design The values for these components are selected to provide example were selected for best load transient response fast transient response times. and small PCB area. Additional design information is The resistor divider network of R1 and R4 sets the output available at www.ti.com. voltage for the circuit at 1.8 V. R1 along with R2, R3, C1, INPUT FILTER C2, and C4 forms the loop compensation network for the circuit. For this design, a Type-3 topology is used. The input voltage is a nominal 3.3 VDC. The input filter (C10) is a 10-µF ceramic capacitor (Taiyo Yuden). C12 is OPERATING FREQUENCY also a 10-µF ceramic capacitor (Taiyo Yuden) that In the application circuit, RT is grounded through a 71.5-kΩ provides high-frequency decoupling of the TPS54910 resistor to select the operating frequency of 700 kHz. To from the input supply. C12 must be located as close as set a different frequency, place a 68-kΩ to 180-kΩ resistor possible to the device. Ripple current is carried in both C10 between RT (pin 28) and analog ground or leave RT and C12, and the return path to PGND must avoid the floating to select the default of 350 kHz. The resistance can current circulating in the output capacitors C5, C7, and C8. be approximated using the following equation: R(cid:1) 500kHz (cid:2)100[k(cid:1)] SwitchingFrequency (1) 8

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 OUTPUT FILTER to the ground area under the device as shown. The only components that should tie directly to the power ground The output filter is composed of a 0.65-µH inductor and plane are the input capacitors, the output capacitors, the 3 x 22-µF capacitor. The inductor is a low dc-resistance input voltage decoupling capacitor, and the PGND pins of (.017 Ω) type, Pulse Engineering PA0277. The capacitors the TPS54910. Use a separate wide trace for the analog used are 22-µF, 6.3-V ceramic types with X5R dielectric. ground signal path. This analog ground should be used for The feedback loop is compensated so that the unity gain the voltage set point divider, timing resistor RT, slow start frequency is approximately 75 kHz. capacitor, and bias capacitor grounds. Connect this trace PCB LAYOUT directly to AGND (Pin 1). The PH pins should be tied together and routed to the Figure 11 shows a generalized PCB layout guide for the output inductor. Since the PH connection is the switching TPS54910. The VIN pins should be connected together on node, the inductor should be located very close to the PH the printed circuit board (PCB) and bypassed with a low pins and the area of the PCB conductor minimized to ESR ceramic bypass capacitor. Care should be taken to prevent excessive capacitive coupling. minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54910 ground Connect the boot capacitor between the phase node and pins. The minimum recommended bypass capacitance is the BOOT pin as shown. Keep the boot capacitor close to 10 µF ceramic with a X5R or X7R dielectric and the the IC and minimize the conductor trace lengths. optimum placement is closest to the VIN pins and the Connect the output filter capacitor(s) as shown between PGND pins. the VOUT trace and PGND. It is important to keep the loop The TPS54910 has two internal grounds (analog and formed by the PH pins, Lout, Cout and PGND as small as power). The analog ground ties to all of the noise−sensitive practical. signals, while the power ground ties to the noisier power Place the compensation components from the VOUT trace signals. Noise injected between the two grounds can to the VSENSE and COMP pins. Do not place these degrade the performance of the TPS54910, particularly at components too close to the PH trace. Due to the size of higher output currents. Ground noise on an analog ground the IC package and the device pinout, the components will plane can also cause problems with some of the control have to be routed somewhat close, but maintain as much and bias signals. For these reasons, separate analog and separation as possible while still keeping the layout power ground traces are recommended. There should be compact. an area of ground on the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Connect the bias capacitor from the VBIAS pin to analog Use vias to connect this ground area to any internal ground ground using the isolated analog ground trace. If a planes. Use additional vias at the ground side of the input slow−start capacitor or RT resistor is used, or if the SYNC and output filter capacitors as well. The AGND and PGND pin is used to select 350 kHz operating frequency, connect pins should be tied to the PCB ground by connecting them them to this trace as well. 9

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 ANALOG GROUND TRACE FREQUENCY SET RESISTOR AGND RT VSENSE SYNC SLOW START CAPACITOR COMPENSATION COMP SS/ENA NETWORK BIAS CAPACITOR PWRGD VBIAS BOOT CAPACITOR BOOT VIN EXPOSED PH POWERPAD VIN VOUT AREA PH VIN PH VIN VIN PH PH VIN PH PGND OUTPUT INDUCTOR PH PGND OUTPUT PH PGND FILTER CAPACITOR PH PGND INPUT INPUT PH PGND BYPASS BULK CAPACITOR FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 11. TPS54910 PCB Layout 10

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 LAYOUT CONSIDERATIONS FOR THERMAL operation is desired. Connection from the exposed area of PERFORMANCE the PowerPAD to the analog ground plane layer must be made using 0.013-inch diameter vias to avoid solder For operation at full rated load current, the analog ground wicking through the vias. plane must provide an adequate heat dissipating area. A 3-inch by 3-inch plane of 1 ounce copper is recommended, Eight vias must be in the PowerPAD area with four though not mandatory, depending on ambient temperature additional vias located under the device package. The size and airflow. Most applications have larger areas of internal of the vias under the package, but not in the exposed ground plane available, and the PowerPAD must be thermal pad area, can be increased to 0.018. Additional connected to the largest area available. Additional areas vias beyond the twelve recommended that enhance on the top or bottom layers also help dissipate heat, and thermal performance must be included in areas not under any area available must be used when 6 A or greater the device package. Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside 8 PL Ø0.0130 Powerpad Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground 4 PL Ø0.0180 Area Is Extended. Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance 0.0150 0.06 0.0339 0.0650 0.0500 0.3820 0.3478 0.0500 0.2090 0.0500 0.0256 0.0650 0.0339 Minimum Recommended Exposed Copper Area for Powerpad. 5mm 0.1700 Stencils May Require 10 Percent 0.1340 Larger Area Minimum Recommended Top Side Analog Ground Area 0.0630 0.0400 Figure 12. Recommended Land Pattern for 28-Pin PWP PowerPAD 11

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 PERFORMANCE GRAPHS EFFICIENCY LOAD REGULATION LINE REGULATION vs vs vs OUTPUT CURRENT OUTPUT CURRENT INPUT VOLTAGE 100 1.003 1.001 95 fs = 700 kHz, 90 1.002 TVAI == 32.53° CV,, 11..00000068 Efficiency − % 6778850505 Load Regulation01..9090910 VO = 1.8 V Line Regulation0011....99009900990016824 IIOO == 94 .5A A fsI O= 7=0 00 AkHz, 5650 fVVsIO == = 73 02.30.5 Vk V,Hz, 0.998 00..99999924 TVVAIO = == 3 21.53.8° CV V,, 50 0.997 0.999 0 1 2 3 4 5 6 7 8 9 10 11 12 0 2 4 6 8 10 3 3.2 3.4 3.6 3.8 4 IO − Output Current − A IO − Output Current − A VI − Input Voltage − V Figure 13 Figure 14 Figure 15 AMBIENT TEMPERATURE vs LOAD CURRENT(1) OUTPUT RIPPLE VOLTAGE TRANSIENT RESPONSE °Ambient Temperature − C 11102134567895555555555 fTVVsJIO = = = = 7 3 101.230.58 V°k VC,H,z, Output Ripple Voltage − 10 mV/div fIVVsOIO === = 793 01 .3A0.8 ,Vk V,Hz, − Output Voltage − 10 mV/divVO VVIO = = 3 1.3.8 V V, 2 A to 6.5 A − Output Current − 2 A/divO I 250 2 4 6 8 10 12 14 16 t − Time − 1 µs/div t − Time − 5 µs/div IO − Output Current − A Figure 16 Figure 17 Figure 18 SLOW-START TIMING v di V/ 1 e − VI = 3.3 V, Voltag 0.047 µfVO = 1.8 V V/div put slow-start capacitor − 1 − In age VI olt V ut p ut O − O V t −Time − 5 ms/div Figure 19 (1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings 12

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 DETAILED DESCRIPTION VBIAS REGULATOR (VBIAS) The VBIAS regulator provides internal analog and digital UNDERVOLTAGE LOCK OUT (UVLO) blocks with a stable supply voltage over variations in The TPS54910 incorporates an under voltage lockout junction temperature and input voltage. A high quality, circuit to keep the device disabled when the input voltage low-ESR, ceramic bypass capacitor is required on the (VIN) is insufficient. During power up, internal circuits are VBIAS pin. X7R or X5R grade dielectrics are held inactive until VIN exceeds the nominal UVLO recommended because their values are more stable over threshold voltage of 2.95 V. Once the UVLO start threshold temperature. The bypass capacitor must be placed close is reached, device start-up begins. The device operates to the VBIAS pin and returned to AGND. until VIN falls below the nominal UVLO stop threshold of External loading on VBIAS is allowed, with the caution that 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs internal circuits require a minimum VBIAS of 2.70V, and rising and falling edge deglitch circuit reduce the likelihood external loads on VBIAS with ac or digital switching noise of shutting the device down due to noise on VIN. may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. SLOW-START/ENABLE (SS/ENA) VOLTAGE REFERENCE The slow-start/enable pin provides two functions. First, the The voltage reference system produces a precise V ref pin acts as an enable (shutdown) control by keeping the signal by scaling the output of a temperature stable device turned off until the voltage exceeds the start bandgap circuit. During manufacture, the bandgap and threshold voltage of approximately 1.2 V. When SS/ENA scaling circuits are trimmed to produce 0.891 V at the exceeds the enable threshold, device start-up begins. The output of the error amplifier, with the amplifier connected reference voltage fed to the error amplifier is linearly as a voltage follower. The trim procedure adds to the high ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the precision regulation of the TPS54910, since it cancels converter output voltage reaches regulation in offset errors in the scale and error amplifier circuits. approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of OSCILLATOR AND PWM RAMP triggering the enable due to noise. The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a The second function of the SS/ENA pin provides an static digital input. If a different frequency of operation is external means of extending the slow-start time with a required for the application, the oscillator frequency can be low-value capacitor connected between SS/ENA and externally adjusted from 280 to 700 kHz by connecting a AGND. resistor between the RT pin to ground and floating the Adding a capacitor to the SS/ENA pin has two effects on SYNC pin. The switching frequency is approximated by start-up. First, a delay occurs between release of the the following equation, where R is the resistance from RT SS/ENA pin and start-up of the output. The delay is to AGND: proportional to the slow-start capacitor value and lasts SwitchingFrequency(cid:1)100k(cid:1)(cid:2)500[kHz] (4) until the SS/ENA pin reaches the enable threshold. The R start-up delay is approximately: External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving 1.2 V (2) t (cid:1)C (cid:2) a synchronization signal into SYNC and connecting a d (SS) 5 (cid:2)A resistor from RT to AGND. Choose a RT resistor that sets the free running frequency to 80% of the synchronization Second, as the output becomes active, a brief ramp-up at signal. The following table summarizes the frequency the internal slow-start rate may be observed before the selection configurations: externally set slow-start rate takes control and the output SWITCHING rises at a rate proportional to the slow-start capacitor. The SYNC PIN RT PIN FREQUENCY slow-start time set by the capacitor is approximately: 350 kHz, internally set Float or AGND Float 550 kHz, internally set ≥2.5 V Float 0.7 V (3) t(SS)(cid:1)C(SS)(cid:2) 5 (cid:2)A Externally set 280 Float R = 68 kΩ to 180 kΩ kHz to 700 kHz Externally R = RT value for 80% The actual slow-start time is likely to be less than the above synchronized Synchronization of external synchro- signal approximation due to the brief ramp-up at the internal rate. frequency nization frequency 13

TPS54910 www.ti.com SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005 ERROR AMPLIFIER during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver The high performance, wide bandwidth, voltage error does not turn on until the voltage at the gate of the low-side amplifier sets the TPS54910 apart from most dc/dc FET is below 2 V. While the low-side driver does not turn converters. The user is given the flexibility to use a wide on until the voltage at the gate of the high-side MOSFET range of output L and C filter components to suit the is below 2 V. particular application needs. Type-2 or Type-3 compensation can be employed using external The high-side and low-side drivers are designed with compensation components. 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied PWM CONTROL from VIN, while the high-side drive is supplied from the Signals from the error amplifier output, oscillator, and BOOT pin. A bootstrap circuit uses an external BOOT current limit circuit are processed by the PWM control capacitor and an internal 2.5-Ω bootstrap switch logic. Referring to the internal block diagram, the control connected between the VIN and BOOT pins. The logic includes the PWM comparator, OR gate, PWM latch, integrated bootstrap switch improves drive efficiency and and portions of the adaptive dead-time and control-logic reduces external component count. block. During steady-state operation below the current OVERCURRENT PROTECTION limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once The cycle-by-cycle current limiting is achieved by sensing the PWM latch is set, the low-side FET remains on for a the current flowing through the high-side MOSFET and minimum duration set by the oscillator pulse width. During comparing this signal to a preset overcurrent threshold. this period, the PWM ramp discharges rapidly to its valley The high side MOSFET is turned off within 200 ns of voltage. When the ramp begins to charge back up, the reaching the current limit threshold. A 100-ns leading edge low-side FET turns off and high-side FET turns on. As the blanking circuit prevents current limit false tripping. PWM ramp voltage exceeds the error amplifier output Current limit detection occurs only when current flows from voltage, the PWM comparator resets the latch, thus VIN to PH when sourcing current to the output filter. Load turning off the high-side FET and turning on the low-side protection during current sink operation is provided by FET. The low-side FET remains on until the next oscillator thermal shutdown. pulse discharges the PWM ramp. THERMAL SHUTDOWN During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the The device uses the thermal shutdown to turn off the power PWM peak voltage. If the error amplifier is high, the PWM MOSFETs and disable the controller if the junction latch is never reset, and the high-side FET remains on until temperature exceeds 150°C. The device is released from the oscillator pulse signals the control logic to turn the shutdown automatically when the junction temperature high-side FET off and the low-side FET on. The device decreases to 10°C below the thermal shutdown trip point, operates at its maximum duty cycle until the output voltage and starts up under control of the slow-start circuit. rises to the regulation set-point, setting VSENSE to Thermal shutdown provides protection when an overload approximately the same voltage as VREF. If the error condition is sustained for several milliseconds. With a amplifier output is low, the PWM latch is continually reset persistent fault condition, the device cycles continuously; and the high-side FET does not turn on. The low-side FET starting up by control of the soft-start circuit, heating up due remains on until the VSENSE voltage decreases to a to the fault condition, and then shutting down upon range that allows the PWM comparator to change states. reaching the thermal shutdown trip point. This sequence The TPS54910 is capable of sinking current continuously repeats until the fault condition is removed. until the output reaches the regulation set-point. POWER-GOOD (PWRGD) If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the The power good circuit monitors for under voltage error amplifier output. The high-side FET turns off and conditions on VSENSE. If the voltage on VSENSE is 10% low-side FET turns on to decrease the energy in the output below the reference voltage, the open-drain PWRGD inductor and consequently the output current. This output is pulled low. PWRGD is also pulled low if VIN is process is repeated each cycle in which the current limit less than the UVLO threshold or SS/ENA is low. When VIN comparator is tripped. ≥ UVLO threshold, SS/ENA ≥ enable threshold, and VSENSE > 90% of V , the open drain output of the DEAD-TIME CONTROL AND MOSFET ref PWRGD pin is high. A hysteresis voltage equal to 3% of DRIVERS V and a 35 µs falling edge deglitch circuit prevent ref Adaptive dead-time control prevents shoot-through tripping of the power good comparator due to high current from flowing in both N-channel power MOSFETs frequency noise. 14

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54910PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54910 & no Sb/Br) TPS54910PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54910 & no Sb/Br) TPS54910PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54910 & no Sb/Br) TPS54910PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54910 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 22-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54910PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 22-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54910PWPR HTSSOP PWP 28 2000 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW PWP 28 PowerPADTM TSSOP - 1.2 mm max height 4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224765/A www.ti.com

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