6,4 mm X 9,7 mm TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK PWM ™ SWITCHER WITH INTEGRATED FETS (SWIFT ) FEATURES DESCRIPTION (cid:1) 30-mΩ MOSFET Switches for High Efficiency As a member of the SWIFT™ family of dc/dc regulators, at 8-A Continuous Output the TPS54810 low-input voltage high-output current (cid:1) 0.9-V to 3.3-V Adjustable Output Voltage synchronous buck PWM converter integrates all Range With 1% Accuracy required active components. Included on the substrate (cid:1) Externally Compensated with the listed features are a true, high performance, (cid:1) Fast Transient Response voltage error amplifier that enables maximum (cid:1) Wide PWM Frequency: performance under transient conditions and flexibility in Fixed 350 kHz, 550 kHz or choosing the output filter L and C components; an Adjustable 280 kHz to 700 kHz under-voltage-lockout circuit to prevent start-up until (cid:1) the input voltage reaches 3.8 V; an internally or Load Protected by Peak Current Limit and externally set slow-start circuit to limit in-rush currents; Thermal Shutdown (cid:1) and a power good output useful for processor/logic Integrated Solution Reduces Board Area and reset, fault signaling, and supply sequencing. Total Cost The TPS54810 is available in a thermally enhanced APPLICATIONS 28-pin TSSOP (PWP) PowerPAD™ package, which (cid:1) Low-Voltage, High-Density Systems With eliminates bulky heatsinks. TI provides evaluation Power Distributed at 5 V modules and the SWIFT™ designer software tool to aid (cid:1) Point of Load Regulation for High in quickly achieving high-performance power supply Performance DSPs, FPGAs, ASICs and designs to meet aggressive equipment development Microprocessors cycles. (cid:1) Broadband, Networking, and Optical Communications Infrastructure (cid:1) Portable Computing/Notebook PCs EFFICIENCY AT 700 HZ SIMPLIFIED SCHEMATIC 100 VI = 5 V Input Output 95 VO = 3.3 V VIN PH 90 TPS54810 BOOT 85 % PGND − 80 y VBIAS enc 75 VSCEONMSEP Effici 70 65 VSENSE 60 AGND 55 50 Compensation Network 0 1 2 3 4 5 6 7 8 9 10 IL − Load Current − A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products Copyright © 2002, Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA OUTPUT VOLTAGE PACKAGE PART NUMBER −40°C to 85°C 0.9 V to 3.3 V PLASTIC HTSSOP (PWP)(1) TPS54810PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54810PWPR). See the application section of the data sheet for PowerPAD™ drawing and layout information. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS54810 UNIT VIN, SS/ENA, SYNC −0.3 to 7 RT −0.3 to 6 IInputt vollttaage raange, VVI VSENSE −0.3 to 4 VV BOOT −0.3 to 17 VBIAS, COMP, PWRGD −0.3 to 7 OOuttputt vollttaage raange, VVO PH −0.6 to 10 VV PH Internally Limited SSource currentt, IIO COMP, VBIAS 6 mA PH 12 A SSiinnkk ccuurrrreenntt,, IISS COMP 6 mAA SS/ENA, PWRGD 10 Voltage differential AGND to PGND ±0.3 V Operating virtual junction temperature range, TJ −40 to 125 °C Storage temperature, Tstg −65 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Input voltage range, VI 4 6 V Operating junction temperature, TJ −40 125 °C DISSIPATION RATINGS(1) (2) PACKAGE THERMAL IMPEDANCE TA ≤ 25°C TA = 70°C TA = 85°C JUNCTION-TO-AMBIENT POWER RATING POWER RATING POWER RATING 28-Pin PWP with solder 18.2 °C/W 5.49 W(2) 3.02 W 2.20 W 28-Pin PWP without solder 40.5 °C/W 2.48 W 1.36 W 0.99 W (1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. (2) Test Board Conditions: 1. 3” x 3”, 4 layers, thickness: 0.062” 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 0.5 oz. copper ground planes on the 2 internal layers 5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet) (3) Maximum power dissipation may be limited by over current protection. 2

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN 4.0 6.0 V fs = 350 kHz, SYNC≤ 0.8 V, RT open, 11 15.8 PH pin open I(Q) Quiescent current fs = 550 kHz, SYNC≥ 2.5 V, RT open, 16 23.5 mA PH pin open Shutdown, SS/ENA = 0 V 1.0 1.4 UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO 3.8 3.85 V Stop threshold voltage, UVLO 3.40 3.50 V Hysteresis voltage, UVLO 0.14 0.16 V Rising and falling edge deglitch, UVLO (1) 2.5 µs BIAS VOLTAGE Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 2.90 V Output current, VBIAS (2) 100 µA CUMULATIVE REFERENCE Vref Accuracy 0.882 0.891 0.900 V REGULATION LLiinnee rreegguullaattiioonn((11)) ((33)) IILL == 44 AA,, ffss == 355500 kkHHzz,, TTJJ == 8855°°CC 00..0044 %%//VV LLooaadd rreegguullaattiioonn((11)) ((33)) IILL == 00 AA ttoo 88 AA,, ffss == 355500 kkHHzz,, TTJJ == 8855°°CC 00..0033 %%//AA OSCILLATOR SYNC ≤ 0.8 V, RT open 280 350 420 IInntteerrnnaallllyy sseett—ffrreeee rruunnnniinngg ffrreeqquueennccyy rraannggee kkHHzz SYNC ≥ 2.5 V, RT open 440 550 660 RT = 180 kΩ (1% resistor to AGND) 252 280 308 EExxtteerrnnaallllyy sseett—ffrreeee rruunnnniinngg ffrreeqquueennccyy rraannggee RT = 100 kΩ (1% resistor to AGND) 460 500 540 kkHHzz RT = 68 kΩ (1% resistor to AGND) 663 700 762 High level threshold, SYNC 2.5 V Low level threshold, SYNC 0.8 V Pulse duration, external sychronization, SYNC (1) 50 ns Frequency range, SYNC (1) 330 700 kHz Ramp valley (1) 0.75 V Ramp amplitude (peak-to-peak) (1) 1 V Minimum controllable on time (1) 200 ns Maximum duty cycle (1) 90% (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 9 3

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS CONTINUED TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain 1 kΩ COMP to AGND(1) 90 110 dB Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND(1) 3 5 MHz Error amplifier common mode input voltage Powered by internal LDO(1) 0 VBIAS V range Input bias current, VSENSE VSENSE = Vref 60 250 nA Output voltage slew rate (symmetric), COMP 1.0 1.4 V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead- 10-mV overdrive(1) 70 85 ns time) SLOW-START/ENABLE Enable threshold voltage, SS/ENA 0.82 1.20 1.40 V Enable hysteresis voltage, SS/ENA (1) 0.03 V Falling edge deglitch, SS/ENA (1) 2.5 µs Internal slow-start time 2.6 3.35 4.1 ms Charge current, SS/ENA SS/ENA = 0V 3 5 8 µA Discharge current, SS/ENA SS/ENA = 1.3 V, VI = 1.5 V 1.5 2.3 4.0 mA POWER GOOD Power good threshold voltage VSENSE falling 90 %Vref Power good hysteresis voltage(1) 3 %Vref Power good falling edge deglitch(1) 35 µs Output saturation voltage, PWRGD I(sink) = 2.5 mA 0.18 0.3 V Leakage current, PWRGD VI = 3.6 V 1 µA CURRENT LIMIT VI = 4.5 V(1), output shorted 9 11 CCuurrrreenntt lliimmiitt AA VI = 6 V(1), output shorted 10 12 Current limit leading edge blanking time 100 ns Current limit total response time 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) 135 150 165 (cid:2)C Thermal shutdown hysteresis(1) 10 (cid:2)C OUTPUT POWER MOSFETS rDS(on) PPower MMOOSSFFEETT swiittchhes VVII == 46. 5V (V2)(2) 2360 4670 mΩΩ (1) Specified by design (2) Matched MOSFETs, low-side rDS(on) production tested, high-side rDS(on) production tested. 4

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 PWP PACKAGE (TOP VIEW) AGND 1 28 RT VSENSE 2 27 SYNC COMP 3 26 SS/ENA PWRGD 4 25 VBIAS BOOT 5 24 VIN PH 6 23 VIN PH 7 THERMAL 22 VIN PH 8 PAD 21 VIN PH 9 20 VIN PH 10 19 PGND PH 11 18 PGND PH 12 17 PGND PH 13 16 PGND PH 14 15 PGND Terminal Functions TERMINAL DDEESSCCRRIIPPTTIIOONN NAME NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD to AGND. BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE. PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. PWRGD 4 Power good open drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or the internal shutdown signal is active. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency. SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. SYNC 27 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. VIN 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low-ESR 10-µF ceramic capacitor. VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider. 5

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 FUNCTIONAL BLOCK DIAGRAM AGND VBIAS VIN Enable Comparator SS/ENA VBIAS REG Falling SHUTDOWN 1.2 V Edge ILIM VIN Deglitch Thermal Comparator 3 − 6 V Hysteresis: 0.03 V 2.5 µs Shutdown Leading 150°C Edge VIN UVLO Blanking Comparator Falling 100 ns and VIN Rising BOOT 3.8 V Edge Hysteresis: 0.16 V Deglitch 30 mΩ 2.5 µs SS_DIS SHUTDOWN PH LOUT VO Internal/External Slow-Start + (Internal Slow-Start Time = 3.35 ms) − R Q Adaptive Dead-Time CO and Error S Control Logic Amplifier PWM Reference Comparator VIN VREF = 0.891 V 30 mΩ OSC PGND Powergood Comparator PWRGD VSENSE Falling 0.90 Vref Edge TPS54810 Deglitch Hysteresis: 0.03 Vref SHUTDOWN 35 µs VSENSE COMP RT SYNC RELATED DC/DC PRODUCTS (cid:1) TPS56300—dc/dc controller (cid:1) PT6600 series—9-A plugin modules 6

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS DRAIN-SOURCE INTERNALLY SET ON-STATE RESISTANCE OSCILLATOR FREQUENCY vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Ωm 60 VI = 5 V, − kHz 750 Drain Source On-State Reststance − 12345000000−40 IO− =15 8 A10 35 60 85 110 135 f − Internally Set Oscillator Frequency 234565555500000−40 SSYYNNCC 0 ≤≥ 02..85 VV 25 85 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 1 Figure 2 EXTERNALLY SET OSCILLATOR FREQUENCY VOLTAGE REFERENCE DEVICE POWER LOSSES vs vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE LOAD CURRENT y − kHz 800 0.895 4.55 TfsJ = = 7 10205 k°CHz nc 700 V 0.893 W 4 cillator Freque 560000 RT = 68 k e Reference − 0.891 wer Losses − 23..553 Externally Set Os 340000 RRTT == 110800 kk − VoltagVref00..888879 Device Po 01..5512 VI = 5 V f − 200−40 0 25 85 125 0.885−40 0 25 85 125 00 1 2 3 4 5 6 7 8 TJ − Junction Temperature − °C TJ − Junction Temperature − °C IL − Load Current − A Figure 3 Figure 4 Figure 5 OUTPUT VOLTAGE REGULATION INTERNAL SLOW-START TIME vs ERROR AMPLIFIER vs INPUT VOLTAGE OPEN LOOP RESPONSE JUNCTION TEMPERATURE 0.895 140 0 3.80 V − Output Voltage Regulation − VO0000....888888997913 Gain − dB110224680000000 GPahRCTianALLs =e== 211560°0 Ck ΩpF,, −−−−−−−−−11111864286420000000000Phase − Degrees Internal Slow-Start Time − ms 233333......902356050505 0.885 −20 −200 2.75 4.5 4.8 5.1 5.4 5.7 6 1 10 100 1 k 10 k 100 k 1 M 10 M −40 0 25 85 125 VI − Input Voltage − V f − Frequency − Hz TJ − Junction Temperature − °C Figure 6 Figure 7 Figure 8 7

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical 1.8 V. For proper thermal performance, the PowerPAD TPS54810 application. The TPS54810 (U1) can provide underneath the integrated circuit TPS54810 needs to be up to 8 A of output current at a nominal output voltage of soldered well to the printed-circuit board. VI C10 C12 U1 10 µF 10 µF TPS54810PWP R6 28 24 RT VIN 71.5 kΩ 23 VIN 27 22 R5 SYNC VIN 10 kΩ VIN 21 C6 26 20 SS/ENA VIN 0.047 µF PH 14 C3 25 13 VBIAS PH 1 µF PH 12 4 PWRGD PH 11 L1 10 0.65 µH C1 R2 R3 C4 PH 3 9 COMP PH VO 1000 pF 301 Ω 10 kΩ 3300 pF PH 8 C8 C7 C5 C2 7 22 µF 22 µF 22 µF PH R1 6 PH 10 kΩ 150 pF 2 VSENSE BOOT 5 C9 PGND 19 0.047 µF 18 PGND R7 R4 17 2.4 Ω PGND 9.76 kΩ 1 16 AGND PGND 15 C11 PGND 3300 pF PWRPAD Analog and Power Grounds are Tied at the Pad Under the Package of IC Figure 9. Application Circuit COMPONENT SELECTION at 1.8V. R1, along with R2, R3, C1, C2, and C4 forms the loop compensation network for the circuit. For this design, The values for the components used in this design a Type 3 topology is used. example were selected for low output ripple voltage and small PCB area. Additional design information is available OPERATING FREQUENCY at www.ti.com. In the application circuit, RT is grounded through a 71.5kΩ resistor to select the operating frequency of 700 kHz. To INPUT FILTER set a different frequency, place a 68kΩ to 180 kΩ resistor between RT (pin 28) and analog ground or leave RT The input voltage is a nominal 5 VDC. The input filter C10 floating to select the default of 350 kHz. The resistance can is a 10-µF ceramic capacitor (Taiyo Yuden). C12, also a be approximated using the following equation: 10-µF ceramic capacitor (Taiyo Yuden) provides high frequency decoupling of the TPS54810 from the input R(cid:1) 500kHz (cid:2)100[k(cid:1)] supply and must be located as close as possible to the SwitchingFrequency (1) device. Ripple current is carried in both C10 and C12, and the return path to PGND should avoid the current OUTPUT FILTER circulating in the output capacitors C5, C7, and C8. The output filter is composed of a 0.65-µH inductor and FEEDBACK CIRCUIT 3x22-µF capacitor. The inductor is a low dc resistance (0.017 Ω) type, Pulse Engineering PA0277. The The values for these components have been selected to capacitors used are 22-µF, 6.3 V ceramic types with X5R provide low output ripple voltage. The resistor divider dielectric. The feedback loop is compensated so that the network of R1 and R4 sets the output voltage for the circuit unity gain frequency is approximately 75 kHz. 8

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 PCB LAYOUT capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54810. Use a separate wide trace Figure 10 shows a generalized PCB layout guide for the for the analog ground signal path. The analog ground is TPS54810 used for the voltage set point divider, timing resistor RT, The VIN pins are connected together on the printed-circuit slow-start capacitor and bias capacitor grounds. Connect board (PCB) and bypassed with a low-ESR this trace directly to AGND (Pin 1). ceramic-bypass capacitor. Care should be taken to The PH pins are tied together and routed to the output minimize the loop area formed by the bypass capacitor inductor. Since the PH connection is the switching node, connections, the VIN pins, and the TPS54810 ground the inductor is located close to the PH pins. The area of the pins. The minimum recommended bypass capacitance is PCB conductor is minimized to prevent excessive 10-µF ceramic capacitor with a X5R or X7R dielectric and capacitive coupling. the optimum placement is closest to the VIN pins and the PGND pins. Connect the boot capacitor between the phase node and the BOOT pin as shown Keep the boot capacitor close to The TPS54810 has two internal grounds (analog and the IC and minimize the conductor trace lengths. power). Inside the TPS54810, the analog ground ties to all of the noise sensitive signals, while the power ground ties Connect the output filter capacitor(s) as shown between to the noisier power signals. Noise injected between the the VOUT trace and PGND. It is important to keep the loop two grounds can degrade the performance of the formed by the PH pins, LOUT, COUT and PGND as small as TPS54810, particularly at higher output currents. Ground practical. noise on an analog ground plane can also cause problems Place the compensation components from the VOUT trace with some of the control and bias signals. For these to the VSENSE and COMP pins. Do not place these reasons, separate analog and power ground traces are components too close to the PH trace. Due to the size of recommended. There is an area of ground on the top layer the IC package and the device pin-out, they must be routed directly under the IC, with an exposed area for connection close, but maintain as much separation as possible while to the PowerPAD. Use vias to connect this ground area to still keeping the layout compact. any internal ground planes. Additional vias are also used at the ground side of the input and output filter capacitors. Connect the bias capacitor from the VBIAS pin to analog The AGND and PGND pins are tied to the PCB ground by ground using the isolated analog ground trace. If a connecting them to the ground area under the device as slow-start capacitor or RT resistor is used, or if the SYNC shown. The only components that tie directly to the power pin is used to select 350-kHz operating frequency, connect ground plane are the input capacitors, the output them to this trace. 9

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 ANALOG GROUND TRACE FREQUENCY SET RESISTOR AGND RT VSENSE SYNC SLOW START CAPACITOR COMPENSATION COMP SS/ENA NETWORK BIAS CAPACITOR PWRGD VBIAS BOOT CAPACITOR BOOT VIN EXPOSED PH POWERPAD VIN VOUT AREA PH VIN PH VIN VIN PH PH VIN PH PGND OUTPUT INDUCTOR PH PGND OUTPUT PH PGND FILTER CAPACITOR PH PGND INPUT INPUT PH PGND BYPASS BULK CAPACITOR FILTER TOPSIDE GROUNDAREA VIA to Ground Plane Figure 10. PCB Layout 10

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 LAYOUT CONSIDERATIONS FOR THERMAL any area available should be used when 8 A or greater PERFORMANCE operation is desired. Connection from the exposes area of the PowerPAD to the analog ground plane layer should be For operation at full rated load current, the analog ground made using 0.013 inch diameter vias to avoid solder plane must provide adequate heat dissipating area. A 3 wicking through the vias. Eight vias should be in the inch by 3 inch plane of 1 ounce copper is recommended, PowerPAD area with four additional vias located under the though not mandatory, depending on ambient temperature device package. The size of the vias under the package, and airflow. Most applications have larger areas of internal but not in the exposed thermal pad area, can be increased ground plane available, and the PowerPAD should be to 0.018. Additional vias beyond the twelve recommended connected to the largest area available. Additional areas that enhance thermal performance should be included in on the top or bottom layers also help dissipate heat, and areas not under the device package. Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside 8 PL Ø0.0130 Powerpad Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground 4 PL Ø0.0180 Area Is Extended. Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance 0.0150 0.06 0.0339 0.0650 0.0500 0.3820 0.3478 0.0500 0.2090 0.0500 0.0256 0.0650 0.0339 Minimum Recommended Exposed Copper Area for Powerpad. 5-mil 0.1700 Stencils May Require 10 Percent 0.1340 Larger Area Minimum Recommended Top Side Analog Ground Area 0.0630 0.0400 Figure 11. Recommended Land Pattern for the 28−Pin PWP PowerPAD 11

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 PERFORMANCE GRAPHS (FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9) EFFICIENCY LOAD REGULATION LINE REGULATION vs vs vs OUTPUT CURRENT OUTPUT CURRENT INPUT VOLTAGE 100 1.003 1.001 95 VVIO = = 5 1 V.8 V VVIO = = 5 1 V.8 V 1.0008 8 A VVIO = = 5 1 V.8 V 90 fs = 700 kHz 1.002 TA = 25°C 1.0006 TA = 25°C Efficiency − % 6778850505 Load Regulation01..9090911 fs = 700 kHz Line Regulation0011....99009900990016824 4 A 0 A fs = 700 kHz 60 0.9994 0.998 55 0.9992 50 0.997 0.999 0 2 4 6 8 10 0 2 4 6 8 10 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 IO − Output Current − A IO − Output Current − A VI − Input Voltage − V Figure 12 Figure 13 Figure 14 AMBIENT TEMPERATURE vs OUTPUT CURRENT (1) OUTPUT RIPPLE VOLTAGE TRANSIENT RESPONSE 125 v 115 TJ = 25°C VI = 5 V V/di VI = 5 V °− Ambient Temperature −TCA 10345678955555555 fs = 7V0I 0= k5H Vz Output Ripple Voltage − 10 mV/div VIfOsO == = 76 01 A0.8 k VHz − Output Voltage − 100 mVO 2 A to 6.5 A − Output Current − 2 A/divO I 25 0 1 2 3 4 5 6 7 8 t − Time − 1 µs/div t − Time − 20 µs/div IO − Output Current − A Figure 15 Figure 16 Figure 17 SLOW-START TIMING VI = 5 V, div 0.04 µF V/ Slow-start Cap 2 − e g a ut Volt V/div Inp − 2 e g a olt V ut p ut O 4.0 ms/div Figure 18 (1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings 12

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 DETAILED DESCRIPTION low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are Under Voltage Lock Out (UVLO) recommended because their values are more stable over temperature. The bypass capacitor should be placed close The TPS54810 incorporates an under voltage lockout to the VBIAS pin and returned to AGND. circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are External loading on VBIAS is allowed, with the caution that held inactive until VIN exceeds the nominal UVLO internal circuits require a minimum VBIAS of 2.70V, and threshold voltage of 3.80 V. Once the UVLO start threshold external loads on VBIAS with ac or digital switching noise is reached, device start-up begins. The device operates may degrade performance. The VBIAS pin may be useful until VIN falls below the nominal UVLO stop threshold of as a reference voltage for external circuits. 3.5 V. Hysteresis in the UVLO comparator, and a 2.5-µs Voltage Reference rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. The voltage reference system produces a precise V ref signal by scaling the output of a temperature stable Slow-Start/Enable (SS/ENA) bandgap circuit. During manufacture, the bandgap and The slow-start/enable pin provides two functions. First, the scaling circuits are trimmed to produce 0.891 V at the pin acts as an enable (shutdown) control by keeping the output of the error amplifier, with the amplifier connected device turned off until the voltage exceeds the start as a voltage follower. The trim procedure adds to the high threshold voltage of approximately 1.2 V. When SS/ENA precision regulation of the TPS54810, since it cancels exceeds the enable threshold, device start up begins. The offset errors in the scale and error amplifier circuits. reference voltage fed to the error amplifier is linearly Oscillator and PWM Ramp ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in The oscillator frequency can be set to internally fixed approximately 3.35 ms. Voltage hysteresis and a 2.5-µs values of 350 kHz or 550 kHz using the SYNC pin as a falling edge deglitch circuit reduce the likelihood of static digital input. If a different frequency of operation is triggering the enable due to noise. required for the application, the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a The second function of the SS/ENA pin provides an resistor between the RT pin and AGND and floating the external means of extending the slow-start time with a SYNC pin. The switching frequency is approximated by low-value capacitor connected between SS/ENA and the following equation, where R is the resistance from RT AGND. to AGND: Adding a capacitor to the SS/ENA pin has two effects on SwitchingFrequency(cid:1)100k(cid:1)(cid:2)500[kHz] start-up. First, a delay occurs between release of the R (4) SS/ENA pin and start up of the output. The delay is proportional to the slow-start capacitor value and lasts until External synchronization of the PWM ramp is possible the SS/ENA pin reaches the enable threshold. The over the frequency range of 330 kHz to 700 kHz by driving start-up delay is approximately: a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor which t (cid:1)C (cid:2)1.2 V sets the free running frequency to 80% of the d (SS) 5 (cid:2)A (2) synchronization signal. The following table summarizes the frequency selection configurations: Second, as the output becomes active, a brief ramp-up at SWITCHING FRE- SYNC PIN RT PIN the internal slow-start rate may be observed before the QUENCY externally set slow-start rate takes control and the output 350 kHz, internally set Float or AGND Float rises at a rate proportional to the slow-start capacitor. The ramp-up time set by the capacitor is approximately: 550 kHz, internally set =2.5 V Float Externally set 280 kHz Float R = 68 k to 180 k 0.7 V t (cid:1)C (cid:2) to 700 kHz (d) (SS) 5 (cid:2)A (3) Externally synchro- Synchronization R = RT value for 85% nized frequency signal of external synchro- The actual ramp-up time is likely to be less than the above nization frequency approximation due to the brief ramp-up at the internal rate. Error Amplifier VBIAS Regulator (VBIAS) The high performance, wide bandwidth, voltage error The VBIAS regulator provides internal analog and digital amplifier sets the TPS54810 apart from most dc/dc blocks with a stable supply voltage over variations in converters. The user is given the flexibility to use a wide junction temperature and input voltage. A high quality, range of output L and C filter components to suit the 13

TPS54810 www.ti.com SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005 particular application needs. Type 2 or type 3 compensa- FET is below 2 V. While the low-side driver does not turn tion can be employed using external compensation on until the voltage at the gate of the high-side MOSFET components. is below 2 V. The high-side and low-side drivers are designed with PWM Control 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied Signals from the error amplifier output, oscillator, and from VIN, while the high-side drive is supplied from the current limit circuit are processed by the PWM control BOOT pin. A bootstrap circuit uses an external BOOT logic. Referring to the internal block diagram, the control capacitor and an internal 2.5-Ω bootstrap switch logic includes the PWM comparator, OR gate, PWM latch, connected between the VIN and BOOT pins. The and portions of the adaptive dead-time and control logic integrated bootstrap switch improves drive efficiency and block. During steady-state operation below the current reduces external component count. limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once Overcurrent Protection the PWM latch is reset, the low-side FET remains on for a The cycle by cycle current limiting is achieved by sensing minimum duration set by the oscillator pulse width. During the current flowing through the high-side MOSFET and this period, the PWM ramp discharges rapidly to its valley comparing this signal to a preset overcurrent threshold. voltage. When the ramp begins to charge back up, the The high side MOSFET is turned off within 200 ns of low-side FET turns off and high-side FET turns on. As the reaching the current limit threshold. A 100 ns leading edge PWM ramp voltage exceeds the error amplifier output blanking circuit prevents false tripping of the current limit voltage, the PWM comparator resets the latch, thus when the high side switch is turning on. Current limit turning off the high-side FET and turning on the low-side detection occurs only when current flows from VIN to PH FET. The low-side FET remains on until the next oscillator when sourcing current to the output filter. Load protection pulse discharges the PWM ramp. during current sink operation is provided by thermal shutdown. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the Thermal Shutdown PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until The device uses the thermal shutdown to turn off the power the oscillator pulse signals the control logic to turn the MOSFETs and disable the controller if the junction high-side FET off and the low-side FET on. The device temperature exceeds 150°C. The device is released from operates at its maximum duty cycle until the output voltage shutdown automatically when the junction temperature rises to the regulation set-point, setting VSENSE to decreases to 10°C below the thermal shutdown trip point, approximately the same voltage as VREF. If the error and starts up under control of the slow-start circuit. amplifier output is low, the PWM latch is continually reset Thermal shutdown provides protection when an overload and the high-side FET does not turn on. The low-side FET condition is sustained for several milliseconds. With a remains on until the VSENSE voltage decreases to a persistent fault condition, the device cycles continuously; range that allows the PWM comparator to change states. starting up by control of the soft-start circuit, heating up due The TPS54810 is capable of sinking current continuously to the fault condition, and then shutting down upon until the output reaches the regulation set-point. reaching the thermal shutdown trip point. This sequence repeats until the fault condition is removed. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the Power Good (PWRGD) error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output The power good circuit monitors for under voltage inductor and consequently the output current. This conditions on VSENSE. If the voltage on VSENSE is 10% process is repeated each cycle in which the current limit below the reference voltage, the open-drain PWRGD comparator is tripped. output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold or SS/ENA is low. When VIN ≥ UVLO threshold, SS/ENA ≥ enable threshold, and Dead-Time Control and MOSFET Drivers VSENSE > 90% of V , the open drain output of the ref PWRGD pin is high. A hysteresis voltage equal to 3% of Adaptive dead-time control prevents shoot-through V and a 35 µs falling edge deglitch circuit prevent ref current from flowing in both N-channel power MOSFETs tripping of the power good comparator due to high during the switching transitions by actively controlling the frequency noise. turnon times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side 14

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54810PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54810 & no Sb/Br) TPS54810PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54810 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54810PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54810PWPR HTSSOP PWP 28 2000 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW PWP 28 PowerPADTM TSSOP - 1.2 mm max height 4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224765/A www.ti.com

None

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated