TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 4.5V to 18V Input, 5.5-A Synchronous Step-Down Converter CheckforSamples:TPS54525 FEATURES DESCRIPTION 1 • D-CAP2™ModeEnablesFastTransient The TPS54525 is an adaptive on-time D-CAP2™ 23 mode synchronous buck converter. The TPS54525 Response enables system designers to complete the suite of • LowOutputRippleandAllowsCeramicOutput various end equipment’s power bus regulators with a Capacitor cost effective, low component count, low standby • WideV InputVoltageRange:4.5Vto18V current solution. The main control loop for the IN TPS54525 uses the D-CAP2™ mode control which • OutputVoltageRange:0.76Vto5.5V provides a very fast transient response with no • HighlyEfficientIntegratedFET’sOptimized external compensation components. The TPS54525 forLowerDutyCycleApplications also has a proprietary circuit that enables the device –63mΩ (HighSide)and33mΩ (LowSide) to adopt to both low equivalent series resistance • HighEfficiency,lessthan10μAatshutdown (ESR) output capacitors, such as POSCAP or SP- CAP, and ultra-low ESR ceramic capacitors. The • HighInitialBandgapReferenceAccuracy device operates from 4.5-V to 18-V VIN input. The • AdjustableSoftStart output voltage can be programmed between 0.76 V • Pre-BiasedSoftStart and 5.5 V. The device also features an adjustable soft start time and a power good function. The • 650-kHzSwitchingFrequency(f ) SW TPS54525 is available in the 14-pin HTSSOP • CycleByCycleOverCurrentLimit package, and designed to operate from –40°C to • PowerGoodOutput 85°C. APPLICATIONS • WideRangeofApplicationsforLowVoltage System VO(50 mV/div ac coupled) – DigitalTVPowerSupply – HighDefinitionBlu-rayDisc™Players – NetworkingHomeTerminal I (2A/div) OUT – DigitalSetTopBox(STB) U1 TPS54525 Slew Rate (0.35A/µsec) Time Scale (100µsec/div) 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. D-CAP2,PowerPADaretrademarksofTexasInstruments. 2 Blu-rayDiscisatrademarkofBlu-rayDiscAssociation. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2012–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) T PACKAGE(2) (3) ORDERABLEPARTNUMBER PIN TRANSPORT A MEDIA,QUANTITY PowerPAD™ TPS54525PWP Tube –45°Cto85°C 14 (HTSSOP)–PWP TPS54525PWPR TapeandReel (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (3) AllpackageoptionshaveCuNIPDAUlead/ballfinish. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT VIN1,VIN2EN –0.3 20 V VBST –0.3 26 V VBST(10nstransient) –0.3 28 V Inputvoltagerange, VBST(vsSW1,SW2) –0.3 6.5 V VFB,VO,SS,PG –0.3 6.5 V SW1,SW2 –2 20 V SW1,SW2(10nstransient) –3 22 V VREG5 –0.3 6.5 V Outputvoltagerange PGND1,PGND2 –0.3 0.3 V VoltagefromGNDtoPowerPAD™,V –0.2 0.2 V diff HumanBodyModel(HBM) 2 kV Electrostaticdischarge ChargedDeviceModel(CDM) 500 V Operatingjunctiontemperature,T –40 150 °C J Storagetemperature,T –55 150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. THERMAL INFORMATION TPS54525 THERMALMETRIC(1) PWP UNITS 14PINS θ Junction-to-ambientthermalresistance 43.7 JA θ Junction-to-case(top)thermalresistance 33.1 JCtop θ Junction-to-boardthermalresistance 28.4 JB °C/W ψ Junction-to-topcharacterizationparameter 1.3 JT ψ Junction-to-boardcharacterizationparameter 28.2 JB θ Junction-to-case(bottom)thermalresistance 4.7 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 2 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyinputvoltagerange 4.5 18 V IN VBST –0.3 24 VBST(10nstransient) –0.3 27 VBST(vsSW1,SW2) -0.3 5.7 SS,PG –0.3 5.7 V Inputvoltagerange EN –0.3 18 V I VO,VFB –0.3 5.5 SW1,SW2 –1.8 18 SW1,SW2(10nstransient) –3 21 PGND1,PGND2 –0.3 0.1 V Outputvoltagerange VREG5 –0.3 5.7 V O I OutputCurrentrange I 0 5 mA O VREG5 T Operatingfree-airtemperature –40 85 °C A T Operatingjunctiontemperature –40 150 °C J ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT V current,T =25°C,EN=5V, I Operating-non-switchingsupplycurrent IN A 900 1400 μA VIN V =0.8V VFB I Shutdownsupplycurrent V current,T =25°C,EN=0V 3.6 10 μA VINSDN IN A LOGICTHRESHOLD V ENhigh-levelinputvoltage 1.6 V ENH V ENlow-levelinputvoltage 0.6 V ENL R ENpinresistancetoGND V =12V 220 440 880 kΩ EN EN VFBVOLTAGEANDDISCHARGERESISTANCE T =25°C,V =1.05V,continuousmode 757 765 773 A O VFBTH VFBthresholdvoltage TmAod=e–(41)0°Cto85°C,VO=1.05V,continuous 754 776 mV I VFBinputcurrent V =0.8V,T =25°C 0 ±0.15 μA VFB VFB A R V dischargeresistance V =0V,V =0.5V,T =25°C 50 100 Ω Dischg O EN O A VREG5OUTPUT T =25°C,6.0V<V <18V, V VREG5outputvoltage A IN 5.2 5.5 5.7 V VREG5 0<I <5mA VREG5 V VREG5Lineregulation 6.0V<V <18V,I =5mA 20 mV VREG5 IN VREG5 V VREG5Loadregulation 0mA<I <5mA 100 mV VREG5 VREG5 I VREG5Outputcurrent V =6V,V =4V,T =25°C 60 mA VREG5 IN VREG5 A MOSFET R Highsideswitchresistance T =25°C,V -V =5.5V 63 mΩ dsonh A BST SW1,2 R Lowsideswitchresistance T =25°C 33 mΩ dsonl A (1) Notproductiontested. Copyright©2012–2013,TexasInstrumentsIncorporated 3 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT I Currentlimit L =1.5μH(2) 6.1 6.9 8.4 A ocl OUT THERMALSHUTDOWN Shutdowntemperature (2) 165 T Thermalshutdownthreshold °C SDN Hysteresis (2) 35 ON-TIMETIMERCONTROL T Ontime V =12V,V =1.05V 155 ns ON IN O T Minimumofftime T =25°C,V =0.7V 260 330 ns OFF(MIN) A VFB SOFTSTART I SSchargecurrent V =1V 4.2 6.0 7.8 μA SSC SS I SSdischargecurrent V =0.5V 0.1 0.2 mA SSD SS POWERGOOD V rising(good) 85 90 95 % VFB V PGthreshold THPG V falling(fault) 85 % VFB I PGsinkcurrent V =0.5V 2.5 5 mA PG PG OUTPUTUNDERVOLTAGEANDOVERVOLTAGEPROTECTION V OutputOVPtripthreshold OVPdetect 120 125 130 % OVP T OutputOVPpropdelay 10 μs OVPDEL UVPdetect 60 65 70 % V OutputUVPtripthreshold UVP Hysteresis 10 % T OutputUVPdelay 0.25 ms UVPDEL T OutputUVPenabledelay Relativetosoft-starttime x1.7 UVPEN UVLO WakeupVREG5voltage 3.31 3.61 3.91 V UVLOthreshold FallVREG5voltage 2.82 3.12 3.42 V UVLO HysteresisVREG5voltage 0.37 0.49 0.61 (2) Notproductiontested. 4 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 DEVICE INFORMATION PWPPACKAGE (TOPVIEW) VO 1 VIN2 14 2 VFB VIN1 13 3VREG5 POWER PAD VBST12 TPS54525 4 SS SW2 11 PWP HTSSOP14 5 GND SW1 10 6 PG PGND29 7 EN PGND18 PINFUNCTIONS PIN DESCRIPTION NAME NO. VO 1 Connecttooutputofconverter.Thispinisusedforoutputdischargefunction. VFB 2 Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider. 5.5Vpowersupplyoutput.Acapacitor(typical1µF)shouldbeconnectedtoGND.VREG5isnotactive VREG5 3 whenENislow. SS 4 Soft-startcontrol.AnexternalcapacitorshouldbeconnectedtoGND. GND 5 Signalgroundpin PG 6 Opendrainpowergoodoutput EN 7 Enablecontrolinput.ENisactivehighandmustbepulleduptoenablethedevice. Groundreturnsforlow-sideMOSFET.Alsoserveasinputsofcurrentcomparators.ConnectPGNDand PGND1,PGND2 8,9 GNDstronglytogetherneartheIC. Switchnodeconnectionbetweenhigh-sideNFETandlow-sideNFET.Alsoserveasinputstocurrent SW1,SW2 10,11 comparators. Supplyinputforhigh-sideNFETgatedriver(boostterminal).Connectcapacitorfromthispinto VBST 12 respectiveSW1,SW2terminals.AninternalPNdiodeisconnectedbetweenVREG5toVBSTpin. PowerinputandconnectedtohighsideNFETdrain.Supplyinputfor5-Vinternallinearregulatorforthe VIN1,VIN2 13,14 controlcircuitry. Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Shouldbeconnected PowerPAD™ Backside toPGND. Copyright©2012–2013,TexasInstrumentsIncorporated 5 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com FUNCTIONALBLOCKDIAGRAM -35% UV VIN2 VIN 14 OV 13VIN1 1 VO +25% VREG5 VBST 12 Controllogic Ref SS 1shot SW2 VO 2 11 VFB XCON SW1 10 SGND VREG5 VREG5 Ceramic 3 Capacitor 1uF SS 4 9 PGND2 PGND1 Softstart 8 PGND SS SW OCP PGND 5 GND SGND Ref VIN 6 PG -10% UV VREG5 OV Protection UVLO UVLO Logic EN EN 7 TSD Logic REF Ref 6 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 OVERVIEW The TPS54525 is a 5.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESRoutputcapacitorsincludingceramicandspecialpolymertypes. DETAILED DESCRIPTION PWMOperation The main control loop of the TPS54525 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2™modecontrol. PWMFrequencyandAdaptiveOn-TimeControl TPS54525 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54525 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the outputvoltage,therefore,whenthedutyratioisVOUT/VIN,thefrequencyisconstant. SoftStartandPre-BiasedSoftStart The soft start function is adjustable. When the EN pin becomes high, 6-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 6μA. C (nF)xV ´1.1 C (nF)x0.765´1.1 SS REF SS t (ms)= = SS I (mA) 6 SS (1) The TPS54525 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage V ), the controller slowly activates synchronous rectification by starting FB the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by- cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal modeoperation. PowerGood The TPS54525 has power-good open drain output. The power good function is activated after soft start has finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is within -10% of the target value, internal comparators detect power good state and the power good signal becomeshigh.Rpgresistervalue,whichisconnectedbetweenPGandVREG5,isrequiredfrom25kΩto150kΩ. Ifthefeedbackvoltagegoesunder15%ofthetargetvalue,thepowergoodsignalbecomeslow. Copyright©2012–2013,TexasInstrumentsIncorporated 7 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com VREG5 VREG5 is an internally generated voltage source used by the TPS54525. It is derived directly from the input voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5 regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage (3.6 V typical) for the TPS54525 to function. Connect a 1 µF capacitor between pin 3 of the TPS54525 and power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external use. It is recommended to use no more than 5 mA for external loads. The VREG5 output is disabled when the TPS54525ENpinisopenorpulledlow. OutputDischargeControl TPS54525 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to avoidthepossibilityofcausingnegativevoltageattheoutput. CurrentProtection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by V , IN V , the on-time and the output inductor value. During the on time of the low-side FET switch, this current OUT decreases linearly. The average value of the switch current is the load current I . If the measured voltage is OUT above the voltage proportional to the current limit, Then , the device constantly monitors the low-side FET switch voltage,whichisproportionaltotheswitchcurrent,duringthelow-sideon-time. The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switchingcycles,theon-timeissettoafixedvalueandthecurrentismonitoredinthesamemanner. There are some important considerations for this type of overcurrent protection. The load current one half of the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output undervoltage protection circuit to be activated. When the over current conditionisremoved,theoutputvoltagereturnstotheregulatedvalue.Thisprotectionisnon-latching. Over/UnderVoltageProtection TPS54525 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high and the circuit latches as both the high-side and low-side MOSFET drivers turn off. When the feedback voltage becomes lower than 65% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 250 μs, the device latches off both internal top and bottom MOSFET. This function is enabled approximately1.7xsoftstarttime. UVLOProtection Undervoltage lock out protection (UVLO) monitors the voltage of the V pin. When the V voltage is lower REG5 REG5 thanUVLOthresholdvoltage,theTPS54525isshutoff.Thisisprotectionisnon-latching. ThermalShutdown TPS54525 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), thedeviceisshutoff.Thisisnon-latchprotection. 8 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 TYPICAL CHARACTERISTICS V =12V,T =25°C(unlessotherwisenoted) IN A V CURRENT V SHUTDOWNCURRENT IN IN vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 1200 12 1000 10 A) µ nt ( e A) 800 Curr 8 urrent (µ 600 utdown 6 C h Supply 400 urrent−S 4 C y pl p u S 200 2 VIN = 12 V VIN = 12 V 0 0 −50 0 50 100 150 −50 0 50 100 150 Junction Temperature (°C) Junction Temperature (°C) G001 G002 Figure1. Figure2. ENCURRENT 1.05-VOUTPUTVOLTAGE vs vs ENVOLTAGE OUTPUTCURRENT 50 1.09 VO = 1.05 V 45 1.08 40 35 µA) V) 1.07 Current ( 2350 Voltage ( 1.06 N Input 20 Output E 1.05 15 10 1.04 VIN = 5 V 5 VIN = 12 V VIN = 12 V VIN = 18 V 0 1.03 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 EN Input Voltage (V) Output Current (A) G002 G004 Figure3. Figure4. Copyright©2012–2013,TexasInstrumentsIncorporated 9 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com TYPICAL CHARACTERISTICS V =12V,T =25°C(unlessotherwisenoted) IN A 1.05-VOUTPUTVOLTAGE vs 1.05-V,50-mAto5.5-ALOAD INPUTVOLTAGE TRANSIENTRESPONSE 1.07 V (50 mV/div ac coupled) O 1.06 V) e ( g a olt 1.05 IOUT(2A/div) V ut p ut O 1.04 Slew Rate (0.35A/µsec) IO = 0 A IO = 1 A Time Scale (100µsec/div) 1.03 0 5 10 15 20 Input Voltage (V) G005 Figure5. Figure6. EFFICIENCY vs START-UPWAVEFORM OUTPUTCURRENT 100 EN (10 V/div) 90 80 70 VREG5 (5 V/div) %) 60 VO(500 mV/div) y ( nc 50 e ci Effi 40 30 PG (5 V/div) 20 VOUT = 1.8 V 10 VOUT = 2.5 V VOUT = 3.3 V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Current (A) G005 Figure7. Figure8. 10 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 TYPICAL CHARACTERISTICS V =12V,T =25°C(unlessotherwisenoted) IN A SWITCHINGFREQUENCY SWITCHINGFREQUENCY vs vs INPUTVOLTAGE(I =1A) OUTPUTCURRENT O 800 800 750 700 700 z) z) H H k k y ( y ( 650 c c n n e e u u eq 600 eq 600 Fr Fr g g n n hi hi 550 c c wit wit S S 500 500 VOUT = 1.05 V 450 VOUT = 1.05 V VOUT = 1.8 V VOUT = 1.8 V VOUT = 3.3 V VOUT = 3.3 V 400 400 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Current (A) G006 G007 Figure9. Figure10. VOLTAGERIPPLEATOUTPUT(I =5.5A) VOLTAGERIPPLEATINPUT(I =5.5A) O O V = 1.05 V V = 1.05 V O O V (10 mV/div ac coupled) V (50 mV/div ac coupled) O IN SW (5 V/div) SW (5 V/div) Figure11. Figure12. Copyright©2012–2013,TexasInstrumentsIncorporated 11 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com TYPICAL CHARACTERISTICS V =12V,T =25°C(unlessotherwisenoted) IN A OUTPUTCURRENT vs AMBIENTTEMPERATURE 6 5 4 A) nt ( e urr 3 C ut p ut O 2 1 VOUT = 1.0 − 4.5 V VOUT = 5.0 V VIN = 12 V VOUT = 5.5 V 0 −50 −25 0 25 50 75 100 Ambient Temperature (°C) G008 Figure13. 12 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 DESIGN GUIDE StepByStepDesignProcedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent • Outputvoltageripple • Inputvoltageripple U1 TPS54525PWP Figure14. Showstheschematicdiagramforthisdesignexample. OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1%toleranceorbetterdividerresistors.StartbyusingEquation2tocalculateV . OUT To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptibletonoiseandvoltageerrorsfromtheVFBinputcurrentwillbemorenoticeable. ( R1) VOUT=0.765 • 1 + −R2 (2) OutputFilterSelection TheoutputfilterusedwiththeTPS54525isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L ´C OUT OUT (3) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54525. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable1 Copyright©2012–2013,TexasInstrumentsIncorporated 13 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com Table1.RecommendedComponentValues OutputVoltage(V) R1(kΩ) R2(kΩ) C4(pF)(1) L1(µH) C8+C9(µF) 1 6.81 22.1 1.0-1.5 22-68 1.05 8.25 22.1 1.0-1.5 22-68 1.2 12.7 22.1 1.0-1.5 22-68 1.5 21.5 22.1 1.5 22-68 1.8 30.1 22.1 5-22 1.5 22-68 2.5 49.9 22.1 5-22 2.2 22-68 3.3 73.2 22.1 5-22 2.2 22-68 5 124 22.1 5-22 3.3 22-68 (1) Optional For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor(C4)inparallelwithR1. Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by addingafeedforwardcapacitor(C4)inparallelwithR1 The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for f . SW Use 650 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS SW currentofEquation6. V V - V Ilp - p = OUT • IN (max) OUT V L •f IN (max) O SW (4) Ilp - p I = I +  lpeak O 2 (5) − √ 1 I = I 2+ −Ilp - p2 Lo(RMS) O 12 (6) For this design example, the calculated peak current is 6.01 A and the calculated RMS current is 5.5 A. The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11 A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54525 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 7 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V • (V - V ) I =−−OUT IN OUT CO(RMS) √12 •V •L •f IN O SW (7) For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.284Aandeachoutputcapacitorisratedfor4A. InputCapacitorSelection The TPS54525 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor from pin 14 to ground is recommended to improve the EMI performance. The capacitor voltage rating needstobegreaterthanthemaximuminputvoltage. BootstrapCapacitorSelection A 0.1 µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommendedtouseaceramiccapacitor. 14 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 VREG5CapacitorSelection A 1.0 µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommendedtouseaceramiccapacitor. THERMAL INFORMATION This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC). For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002andApplicationBrief,PowerPAD™MadeEasy,TexasInstrumentsLiteratureNo.SLMA004. Theexposedthermalpaddimensionsforthispackageareshowninthefollowingillustration. 14 8 Thermal Pad 2.46 ° 1 7 2.31 Figure15. ThermalPadDimensions Copyright©2012–2013,TexasInstrumentsIncorporated 15 ProductFolderLinks:TPS54525

TPS54525 SLVSB82A–MAY2012–REVISEDJULY2013 www.ti.com LAYOUT CONSIDERATIONS • Keeptheinputswitchingcurrentloopassmallaspossible. • Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedbackpinofthedevice. • Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. • Makeasinglepointconnectionfromthesignalgroundtopowerground. • Donotallowswitchingcurrenttoflowunderthedevice. • VREG5capacitorshouldbeplacednearthedevice,andconnectedPGND. • OutputcapacitorshouldbeconnectedtoabroadpatternofthePGND. • Voltagefeedbackloopshouldbeasshortaspossible,andpreferablywithgroundshield. • LowerresistorofthevoltagedividerwhichisconnectedtotheVFBpinshouldbetiedtoSGND. • ProvidingsufficientviaispreferableforVIN,SWandPGNDconnection. • PCBpatternforVINandSWshouldbeasbroadaspossible. • VINCapacitorshouldbeplacedasnearaspossibletothedevice. • Thetopsidepowerground(PGND)copperfillareaneartheICshouldbeaslargeaspossible.Thiswillaidin thermaldissipationaswelllowerconductionlossesinthegroundreturn • Exposed pad of device must be connected to PGND with solder. The PGND area under the IC should be as large as possible and completely cover the exposed thermal pad. The bottom side of the board should contain a large copper area under the device that is directly connected to the exposed area with small diameter vias. Small diameter vias will prevent solder from being drawn away from the exposed thermal pad. Any additional internal layers should also contain copper ground areas under the device and be connected to thethermalvias. 16 Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54525

TPS54525 www.ti.com SLVSB82A–MAY2012–REVISEDJULY2013 VIN Additional Thermal VIN Vias VCIUNR ORVEENRT INPUT STABILITY BYPASS CAPACITOR CAPACITOR FEEDBACK VOUT EXPOSED VIN2 RESISTORS POWERPAD AREA VFB VIN1 BOOST VREG5 VBST CAPACITOR VOUT BIAS SS SW1 CAP GND SW2 OUTPUT INDUCTOR OUTPUT PG PGND1 SLOW FILTER START CAPACITOR CAP EN PGND2 Connection to POWER GROUND on internal or ANALOG Additional bottom layer GROUND Thermal TRACE Vias To Enable Control POWER GROUND VIAto Ground Plane Etch on Bottom Layer or Under Component Figure16. PCBLayout spacer REVISION HISTORY ChangesfromRevisionMay2012(#IMPLIED)toRevisionA Page • DeletedV -T =0°Cto85°C,V =1.05V,continuousmodefromtheElectricalCharacteristics. ............................... 3 FBTH A O • ChangedV -T =–40°Cto85°C,V =1.05V,continuousmodeFrom:MIN=751MAX=779mVTo:MIN= FBTH A O 754MAX=776mVintheElectricalCharacteristics ............................................................................................................ 3 • ChangedtheOver/UnderVoltageProtectionsection.From:"asthehigh-sideMOSFETdriverturnsoffandthelow- sideMOSFETturnson"To:"asboththehigh-sideandlow-sideMOSFETdriversturnoff" ............................................... 8 Copyright©2012–2013,TexasInstrumentsIncorporated 17 ProductFolderLinks:TPS54525

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54525PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54525 & no Sb/Br) TPS54525PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54525 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54525PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54525PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 PackMaterials-Page2

None

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated