TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 4-A OUTPUT SINGLE SYNCHRONOUS STEP DOWN SWITCHER WITH INTEGRATED FET ( SWIFT™) CheckforSamples:TPS54425 FEATURES DESCRIPTION 1 • D-CAP2™ModeEnablesFastTransient The TPS54425 is an adaptive on-time D-CAP2™ 23 mode synchronous buck converter. The TPS54425 Response enables system designers to complete the suite of • LowOutputRippleandAllowsCeramicOutput various end equipment’s power bus regulators with a Capacitor cost effective, low component count, low standby • WideV InputVoltageRange:4.5Vto18V current solution. The main control loop for the IN TPS54425 uses the D-CAP2™ mode control which • OutputVoltageRange:0.76Vto5.5V provides a very fast transient response with no • HighlyEfficientIntegratedFET’sOptimized external compensation components. The TPS54425 forLowerDutyCycleApplications also has a proprietary circuit that enables the device –65mΩ (HighSide)and55mΩ (LowSide) to adopt to both low equivalent series resistance • HighEfficiency,lessthan10μAatshutdown (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The • HighInitialBandgapReferenceAccuracy device operates from 4.5-V to 18-V VIN input. The • AdjustableSoftStart output voltage can be programmed between 0.76 V • Pre-BiasedSoftStart and 5.5 V. The device also features an adjustable soft start time and a power good function. The • 700-kHzSwitchingFrequency(f ) SW TPS54425 is available in the 14-pin HTSSOP • CycleByCycleOverCurrentLimit package, and designed to operate from –40°C to • PowerGoodOutput 85°C. APPLICATIONS • WideRangeofApplicationsforLowVoltage System – DigitalTVPowerSupply – HighDefinitionBlu-rayDisc™Players – NetworkingHomeTerminal – DigitalSetTopBox(STB) Vout (50 mV/div) Iout (2A/div) 100ms/div 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SWIFT,D-CAP2,PowerPADaretrademarksofTexasInstruments. 2 Blu-rayDiscisatrademarkofBlu-rayDiscAssociation. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2011,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) T PACKAGE(2) (3) ORDERABLEPARTNUMBER PIN TRANSPORT A MEDIA,QUANTITY PowerPAD™ TPS54425PWP Tube –45°Cto85°C 14 (HTSSOP)–PWP TPS54425PWPR TapeandReel (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (3) AllpackageoptionshaveCuNIPDAUlead/ballfinish. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) VALUE UNIT VIN1,VIN2EN –0.3to20 V VBST –0.3to26 V VBST(10nstransient) –0.3to28 V V Inputvoltagerange I VFBVO,SS,PG –0.3to6.5 V SW1,SW2 –2to20 V SW1,SW2(10nstransient) –3to22 V VREG5 –0.3to6.5 V V Outputvoltagerange O PGND1,PGND2 –0.3to0.3 V V VoltagefromGNDtoPOWERPAD –0.2to0.2 V diff Electrostatic HumanBodyModel(HBM) 2 kV ESDrating discharge ChargedDeviceModel(CDM) 500 V T Operatingjunctiontemperature –40to150 °C J T Storagetemperature –55to150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. THERMAL INFORMATION TPS54425 THERMALMETRIC(1) PWP UNITS 14PINS θ Junction-to-ambientthermalresistance 55.6 JA θ Junction-to-case(top)thermalresistance 51.3 JCtop θ Junction-to-boardthermalresistance 26.4 JB °C/W ψ Junction-to-topcharacterizationparameter 1.8 JT ψ Junction-to-boardcharacterizationparameter 20.6 JB θ Junction-to-case(bottom)thermalresistance 4.3 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 2 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyinputvoltagerange 4.5 18 V IN VBST –0.3 24 VBST(10nstransient) –0.3 27 SS,PG –0.1 5.7 EN –0.1 18 V Inputvoltagerange V I VO,VFB –0.1 5.5 SW1,SW2 –1.8 18 SW1,SW2(10nstransient) –3 21 PGND1,PGND2 –0.1 0.1 V Outputvoltagerange VREG5 –0.1 5.7 V O I OutputCurrentrange I 0 10 mA O VREG5 T Operatingfree-airtemperature –40 85 °C A T Operatingjunctiontemperature –40 150 °C J ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT V current,T =25°C,EN=5V, I Operating-non-switchingsupplycurrent IN A 850 1300 μA VIN V =0.8V FB I Shutdownsupplycurrent V current,T =25°C,EN=0V 1.8 10 μA VINSDN IN A LOGICTHRESHOLD V ENhigh-levelinputvoltage EN 2 V ENH V ENlow-levelinputvoltage EN 0.4 V ENL V VOLTAGEANDDISCHARGERESISTANCE FB T =25°C,V =1.05V,continuousmode 757 765 773 A O T =0°Cto85°C,V =1.05V,continuous V V thresholdvoltage mAode(1) O 753 777 mV FBTH FB T =–40°Cto85°C,V =1.05V,continuous mAode(1) O 751 779 I V inputcurrent V =0.8V,T =25°C 0 ±0.1 μA VFB FB FB A R V dischargeresistance EN=0V,V =0.5V,T =25°C 50 100 Ω Dischg O O A V OUTPUT REG5 T =25°C,6.0V<V <18V, V V outputvoltage A IN 5.3 5.5 5.7 V VREG5 REG5 0<I <5mA VREG5 V Lineregulation 6.0V<V <18V,I =5mA 20 mV LN5 IN VREG5 V Loadregulation 0mA<I <5mA 100 mV LD5 VREG5 I Outputcurrent V =6V,V =4V,T =25°C 70 mA VREG5 IN REG5 A MOSFET R Highsideswitchresistance 25°C,V -SW1,2=5.5V 63 mΩ dsonh BST R Lowsideswitchresistance 25°C 55 mΩ dsonl (1) Notproductiontested. Copyright©2010–2011,TexasInstrumentsIncorporated 3

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT I Currentlimit L =1.5μH(2),T =-20ºCto85ºC 4.7 5.4 7.5 A ocl OUT A THERMALSHUTDOWN Shutdowntemperature (2) 165 T Thermalshutdownthreshold °C SDN Hysteresis (2) 30 ON-TIMETIMERCONTROL T Ontime V =12V,V =1.05V 145 ns ON IN O T Minimumofftime T =25°C,V =0.7V 260 310 ns OFF(MIN) A FB SOFTSTART I SSchargecurrent V =0V 1.4 2.0 2.6 μA SSC SS I SSdischargecurrent V =0.5V 0.1 0.2 mA SSD SS POWERGOOD V rising(good) 85 90 95 % FB V PGthreshold THPG V falling(fault) 85 % FB I PGsinkcurrent PG=0.5V 2.5 5 mA PG OUTPUTUNDERVOLTAGEANDOVERVOLTAGEPROTECTION V OutputOVPtripthreshold OVPdetect 115 120 125 % OVP T OutputOVPpropdelay 10 μs OVPDEL UVPdetect 60 65 70 % V OutputUVPtripthreshold UVP Hysteresis 10 % T OutputUVPdelay 0.25 ms UVPDEL T OutputUVPenabledelay Relativetosoft-starttime x1.7 UVPEN UVLO WakeupV voltage 3.5 3.8 4.1 REG5 V UVLOthreshold V UVLO HysteresisV voltage 0.23 0.35 0.47 REG5 (2) Notproductiontested. 4 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 DEVICE INFORMATION PWP PACKAGE (TOPVIEW) VO 1 VIN2 14 2 VFB VIN1 13 3VREG5 POWER PAD VBST12 TPS54425 4 SS SW2 11 PWP HTSSOP14 5 GND SW1 10 6 PG PGND29 7 EN PGND18 PINFUNCTIONS PIN DESCRIPTION NAME NO. VO 1 Connecttooutputofconverter.ThisterminalisusedforOn-TimeAdjustment. VFB 2 Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider. 5.5Vpowersupplyoutput.Acapacitor(typical1µF)shouldbeconnectedtoGND.VREG5isnotactive VREG5 3 whenENislow. SS 4 Soft-startcontrol.AexternalcapacitorshouldbeconnectedtoGND. GND 5 Signalgroundpin PG 6 Opendrainpowergoodoutput EN 7 Enablecontrolinput.ENisactivehighandmustbepulleduptoenablethedevice. Groundreturnsforlow-sideMOSFET.Alsoserveasinputsofcurrentcomparators.ConnectPGNDand PGND1,PGND2 8,9 GNDstronglytogetherneartheIC. Switchnodeconnectionbetweenhigh-sideNFETandlow-sideNFET.Alsoserveasinputstocurrent SW1,SW2 10,11 comparators. Supplyinputforhigh-sideNFETgatedriver(boostterminal).Connectcapacitorfromthispinto VBST 12 respectiveSW1,SW2terminals.AninternalPNdiodeisconnectedbetweenVREG5toVBSTpin. PowerinputandconnectedtohighsideNFETdrain.Supplyinputfor5-Vinternallinearregulatorforthe VIN1,VIN2 13,14 controlcircuitry. Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Shouldbeconnected PowerPAD™ Backside toPGND. Copyright©2010–2011,TexasInstrumentsIncorporated 5

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com FUNCTIONALBLOCKDIAGRAM -35% UV 14VIN2 VIN VIN1 OV 13 1 VO +20% VREG5 VBST 12 Controllogic Ref SS 1shot SW VO 2 11 VFB XCON 10 SGND VREG5 VREG5 Ceramic 3 Capacitor 1uF SS 4 98 PGND Softstart PGND SS SW OCP PGND 5 GND SGND Ref VCC 6 PG -10% UV VREG5 OV Protection UVLO UVLO Logic EN EN 7 TSD Logic REF Ref 6 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 OVERVIEW The TPS54425 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESRoutputcapacitorsincludingceramicandspecialpolymertypes. DETAILED DESCRIPTION PWMOperation The main control loop of the TPS54425 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2™modecontrol. PWMFrequencyandAdaptiveOn-TimeControl TPS54425 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54425 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the outputvoltage,therefore,whenthedutyratioisVOUT/VIN,thefrequencyisconstant. SoftStartandPre-BiasedSoftStart The soft start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 2μA. C6(nF)•Vref C6(nF)•0.765 Tss(ms) = − = − Iss(µA) 2 (1) The TPS54425 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage V ), the controller slowly activates synchronous rectification by starting FB the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normalmodeoperation. PowerGood The TPS54425 has power-good open drain output. The power good function is activated after soft start has finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is within -10% of the target value, internal comparators detect power good state and the power good signal becomeshigh.Rpgresistervalue,whichisconnectedbetweenPGandVREG5,isrequiredfrom20kΩto150kΩ. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 5 μs internaldelay. Copyright©2010–2011,TexasInstrumentsIncorporated 7

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com VREG5 VREG5 is an internally generated voltage source used by the TPS54425. It is derived directly from the input voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5 regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage (3.8 V typical) for the TPS54425 to function. Connect a 1.0 µF capacitor between pin 3 of the TPS54425 and power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external use and can typically source up to 70 mA. The VREG5 output is disabled when the TPS54425 EN pin is open or pulledlow. OutputDischargeControl TPS54425 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to avoidthepossibilityofcausingnegativevoltageattheoutput. CurrentProtection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by V , IN V , the on-time and the output inductor value. During the on time of the low-side FET switch, this current OUT decreases linearly. The average value of the switch current is the load current I . If the measured voltage is OUT above the voltage proportional to the current limit, Then , the device constantly monitors the low-side FET switch voltage,whichisproportionaltotheswitchcurrent,duringthelow-sideon-time. The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switchingcycles,theon-timeissettoafixedvalueandthecurrentismonitoredinthesamemanner. There are some important considerations for this type of overcurrent protection. The load current one half of the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output undervoltage protection circuit to be activated. When the over current conditionisremoved,theoutputvoltagereturnstotheregulatedvalue.Thisprotectionisnon-latching. Over/UnderVoltageProtection TPS54425 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches as the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback voltage becomes lower than 65% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 250 μs, the device latches off both internal top and bottom MOSFET. This functionisenabledapproximately1.7xsoftstarttime. UVLOProtection Undervoltage lock out protection (UVLO) monitors the voltage of the V pin. When the V voltage is lower REG5 REG5 thanUVLOthresholdvoltage,theTPS54425isshutoff.Thisisprotectionisnon-latching. ThermalShutdown TPS54425 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), thedeviceisshutoff.Thisisnon-latchprotection. 8 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 TYPICAL CHARACTERISTICS V CURRENT V SHUTDOWNCURRENT CC CC vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 1200 8 1000 A m Am nt - 6 nt - 800 urre e C rr n u w y C 600 do 4 pl ut p h u S - S 400 n - C d C s I c 2 c v 200 I 0 0 -50 0 50 100 150 -50 0 50 100 150 T - Junction Temperature - °C T - Junction Temperature - °C J J Figure1. Figure2. ENCURRENT 1.05-VOUTPUTVOLTAGE vs vs ENVOLTAGE OUTPUTCURRENT 100 1.1 80 1.075 V = 18 V A V I V = 12 V rrent -m 60 oltage - I u V ut C put 1.05 VI= 5 V N - Inp 40 - OutO E V 1.025 20 0 1 0 5 10 15 20 0 1 2 3 4 EN - Input Voltage - V IO- Output Current -A Figure3. Figure4. Copyright©2010–2011,TexasInstrumentsIncorporated 9

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.05-VOUTPUTVOLTAGE vs 1.05-V,50-mAto2-ALOAD INPUTVOLTAGE TRANSIENTRESPONSE 1.1 Vout (50 mV/div) 1.075 V IO= 0A e - g a olt V ut 1.05 IO= 1A p ut O - O V 1.025 Iout (2A/div) 1 0 5 10 15 20 V - Input Voltage - V I 100ms/div Figure5. Figure6. EFFICIENCY vs START-UPWAVEFORM OUTPUTCURRENT 100 V = 3.3 V O EN (10 V/div) 90 80 VO= 2.5 V % V = 1.8 V y - O c Vout (0.5 V/div) n 70 e ci Effi 60 PG (5 V/div) 50 40 0 1 2 3 4 I - Output Current -A 400ms/div O Figure7. Figure8. 10 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 TYPICAL CHARACTERISTICS (continued) SWITCHINGFREQUENCY SWITCHINGFREQUENCY vs vs INPUTVOLTAGE(I =1A) OUTPUTCURRENT O 800 800 z z kH 700 kH 700 V = 1.8 V y - VO= 1.8 V y - O c c n n e e u u q q e e Fr 600 Fr 600 g g hin hin VO= 3.3 V witc VO= 3.3 V witc S S - 500 - 500 w w s s f f 400 400 0 5 10 15 20 0 1 2 3 4 V - Input Voltage - V I - Output Current -A I O Figure9. Figure10. VOLTAGERIPPLEATOUTPUT(I =2A) VOLTAGERIPPLEATINPUT(I =2A) O O VO= 1.05 V VO= 1.05 V V (10 mV/div) VIN (50 mV/div) O SW (5 V/div) SW (5 V/div) Figure11. Figure12. Copyright©2010–2011,TexasInstrumentsIncorporated 11

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com DESIGN GUIDE StepByStepDesignProcedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent • Outputvoltageripple • Inputvoltageripple Figure13. Showstheschematicdiagramforthisdesignexample. OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1%toleranceorbetterdividerresistors.StartbyusingEquation2andEquation3tocalculateV . OUT To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptibletonoiseandvoltageerrorsfromtheVFBinputcurrentwillbemorenoticeable. Foroutputvoltagefrom0.76Vto2.5V: ( R1) VOUT=0.765 • 1 + −R2 (2) Foroutputvoltageover2.5V: ( ) ¾R1 V =(0.763 + 0.0017 ·V )· 1 + OUT OUT_SET R2 (3) Where: V =TargetV voltage. OUT_SET OUT OutputFilterSelection TheoutputfilterusedwiththeTPS54425isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L ´C OUT OUT (4) 12 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54425. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable1 Table1.RecommendedComponentValues OutputVoltage(V) R1(kΩ) R2(kΩ) C4(pF)(1) L1(µH) C8+C9(µF) 1 6.81 22.1 1.5 22-68 1.05 8.25 22.1 1.5 22-68 1.2 12.7 22.1 1.5 22-68 1.8 30.1 22.1 10-22 2.2 22-68 2.5 49.9 22.1 10-22 2.2 22-68 3.3 73.2 22.1 10-22 2.2 22-68 5 121 22.1 10-22 3.3 22-68 (1) Optional For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor(C4)inparallelwithR1. Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by addingafeedforwardcapacitor(C4)inparallelwithR1 The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for f . SW Use 700 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS SW currentofEquation7. V V - V Ilp - p = OUT • IN (max) OUT V L •f IN (max) O SW (5) Ilp - p I = I +  lpeak O 2 (6) − √ 1 I = I 2+ −Ilp - p2 Lo(RMS) O 12 (7) For this design example, the calculated peak current is 4.47A and the calculated RMS current is 4.009 A. The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11 A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54425 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 8 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V • (V - V ) I =−−OUT IN OUT CO(RMS) √12 •V •L •f IN O SW (8) For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.271Aandeachoutputcapacitorisratedfor4A. Copyright©2010–2011,TexasInstrumentsIncorporated 13

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com InputCapacitorSelection The TPS54425 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The capacitorvoltageratingneedstobegreaterthanthemaximuminputvoltage. BootstrapCapacitorSelection A 0.1 µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommendedtouseaceramiccapacitor. VREG5CapacitorSelection A 1.0 µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommendedtouseaceramiccapacitor. THERMAL INFORMATION This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC). For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002andApplicationBrief,PowerPAD™MadeEasy,TexasInstrumentsLiteratureNo.SLMA004. Theexposedthermalpaddimensionsforthispackageareshowninthefollowingillustration. 14 8 Thermal Pad 2.46 ° 1 7 2.31 Figure14. ThermalPadDimensions 14 Copyright©2010–2011,TexasInstrumentsIncorporated

TPS54425 www.ti.com SLVSA84C–AUGUST2010–REVISEDJULY2011 LAYOUT CONSIDERATIONS 1. Keeptheinputswitchingcurrentloopassmallaspossible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedbackpinofthedevice. 3. Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. 4. Makeasinglepointconnectionfromthesignalgroundtopowerground. 5. Donotallowswitchingcurrenttoflowunderthedevice. 6. KeepthepatternlinesforVINandPGNDbroad. 7. ExposedpadofdevicemustbeconnectedtoPGNDwithsolder. 8. VREG5capacitorshouldbeplacednearthedevice,andconnectedPGND. 9. OutputcapacitorshouldbeconnectedtoabroadpatternofthePGND. 10. Voltagefeedbackloopshouldbeasshortaspossible,andpreferablywithgroundshield. 11. LowerresistorofthevoltagedividerwhichisconnectedtotheVFBpinshouldbetiedtoSGND. 12. ProvidingsufficientviaispreferableforVIN,SWandPGNDconnection. 13. PCBpatternforVIN,SW,andPGNDshouldbeasbroadaspossible. 14. VINCapacitorshouldbeplacedasnearaspossibletothedevice. VIN Additional Thermal VIN Vias VCIUNR ORVEENRT INPUT STABILITY BYPASS CAPACITOR CAPACITOR FEEDBACK VOUT EXPOSED VIN2 RESISTORS POWERPAD AREA VFB VIN1 BOOST VREG5 VBST CAPACITOR VOUT BIAS SS SW1 CAP GND SW2 OUTPUT INDUCTOR OUTPUT PG PGND1 SLOW FILTER START CAPACITOR CAP EN PGND2 Connection to POWER GROUND on internal or ANALOG Additional bottom layer GROUND Thermal TRACE Vias To Enable Control POWER GROUND VIAto Ground Plane Etch on Bottom Layer or Under Component Figure15. PCBLayout Copyright©2010–2011,TexasInstrumentsIncorporated 15

TPS54425 SLVSA84C–AUGUST2010–REVISEDJULY2011 www.ti.com REVISION HISTORY ChangesfromOriginal(August2010)toRevisionA Page • AddedV =12VtotheconditionsstatementintheElectricalCharacteristicstable ........................................................... 3 IN ChangesfromRevisionA(October2010)toRevisionB Page • ChangedtheFUNCTIONALBLOCKDIAGRAM .................................................................................................................. 6 • ChangedthePowerGoodsection ........................................................................................................................................ 7 • ChangedtheCurrentProtectionsection............................................................................................................................... 8 • AddedNote1toTable1..................................................................................................................................................... 13 ChangesfromRevisionB(February2011)toRevisionC Page • ChangedELECCHARtable,UVLOthresholdMINfrom3.55Vto3.5V,MAXfrom4.05Vto4.1V................................. 4 16 Copyright©2010–2011,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing Qty (2) (3) (4) TPS54425PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54425 & no Sb/Br) TPS54425PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54425 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Apr-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54425PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Apr-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54425PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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