Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 TPS54388-Q1 Automotive 2.95-V to 6-V, 3-A , 2-MHz Synchronous Buck Converter 1 Features 3 Description • AEC-Q100-QualifiedforAutomotiveApplications: The TPS54388-Q1 device is a full-featured 6-V, 3-A, 1 synchronous step-down current-mode converter with – TemperatureGrade1: –40°Cto+125°C,T A twointegratedMOSFETs. • Two12-mΩ (typical)MOSFETsforHighEfficiency The TPS54388-Q1 device enables small designs by at3-ALoads integrating the MOSFETs, implementing current- • 200-kHzto2-MHzSwitchingFrequency mode control to reduce external component count, • 0.8V± 1%VoltageReferenceOverTemperature reducing inductor size by enabling up to 2-MHz (–40°Cto+150°C) switching frequency, and minimizing the IC footprint with a small 3-mm × 3-mm thermally enhanced QFN • SynchronizestoExternalClock package. • AdjustableSlowStartandSequencing The TPS54388-Q1 device provides accurate • UVandOVPower-GoodOutput regulation for a variety of loads with an accurate ±1% • –40°Cto+150°COperatingJunctionTemperature voltagereference(V )overtemperature. ref Range The integrated 12-mΩ MOSFETs and 515-μA typical • ThermallyEnhanced3-mm× 3-mm16-pinWQFN supply current maximize efficiency. Entering • PinCompatibletoTPS54418 shutdown mode using the enable pin reduces • CreateaCustomDesignusingtheTPS54388-Q1 shutdownsupplycurrentto5.5µA,typical. withtheWEBENCH®PowerDesigner The internal undervoltage lockout setting is at 2.45 V, butprogrammingthethresholdwitharesistornetwork 2 Applications on the enable pin can increase the setting. The slow- start pin sets the output-voltage start-up ramp. An • AutomotiveHeadUnit open-drain power-good signal indicates when the • AutomotiveInstrumentCluster outputiswithin93%to107%ofitsnominalvoltage. • AutomotiveADASCamera Frequencyfoldbackandthermalshutdown protect the deviceduringanovercurrentcondition. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) TPS54388-Q1 WQFN(16) 3.00mm×3.00mm (1) Forallavailablepackages,seetheorderableaddendumat theendofthedatasheet. SimplifiedSchematic EfficiencyCurve TPS54388-Q1 C(BOOT) 100 V(VIN) VIN BOOT 95 V(VIN)= 3 V C(I) R4 L(O) 90 V(VIN)= 5 V EN PH V O R5 C(O) 85 PWRGD R1 y (%) 80 VSENSE enc 75 ci SS/TR R2 Effi 70 RT/CLK C(SS) COMP GND 65 Rt R3 AGND 60 C1 Thermal Pad 55 f(SW)= 500 kHz VO= 1.8 V 50 0 1 2 3 4 5 6 Output Current (A) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 22 2 Applications........................................................... 1 8.1 ApplicationInformation............................................22 3 Description............................................................. 1 8.2 TypicalApplication .................................................22 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 31 5 PinConfigurationandFunctions......................... 3 10 Layout................................................................... 31 6 Specifications......................................................... 4 10.1 LayoutGuidelines.................................................31 6.1 AbsoluteMaximumRatings......................................4 10.2 LayoutExample....................................................32 6.2 ESDRatings ............................................................4 11 DeviceandDocumentationSupport................. 33 6.3 RecommendedOperatingConditions.......................4 11.1 Third-PartyProductsDisclaimer...........................33 6.4 ThermalInformation..................................................5 11.2 DeviceSupport......................................................33 6.5 ElectricalCharacteristics..........................................5 11.3 DocumentationSupport........................................33 6.6 TypicalCharacteristics..............................................7 11.4 ReceivingNotificationofDocumentationUpdates33 7 DetailedDescription............................................ 11 11.5 CommunityResource............................................34 7.1 Overview.................................................................11 11.6 Trademarks...........................................................34 7.2 FunctionalBlockDiagram.......................................12 11.7 ElectrostaticDischargeCaution............................34 7.3 FeatureDescription.................................................12 11.8 Glossary................................................................34 7.4 DeviceFunctionalModes........................................13 12 Mechanical,Packaging,andOrderable Information........................................................... 34 4 Revision History ChangesfromRevisionD(April2015)toRevisionE Page • Editorialchangesonly,notechnicalrevisions;addedlinksforWEBENCH .......................................................................... 1 • Addedtopnavigatoriconforreferencedesign ..................................................................................................................... 1 • AddedtheReceivingNotificationofDocumentationUpdatessectionandchangedtheESDnotice ................................. 33 ChangesfromRevisionC(September2014)toRevisionD Page • Changedpinoutdrawingtotopview...................................................................................................................................... 3 • ChangedEquation8andEquation9................................................................................................................................... 17 ChangesfromRevisionB(July2012)toRevisionC Page • UpdatedthedatasheettothenewTIdatasheetstandard................................................................................................... 1 • AddedAEC-Q100listitemstotheFeaturessection ............................................................................................................. 1 • Changedpinoutdiagramtobottomview ............................................................................................................................... 3 • AddedMINvaluestoBOOTandBOOT-PHparameters....................................................................................................... 4 • ChangedthemaxvaluefortheinputvoltageontheENandRT/CLKpinsintheAbsoluteMaximumRatingstable ..........4 • Deletednoteswithtest-boardinformationfromtheThermalInformationtable .................................................................... 5 • UpdatedtheThermalInformationtablewithnewvalues ...................................................................................................... 5 • Simplifieddiscussionforimplementationofratiometricandsimultaneouspower-supplysequencingandchangedthe followingequationscorrespondingly.................................................................................................................................... 16 • ChangedtocalculateddeterminationofRtresistor ............................................................................................................ 17 ChangesfromRevisionA(June,2011)toRevisionB Page • Removed(SWIFT™)fromtitle............................................................................................................................................... 1 • RemovedthelasttwosentencesinthedescriptioncontainingSwitcherPro™andSWIFT™references............................. 1 • Removedlastsentenceoffirstparagraph,"UseSwitcherProsoftwareforamoreaccuratedesign."................................ 27 2 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 5 Pin Configuration and Functions RTEPackage 16-PinWQFNWithExposedThermalPad TopView D G T R O N N W O VI E P B 6 5 4 3 1 1 1 1 VIN 1 12 PH VIN 2 11 PH Thermal Pad GND 3 10 PH GND 4 9 SS/TR 5 6 7 8 D E P K N S M L G N O C A E C T/ S R V PinFunctions PIN I/O(1) DESCRIPTION NAME NO. AGND 5 — ConnectanaloggroundelectricallytoGNDclosetothedevice. ThedevicerequiresabootstrapcapacitorbetweenBOOTandPH.Avoltageonthiscapacitorthatis BOOT 13 O belowtheminimumrequiredbytheBOOTUVLOforcestheoutputtoswitchoffuntilthecapacitor recharges. Erroramplifieroutput,andinputtotheoutput-switchcurrentcomparator.Connectfrequency- COMP 7 O compensationcomponentstothispin. Enablepin,internalpullup-currentsource.Pullbelow1.2Vtodisable.Floattoenable.Onecanusethis EN 15 I pintosettheon-offthreshold(adjustUVLO)withtwoadditionalresistors. 3 GND — Powerground.Directlyconnectthispinelectricallytothethermalpadunderthedevice. 4 10 Thesourceoftheinternalhigh-sidepowerMOSFET,anddrainoftheinternallow-side(synchronous) PH 11 O rectifierMOSFET 12 Anopen-drainoutput;assertedlowifoutputvoltageislowduetothermalshutdown,overcurrent,over- PWRGD 14 O orundervoltage,orENshutdown. RT/CLK 8 I Resistor-timingorexternal-clockinputpin Slowstartandtracking.Anexternalcapacitorconnectedtothispinsetstheoutput-voltagerisetime. SS/TR 9 I Anotheruseofthispinisfortracking. 1 VIN 2 I Inputsupplyvoltage,2.95Vto6V 16 VSENSE 6 I Invertingnodeofthetransconductance(g )erroramplifier m ConnecttheGNDpintotheexposedthermalpadforproperoperation.Connectthisthermalpadtoany Thermalpad — internalPCBgroundplanesusingmultipleviasforgoodthermalperformance. (1) I=input,O=output Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VIN –0.3 7 EN –0.3 7 BOOT –0.3 PH+7 VSENSE –0.3 3 Inputvoltage V COMP –0.3 3 PWRGD –0.3 7 SS/TR –0.3 3 RT/CLK –0.3 7 BOOT-PH –0.3 7 Outputvoltage PH –0.6 7 V PH10-nstransient –2 10 EN 100 Sourcecurrent µA RT/CLK 100 COMP 100 µA Sinkcurrent PWRGD 10 mA SS/TR 100 µA Junctiontemperature,T –40 150 °C J Ambienttemperature,T –40 125 °C A Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,anddonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perAECQ100-002(1) ±2000 Electrostatic V(ESD) discharge Chargeddevicemodel(CDM),perAEC Cornerpins(1,16,4,5,8,9,12,and13) ±750 V Q100-011 Otherpins ±500 (1) AECQ100-002indicatesHBMstressingisdoneinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 6.3 Recommended Operating Conditions overoperatingfree-airtemperature(unlessotherwisenoted) MIN NOM MAX UNIT V Inputvoltage 2.95 6 V (VIN) T Operatingambienttemperature –40 125 ºC A 4 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 6.4 Thermal Information TPS54388-Q1 THERMALMETRIC(1) RTE(WQFN) UNIT 16PINS R Junction-to-ambientthermalresistance 43.5 °C/W θJA R Junction-to-case(top)thermalresistance 46.1 °C/W θJC(top) R Junction-to-boardthermalresistance 15.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 15.5 °C/W JB R Junction-to-case(bottom)thermalresistance 3.8 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report(SPRA953). 6.5 Electrical Characteristics T =–40°Cto150°C,V =2.95to6V(unlessotherwisenoted) J (VIN) DESCRIPTION TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) VINUVLOstart 2.28 2.5 Internalundervoltagelockoutthreshold V VINUVLOstop 2.45 2.6 Shutdownsupplycurrent V =0V,25°C,2.95V≤V ≤6V 5.5 15 μA (EN) (VIN) Quiescentcurrent,I V =0.9V,V =5V,25°C,Rt=400kΩ 515 750 μA (q) (SENSE) (VIN) ENABLEANDUVLO(ENPIN) Rising 1.25 Enablethreshold V Falling 1.18 Enablethreshold+50mV –1.6 Inputcurrent μA Enablethreshold–50mV –1.6 VOLTAGEREFERENCE(VSENSEPIN) Voltagereference 2.95V≤V ≤6V,–40°C<T <150°C 0.79 0.8 0.811 V (VIN) J MOSFET V =5V 12 30 (BOOT-PH) High-sideswitchresistance mΩ V =2.95V 16 30 (BOOT-PH) V =5V 13 30 (VIN) Low-sideswitchresistance mΩ V =2.95V 17 30 (VIN) ERRORAMPLIFIER Inputcurrent 2 nA Error-amplifiertransconductance(g ) –2μA<I <2μA,V =1V 245 μS m (COMP) (COMP) Error-amplifiertransconductance(g )during –2μA<I <2μA,V =1V, m (COMP) (COMP) 79 μS slowstart V =0.4V (VSENSE) Erroramplifiersourceandsink V =1V,100-mVoverdrive ±20 μA (COMP) COMPtohigh-sideFETcurrentg 25 S m Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Electrical Characteristics (continued) T =–40°Cto150°C,V =2.95to6V(unlessotherwisenoted) J (VIN) DESCRIPTION TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT Currentlimitthreshold 3.7 6.5 A THERMALSHUTDOWN Thermalshutdown 168 °C Hysteresis 20 °C TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) SwitchingfrequencyrangeusingRTmode 200 2000 kHz Switchingfrequency Rt=400kΩ 400 500 600 kHz SwitchingfrequencyrangeusingCLKmode 300 2000 kHz MinimumCLKpulseduration 75 ns RT/CLKvoltage Rt=400kΩ 0.5 V RT/CLKhighthreshold 1.6 2.5 V RT/CLKlowthreshold 0.4 0.6 V DelayfromRT/CLKfallingedgetoPHrising Measureat500kHzwithRTresistorinserieswith 90 ns edge devicepin PLLlock-intime Measureat500kHz 45 μs PH(PHPIN) Measuredat50%pointonPH,I =3A 75 O Minimumon-time Measuredat50%pointonPH,V =6V, ns (VIN) 120 I =0A O Priortoskippingoffpulses,BOOT-PH=2.95V, Minimumoff-time 60 ns I =3A O Risetime V =6V,6A 2.25 (VIN) V/ns Falltime V =6V,6A 2 (VIN) BOOT(BOOTPIN) BOOTchargeresistance V =5V 16 Ω (VIN) BOOT-PHUVLO V =2.95V 2.1 V (VIN) SLOWSTARTANDTRACKING(SS/TRPIN) Chargecurrent V =0.4V 2 μA (SS/TR) SS/TRtoVSENSEmatching V =0.4V 50 mV (SS/TR) SS/TRtoreferencecrossover 98%ofnormalreferencevoltage 1.1 V SS/TRdischargevoltage(overload) V =0V 61 mV (VSENSE) SS/TRdischargecurrent(overload) V =0V,V =0.4V 350 µA (VSENSE) (SS/TR) SSdischargecurrent(UVLO,EN,thermal V =5V,V =0.5V 1.9 mA fault) (VIN) (SS/TR) POWERGOOD(PWRGDPIN) VSENSEfalling(Fault) 91 VSENSErising(Good) 93 VSENSEthreshold %V ref VSENSErising(Fault) 109 VSENSEfalling(Good) 107 Hysteresis VSENSEfalling 2 %V ref Output-highleakage V =V ,V =5.5V 7 nA (VSENSE) ref (PWRGD) On-resistance 56 100 Ω Outputlow I =3mA 0.3 V (PWRGD) MinimumVINforvalidoutput V <0.5Vat100μA 0.65 1.6 V (PWRGD) 6 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 6.6 Typical Characteristics W) 0.025 525 nce ( 0.023 High-Side rDS(on), V(VIN)= 3.3 V 520 Resista 00..001291 Low-Side rDS(on), V(VIN)= 3.3 V kHz) 551105 ain-Source On-State 00000.....000000111193571 Low-Side rDS(on), V(VIN)= 5H Vigh-Side rDS(on), V(VIN)= 5 V Switching Frequency ( 444558990050505 Dr 0.007 c 480 Stati 0.005–50 –25 0 25 50 75 100 125 150 475 -50 -25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) Rt=400kΩ V =5V (VIN) Figure1.High-SideandLow-SiderDS(on)vsTemperature Figure2.FrequencyvsTemperature 8 0.807 7.5 A) 0.805 urrent ( 6.57 V(VIN)= 3.3 V ce (V) 0.803 Side Switching C 45..5556 V(VIN)= 5 V Voltage Referen 0000....777899905791 h- 4 g Hi 3.5 0.793 3 0.791 –50 –25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) V =3.3V (VIN) Figure3.High-SideCurrentLimitvsTemperature Figure4.VoltageReferencevsTemperature 2000 100 1800 Hz) 1600 ency (%) 75 V(VSENSE)Falling witching Frequency (k 111802400000000 minal Switching Frequ 2550 V(VSENSE)Rising S o 600 N 400 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 200 V(VSENSE)(V) 80 180 280 380 480 580 680 780 880 980 Resistance (kΩ) Figure5.SwitchingFrequencyvsRTResistance,Low- Figure6.SwitchingFrequencyvsV(VSENSE) FrequencyRange Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Typical Characteristics (continued) 310 105 100 290 95 e (S)m 270 e (S)m 90 nc 250 nc 85 a a Transconduct 221300 Transconduct 778050 65 190 60 170 –50 –25 0 25 50 75 100 125 150 55 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) V(VIN)=3.3V V(VIN)=3.3V Figure7.TransconductancevsTemperature Figure8.Transconductance(SlowStart)vsJunction Temperature 1.3 –3 1.29 1.28 –3.1 1.27 V(VIN)= 3.3 V, rising –3.2 1.26 V)1.25 A) –3.3 hreshold (1111....22221234 Current (m –––333...654 T 1.2 n 1.19 V(VIN)= 3.3 V, falling Pi –3.7 1.18 –3.8 1.17 1.16 –3.9 1.15 –4 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) V =5V V =Threshold+50mV (VIN) (EN) Figure9.ENPinVoltagevsTemperature Figure10.ENPinCurrentvsTemperature –1 –1.4 –1.2 –1.6 –1.4 A) –1.8 –1.6 m Pin Current (A)m –––221–...4228 Charge Current ( ––22–..422 –2.6 –2.6 –2.8 –2.8 –3 –3 –50 –25 0 25 50 75 100 125 150 –50 –30 –10 10 30 50 70 90 110 130 150 JunctionTemperature (°C) JunctionTemperature (°C) V =5V V =Threshold–50mV V =5V (VIN) (EN) (VIN) Figure11. ENPinCurrentvsTemperature Figure12.ChargeCurrentvsTemperature 8 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Typical Characteristics (continued) 2.8 8 2.7 A) 7 m 2.6 nt ( 6 e nput Voltage (V)222...345 UVLO Start Switching wn Supply Curr 345 I2.2 UVLO Stop Switching do 2 ut h 2.1 S 1 2 0 -50 -25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) V =3.3V (VIN) Figure13.InputVoltagevsTemperature Figure14.ShutdownSupplyCurrentvsTemperature 8 800 A) 7 700 m Current ( 56 nt (Am) 600 ply 4 urre 500 p C Su y utdown 23 Suppl 400 Sh 300 1 0 200 3 3.5 4 4.5 5 5.5 6 –50 –25 0 25 50 75 100 125 150 Input Voltage (V) JunctionTemperature (°C) T =25ºC V =3.3V J (VIN) Figure15.ShutdownSupplyCurrentvsInputVoltage Figure16.VINSupplyCurrentvsJunctionTemperature 800 110 108 700 106 Supply Current (Am) 456000000 Threshold (% of V)ref111999000468024 PPWVWV(RV(RVSGSGEEDNDNS SD EDE)e)eRaFasiasssliselnienrgtrg,ete,dd PVW(VPVRSWE(GVNSRDSEEGNA)SDRsEsAi)seFsirnsategelld,irntegd, 300 92 90 200 88 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature(°C) TJ=25ºC V(VIN)=5V Figure17.VINSupplyCurrentvsInputVoltage Figure18.PWRGDThresholdvsTemperature Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Typical Characteristics (continued) W)100 100 nce ( 90 90 a st 80 80 Resi 70 mV)70 State 60 set (60 n- 50 Off50 ce O 40 nse 40 Sour 30 Vse30 ain- 20 20 c Dr 10 10 ati 0 0 St –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) V(VIN)=5V V(VIN)=5V V(SS/TR)=0.4V Figure19.PWRGDOn-ResistancevsTemperature Figure20.SS/TR-to-VSENSEOffsetvsTemperature 10 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 7 Detailed Description 7.1 Overview The TPS54388-Q1 device is a 6-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients, the device implements a constant- frequency, peak-current-mode control, which reduces output capacitance and simplifies external frequency- compensation design. The wide switching-frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output-filter components. A resistor to ground on the RT/CLK pin sets the switching frequency. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the power-switchturnontoafallingedgeofanexternalsystemclock. The TPS54388-Q1 device has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup current source that one can use to adjust the input-voltage undervoltage lockout (UVLO) with two external resistors. In addition, the pullup current provides a default condition, allowing the device to operate when the EN pinisfloating.Thetotaloperatingcurrentforthe TPS54388-Q1 deviceistypically515μAwhennotswitchingand undernoload.Withthedevicedisabled,thesupplycurrentistypically5.5μA. The integrated 12-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous output currents upto3A. The TPS54388-Q1 device reduces the external component count by integrating the boot recharge diode. A capacitor between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A UVLO circuit monitors the boot-capacitor voltage and turns off the high-side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54388-Q1 device to operate approaching 100% duty cycle.Thelowerlimitforsteppingdowntheoutputvoltageisthe0.8-Vreference. TheTPS54388-Q1 devicehasapower-goodcomparator(PWRGD)with2%hysteresis. The TPS54388-Q1 device minimizes excessive output overvoltage transients by taking advantage of the overvoltage power-good comparator. A regulated output voltage exceeding 109% of the nominal voltage activates the overvoltage comparator, turning off the high-side MOSFET and masking it from turning on until the outputvoltageislowerthan107%ofthenominalvoltage. Auseofthe SS/TR (slow start pr tracking) pin is to minimize inrush currents or provide power-supply sequencing during power up. Couple a small-value capacitor to the pin for slow start. Discharging the SS/TR pin before the outputpowersupensuresarepeatablerestartafteranovertemperaturefault,UVLOfault,ordisabledcondition. The use of a frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditionstohelplimittheinductorcurrent. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 7.2 Functional Block Diagram PWRGD EN VIN Shutdown i(1) i(hys) Thermal Shutdown UVLO Enable 91% Logic Comparator Shutdown Shutdown Logic 109% Enable Threshold Boot Voltage Charge Reference COMMinPimCulammp UBVoLoOt Current Sense Error Amplifier PWM VSENSE Comparator BOOT SS/TR Logic and PWM Latch Shutdown Logic S Slope Compensation COMP PH Frequency Shift Overload Maximum Recovery Clamp Oscillator GND With PLL TPS54388-Q1 Block Diagram AGND Thermal Pad RT/CLK 7.3 Feature Description 7.3.1 Fixed-FrequencyPWMControl The TPS54388-Q1 device uses an adjustable fixed-frequency, peak-current-mode control. An error amplifier, which drives the COMP pin, compares the output voltage through external resistors on the VSENSE pin to an internal voltage reference. An internal oscillator initiates the turnon of the high-side power switch. The device compares the error-amplifier output to the high-side power-switch current. When the sensed voltage derived from the power-switch current reaches the COMP voltage level, the high-side power switch turns off and the low-side power switch turns on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level, and alsoimplementsaminimumclampforimprovedtransient-responseperformance. 7.3.2 SlopeCompensationandOutputCurrent The TPS54388-Q1 device adds a compensating ramp to the switch-current signal. This slope compensation preventssub-harmonicoscillationsasduty cycle increases. The available peak inductor current remains constant overthefullduty-cyclerange. 12 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Feature Description (continued) 7.3.3 BootstrapVoltage(BOOT)andLow-DropoutOperation The TPS54388-Q1 device has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.1 μF. TI recommends a ceramic capacitor with an X7R- or X5R-grade dielectric with a voltageratingof10Vorhigherbecauseofthestablecharacteristicsovertemperatureandvoltage. The TPS54388-Q1 design improves dropout by operating at 100% duty cycle as long as the BOOT-to-PH pin voltage is greater than 2.2 V. A UVLO circuit turns off the high-side MOSFET, allowing for the low-side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current sourced from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh thecapacitor.Thus,theeffectivedutycycleoftheswitchingregulatorishigh. 7.3.4 ErrorAmplifier The TPS54388-Q1 device has a transconductance amplifier that it uses as an error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance of the error amplifier is 245 μS during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the g is typically greater than 79 μS, but less m than245μS. 7.3.5 VoltageReference The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output of a temperature-stable band-gap circuit. The band-gap and scaling circuits produce 0.8 V at the non-inverting inputoftheerroramplifier. 7.4 Device Functional Modes 7.4.1 AdjustingtheOutputVoltage A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends using divider resistorswith1%toleranceorbetter.Startwith100kΩ fortheR1resistoranduseEquation1to calculate R2. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is moresusceptibletonoise,andvoltageerrorsfromtheVSENSEinputcurrentarenoticeable. æ 0.8 V ö R2=R1´ç ÷ V -0.8 V è O ø (1) TPS54388-Q1 V O R1 VSENSE - R2 0.8 V + Figure21. Voltage-DividerCircuit Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Device Functional Modes (continued) 7.4.2 EnableFunctionalityandAdjustingUndervoltageLockout The VIN pin voltage on the VIN pin falling below 2.6 V disables the TPS54388-Q1 device. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 22 to adjust the input voltage UVLO by using two external resistors. TI recommends using the EN resistors to set the UVLO falling threshold (V ) above 2.6 V. Set the rising threshold (V ) to provide enough hysteresis to allow for any input (STOP) (START) supply variations. The EN pin has an internal pullup current source that provides the default condition of TPS54388-Q1 operation when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, the circuitry adds an additional 1.6 μA of hysteresis. Pulling the EN pin below 1.18 V removes the 1.6 μA. This additional current facilitatesinputvoltagehysteresis. TPS54388-Q1 VIN Ihys 1.6mA R1 I1 1.6mA + EN R2 - Figure22. AdjustableUndervoltageLockout æV ö V ç (ENFALLING) ÷ - V (START) ç ÷ (STOP) V è (ENRISING) ø R1 = æ V ö I ç1- (ENFALLING) ÷+I (1)ç ÷ (hys) V è (ENRISING) ø where • V =1.18V (ENFALLING) • V =1.25V (ENRISING) • I =1.6µA (1) • I =1.6µA (2) (hys) R1´V (ENFALLING) R2= V -V +R1´(I +I ) (STOP) (ENFALLING) (1) (hys) (3) 7.4.3 Slow-StartorTrackingPin The TPS54388-Q1 device regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow-start time. The TPS54388-Q1 device has an internal pullup current source of 2 μA, which charges the external slow-start capacitor. Equation 4 calculates the required slow- start capacitor value, where t is the desired slow start time in ms, I is the internal slow start charging (SS/TR) (SS/TR) currentof2μA,andV istheinternalvoltagereferenceof0.8V. ref t (ms) ´ I (mA) (SS/TR) (SS/TR) C (nF)= (SS/TR) V (V) ref (4) 14 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Device Functional Modes (continued) If during normal operation, VIN goes below UVLO, the EN pin goes below 1.2 V, or a thermal shutdown event occurs, the TPS54388-Q1 device stops switching. On VIN going above UVLO, the release or pulling high of EN, or exit from a thermal shutdown, SS/TR discharges to below 60 mV before re-initiation of a power-up sequence. The VSENSE voltage follows the SS/TR pin voltage with a 50-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset increases as theeffectivesystemreferencetransitionsfromtheSS/TRvoltagetotheinternalvoltagereference. 7.4.4 Sequencing One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. Implementation of the sequential method uses an open-drain or open-collector output of the power-on-reset pin of another device. Figure 23 shows the sequential method. Couple the power-good to the EN pin on the TPS54388-Q1 devicetoenablethesecondpowersupplyoncetheprimarysupplyreachesregulation. One can accomplish ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, double the pullup current source in Equation4.Figure25showstheratiometricmethod. TPS54388-Q1 PWRGD EN EN EN1 SS/TR SS/TR EN2 PWRGD V O(1) V O(2) Figure23.SequentialStart-UpSequence Figure24.SequentialStart-UpUsingENand PWRGD Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Device Functional Modes (continued) TPS54388-Q1 EN1 SS/TR1 EN PWRGD1 SS TPS54388-Q1 VO(1) EN2 V O(2) SS/TR2 PWRGD2 Figure25.SchematicforRatiometricStart-Up Figure26.RatiometricStart-UpWithV Leading O(1) Sequence V O(2) One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 27 to the output of the power supply that requires tracking, or to another voltage reference source. Using Equation 5 and Equation 6, one can calculate the tracking resistors to initiate V O(2) slightly before, after, or at the same time as V . V – V is 0 V for simultaneous sequencing. Including O(1) O(1) O(2) V and I as variables in the equations minimizes the effect of the inherent SS/TR-to-VSENSE offset (ssoffset) (SS/TR) (V ) in the slow-start circuit and the offset created by the pullup current source (I ) and tracking resistors. (ssoffset) (ss) Because the SS/TR pin requires pulling below 60 mV before starting after an EN, UVLO, or thermal-shutdown fault, select the tracking resistors carefully to ensure the device can restart after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 7 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V becomes (ssoffset) larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference as shown inFigure26. V V R1= O(1) ´ (ssoffset) V I ref (SS/TR) (5) V ´ R1 R2= ref V -V O(1) ref (6) R1> 2930´V - 145´(V -V ) O(1) O(1) O(2) (7) 16 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Device Functional Modes (continued) TPS54388-Q1 BOOT1 EN1 PH1 V EN1 O(1) SS/TR1 PWRGD1 SS2 VO(1) R1 TPS54388-Q1 VO(2) BOOT2 EN2 PH2 V O(2) SS/TR2 R2 VSENSE2 PWRGD2 Figure27.RatiometricandSimultaneousStart-Up Figure28.RatiometricStart-UpUsingCoupled Sequence SS/TRPins 7.4.5 ConstantSwitchingFrequencyandTimingResistor(RT/CLKPin) The switching frequency of the TPS54388-Q1 device is adjustable over a wide range from 200 kHz to 2000 kHz by placing a resistor on the RT/CLK pin with a value calculated by Equation 8. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The voltage on RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use Equation 8 or thecurveinFigure5. 247530 (MW/s) Rt(kW)= f 1.0533(kHz) (SW) (8) 131904 (MW/s) f (kHz)= (SW) Rt0.9492(kW) (9) To reduce the solution size, one would typically set the switching frequency as high as possible, but consider tradeoffsoftheefficiency,maximuminputvoltage,andminimumcontrollableon-time. The minimum controllable on-time is typically 60 ns at full-current load and 120 ns at no load, and limits the maximumoperatinginputvoltageoroutputvoltage. 7.4.6 OvercurrentProtection The TPS54388-Q1 device implements a cycle-by-cycle current limit. During each switching cycle, the device compares a voltage derived from the high-side switch current to the voltage on the COMP pin. When the instantaneous switch-current voltage intersects the COMP voltage, the high-side switch turns off. During overcurrentconditionsthatpulltheoutputvoltagelow,theerroramplifierresponds by driving the COMP pin high, increasingtheswitchcurrent.Aninternalclampontheerror-amplifieroutputfunctionsasaswitch-currentlimit. 7.4.7 FrequencyShift To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54388-Q1 device implements a frequency shift. Without this frequency shift, during an overcurrent condition the low-side MOSFET might not turn off long enough to reduce the current in the inductor, causing a current runaway. With frequency shift, during an overcurrent condition there is a switching-frequency reduction from 100% to 50%, then 25%, as the voltage decreases from 0.8 V to 0 V on the VSENSE pin. The frequency shift allows the low-side MOSFET to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increasesasthevoltageonVSENSEincreasesfrom0Vto0.8V.SeeFigure6 fordetails. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Device Functional Modes (continued) 7.4.8 ReverseOvercurrentProtection The TPS54388-Q1 device implements low-side current protection by detecting the voltage across the low-side MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side MOSFET if the reverse current is typically more than 4.5 A. By implementing this additional protection scheme, the converter is able to protect itself from excessive current during power cycling and start-up into pre-biased outputs. 7.4.9 SynchronizeUsingtheRT/CLKPin The RT/CLK pin synchronizes the converter to an external system clock. See Figure 29. To implement the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75 ns. If the square wave pulls the pin above the PLL upper threshold, a mode change occurs, and the pin becomes a synchronization input. The CLK mode disables the internal amplifier, and the pin becomes a high-impedance clock input to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the mode returns to the frequency set by the resistor. The square-wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V, typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge ofPHsynchronizestothefallingedgeoftheRT/CLKpin. TPS54388-Q1 SYNC Clock = 2 V/div RT/CLK PLL PH = 2 V/div Clock Rt Source Time = 500 ns/div Figure29.SynchronizingtoaSystemClock Figure30.PlotofSynchronizingtoaSystemClock 7.4.10 PowerGood(PWRGDPin) TheoutputofthePWRGDpinisanopen-drainMOSFET.Theoutputgoeslowwhenthe VSENSE voltage enters the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 107% of the internal voltage reference, the PWRGD output MOSFET turns off. TI recommends using a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. PWRGD is inavalidstateoncetheVINinputvoltageisgreaterthan1.1V. 7.4.11 OvervoltageTransientProtection The TPS54388-Q1 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold, which is 109% of the internal voltage reference. If the VSENSE pin voltage goes higher than the OVTP threshold, the high-side MOSFET turns off, preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET turns on in thenextclockcycle. 7.4.12 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 148°C, the device reinitiates the power-up sequence bydischargingtheSS/TRpintobelow60mV.Thethermalshutdownhysteresisis20°C. 18 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Device Functional Modes (continued) 7.4.13 Small-SignalModelforLoopResponse Figure 31 shows an equivalent model for the TPS54388-Q1 control loop, which one can model in a circuit- simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a g of 245 μS. One can model the error amplifier using an ideal voltage- m controlledcurrentsource.The resistor R0 and capacitor C0 model the open-loop gain and frequency response of the amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the frequency-response measurements. Plotting a over c vs frequency shows the small-signal response of the frequency compensation. Plotting a over b vs frequency shows the small-signal response of the overall loop. Check the dynamic loop response by replacing R with a current source that has the appropriate load-step (L) amplitudeandsteprateinatime-domainanalysis. PH V Power Stage O 25 S a b R R1 (ESR) COMP R (L) c VSENSE 0.8 V C R3 (OUT) C0 g C2 R0 m R2 245 µS C1 Figure31. Small-SignalModelforLoopResponse 7.4.14 SimpleSmall-SignalModelforPeak-Current-ModeControl Figure 31 is a simple small-signal model that one can use to understand how to design the frequency compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor approximates the TPS54388-Q1 power stage. Equation 10 shows the control-to- output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current divided by the change in COMP pin voltage (node c in Figure 31) is the power-stage transconductance. The g for the TPS54388-Q1 device is 25 S. The low-frequency gain of the power-stage m frequency response is the product of the transconductance and the load resistance as shown in Equation 11. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current (see Equation 12). The dashed line in the right half of Figure 32 highlights the combined effect. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same forvaryingloadconditions,whichmakesiteasiertodesignthefrequencycompensation. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com Device Functional Modes (continued) VO VC Adc R ESR fp RL gm ps C OUT fz Figure32. SimpleSmall-SignalModelandFrequencyResponseforPeak-Current-ModeControl æ s ö ç1+ ÷ VO =A ´ çè 2p ×f(z) ÷ø (dc) V(C) æ s ö ç1+ ÷ ç 2p ×f ÷ è (p) ø (10) A =g ´ R (dc) m(ps) (L) (11) 1 f = (p) C ´R ´ 2p (OUT) (L) (12) 1 f = (z) C ´R ´2p (OUT) (ESR) (13) 7.4.15 Small-SignalModelforFrequencyCompensation The TPS54388-Q1 device uses a transconductance amplifier for the error amplifier and readily supports two of thecommonly used frequency-compensation circuits. Figure 33 shows the compensation circuits. The most-likely implementation of Type 2B circuits is in high-bandwidth power-supply designs using low-ESR output capacitors. Type2Acontainsoneadditionalhigh-frequencypoletoattenuatehigh-frequencynoise. VO R1 VSENSE Type 2A Type 2B gm COMP ea R2 Vref RO CO R3 C2 R3 5pF C1 C1 Figure33. TypesofFrequencyCompensation 20 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Device Functional Modes (continued) ThedesignguidelinesforTPS54388-Q1 loopcompensationareasfollows: 1. Calculate the modulator pole, f , and the ESR zero, f , using Equation 14 and Equation 15. The (p,mod) (z,mod) output capacitor (C ) may require derating if the output voltage is a high percentage of the capacitor (OUT) rating.Usethemanufacturerinformationfor the capacitor to derate the capacitor value. Use Equation 16 and Equation 17 to estimate a starting point for the crossover frequency, f . Equation 16 is the geometric mean (c) of the modulator pole and the ESR zero, and Equation 17 is the mean of the modulator pole and the switching frequency. Use the lower value of Equation 16 or Equation 17 as the maximum crossover frequency. I O(max) f = (p,mod) 2p´V ´C O (OUT) (14) 1 f = (z,mod) 2p´R ´C (ESR) (OUT) (15) f = f ´f (c) (p,mod) (z,mod) (16) f f = f ´ (SW) (c) (p,mod) 2 (17) 2. DetermineR3usingEquation18. 2p´f ´V ´C (c) O (OUT) R3= g ´V ´ g m(ea) ref m(ps) where • g istheamplifiergain(245μS) m(ea) • g isthepower-stagegain(25S) (18) m(ps) 3. Placeacompensationzeroatthedominantpole: 1 f = (p) C ´R ´ 2p (OUT) (L) (19) 4. DetermineC1usingEquation20. R ´ C (L) (OUT) C1= R3 (20) verticalspacer 5. C2isoptional.Useit,ifnecessary,tocancelthezerofromtheESRofC . (OUT) R ´C (ESR) (OUT) C2= R3 (21) Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information Details on how to use this device in automotive applications appear throughout this device specification. The following sections provide the typical application use case with equations and methods on selecting the external components,aswellaslayoutguidelines. 8.2 Typical Application TPS54388RTE Figure34. High-Frequency,1.8-VOutputPower-SupplyDesignWithAdjustedUVLO 8.2.1 DesignRequirements This example details the design of a high-frequency switching-regulator design using ceramic output capacitors. To start the design process, it is necessary to know a few parameters. Determination of these parameters is typicallyatthesystemlevel.Forthisexample,startwiththefollowingknownparameters: Table1.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Outputvoltage 1.8V Transientresponse,1-Ato2-Aloadstep ΔV =5% (out) Maximumoutputcurrent 3A Inputvoltage 5Vnominal,3Vto5V Output-voltageripple <30mVp-p Switchingfrequency,f 1000kHz (sw) 22 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 8.2.2 DetailedDesignProcedure 8.2.2.1 CustomDesignWithWEBENCH® Tools ClickheretocreateacustomdesignusingtheTPS54388-Q1devicewiththeWEBENCH® PowerDesigner. 1. Startbyenteringtheinputvoltage(V ),outputvoltage(V ),andoutputcurrent(I )requirements. IN OUT OUT 2. Optimizethedesignforkeyparameterssuchasefficiency,footprint,andcostusingtheoptimizerdial. 3. ComparethegenerateddesignwithotherpossiblesolutionsfromTexasInstruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricingandcomponentavailability. Inmostcases,theseactionsareavailable: • Runelectricalsimulationstoseeimportantwaveformsandcircuitperformance • Runthermalsimulationstounderstandboardthermalperformance • ExportcustomizedschematicandlayoutintopopularCADformats • PrintPDFreportsforthedesign,andsharethedesignwithcolleagues GetmoreinformationaboutWEBENCHtoolsatwww.ti.com/WEBENCH. 8.2.2.2 SelectingtheSwitchingFrequency The first step is to decide on a switching frequency for the regulator. Typically, one would choose the highest switching frequency possible to produce the smallest solution size. The high switching frequency allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter performance. The converter is capable of running from 200 kHz to 2 MHz. Unless a small solution size is an ultimate goal, select a moderate switching frequency of 1 MHz to achieve both a small solution size and high- efficiency operation. Using Equation 8, calculate R5 to be 180 kΩ. Choose a standard 1% 182-kΩ value for the design. 8.2.2.3 OutputInductorSelection Theinductorselectedworksfortheentire TPS54388-Q1 input-voltagerange. To calculate the value of the output inductor, use Equation 22. The k coefficient represents the amount of inductor ripple current relative to the (IND) maximum output current. The output capacitor filters the inductor ripple current. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor, because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at thediscretionofthedesigner;however,k isnormallyfrom0.1to0.3forthemajorityofapplications. (IND) For this design example, use k = 0.3, and the inductor value calculates to be 1.36 μH. For this design, (IND) choose the nearest standard value of 1.5 μH. For the output-filter inductor, it is important not to exceed the rms- current and saturation-current ratings. Find the rms and peak inductor current using Equation 24 and Equation25. Forthisdesign,thermsinductorcurrentis3.01Aandthepeakinductorcurrentis3.72A.Thechosen inductor is a Coilcraft XLA4020-152ME_ or equivalent. It has a saturation current rating 0f 9.6 A and an RMS current rating of7.5A. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitch-currentlimitratherthanthepeakinductorcurrent. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com V - V V L1= I(max) O ´ O I ´ k V ´ f O (IND) I(max) (SW) (22) V - V V I = I(max) O ´ O (ripple) L1 V ´ f I(max) (SW) (23) 2 I = I 2 + 1 ´ æç VO ´ (VI(max) - VO) ö÷ (Lrms) O 12 çV ´ L1 ´ f ÷ è I(max) (SW) ø (24) I (ripple) I =I + (Lpeak) O 2 (25) 8.2.2.4 OutputCapacitor Three primary considerations must be considered for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large changeinloadcurrent.Basetheoutput-capacitanceselectiononthemost-stringentofthesethreecriteria. The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after removal of the input power. The regulator is temporarily not able to supply sufficient output current if there is a large, fast increase in the current requirement of the load, such as transitioning from no load to a full load. The regulator usually requires two or more clock cycles for the control loop to see the change in load current and output voltage and then adjust the duty cycle to react to the change. The output capacitor must be large enough to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessarytomeetthisrequirement. For this example, the specification for transient-load response is a 5% change in V for a load step from 0 A (no O load) to 1.5 A (50% load). For this example, ΔI = 1.5 A – 0 A = 1.5 A and ΔV = 0.05 × 1.8 V = 0.09 V. Using O O these numbers gives a minimum capacitance of 33 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in thiscalculation. Equation 27 calculates the minimum output capacitance needed to meet the output-voltage ripple specification. Inthiscase,themaximumoutput-voltagerippleis30mV.Underthisrequirement,Equation27yields2.3 µF. 2 ´ DI O C > (OUT) f ´ DV (SW) O where • ΔI isthechangeinoutputcurrent O • f istheregulatorswitchingfrequency (SW) • ΔV istheallowablechangeintheoutputvoltage (26) O 1 1 C > ´ (OUT) 8´f V (SW) O(ripple) I (ripple) where • f istheswitchingfrequency (SW) • V isthemaximumallowableoutputvoltageripple O(ripple) • I istheinductorripplecurrent (27) (ripple) Use Equation 28 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple specification. Equation 28 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic capacitorismuchlessthan55mΩ. 24 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 Factoring in additional capacitance deratings for aging, temperature, and dc bias increases this minimum value. Forthisexample,usetwo22-μF,10-VX5Rceramiccapacitorswith3mΩ ofESR. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. Select an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the root-mean-square (rms) value of the maximum ripple current. Use Equation 29 to calculate the rms ripplecurrentthattheoutputcapacitormustsupport.Forthisapplication,Equation29 yields333mA. V O(ripple) R < (ESR) I (ripple) (28) V ´ (V - V ) O I(max) O I = (Co,rms) 12´V ´ L1 ´ f I(max) (SW) (29) 8.2.2.5 InputCapacitor The TPS54388-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at least 4.7 μF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.Thecapacitormustalsohavearipple-currentrating greater than the maximum input-current ripple of the TPS54388-Q1 device.CalculatetheinputripplecurrentusingEquation30. The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. Minimize the capacitance variations due to temperature by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are the usual selection for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output- capacitor selection must also take dc bias into account. The capacitance value of a capacitor decreases as the dcbiasacrossthatcapacitorincreases. This example design requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum input voltage. For this example, the selection is one 10-μF 10-V and one 0.1-μF 10-V capacitor in parallel. The input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple using Equation 31. Using the design example values, I = 3 A, C = 10 μF, and f = 1 MHz, yields an O(max) (IN) (SW) inputvoltagerippleof76mVandanrmsinputripplecurrentof1.47A. ( ) I = I ´ VO ´ VI(min) - VO (Ci,rms) O V V I(min) I(min) (30) I ´ 0.25 DV = O(max) I C ´f (IN) (SW) (31) 8.2.2.6 Slow-StartCapacitor The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. Slow start is useful if a load requires a controlled rate of voltage slew. Another use for slow start is if the output capacitance is large and would require large amounts of current to charge the capacitor quickly to the output-voltage level. The large current necessary to charge the capacitor may make the TPS54388-Q1 device reach the current limit, or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems. Calculate the slow-start capacitor value using Equation 32. For the example circuit, the slow-start time is not too critical because the output-capacitor value is 44 μF, which does not require much current to charge to 1.8 V. The example circuit has the slow-start time set to an arbitrary value of 4 ms, which requires a 10-nF capacitor. In the TPS54388-Q1 device,I is2.2μAandV is0.8V. (SS/TR) ref t (ms) ´ I (mA) (SS) (SS/TR) C (nF)= (SS) V (V) ref (32) Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 8.2.2.7 BootstrapCapacitorSelection Connect a 0.1-μF ceramic capacitor between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage rating. 8.2.2.8 Output-VoltageandFeedback-ResistorSelection For the example design, the R6 selection is 100 kΩ. Using Equation 33, calculate R7 as 80 kΩ. The nearest standard1%resistoris80.5kΩ. V R7= ref ´R6 V - V O ref (33) Because of the internal design of the TPS54388-Q1 device, there is a minimum output-voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, an output voltage limit may exist due to the minimum controllable on-time. In this case, Equation 34 gives the minimumoutputvoltage: ( ) ( ) V =t ´f ´ V -I ´2´r -I ´ R +r O(min) (ONmin) (SWmax) I(max) O(min) DS(on) O(min) (L) DS(on) where • V =minimumachievableoutputvoltage O(min) • t =minimumcontrollableon-time(65nstypical,120nswithnoload) (ONmin) • f =maximumswitchingfrequency,includingtolerance (SWmax) • V =maximuminputvoltage I(max) • I =minimumloadcurrent O(min) • r =minimumhigh-sideMOSFETon-resistance(15mΩ–19mΩ) DS(on) • R =seriesresistanceofoutputinductor (34) (L) There is also a maximum achievable output voltage, which is limited by the minimum off-time. Equation 35 gives themaximumoutputvoltage. ( ) ( ) ( ) V = 1-t ´f ´ V -I ´2´r -I ´ R +r O(max) (OFFmax) (SWmax) I(min) O(max) DS(on) O(max) (L) DS(on) where • V =maximumachievableoutputvoltage O(max) • t =maximumoff-time(60ns,typical) (OFFmax) • f =maximumswitchingfrequency,includingtolerance (SWmax) • V =minimuminputvoltage I(min) • I =maximumloadcurrent O(max) • r =maximumhigh-sideMOSFETon-resistance(19mΩ–30mΩ) DS(on) • R =seriesresistanceofoutputinductor (35) (L) 26 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 8.2.2.9 Compensation The industry uses several techniques to compensate dc-dc regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54388-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is usually lowerthanthecrossoverfrequencyusedinthecalculations. To get started, calculate the modulator pole, f , and the ESR zero, f , using Equation 36 and (p,mod) (z,mod) Equation 37. For C , derating the capacitor is not necessary, as the 1.8-V output is a small percentage of the (OUT) 10-V capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, f . For the example design, f is 6.03 kHz and f is 1210 kHz. Equation 38 is (c) (p,mod) (z,mod) the geometric mean of the modulator pole and the ESR zero, and Equation 39 is the mean of the modulator pole and the switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of Equation 38 or Equation 39 as the approximate crossover frequency. For this example, f is 56 kHz. Next, (c) calculate the values of the compensation components. Use a resistor in series with a capacitor to create a compensatingzero.Acapacitorinparallelwiththesetwocomponentsformsthecompensatingpole(ifneeded). I O(max) f = (p,mod) 2p´V ´C O (OUT) (36) 1 f = (z,mod) 2p´R ´C (ESR) (OUT) (37) f = f ´f (c) (p,mod) (z,mod) (38) f f = f ´ (SW) (c) (p,mod) 2 (39) Thecompensationdesigntakesthefollowingsteps: 1. Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value for the compensation network. In this example, the anticipated crossover frequency (f ) is 56 kHz. The power-stage (c) gain(g )is25Sandtheerror-amplifiergain(g )is245μS. m(ps) m(ea) 2p´f ´V ´C (c) O (OUT) R3= g ´V ´ g m(ea) ref m(ps) (40) 2. Place a compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the capacitorforthecompensationnetworkusingEquation41. R0´C0 C3= R3 (41) 3. One can include an additional pole to attenuate high-frequency noise. In this application, the extra pole is not necessary. Fromtheproceduresabove,thecompensationnetworkincludesa7.68-kΩ resistoranda3300-pFcapacitor. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 8.2.2.10 Power-DissipationEstimate Thefollowingformulas show how to estimate the IC power dissipation under continuous-conduction mode (CCM) operation. The power dissipation of the IC (P ) includes conduction loss (P ), dead-time loss (P ), switching T (con) (d) loss(P ),gate-driveloss(P )andsupply-currentloss(P ). (SW) (gd) (q) P = I 2´r (con) O DS(on)(Temp) where • I istheoutputcurrent(A) O • r istheon-resistanceofthehigh-sideMOSFETatagiventemperature(Ω) (42) DS(on)(Temp) P = f ´I ´0.7´60´10-9 (d) (SW) O where • f istheswitchingfrequency(Hz) (43) (SW) P = 1/2 ´V ´I ´f ´8´10-9 (SW) I O (SW) where • V istheinputvoltage(V) (44) I P = 2 ´V ´f ´2´10-9 (gd) I (SW) (45) P = V ´515´10-6 (q) I (46) Therefore: P = P +P +P +P +P T (con) (d) (SW) (gd) (q) (47) ForagivenT ,useEquation48tocalculatethejunctiontemperature. A T = T +R ´P J A qJA T where • T isthejunctiontemperature(°C) J • T istheambienttemperature(°C) A • R isthethermalresistanceofthepackage(°C/W) θJA • P isthetotaldevicepowerdissipation(W) (48) T ForagivenT =150°C,useEquation49 tocalculatethemaximumambienttemperature. J(max) T = T -R ´P A(max) J(max) qJA T where • T ismaximumjunctiontemperature(°C) J(max) • T ismaximumambienttemperature(°C) (49) A(max) Additional power losses occur in the regulator circuit because of the inductor ac and dc losses and trace resistancethatimpacttheoverallefficiencyoftheregulator. 28 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 8.2.3 ApplicationCurves 100 100 90 90 80 V = 3.3 V 80 (VIN) 70 70 V = 5 V Efficiency (%) 456000 (VIN) Efficiency (%)456000 V(VIN)= 3.3 V V(VIN)= 5 V 30 30 20 20 10 10 0 0 0 0.5 1 1.5 2 2.5 3 0.001 0.01 0.1 1 10 Output Current (A) Output Current (A) VO=1.8V VO=1.8V Figure35.EfficiencyvsLoadCurrent Figure36.EfficiencyvsLoadCurrent 100 100 1.8 V 2.5 V 95 95 90 90 85 85 2.5 V 1.8 V ncy (%) 7850 1.05 V 1.2 V 1.5 V ncy (%) 7850 3.3 V 1.5 V 1.2 V 1.05V e e Effici 70 Effici 70 65 65 60 60 55 55 50 50 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 Output Current (A) Output Current (A) V =3.3V f =1MHz T =25°C V =5V f =1MHz T =25°C (VIN) (SW) A (VIN) (SW) A Figure37.EfficiencyvsLoadCurrent Figure38.EfficiencyvsLoadCurrent V(VIN)= 2 V/div V(VIN)= 2 V/div EN = 1 V/div EN = 1 V/div SS/TR = 1 V/div SS/TR = 1 V/div VO= 1 V/div VO= 1 V/div Time = 5 ms/div Time = 500ms/div Figure39.PowerUpVO,V(VIN) Figure40.PowerDownVO,V(VIN) Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com VO= 100 mV/div (ac-coupled) V(VIN)= 5 V/div V = 2 V/div O I = 1A/div (0-Ato 1.5-Aload step) O EN = 2 V/div PWRGD = 5 V/div Time = 200 µs/div Time = 5 ms/div Figure41.TransientResponse,1.5-AStep Figure42.PowerUpVO,V(VIN) V = 5 V/div (VIN) V = 20 mV/div (ac-coupled) O V = 2 V/div O PH = 2 V/div EN = 2 V/div PWRGD = 5 V/div Time = 5 ms/div Time = 500 ns/div Figure43.PowerUpV ,EN Figure44.OutputRipple,3A O 60 180 50 150 V = 100 mV/div (ac coupled) (VIN) 40 120 30 90 20 60 es) ain (dB) 100 300 e (degre G–10 –30 s PH = 2 V/div a –20 –60 Ph –30 –90 –40 –120 –50 Gain –150 Phase –60 –180 10 100 1000 10k 100k 1M Frequency - Hz Time = 500 ns/div V(VIN)=5V IO=3A Figure45.InputRipple,3A Figure46.Closed-LoopResponse 30 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 0.4 0.4 0.3 0.3 eviation (%) 00..21 V(VIN)= 5 V eviation (%) 00..21 D D e 0 e 0 Voltag –0.1 V(VIN)= 3.3 V Voltag–0.1 ut ut utp –0.2 utp–0.2 O O –0.3 –0.3 –0.4 –0.4 0 0.5 1 1.5 2 2.5 3 3 3.5 4 4.5 5 5.5 6 Output Current (A) Input Voltage (V) I =2A O Figure47.LoadRegulationvsLoadCurrent Figure48.RegulationvsInputVoltage 9 Power Supply Recommendations By design, the TPS54388-Q1 device works with an analog supply voltage range of 2.95 V to 6 V. Ensure good regulation for the input supply, and connect the supply to the VIN pins with the appropriate input capacitor as calculated in the Input Capacitor section. If the input supply is located more than a few inches from the TPS54388-Q1 device,thedesignmayrequireextracapacitanceinadditiontotherecommendedvalue. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power-supply design. The signal paths, which conduct fast-changing currents or voltages, can interact with stray inductance or parasitic capacitance in several ways to generate noise or degrade the power-supply performance. Take care to minimize the loop area formed by the bypass-capacitor connectionsandtheVINpins.SeeFigure49foraPCB layout example. Tie the GND pins and AGND pin directly to the thermal pad under the IC. Connect the thermal pad to any internal PCB ground planes using multiple vias directly under the IC. Use additional vias to connect the top-side ground area to any internal planes near the input and output capacitors. For operation at full-rated load, the top-side ground area, along with any additional internalgroundplanes,mustprovideadequateheat-dissipatingarea. Locate the input bypass capacitor as close to the IC as possible. Route the PH pin to the output inductor. Because the PH connection is the switching node, locate the output inductor close to the PH pins, and minimize the area of the PCB conductor to prevent excessive capacitive coupling. Also. locate the boot capacitor close to the device. Connect the sensitive analog ground connections for the feedback voltage divider, compensation components, slow-start capacitor, and frequency-set resistor to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise, so locate the Rt resistor as close as possible to the IC, and connect it with minimal lengths of trace. Place the additional external components approximately as shown. It may be possible to obtain acceptable performance with alternative PCB layouts. However, this layout, meant as a guideline,producesgoodresults. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 10.2 Layout Example VIAto UVLO SET Ground RESISTORS Plane VIN D T VIN EN WRG BOO BOOT P CAPACITOR VIN INPUT OUTPUT VOUT VIN PH BYPASS INDUCTOR CAPACITOR VIN EXPOSED PH OUTPUT POWERPAD FILTER PH GND AREA PH CAPACITOR GND SS SLOW START AGND VSENSE COMP RT/CLK CAPACITOR FEEDBACK ANALOG RESISTORS GROUND TRACE FREQUENCY SET RESISTOR COMPENSATION NETWORK TOPSIDE GROUND AREA VIA to Ground Plane Figure49. PCBLayoutExample 32 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 www.ti.com SLVSAF1E–OCTOBER2010–REVISEDMAY2019 11 Device and Documentation Support 11.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Device Support 11.2.1 DevelopmentSupport 11.2.1.1 CustomDesignWithWEBENCH® Tools ClickheretocreateacustomdesignusingtheTPS54388-Q1devicewiththeWEBENCH® PowerDesigner. 1. Startbyenteringtheinputvoltage(V ),outputvoltage(V ),andoutputcurrent(I )requirements. IN OUT OUT 2. Optimizethedesignforkeyparameterssuchasefficiency,footprint,andcostusingtheoptimizerdial. 3. ComparethegenerateddesignwithotherpossiblesolutionsfromTexasInstruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricingandcomponentavailability. Inmostcases,theseactionsareavailable: • Runelectricalsimulationstoseeimportantwaveformsandcircuitperformance • Runthermalsimulationstounderstandboardthermalperformance • ExportcustomizedschematicandlayoutintopopularCADformats • PrintPDFreportsforthedesign,andsharethedesignwithcolleagues GetmoreinformationaboutWEBENCHtoolsatwww.ti.com/WEBENCH. 11.3 Documentation Support Forrelateddocumentation,seethefollowing: • EnableFunctionalityandAdjustingUndervoltageLockoutforTPS57112-Q1 (SLVA784) • Interfacing TPS57xxx-Q1,TPS65320-Q1 Family, and TPS65321-Q1 Devices With Low Impendence External ClockDrivers(SLVA755) • TPS57112-Q1HighFrequency(2.35MHz)Operation (SLVA743) • TPS54388EVMUser'sGuide(SLVU962) • TPS54388-Q1PinOpenandShortTestResults (SLVA581) 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54388-Q1

TPS54388-Q1 SLVSAF1E–OCTOBER2010–REVISEDMAY2019 www.ti.com 11.5 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.6 Trademarks E2EisatrademarkofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. 11.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 11.8 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated devices. This data is subject to change without notice and without revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,seetheleft-handnavigationpane. 34 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:TPS54388-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54388QRTERQ1 ACTIVE WQFN RTE 16 3000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 5438Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-May-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54388QRTERQ1 WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-May-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54388QRTERQ1 WQFN RTE 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated