Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 TPS54340-Q1 4.5-V to 42-V Input, 3.5-A, Step-Down DC-DC Converter With Eco-Mode™ 1 Features 3 Description • QualifiedforAutomotiveApplications The TPS54340-Q1 device is a 42-V, 3.5-A, step- 1 downregulatorwithanintegratedhigh-sideMOSFET. • AEC-Q100QualifiedWiththeFollowingResults: The device survives load-dump pulses up to 45 V per – DeviceTemperatureGrade1: –40°Cto125°C ISO 7637. Current-mode control provides simple AmbientOperatingTemperatureRange external compensation and flexible component – DeviceHBMESDClassificationLevelH1C selection. A low-ripple pulse-skip mode reduces the no-load supply current to 146 μA. Shutdown supply – DeviceCDMESDClassificationLevelC3B current is reduced to 1 μA when the enable pin is • HighEfficiencyatLightLoadsWithPulseSkipping pulledlow. Eco-mode™ Undervoltage lockout is internally set at 4.3 V but can • 92-mΩ High-SideMOSFET be increased using an external resistor divider at the • 146-μAOperatingQuiescentCurrentand2-µA enable pin. The output voltage start-up ramp is ShutdownCurrent internally controlled to provide a controlled start-up andeliminateovershoot. • 100-kHzto2.5-MHzAdjustableSwitching Frequency A wide adjustable frequency range allows for • SynchronizestoExternalClock optimization of either efficiency or external component size. Frequency foldback and thermal • LowDropoutatLightLoadsWithIntegrated shutdown protects internal and external components BOOTRechargeFET duringanoverloadcondition. • AdjustableUVLOVoltageandHysteresis The TPS54340-Q1 device is available in an 8-pin • 0.8V1%InternalVoltageReference thermally-enhancedHSOICPowerPADpackage. • 8-PinHSOICWith PowerPAD™Package • –40°Cto150°CT OperatingRange DeviceInformation(1) J • Supportedby WEBENCH®SoftwareTool PARTNUMBER PACKAGE BODYSIZE(NOM) TPS54340-Q1 HSOP(8) 4.89mm×3.90mm 2 Applications (1) For all available packages, see the orderable addendum at theendofthedatasheet. • VehicleAccessories:GPS(SeeSLVA412), Entertainment,ADAS,eCall • USBDedicatedChargingPortsandBattery Chargers(SeeSLVA464) • IndustrialAutomationandMotorControl • 12-Vand24-VIndustrial,Automotive,and CommunicationsPowerSystems SPACE SimplifiedSchematic EfficiencyvsLoadCurrent VIN VIN 100 90 TPS54340-Q1 80 EN VOUT= 5V BOOT 70 VOUT % VOUT= 3.3V RT/CLK SW y - 60 nc 50 e R1 ci 40 COMP Effi FB 30 R3 20 V = 12V GND 10 IN fsw = 600 kHz 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 I - Output Current -A O 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................22 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 23 3 Description............................................................. 1 8.1 ApplicationInformation............................................23 4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................23 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 35 6 Specifications......................................................... 4 10 Layout................................................................... 35 6.1 AbsoluteMaximumRatings .....................................4 10.1 LayoutGuidelines.................................................35 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................36 6.3 RecommendedOperatingConditions.......................4 10.3 EstimatedCircuitArea..........................................36 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 37 6.5 ElectricalCharacteristics...........................................5 11.1 DeviceSupport......................................................37 6.6 RT/CLKTimingRequirements..................................5 11.2 DocumentationSupport........................................37 6.7 SwitchingCharacteristics..........................................6 11.3 CommunityResources..........................................37 6.8 TypicalCharacteristics..............................................7 11.4 Trademarks...........................................................37 7 DetailedDescription............................................ 11 11.5 ElectrostaticDischargeCaution............................37 7.1 Overview.................................................................11 11.6 Glossary................................................................37 7.2 FunctionalBlockDiagram.......................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 37 7.3 FeatureDescription.................................................12 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromOriginal(September2013)toRevisionA Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 5 Pin Configuration and Functions DDAPackage 8-PinHSOP TopView BOOT 1 8 SW VIN 2 Thermal 7 GND Pad 9 EN 3 6 COMP RT/CLK 4 5 FB PinFunctions PIN I/O DESCRIPTION NAME NO. AbootstrapcapacitorisrequiredbetweenBOOTandSW.Ifthevoltageonthiscapacitorisbelowthe BOOT 1 O minimumrequiredtooperatethehigh-sideMOSFET,theoutputswitchesoffuntilthecapacitorisrefreshed. Erroramplifieroutputandinputtotheoutputswitchcurrent(PWM)comparator.Connectfrequency COMP 6 O compensationcomponentstothispin. Enablepin,withinternalpullupcurrentsource.Pullbelow1.2Vtodisable.Floattoenable.Adjusttheinput EN 3 I undervoltagelockoutwithtworesistors.SeetheEnableandAdjustingUndervoltageLockoutsection. FB 5 I Invertinginputofthetransconductance(gm)erroramplifier. GND 7 — Ground ResistorTimingandExternalClock.Aninternalamplifierholdsthispinatafixedvoltagewhenusingan externalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLLupperthreshold, RT/CLK 4 I amodechangeoccursandthepinbecomesasynchronizationinput.Theinternalamplifierisdisabledand thepinisahighimpedanceclockinputtotheinternalPLL.Ifclockingedgesstop,theinternalamplifieris reenabledandtheoperatingmodereturnstoresistorfrequencyprogramming. SW 8 I Thesourceoftheinternalhigh-sidepowerMOSFETandswitchingnodeoftheconverter. ThermalPad 9 — GNDpinmustbeelectricallyconnectedtotheexposedpadontheprinted-circuit-boardforproperoperation. VIN 2 I Inputsupplyvoltagewith4.5-Vto42-Voperatingrange. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VIN –0.3 45 EN –0.3 8.4 BOOT 53 Inputvoltage V FB –0.3 3 COMP –0.3 3 RT/CLK –0.3 3.6 BOOT-SW 8 Outputvoltage SW –0.6 45 V SW,10-nsTransient –2 45 Operatingjunctiontemperature –40 150 °C Storagetemperature –65 150 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Supplyinputvoltage 4.5 42 V IN V Outputvoltage 0.8 58.8 V O I Outputcurrent 0 3.5 A O T JunctionTemperature –40 150 °C J 6.4 Thermal Information TPS54340-Q1 THERMALMETRIC(1)(2) DDA(HSOP) UNIT 8PINS R Junction-to-ambientthermalresistance(standardboard) 42 °C/W θJA R Junction-to-case(top)thermalresistance 45.8 °C/W θJC(top) R Junction-to-boardthermalresistance 23.4 °C/W θJB ψ Junction-to-topcharacterizationparameter 5.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 23.4 °C/W JB R Junction-to-case(bottom)thermalresistance 3.6 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. (2) PowerratingataspecificambienttemperatureTAshouldbedeterminedwithajunctiontemperatureof150°C.Thisisthepointwhere distortionstartstosubstantiallyincrease.Seepowerdissipationestimateinapplicationsectionofthisdatasheetformoreinformation. 4 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 6.5 Electrical Characteristics T =–40°Cto150°C,VIN=4.5Vto42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage 4.5 42 V Internalundervoltagelockout Rising 4.1 4.3 4.48 V threshold Internalundervoltagelockout 325 mV thresholdhysteresis Shutdownsupplycurrent EN=0V,25°C,4.5V≤VIN≤42V 2.25 4.5 Operating:nonswitching μA supplycurrent FB=0.9V,TA=25°C 146 175 ENABLEANDUVLO(ENPIN) Enablethresholdvoltage Novoltagehysteresis,risingandfalling 1.1 1.2 1.3 V Enablethreshold50mV –4.6 Inputcurrent μA Enablethreshold–50mV –0.58 –1.2 -1.8 Hysteresiscurrent –2.2 –3.4 -4.5 μA EnabletoCOMPactive VIN=12V,TA=25°C 540 µs INTERNALSOFT-STARTTIME Soft-StartTime fSW=500kHz,10%to90% 2.1 ms Soft-StartTime fSW=2.5MHz,10%to90% 0.42 ms VOLTAGEREFERENCE Voltagereference 0.792 0.8 0.808 V HIGH-SIDEMOSFET On-resistance VIN=12V,BOOT-SW=6V 92 190 mΩ ERRORAMPLIFIER Inputcurrent 50 nA Erroramplifier transconductance(gM) –2μA<ICOMP<2μA,VCOMP=1V 350 μS Erroramplifier transconductance(gM)during –2μA<ICOMP<2μA,VCOMP=1V,VFB=0.4V 77 μS soft-start ErroramplifierDCgain VFB=0.8V 10,000 V/V Minunitygainbandwidth 2500 kHz Erroramplifiersourceand sink V(COMP)=1V,100-mVoverdrive ±30 μA COMPtoSWcurrent 12 A/V transconductance CURRENTLIMIT AllVINandtemperatures,OpenLoop(1) 4.5 5.5 6.8 Currentlimitthreshold Alltemperatures,VIN=12V,OpenLoop(1) 4.5 5.5 6.25 A VIN=12V,TA=25°C,OpenLoop(1) 5.2 5.5 5.85 Currentlimitthresholddelay 60 ns THERMALSHUTDOWN Thermalshutdown 176 °C Thermalshutdownhysteresis 12 °C TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) RT/CLKhighthreshold 1.55 2 V RT/CLKlowthreshold 0.5 1.2 V (1) OpenLoopcurrentlimitmeasureddirectlyattheSWpinandisindependentoftheinductorvalueandslopecompensation. 6.6 RT/CLK Timing Requirements MIN NOM MAX UNIT MinimumCLKinputpulsewidth 15 ns Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com 6.7 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) SwitchingfrequencyrangeusingRT 100 2500 kHz mode ƒ Switchingfrequency R =200kΩ 450 500 550 kHz SW T Switchingfrequencyrangeusing 160 2300 kHz CLKmode RT/CLKfallingedgetoSWrising Measuredat500kHzwithRT 55 ns edgedelay resistorinseries PLLlockintime Measuredat500kHz 78 μs 6 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 6.8 Typical Characteristics 0.25 0.814 ) BOOT-SW = 3 V VIN = 12 V Wesistance ( 0.01.52 BOOT-SW = 6 V erence (V) 00..880049 ate R e Ref 0.799 − On-St()SON 0.00.51 V − VoltagFB00..778994 D R 0 0.784 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ − Junction Temperature (°C) G001 TJ − Junction Temperature (°C) G002 Figure1.ONResistancevsJunctionTemperature Figure2.VoltageReferencevsJunctionTemperature 6.5 6.5 6.3 VIN = 12 V 6.3 TJ=−40°C ent (A) 56..91 ent (A) 56..91 TTJJ== 2155°0C°C Curr 5.7 Curr 5.7 h h witc 5.5 witc 5.5 Side S 55..13 Side S 55..13 High- 4.9 High- 4.9 4.7 4.7 4.5 4.5 −50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 TJ − Junction Temperature (°C) G003 VIN−Input Voltage (V) G004 Figure3.SwitchCurrentLimitvsJunctionTemperature Figure4.SwitchCurrentLimitvsInputVoltage 550 500 Hz) 540 RT = 200 kW , VIN = 12 V Hz) 450 ƒRSTW ( k(WkH) z=) 1=0 912745167· ·fSRWT ((kkHW z))--01.9.09018 k 530 k 400 y ( y ( nc 520 nc 350 e e qu 510 qu 300 e e g Fr 500 g Fr 250 n n hi 490 hi 200 c c wit 480 wit 150 S S − 470 − 100 W W ƒS 460 ƒS 50 450 0 −50 −25 0 25 50 75 100 125 150 200 300 400 500 600 700 800 900 1000 TJ − Junction Temperature (°C) G005 RT/CLK − Resistance (kW ) G006 Figure5.SwitchingFrequencyvsJunctionTemperature Figure6.SwitchingFrequencyvsRT/CLKResistance Low-FrequencyRange Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) 2500 500 VIN = 12 V z) H 450 k 2000 y ( c en 400 equ 1500 B) ng Fr m (d 350 hi 1000 g witc 300 S − 500 W 250 S ƒ 0 200 0 50 100 150 200 −50 −25 0 25 50 75 100 125 150 RT/CLK − Resistance (kW ) G007 TJ − Junction Temperature (°C) G008 Figure7.SwitchingFrequencyvsRT/CLKResistance Figure8.EATransconductancevsJunctionTemperature High-FrequencyRange 120 1.3 110 VIN = 12 V 1.29 VIN = 12 V 1.28 100 1.27 90 V) 1.26 V) 80 old ( 11..2245 gm (uA/ 6700 − Thresh 111...222123 50 N 1.2 E 1.19 40 1.18 1.17 30 1.16 20 1.15 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ − Junction Temperature (°C) G009 TJ − Junction Temperature (°C) G010 Figure9.EATransconductanceDuringSoftStartvs Figure10.ENPinVoltagevsJunctionTemperature JunctionTemperature −0.5 −4 −0.7 VIN= 5 V,IEN=Threshold+50mV −4.1 VIN= 12 V,IEN=Threshold+50mV −0.9 −4.2 −1.1 −4.3 −1.3 −4.4 A) A) (µ −1.5 (µ −4.5 N N IE−1.7 IE−4.6 −1.9 −4.7 −2.1 −4.8 −2.3 −4.9 −2.5 −5 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ−JunctionTemperature (°C) G011 Tj−JunctionTemperature (°C) G012 Figure11.ENPinCurrentvsJunctionTemperature Figure12.ENPinCurrentvsJunctionTemperature 8 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 Typical Characteristics (continued) −2.5 100 A) −2.7 ncy VVFFBB FRaislliinngg esis (µ −−32..19 Freque 75 er g yst −3.3 hin nt H −3.5 witc 50 e S urr −3.7 al C n EN PIN −−−443...319 VIN = 12 V % of Nomi 25 −4.5 0 −50 −25 0 25 50 75 100 125 150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 TJ − Junction Temperature (°C) G112 VFB (V) G013 Figure13.ENPinCurrentHysteresisvs Figure14.SwitchingFrequencyvsFB JunctionTemperature 3 3 VIN = 12 V TJ= 25°C A) 2.5 A) 2.5 µ µ Current ( 2 Current ( 2 Supply 1.5 Supply 1.5 wn 1 wn 1 Shutdo 0.5 Shutdo 0.5 0 0 −50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 TJ − Junction Temperature (°C) G014 VIN−Input Voltage (V) G016 Figure15.ShutdownSupplyCurrentvs Figure16.ShutdownSupplyCurrentvsInputVoltage(V ) IN JunctionTemperature 210 210 VIN = 12 V 190 190 B) A) nt (d 170 nt (µ 170 e e Curr 150 Curr 150 Supply 130 Supply 130 − 110 − 110 V IN VIN 90 90 70 70 −50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 TJ − Junction Temperature (°C) G016 VIN−Input Voltage (V) G018 Figure17.VINSupplyCurrentvsJunctionTemperature Figure18.VINSupplyCurrentvsInputVoltage Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) 2.6 4.5 BOOT-SW UVLO Falling 2.5 BOOT-SW UVLO Rising 4.4 B) 2.4 4.3 d SW) ( 2.3 ge (V) 4.2 − a OT 2.2 olt 4.1 BO 2.1 ut V 4 − ( np V IN 2 I 3.9 1.9 3.8 UVLO Start Switching UVLO Stop Switching 1.8 3.7 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ − Junction Temperature (°C) G018 Tj − Junction Temperature (°C) G019 Figure19.BOOT-SWUVLOvsJunctionTemperature Figure20.InputVoltageUVLOvsJunctionTemperature 10 5.6 V = 12V, Start 9 IN 5.5 Stop T = 25oC J 8 5.4 ms) 7 5.3 me ( 6 V) 5.2 StartTi 54 V (IN55..01 DVrooltpaoguet oft- 3 4.9 Dropout S 2 4.8 Voltage 4.7 1 0 4.6 100 300 500 700 90011001300150017001900210023002500 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Switching Frequency (KHz) G021 Output Current (A) C026 Figure21.Soft-StartTimevsSwitchingFrequency Figure22.5-VStartandStopVoltage (seeLowDropoutOperationandBootstrapVoltage(BOOT)) 10 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 7 Detailed Description 7.1 Overview The TPS54340-Q1 device is a 42-V, 3.5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. The device implements constant-frequency current-mode control, which reduces output capacitance and simplifies external frequency compensation. The wide switching-frequency range of 100 kHz to 2500 kHz allows for either efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase- locked loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turnon to a falling edge of an externalclocksignal. The TPS54340-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin adjusts the inputvoltageundervoltagelockout(UVLO)thresholdwithtwoexternalresistors.Aninternalpullupcurrentsource enables operation when the EN pin is floating. The operating current is 146 μA under no load condition (not switching).Whenthedeviceisdisabled,thesupplycurrentis1μA. The integrated 92-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering 3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54340-Q1 device reduces the external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340-Q1 device to operate at high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltageoftheapplication.Theminimumoutputvoltageistheinternal0.8-Vfeedbackreference. Output-overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP comparator is activated, the high-side MOSFET turns off and remains off until the output voltage is less than 106%ofthedesiredoutputvoltage. The TPS54340-Q1 device includes an internal soft-start circuit that slows the output rise time during start-up to reduce in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency-foldback circuit reduces the switching frequency during start-up and overcurrentfaultconditionstohelpmaintaincontroloftheinductorcurrent. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com 7.2 Functional Block Diagram EN VIN Shutdown Thermal Shutdown UVLO Enable OV Logic Comparator Shutdown Shutdown Logic Enable Threshold Boot Charge Voltage Minimum Boot Reference Clamp UVLO CSuernresnet Pulse Error S kip Amplifier PWM FB Comparator BOOT Logic Shutdown 6 Slope Compensation COMP SW Frequency Foldback Reference DAC for Soft-Start Maximum Clamp Oscillator with PLL GND POWERPAD RT/CLK 7.3 Feature Description 7.3.1 Fixed-FrequencyPWMControl The TPS54340-Q1 device uses fixed-frequency peak-current-mode control with adjustable switching frequency. The output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output at the COMP pin controls the high-side power-switch current. When the high-side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements current limiting by clamping the COMP-pin voltage to a maximum level. The pulse skipping Eco-mode is implemented withaminimumvoltageclampontheCOMPpin. 7.3.2 SlopeCompensationOutputCurrent The TPS54340-Q1 device adds a compensating ramp to the MOSFET switch-current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the high-sideswitchisnotaffectedbytheslopecompensationandremainsconstantoverthefullduty-cyclerange. 12 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 Feature Description (continued) 7.3.3 PulseSkipEco-mode™ The TPS54340-Q1 device operates in a pulse skipping Eco-mode at light-load currents to improve efficiency by reducing switching and gate-drive losses. If the output voltage is within regulation and the peak-switch current at the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-mode. The pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of 600mV. When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited. Becausethedeviceisnotswitching,theoutputvoltagebeginstodecay.Thevoltagecontrollooprespondstothe falling output voltage by increasing the COMP pin voltage. The high-side MOSFET enables and switching resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light-loadcurrentsinEco-mode,theswitchingtransitionsoccursynchronouslywiththeexternalclocksignal. During Eco-mode operation, the TPS54340-Q1 device senses and controls peak switch current, not the average loadcurrent.ThereforetheloadcurrentatwhichthedeviceentersEco-modeisdependentontheoutputinductor value.ThecircuitinFigure34entersEco-modeatabout31.4-mA output current. As the load current approaches zero,thedeviceentersapulse-skipmodeduringwhichitdrawsonly146-μAinputquiescentcurrent. 7.3.4 LowDropoutOperationandBootstrapVoltage(BOOT) The TPS54340-Q1 device provides an integrated-bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor refreshes when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT capacitor is 0.1 μF. For stable performance over temperature and voltage, TI recommends a ceramic capacitorwithanX7RorX5Rgradedielectricwithavoltageratingof10Vorhigher. When operating with a low-voltage difference from input to output, the high-side MOSFET of the TPS54340-Q1 device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the voltage from BOOT to SW drops to less than 2.1 V, the high-side MOSFET turns off and an integrated low-side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high-outputvoltages,itisdisabledat24-Voutputandreenabledwhentheoutputreaches21.5V. Because the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus, the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low- sidediodevoltage,andtheprinted-circuit-boardresistance. The start and stop voltage for a typical 5-V output application is shown in Figure 22, where the V voltage is IN plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within 1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where switchingstops. During high-duty-cycle (low-dropout) conditions, the inductor-current ripple increases when the BOOT capacitor recharges which results in an increase in output voltage ripple. Increased ripple occurs when the off time required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle PWMcontrol. At heavy loads, the minimum input voltage must be increased to ensure a monotonic start-up. Equation 1 calculatestheminimuminputvoltageforthiscondition. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) V max=Dmax×(V min–I max×R +V )–V –I max×R O VIN O DS(on) d d O dc where • Dmax≥0.9 • V =ForwardDropoftheCatchDiode d • R =1/(–0.3×VB2SW2+3.577×VB2SW–4.246) DS(on) • VB2SW=VBOOT+V d • VBOOT=(1.41×V –0.554–V ׃ ×10–6–1.847×103×IB2SW)/(1.41+ƒ ×10-6) VIN d sw sw • IB2SW=100×10–6A (1) 7.3.5 ErrorAmplifier The TPS54340-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft- startvoltage. The frequency compensation components (capacitor, series resistor and capacitor) are connected between the erroramplifieroutputCOMPpinandGNDpin. 7.3.6 AdjustingtheOutputVoltage The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor divider from the output node to the FB pin. TI recommends using divider resistors with a 1% tolerance or better. Select the low-side resistor R for the desired divider current, and use Equation 2 to calculate R . To improve LS HS efficiency at light loads, consider using larger value resistors. However, if the values are too high, the regulator is moresusceptibletonoiseandvoltageerrorsfromtheFBinputcurrentmaybecomenoticeable. æVout - 0.8Vö RHS =RLS ´ ç ÷ è 0.8V ø (2) 7.3.7 EnableandAdjustingUndervoltageLockout The TPS54340-Q1 device is enabled when the VIN-pin voltage rises above 4.3 V and the EN-pin voltage exceeds the enable threshold of 1.2 V. The TPS54340-Q1 device is disabled when the VIN pin voltage falls to less than 4 V, or when the EN pin voltage is less than 1.2 V. The EN pin has an internal pullup current source, I1,of1.2μAthatenablesoperationoftheTPS54340-Q1devicewhentheENpinfloats. If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled to less than 1.2 V, the 3.4 μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 3 to calculate R for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R for UVLO1 UVLO2 thedesiredVINstartvoltage. In applications designed to start at relatively low input voltages (for example 4.5 V) and withstand high input voltages (for example 40 V), the EN pin can experience a voltage greater than the absolute maximum voltage of 8.4Vduringthehigh-inputvoltagecondition.TIrecommendsusingaZenerdiodetoclampthepinvoltagebelow theabsolutemaximumrating. 14 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 Feature Description (continued) VIN TPS54340-Q1 VIN i1 ihys RUVLO1 RUVLO1 10 kW EN EN Node Optional V EN RUVLO2 RUVLO2 5.8 V Figure23.AdjustableUndervoltageLockout Figure24.InternalENClamp (UVLO) V -V R = START STOP UVLO1 I HYS (3) V R = ENA UVLO2 V -V START ENA +I R 1 UVLO1 (4) 7.3.8 InternalSoft-Start The TPS54340-Q1 device has an internal digital soft-start that ramps the reference voltage from 0 V to the final valuein1024switchingcycles.Theinternalsoft-starttime(10%to90%)iscalculatedusingEquation5 1024 t (ms)= SS fSW(kHz) (5) If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft start resets. The softstartalsoresetsinthermalshutdown. 7.3.9 ConstantSwitchingFrequencyandTimingResistor(RT/CLK)Pin) The switching frequency of the TPS54340-Q1 device is adjustable over a wide range from 100 kHz to 2500 kHz by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 6 or Equation 7 or the curves in Figure 5 and Figure 6. To reduce the solution size one typically sets the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage, and minimum controllable on time must be considered. The minimum-controllable on time is typically135nswhichlimitsthemaximumoperatingfrequencyinapplicationswithhighinput-to-outputstep-down ratios. The maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed discussion of the maximum switching frequency is provided in Accurate Current Limit Operation and Maximum SwitchignFrequency. 92417 RT(kW)= fsw(kHz)0.991 (6) 101756 fsw(kHz)= RT(kW)1.008 (7) Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) 7.3.10 AccurateCurrentLimitOperationandMaximumSwitchignFrequency The TPS54340-Q1 device implements peak-current-mode control in which the COMP-pin voltage controls the peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high- side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switchcurrentbydrivingtheCOMPpinhigh.Theerroramplifieroutputisclampedinternallyatalevelwhichsets the peak switch-current limit. The TPS54340-Q1 device provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The relationshipbetweentheinductorvalueandthepeakinductorcurrentisshowninFigure25. Peak Inductor Current Δ A) CLPeak Open Loop Current Limit nt ( e urr C or ct u d n I Δ =V /Lx t CLPeak IN CLdelay t CLdelay t ON Figure25. currentlimitDelay To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340-Q1 device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54340-Q1 device uses a digital-frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short circuit events, the inductor current exceeds the peak current limit because of the high input voltage and the minimum-controllable on time. When the shorted load forces the output voltage low, the inductor current decreases slowly during the switch-offtime.Thefrequencyfoldbackeffectivelyincreasestheofftimebyincreasingtheperiodoftheswitching cycleprovidingmoretimefortheinductorcurrenttorampdown. With a maximum frequency-foldback ratio of 8, there is a maximum frequency at which the inductor current is controlledbyfrequency-foldbackprotection.Equation9calculatesthemaximumswitchingfrequencyatwhichthe inductor current remains under control when V is forced to V . The selected operating frequency must OUT OUT(SC) notexceedthecalculatedvalue. Equation 8 calculates the maximum switching-frequency limitation set by the minimum-controllable on time and the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip switchingpulsestoachievethelowdutycyclerequiredatmaximuminputvoltage. æ ö 1 I ´R +V +V f ( )= ´ç O dc OUT d ÷ SW maxskip tON çèVIN-IO´RDS(on)+Vd ÷ø (8) 16 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 Feature Description (continued) æI ´R +V +V ö fSW(shift) = tfDIV ´çç CVL -Idc ´ROUT(sc)+V d ÷÷ ON è IN CL DS(on) d ø where • I istheoutputcurrent O • I isthecurrentlimit CL • R istheinductorresistance dc • V isthemaximuminputvoltage IN • V istheoutputvoltage OUT • V istheoutputvoltageduringshort OUT(SC) • V isthediodevoltagedrop d • R istheswitchON-resistance DS(on) • t isthecontrollableON-time ON • f isthefrequencydivideequals(1,2,4,or8) (9) DIV 7.3.11 SynchronizationtoRT/CLKPin The RT/CLK pin receives a frequency-synchronization signal from an external system clock. To implement this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in Figure26.ThesquarewaveappliedtotheRT/CLKpinmustswitchlowerthan0.5Vbuthigherthan1.7V,andit must have a pulse-width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of the SW synchronizes to the falling edge of RT/CLK pin signal. The external synchronization circuit must be designed so that the default-frequency set-resistor is connected from the RT/CLK pin to ground when the synchronization signal is off. When using a low-impedance signal source, the frequency set resistor is connected in parallel with an AC-coupling capacitor to a termination resistor (for example 50 Ω) as shown in Figure 26. The two resistors in series provide the default-frequency setting resistance when the signal source is turned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. TI recommendstoAC-couplethesynchronizationsignalthrougha10-pFceramiccapacitortoRT/CLKpin. The first time that the RT/CLK is pulled above the PLL threshold, the TPS54340-Q1 device switches from the RT-resistor free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is removed and the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition from the PLL mode to the resistor-programmed mode, the switching frequency falls to 150 kHz and then increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is reappliedtotheRT/CLKresistor. The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device implements a digital-frequency foldback to enable synchronizing to an external clock during normal start-up and fault conditions. Figure 27, Figure 28 and Figure 29show the device synchronized to an external system clock in continuous-conductionmode(CCM),discontinuous-conductionmode(DCM),andpulse-skipmode(Eco-Mode). SPACER TPS54340-Q1 TPS54340-Q1 RT/CLK RT/CLK PLL PLL RT Hi-Z Clock Clock RT Source Source Figure26. SynchronizingtoaSystemClock Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) SW SW EXT EXT IL IL Figure27.PlotofSynchronizinginCCM Figure28.PlotofSynchronizinginDCM SW EXT IL Figure29.PlotofSynchronizinginEco-Mode™ 7.3.12 OvervoltageProtection The TPS54340-Q1 device incorporates an output-overvoltage-protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low-output capacitance. For example, when the power-supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. In some applications, the power-supply output voltage increasesfasterthantheresponseoftheerroramplifieroutputresultinginanoutputovershoot. 18 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 Feature Description (continued) The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB-pin voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB-pin voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize output overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the internalvoltagereference,thehigh-sideMOSFETresumesnormaloperation. 7.3.13 ThermalShutdown The TPS54340-Q1 device provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature falls to less than 164°C, the device reinitiates the power-up sequencecontrolledbytheinternalsoft-startcircuitry. 7.3.14 Small-SignalModelforLoopResponse Figure 30 shows an equivalent model for the TPS54340-Q1 control loop, which is simulated to check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm EA of 3350 μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor R o and capacitor C model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage o source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a provides the small-signal response of the frequency compensation. Plotting a/b provides the small- signal response of the overall loop. The dynamic loop response is evaluated by replacing R with a current L sourcewiththeappropriateload-stepamplitudeandsteprateinatime-domainanalysis.Thisequivalentmodelis onlyvalidforcontinuousconductionmode(CCM)operation. SW V Power Stage O gm 12A/V ps a b R1 RESR COMP RL c FB C 0.8 V OUT CO RO R3 gm ea C2 350mA/V R2 C1 Figure30. Small-SignalModelforLoopResponse 7.3.15 SimpleSmall-SignalModelforPeak-Current-ModeControl Figure 31 describes a simple small-signal model that is used to design the frequency compensation. The TPS54340-Q1 power stage is approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control-to-output transfer function is shown in Equation 10 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP-pin voltage (node c in Figure 30) is the power-stage transconductance, gm . The gm for the TPS54340-Q1 device is 12 A/V. The low-frequency gain of the power stage is the PS PS productofthetransconductanceandtheloadresistanceasshowninEquation11. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) Astheloadcurrentincreasesanddecreases,thelow-frequencygaindecreasesandincreases,respectively.This variationwiththeloadisproblematicatfirstglance,butfortunatelythedominantpolemoveswiththeloadcurrent (see Equation 12). The combined effect is highlighted by the dashed line in the right half of Figure 31. As the load current decreases, the gain increases and the pole frequency lowers, which keeps the 0-dB crossover frequency the same as load conditions vary. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Because the phase margin is increased by the ESR zero of the output capacitor (see Equation 13), the use of high-ESR aluminum-electrolytic capacitors reducesthenumberfrequencycompensationcomponentsrequiredtostabilizetheoverallloop. V O VC Adc R ESR fp R L gm ps C OUT fz Figure31. SimpleSmall-SignalModelandFrequencyResponseforPeak-Current-ModeControl æ s ö ç1+ ÷ VOUT = Adc´è 2p´fZ ø V æ s ö C ç1+ ÷ è 2p´fP ø (10) Adc=gm ´ R ps L (11) 1 f = P C ´R ´2p OUT L (12) 1 f = Z C ´R ´2p OUT ESR (13) 7.3.16 Small-SignalModelforFrequencyCompensation The TPS54340-Q1 device uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency-compensation circuits. The compensation circuits, Type 2A, Type 2B, and Type 1, are shown in Figure 32. Type 2 circuits are typically implemented in high-bandwidth power-supply designs using low -ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum- electrolytic or tantalum capacitors. Equation 14 and Equation 15 relate the frequency response of the amplifier to thesmall-signalmodelinFigure32.Theopen-loopgainandbandwidtharemodeledusingtheR andC shown O O in Figure 32. See Application and Implementation for a design example using a Type-2A network with a low-ESR outputcapacitor. Equation 14 through Equation 23 are provided as a reference. An alternative is to use WEBENCH software tools tocreateadesignbasedonthepowersupplyrequirements. 20 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 Feature Description (continued) V O R1 FB gm Type 2A Type 2B Type 1 ea COMP Vref R3 C2 R3 R2 RO CO C2 C1 C1 Figure32. TypesofFrequencyCompensation Aol P1 A0 Z1 P2 A1 BW Figure33. FrequencyResponseoftheType-2AandType-2BFrequencyCompensation Aol(V/V) Ro= gm ea (14) gm C = ea O 2p ´ BW (Hz) (15) æ s ö ç1+ ÷ è 2p´fZ1ø EA = A0´ æ s ö æ s ö ç1+ ÷´ç1+ ÷ è 2p´fP1ø è 2p´fP2 ø (16) R2 A0=gm ´ Ro ´ ea R1+R2 (17) R2 A1=gm ´ Ro||R3 ´ ea R1+R2 (18) 1 P1= 2p´Ro´C1 (19) Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) 1 Z1= 2p´R3´C1 (20) 1 P2= type2a 2p ´ R3||R ´ (C2+C ) O O (21) 1 P2= type2b 2p ´ R3||R ´ C O O (22) 1 P2 = type 1 2p ´ R ´ (C2 + C ) O O (23) 7.4 Device Functional Modes The TPS54340-Q1 device is designed to operate with input voltages above 4.5 V. When the VIN voltage is abovethe4.3V,typicalrisingUVLOthresholdandtheENvoltageisabovethe1.2Vtypicalthresholdthedevice is active. If the VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the EN voltage falls below the 1.2-V threshold, the device stops switching and enters a shutdown mode with low supplycurrentof2µAtypical. The TPS54340-Q1 device will operate in CCM when the output current is enough to keep the inductor current above 0 A at the end of each switching period. As a nonsynchronous converter, it will enter DCM at low-output currents when the inductor current falls to 0 A before the end of a switching period. At very low-output current, the COMP voltage will drop to the pulse-skipping threshold, and the device operates in a pulse-skipping Eco- mode. In this mode, the high-side MOSFET does not switch every switching period. This operating mode reduces power loss while regulating the output voltage. For more information on Eco-mode see the Pulse Skip Eco-mode™section. 22 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54340-Q1 device is a 42-V, 3.5-A, step-down regulator with an integrated high-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 3.5 A. Example applications are: 12 V and 24 V industrial, automotive, and communications power systems. Use the following design procedure to select component values for the TPS54340-Q1 device. This procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an interactive design procedure, and accesses a comprehensive database of components when generating a design. The Typical Applications sectionpresentsasimplifieddiscussionofthedesignprocess. 8.2 Typical Applications 8.2.1 BuckConverterWith6-Vto42-VInputand3.3-Vat3.5-AOutput L1 5.6uH C4 0.1uF 3.3V, 3.5AVOUT U1 D1 C6 TPS54340-Q1 (DDA) 100uF B560C 1 8 R5 BOOT SW 6V to 42V 31.6k VIN 2 VIN GND 7 3 6 C1 C2 R1 EN D COMP FB GND FB 4 P 5 2.2uF 2.2uF 365k RT/CLK WR FB P R4 9 11.5k C8 R6 GND R2 R3 47pF 10.2k 86.6k 162k GND C5 5600pF GND GND Figure34. 3.3-VOutputTPS54340-Q1DesignExample 8.2.1.1 DesignRequirements To start the design process, a few parameters must be known. These requirements are typically determined at thesystemlevel.Table1showsthedesignparametersforthisexample. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Applications (continued) Table1.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Outputvoltage 3.3V Transientresponse0.875-Ato2.625A-loadstep ΔV =4% OUT Maximumoutputcurrent 3.5A Inputvoltage 12Vnominal,6Vto42V Outputvoltageripple 0.5%ofV OUT StartInputvoltage(risingVIN) 5.75V StopInputVoltage(fallingVIN) 4.5V 8.2.1.2 DetailedDesignProcedure 8.2.1.2.1 SelectingtheSwitchingFrequency The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible, because this produces the smallest solution size. High switching frequency allows for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch,theinputvoltage,theoutputvoltage,andthefrequency-foldbackprotection. Equation 8 and Equation 9 calculate the upper limit of the switching frequency for the regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skippingorthelackofovercurrentprotectionduringashortcircuit. Thetypicalminimumontime,t ,is135nsfortheTPS54340-Q1.Forthisexample,theoutputvoltageis3.3V onmin and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid pulse skipping from Equation 8. To ensure overcurrent runaway is not a concern during short circuits use Equation 9 to determine the maximum switching frequency for frequency-foldback protection. With a maximum input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 92 mΩ, a current limit value of 4.7 A, and short circuit output voltage of 0.1 V, the maximum switching frequency is 1260kHz. For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 6 or the curve in Figure 6. The switching frequency is set by resistor R shown in Figure 34. For 600 kHz operation, the closest 3 standardvalueresistoris162kΩ. 1 æ3.5 A x 21mW + 3.3 V + 0.7 Vö f = ´ ç ÷ = 712 kHz SW(maxskip) 135ns è 42 V - 3.5 A x 92 mW + 0.7 V ø (24) 8 æ4.7 A x 21mW + 0.1V + 0.7 Vö fSW(shift) = ´ ç ÷ = 1260 kHz 135 ns è 42 V - 4.7 A x 92 mW + 0.7 V ø (25) 92417 RT(kW)= =163kW 600(kHz)0.991 (26) 8.2.1.2.2 OutputInductorSelection(L ) O Tocalculatetheminimumvalueoftheoutputinductor,useEquation27. K is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The IND inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impactstheselectionoftheoutputcapacitorbecausetheoutputcapacitormusthavearipple-currentratingequal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,however,thefollowingguidelinescanbeused. 24 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 For designs using low-ESR output capacitors such as ceramics, a value as high as K = 0.3 is desirable. When IND using higher ESR output capacitors, K = 0.2 yields better results. Because the inductor ripple current is part of IND thecurrent-modePWM-controlsystem,theinductorripplecurrentmustalwaysbegreaterthan150mAforstable PWM operation. In a wide input voltage regulator, the best choice is a relatively large inductor ripple current whichprovidessufficientripplecurrentwiththeinputvoltageattheminimum. For this design example, K = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest IND standard value is 5.6 μH. Not exceeding the RMS current and saturation current ratings of the inductor is important. The RMS and peak inductor current are determined by Equation 29 and Equation 30. For this design, the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE 7443552560,whichhasasaturationcurrentratingof7.5AandanRMScurrentratingof6.7A. As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the regulatorbutallowforalowerinductancevalue. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults, or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current increases up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current ratingequaltoorgreaterthantheswitchcurrentlimitoftheTPS54340-Q1,whichisnominally5.5A. LO(min)= VINIO(mUaTx´)-KIVNODUT ´VIN(mVaOx)U´T fSW = 432.5VA-x30.3.3V ´ 42 V 3´.36V00 kHz = 4.8 mH (27) spacer VOUT´(VIN(max)-VOUT) 3.3 V x (42 V - 3.3 V) I = = = 0.905 A RIPPLE VIN(max)´LO´ fSW 42 V x 5.6 mHx 600 kHz (28) spacer ( )2 IL(rms)= (IOUT)2+112´æçççVOUVTIN´(maVxIN)´(mLaOx)´-fVSOWUT ö÷÷÷ = (3.5 A)2+ 112 ´ æççè432.3VV´´5.6(4m2HV´-630.03kVH)zö÷÷ø2 =3.5 A è ø (29) spacer I 0.905 A I ( )=I + RIPPLE = 3.5 A + = 3.95 A L peak OUT 2 2 (30) 8.2.1.2.3 OutputCapacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in loadcurrent.Theoutputcapacitancemustbeselectedbasedonthemoststringentofthesethreecriteria. The desired response to a large change in the load current is the first criteria. The output capacitor must supply the increased load current until the regulator responds to the load step. The regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator generally requires two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for two clock cycles to maintain the output voltage within the specified range. Equation31showstheminimumoutputcapacitancenecessary,where ΔI isthechangeinoutputcurrent, ƒ OUT SW is the regulators switching frequency and ΔV is the allowable change in the output voltage. For this example, OUT the transient load response is specified as a 4% change in V for a load step from 0.875 A to 2.625 A. OUT Therefore, ΔI is 2.625 A – 0.875 A = 1.75 A and ΔV = 0.04 × 3.3 = 0.13 V. Using these numbers gives a OUT OUT minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum- electrolyticandtantalumcapacitorshavehigherESRthatmustbeincludedinloadstepcalculations. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high- to-low load current. The catch diode of the regulator does not sink current so energy stored in the inductor produces an output-voltage overshoot when the load current rapidly decreases. A typical load-step response is shown in Figure 35. The excess energy absorbed in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 32 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where L O is the value of the inductor, I is the output current under heavy load, I is the output under light load, V is the OH OL f peak output voltage, and V is the initial voltage. For this example, the worst-case load step is from 2.625 A to I 0.875 A. The output voltage increases during this load transition, and the stated maximum in our specification is 4% of the output voltage, which makes V = 1.04 × 3.3 = 3.432. V is the initial capacitor voltage, which is the f I nominaloutputvoltageof3.3V.UsingthesenumbersinEquation32yieldsaminimumcapacitanceof38.6 μF. Equation 33 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ƒ is the switching frequency, V is the maximum allowable output voltage ripple, and I is the SW ORIPPLE RIPPLE inductorripplecurrent.Equation33yields11.4 μF. Equation 34 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.Equation34indicatestheESRmustbelessthan18mΩ. The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within regulationtoleranceduringaloadtransient. Capacitancederatingsforaging,temperature,andDCbiasincreasesthisminimumvalue.Forthisexample,100- μF ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 70 µF, which is well above the minimumrequiredcapacitanceof44.9µF. Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 35 calculates the RMS ripple current that the output capacitor must support. For this example, Equation35yields261mA. 2´DI 2 ´ 1.75 A C > OUT = = 44.9 mF OUT fSW ´DVOUT 600 kHz x 0.13 V (31) ( ) ( ) (I )2- (I )2 2.625 A2-0.875 A2 OH OL COUT >LO x ( ) = 5.6 mHx ( ) = 38.6 mF (V )2- (V)2 3.432 V2 - 3.3 V2 f I (32) 1 1 1 1 C > ´ = x = 11.4 mF OUT 8´ fSW æVORIPPLE ö 8 x 600 kHz æ16.5 mVö ç ÷ ç ÷ è IRIPPLE ø è 0.905 A ø (33) V 16.5 mV R < ORIPPLE = = 18 mW ESR I 0.905 A RIPPLE (34) ( ) VOUT´ VIN(max)-VOUT 3.3 V ´ (42 V - 3.3 V) I = = =261mA COUT(rms) 12´VIN(max)´LO´ fSW 12 ´ 42 V ´ 5.6 mH ´ 600 kHz (35) 8.2.1.2.4 CatchDiode The TPS54340-Q1 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than V . The peak current rating of the diode must be IN(max) greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due totheirlowforwardvoltage.Thelowertheforwardvoltageofthediode,thehighertheefficiencyoftheregulator. Typically,diodeswithhighervoltageandcurrentratingshavehigherforwardvoltages.Adiodewithaminimumof 42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340-Q1 device. For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 V at 5A. 26 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 36 is usedtocalculatethetotalpowerdissipation,includingconductionlossesandAClossesofthediode. The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 36, the total loss in the diode is 2.42W. If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diodewhichhasalowleakagecurrentandslightlyhigherforwardvoltagedrop. ( ) P = VIN(max)-VOUT ´ IOUT´Vfd+Cj´ fSW ´(VIN+Vfd)2 = D V ( ) 2 INmax ( ) 42 V - 3.3 V ´ 3.5 A x 0.7 V 300 pF x 600 kHz x (42 V + 0.7 V)2 + =2.42 W 42 V 2 (36) 8.2.1.2.5 InputCapacitor The TPS54340-Q1 device requires a high-quality ceramic-type X5R or X7R input-decoupling capacitor with at least 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance due to DC-bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input current ripple of the TPS54340-Q1 device. Equation 37 calculates the input ripple current. The value of a ceramic capacitor varies significantly with temperature and the DC bias applied to the capacitor. Selecting a dielectric material that is more stable overtemperature minimizes capacitance variations due to temperature. X5R and X7R ceramic dielectrics are generally selected for switching regulator capacitors, because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC bias acrossacapacitorincreases. For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support the maximum input voltage. Common-standard ceramic-capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used. Table 2 shows several choicesofhighvoltagecapacitors. The input capacitance value determines the input ripple voltage of the regulator. Equation 38 calculates the input voltage ripple. Using the design example values, I = 3.5 A, C = 4.4 μF, ƒ = 600 kHz, yields an input OUT IN SW voltagerippleof331mVandaRMSinputripplecurrentof1.74A. ( ) V VIN(min)-VOUT 3.3 V (6 V - 3.3 V) ICI(rms)=IOUT x VINO(mUTin) x VIN(min) = 3.5 A 6 V ´ 6 V =1.74 A (37) I ´0.25 3.5 A ´ 0.25 DV = OUT = = 331mV IN CIN´ fSW 4.4 mF ´ 600 kHz (38) Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com Table2.CapacitorTypes VENDOR VALUE(μF) EIASIZE VOLTAGE(V) DIALECTRIC COMMENTS 1to2.2 100 1210 GRM32series 1to4.7 50 Murata 1 100 1206 GRM31series 1to2.2 50 1to1.8 50 2220 1to1.2 100 Vishay VJX7Rseries 1to3.9 50 2225 1to1.8 100 X7R 1to2.2 100 1812 CseriesC4532 1.5to6.8 50 TDK 1to2.2 100 1210 CseriesC3225 1to3.3 50 1to4.7 50 1210 1 100 AVX X7Rdielectricseries 1to4.7 50 1812 1to2.2 100 8.2.1.2.6 Bootstrap-CapacitorSelection A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. TI recommends a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltagerating. 8.2.1.2.7 UndervoltageLockoutSetPoint The Undervoltage Lockout (UVLO) is adjusted using an external voltage divider on the EN pin of the TPS54340- Q1 device. The UVLO has two thresholds, one for power up when the input voltage is rising, and one for power- down or brown-outs when the input voltage is falling. For the example design, the supply turns on and starts switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it shouldcontinuetodosountiltheinputvoltagefallsbelow4.5V(UVLOstop). ProgrammableUVLO-thresholdvoltagesaresetusingtheresistordividerofR andR betweenVINand UVLO1 UVLO2 ground connected to the EN pin. Equation 3 and Equation 4 calculate the necessary resistance values. For the example application, a 365 kΩ between VIN and EN (R ) and a 86.6 kΩ between EN and ground (R ) UVLO1 UVLO2 arerequiredtoproducethe8-Vand6.25-Vstartandstopvoltages. V - V 5.75 V - 4.5 V R = START STOP = =368 kW UVLO1 I 3.4 mA HYS (39) V 1.2 V R = ENA = = 87.8 kW UVLO2 V - V 5.75 V - 1.2 V START ENA + I +1.2 mA R 1 365 kW UVLO1 (40) 8.2.1.2.8 OutputVoltageandFeedbackResistorsSelection The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6. Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Because of the input current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher resistor values decreases quiescent current and improves efficiency at low-output currents but canalsointroducenoiseimmunityproblems. V - 0.8 V æ3.3 V - 0.8 Vö RHS = RLS x OUT = 10.2 kW x ç ÷ = 31.9 kW 0.8 V è 0.8 V ø (41) 28 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 8.2.1.2.9 Compensation There are several methods to design compensation for DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero andtheESRzeroisatleast10-timesgreaterthemodulatorpole. To get started, the modulator pole, ƒ , and the ESR zero, ƒ , must be calculated using Equation 42 and p(mod) z1 Equation 43. For C , use a derated value of 70 μF. Use equations Equation 44 and Equation 45 to estimate a OUT starting point for the crossover frequency, ƒ . For the example design, ƒ is 2411 Hz and ƒ is 455 kHz. co p(mod) z(mod) Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of modulator pole and the switching frequency. Equation 44 yields 33.1 kHz and Equation 45 gives 26.9 kHz. Use the lower value of Equation 44 or Equation 45 for an initial crossover frequency. For this example, the target ƒ co is26.9kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensatingzero.Acapacitorinparalleltothesetwocomponentsformsthecompensatingpole. IOUT(max) 3.5 A fP(mod)= 2´p´V ´C = 2 ´ p ´ 3.3 V ´ 70 mF = 2411Hz OUT OUT (42) 1 1 fZ(mod)= 2´p´R ´C = 2 ´ p ´ 5 mW ´ 70 mF = 455 kHz ESR OUT (43) f = f f = 2411Hz x 455 kHz = 33.1kHz co p(mod)x z(mod) (44) f 600 kHz f = f SW = 2411Hz x = 26.9 kHz co p(mod)x 2 2 (45) To determine the compensation resistor, R4, use Equation 46. Assume the power-stage transconductance, gmps, is 12 A/V. The output voltage, V , reference voltage, V , and amplifier transconductance, gmea, are 5 O REF V, 0.8 V, and 350 μA/V, respectively. R4 is calculated as 11.6 kΩ, and a standard value of 11.5 kΩ is selected. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 5740 pF for compensatingcapacitorC5.5600pFisusedforthisdesign. æ2´p´ f ´C ö æ V ö æ2´p´26.9 kHz ´ 70 mF ö æ 3.3 V ö R4=ç co OUT ÷ x ç OUT ÷ = ç ÷xç ÷=11.6 kW è gmps ø èV x gmeaø è 12A/V ø è0.8 V x 350 mA/Vø REF (46) 1 1 C5= = =5740 pF 2´p´R4 x f 2´p´11.5 kW x 2411Hz p(mod) (47) A compensation pole is implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 48 and Equation 49 for C8 to set the compensation pole.TheselectedvalueofC8is47pFforthisdesignexample. C x R 70 mF x 5 mW C8= OUT ESR = =30.4 pF R4 11.5 kW (48) 1 1 C8= = =46.1pF R4 x fsw x p 11.5 kW x 600 kHz x p (49) 8.2.1.2.10 PowerDissipationEstimate The following formulas estimate the power dissipation of the TPS54340-Q1 device under continuous-conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous- conductionmode(DCM). The power dissipation of the IC includes conduction loss (P ), switching loss (P ), gate drive loss (P ) and COND SW GD supply current (P ). For example calculations of the design example with the 12-V typical input voltage, see Q Equation50throughEquation53. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com PCOND =(IOUT)2´RDS(on)´æçèVVOIUNT ö÷ø=3.5 A2 ´ 92 mW ´ 31.23VV = 0.31W (50) spacer PSW = VIN´ fSW ´IOUT´trise =12 V´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W (51) spacer PGD = VIN´QG´ fSW =12 V ´ 3nC´ 600 kHz = 0.022 W (52) spacer P = V ´ I = 12 V´ 146 mA = 0.0018 W Q IN Q where • I istheoutputcurrent(A) OUT • R istheon-resistanceofthehigh-sideMOSFET(Ω) DS(on) • V istheoutputvoltage(V) OUT • V istheinputvoltage(V) IN • ƒ istheswitchingfrequency(Hz) SW • t istheSWpinvoltagerisetimeandcanbeestimatedbytrise=V ×0.16ns/V+3ns rise IN • Q isthetotalgatechargeoftheinternalMOSFET G • I istheoperatingnonswitchingsupplycurrent (53) Q Therefore, P =P +P +P +P =0.31W + 0.123 W + 0.022 W + 0.0018 W =0.457 W TOT COND SW GD Q (54) ForgivenT , A T =T +R ´P J A TH TOT (55) ForgivenT =150°C J(max) T =T -R ´P A(max) J(max) TH TOT where • P isthetotaldevicepowerdissipation(W) tot • T istheambienttemperature(°C) A • T isthejunctiontemperature(°C) J • R isthethermalresistanceofthepackage(°C/W) TH • T ismaximumjunctiontemperature(°C) J(max) • T ismaximumambienttemperature(°C) (56) A(max) Additional power losses occur in the regulator circuit due to the inductor AC and DC losses, the catch diode, and PCBtraceresistanceimpactingtheoverallefficiencyoftheregulator. 8.2.1.2.11 DiscontinuousConductionModeandEco-mode™Boundary With an input voltage of 12 V, the power supply enters discontinuous-conduction mode when the output current is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The inputcurrentdrawis237μAwithnoload. 30 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 8.2.1.3 ApplicationCurves A/div V/div VIN 1 C4: IOUT 10 C4 C3: VOUTac coupled V/div C3 V/div VOUT-3.3V offset m m 00 20 1 Time = 100ms/div Time = 4 ms/div Figure35.LoadTransient Figure36.LineTransient(8Vto40V) v v di di C1: VIN V/ C1: VIN V/ 5 5 C1 v di C3: EN V/ C3 C1 2 v di V/ C3: EN div C2: VOUT 2 C3 V/ 2 C2 div C2 C2: VOUT V/ 2 Time = 2 ms/div Time = 2 ms/div Figure37.Start-upWithVIN Figure38.Start-upWithEN C1: SW C1: SW 10 V/div C1 10 V/div C1 v C4: IL v C4: IL di di A/ A/ 1 m C4 0 0 5 C2: VOUT ac coupled 20 mV/div CC24 10 mV/div C2 C2: VOUT ac coupled Time = 2ms/div Time = 2ms/div Figure39.OutputRippleCCM Figure40.OutputRippleDCM Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com 10 V/div C1 C1: SW 10 V/div C1 C1: SW v C4: IL A/di C4: IL div m C4 A/ 00 1 2 C2: VOUT ac coupled C3: VIN ac coupled v V/di C2 div C2 m V/ C4 0 m 2 0 0 2 Time = 2 ms/div Time = 2ms/div Figure41.OutputRipplePSM Figure42.InputRippleCCM v C1: SW C1: SW di v V/ di 0 V/ 1 C1 2 A/div C4: IL A/div m C4 m C4 500 C3: VIN ac coupled 200 C4: IL mV/div C3 mV/div C3 C3: VOUT ac coupled 50 20 VVIONU=T 5=. 55 VV NENo LFoloaadting Time = 2ms/div Time = 20ms/div Figure43.InputRippleDCM Figure44.LowDropoutOperation IOUT= 100 mA IOUT= 1A EN Floating EN Floating v v di di V/ V/ 2 VIN 2 VIN VOUT VOUT Time = 40ms/div Time = 40ms/div Figure45.LowDropoutOperation Figure46.LowDropoutOperation 32 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 100 100 90 90 80 80 70 70 % % y - 60 y - 60 nc 50 nc 50 e e ci 40 ci 40 Effi Effi 30 30 20 20 6Vin 36Vin 6Vin 36Vin 10 12Vin 10 12Vin 24Vin 42Vin 24Vin 42Vin 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.001 0.01 0.1 1 I - Output Current -A I - Output Current -A O O Figure47.EfficiencyvsLoadCurrent Figure48.Light-LoadEfficiency 100 100 90 90 80 80 70 70 % % y - 60 y - 60 nc 50 nc 50 e e ci 40 ci 40 Effi Effi 30 30 20 20 6Vin 36Vin 6Vin 36Vin 10 12Vin 42Vin 10 12Vin 42Vin 24Vin 24Vin 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.001 0.01 0.1 1 I - Output Current -A I - Output Current -A O O Figure49.EfficiencyvsLoadCurrent Figure50.Light-LoadEfficiency 60 180 1 Phase 0.8 40 120 n - % 0.6 o 0.4 B 20 Gain 60 gree viati 0.2 Gain - d -200 -600 hase - de oltage De -0.20 P V 0.4 ut p -0.6 -40 -120 ut O -0.8 -60 -180 -1 10 100 1000 10000 100000 1000000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Frequency - Hz IO- Output Current -A Figure51.OverallLoop-FrequencyResponse Figure52.RegulationvsLoadCurrent Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com 0.3 % 0.2 n - o ati 0.1 vi e e D 0 g a olt -0.1 V ut p ut 0.2 O -0.3 5 10 15 20 25 30 35 40 45 V - Input Voltage - V IN Figure53.RegulationvsInputVoltage 8.2.2 InvertingPowerSupply The TPS54340-Q1 device can be used to convert a positive input voltage to a negative output voltage. Example applicationsareamplifiersrequiringanegativepowersupply.Foramoredetailedexample,seeSLVA317. VIN + Cin Cboot Lo VIN BOOT SW GND Cd R1 GND + TPS54340-Q1 R2 Co FB VOUT EN COMP RT/CLK Rcomp Czero Cpole RT Figure54. TPS54340-Q1InvertingPowerSupplyfromApplicationNote(SLVA317) 34 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 8.2.3 Split-RailPowerSupply The TPS54340-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and negativevoltagepowersupply.Foramoredetailedexample,seeSLVA369. VOPOS + VIN Copos + Cin Cboot GND VIN BOOT SW Lo Cd R1 + GND Coneg TPS54340-Q1 R2 VONEG FB EN COMP RT/CLK Rcomp Czero Cpole RT Figure55. TPS54340-Q1Split-RailPowerSupplyBasedonApplicationNote(SLVA369) 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range from 4.5 V to 42V. This input supply must remain within this range. If the input supply is located more than a few inches from the TPS54340-Q1 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitorwithavalueof100µFisatypicalchoice. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise ordegradeperformance.SeeFigure56foraPCBlayoutexample. • To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitorwithX5RorX7Rdielectric. • Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching node, the catch diode and output inductor should be located closetotheSWpin,andtheareaofthePCBconductorminimizedtopreventexcessivecapacitivecoupling. • The GND pin should be tied directly to the power pad under the IC and the PowerPAD™. The PowerPAD shouldbeconnectedtointernalPCBgroundplanesusingmultipleviasdirectlyundertheIC. • Foroperationatfullratedload,thetopsidegroundareamustprovideadequateheatdissipatingarea. • The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routedwithminimallengthsoftrace. • Theadditionalexternalcomponentscanbeplacedapproximatelyasshown. • It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout has beenshowntoproducegoodresults,andismeantasaguideline. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 www.ti.com 10.2 Layout Example Vout Output Capacitor Output Topside Inductor Ground Route Boot Capacitor Catch Area Trace on another layer to Diode provide wide path for topside ground Input Bypass Capacitor BOOT SW Vin VIN GND EN COMP UVLO Adjust RT/CLK FB Compensation Resistor Resistors Network Divider Frequency Thermal VIA Set Resistor Signal VIA Figure56. PCBLayoutExample 10.3 Estimated Circuit Area Boxing in the components in the design of Figure 34, the estimated PCB area is 1.025 in2 (661 mm2). This area does not include test points or connectors. If the area must be reduced, then this can be done by using a two sidedassembly,andreplacingthe0603sizedpassiveswithasmaller-sizedequivalent. 36 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54340-Q1

TPS54340-Q1 www.ti.com SLVSBZ1A–SEPTEMBER2013–REVISEDNOVEMBER2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • CreatingGSMPowerSupplyfromTPS54260,SLVA412. • CreatingaUniversalCarChargerforUSBDevicesFromtheTPS54240andTPS2511,SLVA464. • CreateanInvertingPowerSupplyfromaStep-DownRegulator,SLVA317. • CreateaSplit-RailPowerSupplywithaWideInputVoltageBuckRegulator,SLVA369. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks Eco-mode,PowerPAD,E2EaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS54340-Q1

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PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54340QDDAQ1 NRND SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54340Q & no Sb/Br) TPS54340QDDARQ1 NRND SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54340Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2017 OTHER QUALIFIED VERSIONS OF TPS54340-Q1 : •Catalog: TPS54340 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54340QDDARQ1 SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54340QDDARQ1 SOPowerPAD DDA 8 2500 366.0 364.0 50.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4202561/G

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