TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 2A Dual Channel Synchronous Step-Down Switcher with Integrated FET CheckforSamples:TPS54294 FEATURES APPLICATIONS 1 • D-CAP2™ControlMode • Point-of-LoadRegulationinLowPower 2 – FastTransientResponse SystemsforWideRangeofApplications – NoExternalPartsRequiredForLoop – DigitalTVPowerSupply Compensation – NetworkingHomeTerminal – CompatiblewithCeramicOutput – DigitalSetTopBox(STB) Capacitors – DVDPlayer/Recorder • WideInputVoltageRange:4.5Vto18V – GamingConsolesandOther • OutputVoltageRange:0.76Vto7.0V DESCRIPTION • HighlyEfficientIntegratedFETsOptimizedfor LowDutyCycleApplications The TPS54294 is a dual, adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54294 – 150mΩ (HighSide)and100mΩ (LowSide) enables system designers to complete the suite of • HighInitialReferenceAccuracy various end equipment’s power bus regulators with a • Low-Sider Loss-LessCurrentSensing cost effective, low component count, and low standby DS(on) current solution. The main control loops of the • FixedSoftStart:1.0ms TPS54294 use the D-CAP2™ mode control which • Non-SinkingPre-BiasedSoftStart provides a very fast transient response with no • Powergood externalcompensationcomponents.Theadaptiveon- • 700kHzSwitchingFrequency time control supports seamless transition between PWM mode at higher load conditions and Eco- • Cycle-by-CycleOver-CurrentLimitControl mode™ operation at light loads. Eco-mode™ allows • OCL/OVP/UVP/UVLO/TSDProtections the TPS54294 to maintain high efficiency during • AdaptiveGateDriverswithIntegratedBoost lighter load conditions. The TPS54294 is able to PMOSSwitch adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and • OCPConstantDueToThermallyCompensated ultra-low ESR, ceramic capacitors. The device r with4000ppm/℃℃ DS(on) provides convenient and efficient operation with input • 16-PinHTSSOP,16-PinVQFN voltagesfrom4.5Vto18V. • Auto-Skip Eco-mode™　　forHighEfficiencyat The TPS54294 is available in a 4.4mm × 5.0mm 16- LightLoad pin TSSOP (PWP) package, and 4mm x 4mm 16-pin VQFN (RSA) package specified for an ambient temperaturerangefrom–40°Cto85°C. Input Voltage V O 2 = 1.5 V (50 mV/div) 1 VIN1 VIN216 C11 2VBST1 VBST215 C12 VO1 L11 C31 C32 L12 VO2 3 SW1 SW214 C21 C22 4PGND1 TPS54294 PGND213 PGND HTSSOP16 PGND 5 EN1 EN212 Iout (1A/div) 6 PG1 PG211 R11 (PowerPAD) R12 R21 7 VFB1 VFB210 C4 R22 8 GND VREG59 t - Time - 100ms/div PGND SGND SGND 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. D-CAP2,Eco-mode,Eco-Mode,SWIFTaretrademarksofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2011–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION(1) T PACKAGE ORDERINGPARTNUMBER PINS OUTPUTSUPPLY A TPS54294PWPR Tape-and-Reel PWP 16 TPS54294PWP Tube –40℃to85℃ TPS54294RSAR RSA 16 Tape-and-Reel TPS54294RSAT (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) (2) VALUE UNIT VIN1,VIN2,EN1,EN2 –0.3to20 VBST1,VBST2 –0.3to26 VBST1,VBST2(10nstransient) –0.3to28 Inputvoltagerange VBST1–SW1,VBST2–SW2 –0.3to6.5 V VFB1,VFB2 –0.3to6.5 SW1,SW2 –2to20 SW1,SW2(10nstransient) –3to22 VREG5,PG1,PG2 –0.3to6.5 Outputvoltagerange V PGND1,PGND2 –0.3to0.3 HumanBodyModel(HBM) 2 kV Electrostaticdischarge ChargedDeviceModel(CDM) 500 V T Operatingambienttemperaturerange –40to85 °C A T Storagetemperaturerange –55to150 °C STG T Junctiontemperaturerange –40to150 °C J (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"arenotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoICGNDterminal. THERMAL INFORMATION TPS54294 THERMALMETRIC(1) UNITS PWP(16)PINS RSA(16)PINS θ Junction-to-ambientthermalresistance 47.5 34.9 JA θ Junction-to-case(top)thermalresistance 27.1 40.0 JCtop θ Junction-to-boardthermalresistance 20.8 11.8 JB °C/W ψ Junction-to-topcharacterizationparameter 1.0 0.7 JT ψ Junction-to-boardcharacterizationparameter 20.6 11.8 JB θ Junction-to-case(bottom)thermalresistance 2.7 3.3 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 2 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUES UNIT MIN MAX Supplyinputvoltagerange VIN1,VIN2 4.5 18 V VBST1,VBST2 –0.1 24 VBST1,VBST2(10nstransient) –0.1 27 VBST1–SW1,VBST2–SW2 –0.1 5.7 Inputvoltagerange VFB1,VFB2 –0.1 5.7 V EN1,EN2 –0.1 18 SW1,SW2 –1.0 18 SW1,SW2(10nstransient) –3 21 VREG5,PG1,PG2 –0.1 5.7 Outputvoltagerange PGND1,PGND2 –0.1 0.1 V VO1,VO2 0.76 7.0 T Operatingfree-airtemperature –40 85 °C A T OperatingJunctionTemperature –40 150 °C J ELECTRICAL CHARACTERISTICS(1) overrecommendedfree-airtemperaturerange,VIN=12V(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT EN1=EN2=5V, I VINsupplycurrent 1300 2500 µA IN VFB1=VFB2=0.8V I VINshutdowncurrent EN1=EN2=0V 80 200 µA VINSDN FEEDBACKVOLTAGE V VFBxthresholdvoltage CH1=3.3V,CH2=1.5V 758 765 773 mV VFBTHLx TC Temperaturecoefficient Onthebasisof25°C(2) –115 115 ppm/℃ VFBx I VFBInputCurrent VFBx=0.8V –0.35 0.2 0.35 µA VFBx VREG5OUTPUT 6V<VIN1<18V, V VREG5outputvoltage 5.5 V VREG5 I =5mA VREG I Outputcurrent VIN1=6V,VREG5=4V(2) 75 mA VREG5 MOSFETs r Highsideswitchresistance VBSTx-SWx=5.5V (2) 150 mΩ DS(on)H r Lowsideswitchresistance (2) 100 mΩ DS(on)L ON-TIMETIMERCONTROL T SW1OnTime SW1=12V,VO1=1.2V 165 ns ON1 T SW2OnTime SW2=12V,VO2=1.2V 165 ns ON2 T SW1Minofftime VFB1=0.7V(2) 220 ns OFF1 T SW2Minofftime VFB2=0.7V(2) 220 ns OFF2 SOFTSTART T Soft-starttime Internalsoft-starttime 1.0 ms SS (1) xmeanseither1or2,thatis,VFBxmeansVFB1orVFB2. (2) Specifiedbydesign.Notproductiontested. Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overrecommendedfree-airtemperaturerange,VIN=12V(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT POWERGOOD PGfromlowerVOx(goinghigh) 84% V PGxthreshold PGTH PGfromhigherVOx(goinglow) 116% R PGxpull-downresistance VPGx=0.5V 50 75 110 Ω PG DelayforPGxgoinghigh 1.5 ms T PGxdelaytime PGDLY DelayforPGxgoinglow 2 µs T PGxcomparatorstart-updelay PGxcomparatorwake-updelay 1.5 ms PGCOMPSS UVLO VREG5rising 3.83 V VREG5UVLOthreshold V UVREG5 Hysteresis 0.6 LOGICTHRESHOLDs V ENxH-levelthresholdvoltage 2.0 V ENH V ENxL-levelthresholdvoltage 0.4 V ENL R ENxinputresistance ENx=12V 225 450 900 kΩ ENx_IN CURRENTLIMITs I Currentlimit L =2.2µH(3) 2.7 3.9 4.5 A OCL OUT OUTPUTUNDERVOLTAGEANDOVERVOLTAGEPROTECTION(UVP,OVP) V OutputOVPtripthreshold measuredonVFBx 115% 120% 125% OVP T OutputOVPpropdelay 3 10 µs OVPDEL V OutputUVPtripthreshold measuredonVFBx 63% 68% 73% UVP T OutputUVPdelaytime 1.5 ms UVPDEL T OutputUVPenabledelay 1.5 ms UVPEN THERMALSHUTDOWN Shutdowntemperature(3) 155 T Thermalshutdownthreshold °C SD Hysteresis(3) 25 (3) Specifiedbydesign.Notproductiontested. 4 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 DEVICE INFORMATION HTSSOPPACKAGE(TOPVIEW) RSAPACKAGE(TOPVIEW) 2 D 1 VIN1 VIN2 16 W2 GN N2 G2 S P E P 16 15 14 13 2 VBST1 VBST2 15 VBST2 1 12 VFB2 3 SW1 SW2 14 VIN2 2 11 VREG5 PowerPAD 4 PGND1 TPS54294 PGND2 13 VIN1 3 10 GND HTSSOP16 VBST1 4 9 VFB1 5 EN1 EN2 12 5 6 7 8 6 PG1 PG2 11 1 1 1 1 W D N G (PowerPAD) S N E P G 7 VFB1 VFB2 10 P 8 GND VREG5 9 PINFUNCTIONS(1) PIN I/O DESCRIPTION NAME NUMBER PWP RSA VIN1,VIN2 1,16 3,2 I PowerinputsandconnectstobothhighsideNFETdrains. SupplyInputfor5.5Vlinearregulator. VBST1,VBST2 2,15 4,1 I Supplyinputforhigh-sideNFETgatedrivecircuit.Connect0.1µFceramiccapacitor betweenVBSTxandSWxpins.AninternaldiodeisconnectedbetweenVREG5and VBSTx SW1,SW2 3,14 5,16 I/O Switchnodeconnectionsforboththehigh-sideNFETsandlow–sideNFETs.Inputof currentcomparator. PGND1,PGND2 4,13 6,15 I/O Groundreturnsforlow-sideMOSFETs.Inputofcurrentcomparator. EN1,EN2 5,12 7,14 I Enable.PullHightoenableaccordingconverter. PG1,PG2 6,11 8,13 O Opendrainpowergoodoutput.Lowmeanstheoutputvoltageofthecorresponding outputisoutofregulation. VFB1,VFB2 7,10 9,12 I D-CAP2feedbackinputs.Connecttooutputvoltagewithresistordivider. GND 8 10 I/O SignalGND.ConnectsensitiveSSxandVFBxreturenstoGNDatasinglepoint. VREG5 9 11 O Outputof5.5Vlinearregulator.BypasstoGNDwithahigh-qualityceramiccapacitor ofatleast1.0µF.VREG5isactivewhenVIN1isadded. ExposedThermal Backside Backside I/O Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation. Pad MustbeconnectedtoGND. (1) xmeanseither1or2,e.g.VFBxmeansVFB1orVFB2. Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM -16% PG VIN1 Comp +16% VIN1 PG1 -32 UV1 VBST1 0.1uF OV1 VO1 SW1 +20 Re1f VFB1 Err PGND1 PGND1 Com SS1 p Ref_OCL PGND1 SW1 SW1 EN1 OCP1 ZC1 EN EN Logic EN2 Logic VIN1 VREG5 GND CH1Min-off timer 5VREG 1.0.uF CH2Min-off timer Ref1 REF Ref2 SS1 Fixed SoftStart SS2 UV1 UV2 UVLO OV1 Protection VIN2 OV2 Logic UVLO VIN2 TSD -32 UV2 VBST2 0.1uF VO2 OV2 SW2 +20 Ref2 SS2 Err PGND2 PGND2 Com VFB2 p Ref_OCL PGND2 SW2 -16% SW2 PG OCP2 ZC2 Comp +16% PG2 6 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 OVERVIEW The TPS54294 is a 2A/2A dual synchronous step-down (buck) converter with two integrated N-channel MOSFETsforeachchannel.ItoperatesusingD-CAP2™controlmode.ThefasttransientresponseofD-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitryallowstheuseoflowESRoutputcapacitorsincludingceramicandspecialpolymertypes. DETAILED DESCRIPTION PWMOperation The main control loop of the TPS54294 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. Atthebeginningofeachcycle,thehigh-sideMOSFETisturnedon.ThisMOSFETisturnedoffwhentheinternal timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a pseudo-fixedfrequencyovertheinputvoltagerangehenceitiscalledadaptiveon-timecontrol.Thetimerisreset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. Aninternalrampisaddedtothereferencevoltagetosimulateoutputvoltageripple,eliminatingtheneedforESR inducedoutputripplefromD-CAP™control. PWMFrequencyandAdaptiveOn-TimeControl TPS54294 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54294 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set theon-timetimer.Theon-timeisinverselyproportionaltotheinputvoltageandproportionaltotheoutputvoltage, therefore,whenthedutyratioisVOx/VINx,thefrequencyisconstant. Auto-Skip Eco-Mode™Control The TPS54294 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost half as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with smaller load current to the nominal output voltage. The transition point to the light load operation I current Ox(LL) canbeestimatedwithEquation1with700-kHzusedasf . SW 1 (V - V ) ´ V INx Ox Ox I = ´ Ox(LL) 2 ´ L1x ´ f V SW INx (1) SoftStartandPre-BiasedSoftStart The TPS54294 has an internal, 1.0ms, soft-start for each channel. When the ENx pin becomes high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintainedduringstartup. The TPS54294 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage, VFBx), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx) startsandrampsupsmoothlyintoregulationfrompre-biasedstartuptonormalmodeoperation. Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com POWERGOOD The TPS54294 has power-good outputs that are measured on VFBx. The power-good function is activated after the soft-start has finished. If the output voltage is within 16% of the target voltage, the internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay. During start-up, this internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of the power-good signal. If the feedbackvoltagegoesoutsideof±16%ofthetargetvalue,thepower-goodsignalbecomeslowafter2µs. Over-CurrentProtection he output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the measurementaccuracy,thevoltagesensingistemperaturecompensated. During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx, VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I . If the sensed voltage on the OUTx low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is monitoredinthesamemanner. Following are some important considerations for this type of over-current protection. The load current is one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. When the over current condition is removed, the output voltage returns to the regulated value.Thisprotectionisnon-latching. Over/UnderVoltageProtection TPS54294 monitors the resistor divided feedback voltage to detect over and under voltage. If the feedback voltage is higher than 120% of the reference voltage, the OVP comparator output goes high and the circuit latches both the high-side MOSFET driver and the low-side MOSFET driver off. When the feedback voltage is lower than 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1.5ms, TPS54294 latches OFF both the high-side MOSFET and the low-side MOSFET drivers. This function is enabled approximately 1.7 times the softstart time after power-on. The OVP andUVPlatchoffisresetwhenENistoggled. UVLOProtection Under-voltage lock out protection (UVLO) monitors the voltage of the V pin. When the V voltage is lower REG5 REG5 than the UVLO threshold, the TPS54294 shuts down. As soon as the voltage increases above the UVLO threshold,theconverterstartsagain. ThermalShutdown TPS54294 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device shutsdown.Whenthetemperaturefallsbelowthethreshold,theICstartsagain. When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is lowerthan155°C.AslongasVIN1rises,T mustbekeptbelow110°C. J 8 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 TYPICAL CHARACTERISTICS Oneoutputisenabledunlessotherwisenoted.VI=VIN1orVIN2. VIN=12V,T =25°C(unlessotherwisenoted). A 200 VIN1 = VIN2 = 12V EN1 = EN2 = ON 180 A 160 m nt - 140 e Curr 120 n w o 100 d ut h 80 S dn - 60 s c vc 40 I 20 0 -50 0 50 100 150 TJ- Junction Temperature - °C Figure1.InputCurrentvsJunctionTemperature Figure2.InputShutdownCurrentvsJunctionTemperature 100 3.4 90 3.38 80 3.36 Am 70 e - V 3.34 VI= 12 V VI= 18 V Current - 5600 ut Voltag 33.3.23 EN Input 3400 V- OutpO33..2268 VI= 5 V 20 3.24 10 3.22 0 3.2 0 5 10 15 20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 EN Input Voltage - V IO- Output Current -A Figure3.ENCurrentvsENVoltage(VEN=12V) Figure4.VO1=3.3VOutputVoltagevsOutputCurrent 1.55 3.4 1.54 3.38 1.53 3.36 V- Output Voltage - VO1111....14455.89125 VI= 12 V VVII== 5 1 V8 V V- Output Voltage - VO3333....32233.68243 Io1Io=1 1= A10 mA 1.47 3.24 1.46 3.22 1.45 3.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 2 4 6 8 10 12 14 16 18 20 IO- Output Current -A VI- Input Voltage - V Figure5.VO2=1.5VOutputVoltagevsOutputCurrent Figure6.VO1=3.3VOutputVoltagevsInputVoltage Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com TYPICAL CHARACTERISTICS Oneoutputisenabledunlessotherwisenoted.VI=VIN1orVIN2. VIN=12V,T =25°C(unlessotherwisenoted). A 1.55 1.54 1.53 Vo1(50 mV/div) V 1.52 Io2= 1A e - g 1.51 a olt ut V 1.5 Outp 1.49 Io2= 10mA IO 1 (1A/div) - O1.48 V 1.47 1.46 1.45 0 2 4 6 8 10 12 14 16 18 20 VI- Input Voltage - V t - Time - 100ms/div Figure7.VO2=1.5VOutputVoltagevsInputVoltage Figure8.VO1=3.3V,0Ato2ALoadTransientResponse Vo2(50 mV/div) EN1 (10 V/div) V O 1 (1 V/div) IO 2 (1A/div) PG1 (5 V/div) t - Time - 100ms/div t - Time - 400ms/div Figure9.VO2=1.5V,0Ato2ALoadTransientResponse Figure10.VO1=3.3V,SoftStartandPowergood 100 90 En2 (10 V/div) 80 VI= 12 V VI= 18 V V O 2 (0.5 V/div) ncy - % 70 VI= 5 V e ci Effi 60 PG2 (5 V/div) 50 40 0 0.5 1 1.5 2 t - Time - 400ms/div IO- Output Current -A Figure11.VO2=1.5V,SoftStartandPowerGood Figure12.VO1=3.3V,EfficiencyvsOutputCurrent 10 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 TYPICAL CHARACTERISTICS Oneoutputisenabledunlessotherwisenoted.VI=VIN1orVIN2. VIN=12V,T =25°C(unlessotherwisenoted). A 100 100 VI= 18 V 90 VI= 12 V 90 80 VI= 5 V 70 80 Efficiency - % 456000 Efficiency - % 70 VI= 5 V VI= 12 V VI= 18 V 60 30 20 50 10 0 40 0.001 0.01 0.1 0 0.5 1 1.5 2 IO- Output Current -A IO- Output Current -A Figure13.VO1=3.3V,EfficiencyvsOutputCurrent Figure14.VO1=1.5V,EfficiencyvsOutputCurrent 100 900 90 850 IO 1 =1A 80 VI= 18 V 800 Hz 70 VI= 12 V y - k 750 c Efficiency - % 456000 VI= 5 V ching Frequen 667050000 30 Swit 550 20 f - sw 500 10 450 0 400 0.001 0.01 0.1 0 5 10 15 20 IO- Output Current -A VI- Input Voltage - V Figure15.VO2=1.5V,EfficiencyvsOutputCurrent Figure16.VO1=3.3V,SW-frequencyvsInputVoltage 900 1000 850 900 VI= 12 V f - Switching Frequency - kHzsw 556677805050500000000 IO2= 1A f - Switching Frequency - kHzsw 234567800000000000000 450 100 400 0 0 5 10 15 20 0.01 0.1 1 10 VI- Input Voltage - V IO- Output Current -A Figure17.VO2=1.5V,SW-frequencyvsInputVoltage Figure18.VO1=3.3V,SW-frequencyvsOutputCurrent Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com TYPICAL CHARACTERISTICS Oneoutputisenabledunlessotherwisenoted.VI=VIN1orVIN2. VIN=12V,T =25°C(unlessotherwisenoted). A 800 VI= 12 V 700 Vo1= 3.3 V (10 mV/div) Hz 600 k y - c n 500 e u q e g Fr 400 SW1 (5 V/div) n chi 300 wit S f - sw 200 100 0 0.01 0.1 1 10 IO- Output Current -A t - Time - 400 ns/div Figure19.VO2=1.5V,SW-frequencyvsOutputCurrent Figure20.VO1=3.3V,VO1RippleVoltage(I =2A) O1 VIN1= 12 V(50 mV/div) Vo2= 1.5 V(10 mV/div) SW2 (5 V/div) SW1 (5 V/div) t - Time - 400 ns/div t - Time - 400 ns/div Figure21.VO2=1.5V,RippleVoltage(I =2A) Figure22.VIN1InputVoltageRipple(I =2A) O2 O1 VIN2 = 12 V (50 mV/div) SW2 (5 V/div) t - Time - 400 ns/div Figure23.VIN2INPUTVOLTAGERIPPLE(I =2A) O2 12 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 DESIGN GUIDE Step By Step Design Procedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated switchingfrequencyof700kHzisused. VINx 12V ± 10% 1 VIN1 VIN2 16 1V.0O51 V 10Cm1F1 1.L51m1H C0.311mF2 VBST1 VBST2150.1Cm3F2 1.L51m2H C1012mF 1V.O8 2V 3 SW1 SW214 C21 C22 22mF 22mF x2 4 PGND1 TPS54294 PGND213 x2 PGND HTSSOP16 PGND 5 EN1 EN212 R11 6 PG1 PG211 R12 8.25 kW 7 VFB1 VFB2 10 30.1 kW R21 C41uF R22 22.1 kW 8 GND VREG59 22.1 kW PGND SGND SGND Figure24. SchematicDiagramfortheDesignExample Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use 1%toleranceorbetterdividerresistors.StartbyusingEquation2 tocalculateV . Ox To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values willbemoresusceptibletonoiseandvoltageerrorsduetotheVFBxinputcurrentwillbemorenoticeable. æ R1xö VOx =0.765V ´ çè1+R2x÷ø (2) Output Filter Selection TheoutputfilterusedwiththeTPS54294isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L ´ C OUT OUT (3) Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS545294. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero thatreducesthegainrolloffto –20dBperdecadeandincreasesthephaseto90degreesonedecadeabovethe zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable1. Table1.RecommendedComponentValues OUTPUTVOLTAGE(V) R1x(kΩ) R2x(kΩ) Cffx(pF) L1x(µH) C2x(µF) 1 6.81 22.1 1.0-1.5 22-68 1.05 8.25 22.1 1.0-1.5 22-68 1.2 12.7 22.1 1.0-1.5 22-68 1.5 21.5 22.1 1.5 22-68 1.8 30.1 22.1 5-22 1.5 22-68 2.5 49.9 22.1 5-22 2.2 22-68 3.3 73.2 22.1 5-22 2.2 22-68 5 124 22.1 5-22 3.3 22-68 For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor(Cff)inparallelwithR1. The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak currentandtheRMSorheatingcurrentratingmustbegreaterthanthecalculatedRMScurrent. For the calculations, use 700 kHz as the switching frequency, f . Make sure the chosen inductor is rated for the SW peakcurrentofEquation5andtheRMScurrentofEquation6. V V - V ΔI = Ox ´ INx(MAX) Ox L1x V L1x ´ f INx(MAX) SW (4) ΔI I =I + L Lpeakx Ox 2 (5) 1 I = I 2 + ΔI 2 LOx(RMS) Ox 12 L (6) For the above design example, the calculated peak current is 2.46 A and the calculated RMS current is 2.02 A for VO1. The inductor used is a TDK CLF7045-1R5N with a rated current of 7.3A based on the inductance changeandof4.9Abasedonthetemperaturerise. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54294 is intended for use with ceramic or other low ESR capacitors. The recommended value range is from 22µF to 68µF. Use Equation 7 todeterminetherequiredRMScurrentratingfortheoutputcapacitor(s). V ´ (V - V ) I = Ox INx Ox COx(RMS) 12 ´ V ´ L ´ f INx Ox SW (7) For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.19Aandeachoutputcapacitorisratedfor4A. Input Capacitor Selection The TPS54294 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1 µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the SWxnodeovershoots.Thecapacitorsvoltageratingneedstobegreaterthanthemaximuminputvoltage. 14 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 Bootstrap Capacitor Selection A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is recommendedtouseceramiccapacitorswithadielectricofX5Rorbetter. VREG5 Capacitor Selection A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is recommendedtouseaceramiccapacitorwithadielectricofX5Rorbetter. Thermal Information This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. Thisdesignoptimizestheheattransferfromtheintegratedcircuit(IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.SLMA002andApplicationBrief, PowerPAD™MadeEasy,TexasInstrumentsLiteratureNo.SLMA004. Theexposedthermalpaddimensionsforthispackageareshowninthefollowingillustration. Figure25. ThermalPadDimensions Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com Layout Considerations 1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal pad. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductanceandtominimizeradiatedemissions. 3. Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. 4. Makeasinglepointconnectionfromthesignalgroundtopowerground. 5. Donotallowswitchingcurrentstoflowunderthedevice. 6. KeepthepatternlinesforVINxandPGNDxbroad. 7. ExposedpadofdevicemustbesolderedtoPGND. 8. VREG5capacitorshouldbeplacednearthedevice,andconnectedtoGND. 9. OutputcapacitorsshouldbeconnectedwithabroadpatterntothePGND. 10. Voltagefeedbackloopsshouldbeasshortaspossible,andpreferablywithgroundshields. 11. Kelvinconnectionsshouldbebroughtfromtheoutputtothefeedbackpinofthedevice. 12. ProvidingsufficientviasispreferableforVIN,SWandPGNDconnections. 13. PCBpatternforVIN,SW,andPGNDshouldbeasbroadaspossible. 14. VINCapacitorshouldbeplacedasnearaspossibletothedevice. 16 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 VIN2 VIN HIGH FREQUENCY VIN INPUT BYPASS BYPASS CAPACITOR CAPACITOR ～0.1µF 10µF x2 Switching noise VIN1 1 16 VIN2 flows through IC and C .It avoids the thIeNrmal Pad. OUTPUT VBST1 2 15 VBST2 FILTER VO2 CAPACITOR SW1 3 14 SW2 INODUUTCPTUOTR Recommend to keep PGND14 13PGND2 distance more than3-4mm. (to avoid noise scattering, EN1 5 12 EN2 TO ENABLE especially GND plane.) CONTROL Keep PG1 6 11PG2 distance more than1inch POWERGND VFB17 10 VFB2 To feedback GND 8 9VREG5 Feedback resisters BIAS resisters Symmetrical Layout CAP for CH1 and CH2 GND PLANE 2,3or bottom layer Via to GND Plane - Blue parts can be placed on the bottom side - Connect the SWx pins through another layer with the inductor (yellow line) Figure26. TPS54294Layout Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54294

TPS54294 SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 www.ti.com VOUT2 KEEP VIAS > 3-4 mm FROM OUTPUT OUTPUT2 CAPACITORS FILTER CAPACITORS POWER GROUND OUTPUT2 KEEPOUTPUT INDUCTOR VIAS > 25 mm FROM INPUTVIAS TO ENABLE VIN INPUT CONTROL BYPASS CAPACITORS KEEP VIAS > 3-4 mm FROM INPUT CAPACITORS VIN HIGH 2 FREQUENCY D TO POWER BCYAPPAASCSITOR W2 GN N2 G2 GOOD PULL S P E P UP2 BOOST CAPACITOR 16 15 14 13 FEEDBACK RESISTORS VBST2 1 EXPOSEDTHERMAL 12 VFB2 PADAREA VIN2 2 11 VREG5 VIN BIAS ANALOG VIN1 3 10 GND CAP GROUND TRACE VBST1 4 9 VFB1 BOOST CAPACITOR FEEDBACK 5 6 7 8 RESISTORS W1 D1 1N G1 TO POWER VIN HIGH S N E P GOOD PULL FREQUENCY G UP1 BYPASS P CAPACITOR KEEP VIAS > 3-4 mm FROM INPUT CAPACITORS VIN INPUT VIAto Internal or BYPASS Bottom Layer Ground Plane CAPACITORS TO ENABLE VIAto internal or CONTROL Bottom Layer Etch KEEPOUTPUT OUTPUT1 VIAS > 25 mm Etch or Copper Fill INDUCTOR FROM INPUTVIAS onTop Layer Internal or Bottom POWER Layer Ground Plane GROUND Etch on Bottom Layer, OUTPUT1 Internal Layer or FILTER Under Component CAPACITORS KEEP VIAS > 3-4 mm NOTE: ITIS POSSIBLETO PLACE VOUT1 FCRAOPAMC OITUOTRPSUT INTERNALOR SOME COMPONENTS SUCHAS BOTTOM LAYER BOOSTCAPACITORAND FEEDBACK GROUND PLANE RESISTORS ON BOTTOM LAYER Figure27. TPS54294RSAPackageLayout 18 SubmitDocumentationFeedback Copyright©2011–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54294

TPS54294 www.ti.com SLVSB00D–OCTOBER2011–REVISEDSEPTEMBER2013 REVISION HISTORY NOTE:Pagenumbersofcurrentversionmaydifferfrompreviousversions. ChangesfromOriginal(October2011)toRevisionA Page • AddedinputvoltagerangeforVFB1,VFB2toAbsoluteMaximumRatings ........................................................................ 2 • AddedinputvoltagerangeforVFB1,VFB2toRecommendedOperatingConditions ......................................................... 3 • Addedindicationfornotproductiontestedparameters. ....................................................................................................... 3 • Addedindicationfornotproductiontestedparameters. ....................................................................................................... 4 • AddedOver/UnderVoltageProtectionDescription .............................................................................................................. 8 ChangesfromRevisionA(November2011)toRevisionB Page • DeletedV MINandMAXvalues..................................................................................................................................... 3 REG5 • DeletedLineandLoadregulationspecsfromVREG5specification .................................................................................... 3 • Added"Specifiedbydesign.Notproductiontested"annotationtoMOSFETsspecification................................................ 3 • DeletedMINandMAXvaluesfromV specification .................................................................................................... 4 UVREG5 ChangesfromRevisionB(December2011)toRevisionC Page • Removed(SWIFT™)fromthedatasheettitle .................................................................................................................... 1 • Added16-pinVQFNpackagetoFeaturesandDescription ................................................................................................. 1 • AddedRSApinoutimage,pinnamesandfunctionstoDeviceInfoSection ........................................................................ 5 • ChangedTPS54295,2placestoTPS54294inOver/UnderVoltageprotectionsection ..................................................... 8 • AddedRSA-packageboardlayout, .................................................................................................................................... 18 ChangesfromRevisionC(April2013)toRevisionD Page • DeletedT =25°CfromtheELECTRICALCHARACTERISTICSConditionscolumn ......................................................... 3 A • ChangedVINsupplycurrentMaxvalueFrom:2000µATo:2500µA ................................................................................. 3 • ChangedVINshutdowncurrentMaxvalueFrom:150µATo:200µA ................................................................................ 3 Copyright©2011–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54294

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54294PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54294 & no Sb/Br) TPS54294PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54294 & no Sb/Br) TPS54294RSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS & no Sb/Br) 54294 TPS54294RSAT ACTIVE QFN RSA 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS & no Sb/Br) 54294 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54294PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS54294RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS54294RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54294PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54294RSAR QFN RSA 16 3000 367.0 367.0 35.0 TPS54294RSAT QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE 6.6 TYP C A 6.2 PIN 1 INDEX 0.1 C AREA 14X 0.65 SEATING 16 PLANE 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 4.5 16X B 0.19 4.3 0.1 C A B SEE DETAIL A (0.15) TYP 2X 0.95 MAX NOTE 5 4X (0.3) 8 9 2X 0.23 MAX NOTE 5 2.31 17 0.25 1.75 GAGE PLANE 1.2 MAX 0.75 0.15 1 16 0 -8 0.50 0.05 DETA 20AIL A THERMAL 2.46 TYPICAL PAD 1.75 4224559/B 01/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. www.ti.com

EXAMPLE BOARD LAYOUT PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (3.4) NOTE 9 (2.46) 16X (1.5) SYMM METAL COVERED BY SOLDER MASK 1 16X (0.45) 16 (1.2) TYP (R0.05) TYP SYMM 17 (2.31) (5) (0.6) NOTE 9 14X (0.65) ( 0.2) TYP VIA 8 9 SOLDER MASK (1) TYP DEFINED PAD SEE DETAILS (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDE15.000R MASK DETAILS 4224559/B 01/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (2.46) BASED ON 16X (1.5) 0.125 THICK METAL COVERED STENCIL BY SOLDER MASK 1 16X (0.45) 16 (R0.05) TYP (2.31) SYMM 17 BASED ON 0.125 THICK STENCIL 14X (0.65) 8 9 SYMM SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL (5.8) THICKNESSES SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.75 X 2.58 0.125 2.46 X 2.31 (SHOWN) 0.15 2.25 X 2.11 0.175 2.08 X 1.95 4224559/B 01/2019 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. www.ti.com

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