TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET FEATURES CONTENTS 1 • 4.5-Vto28-VInputRange DeviceRatings 2 23 • OutputVoltageRange0.8Vto90%ofInput ElectricalCharacteristics 3 Voltage DeviceInformation 9 • OutputCurrentUpto2A ApplicationInformation 12 • TwoFixedSwitchingFrequencyVersions: DesignExamples 32 – TPS54283:300kHz AdditionalReferences 44 – TPS54286:600kHz DESCRIPTION • TwoSelectableLevelsofOvercurrent Protection(Output2) TPS54283 and TPS54286 are dual output • 0.8-V1.5%VoltageReference non-synchronous buck converters capable of supporting2-Aoutputapplicationsthatoperatefroma • 2.1-msInternalSoftStart 4.5-V to 28-V input supply voltage, and require output • DualPWMOutputs180(cid:176) Out-of-Phase voltagesbetween0.8Vand90%oftheinputvoltage. • RatiometricorSequentialStartupModes With internally-determined operating frequency, soft SelectablebyaSinglePin start time, and control loop compensation, these • 100-mΩInternalHigh-SideMOSFETs converters provide many features with a minimum of • CurrentModeControl external components. Channel 1 overcurrent protection is set at 3 A, while Channel 2 overcurrent • InternalCompensation(SeePage16) protection level is selected by connecting a pin to • Pulse-by-PulseOvercurrentProtection ground, to BP, or left floating. The setting levels are • ThermalShutdownProtectionat148(cid:176) C used to allow for scaling of external components for applications not needing the full load capability of • 14-PinPowerPAD™HTSSOPpackage bothoutputs. APPLICATIONS The outputs may be enabled independently, or may • SetTopBox be configured to allow either ratiometric or sequential startup sequencing. Additionally, the two outputs may • DigitalTV alsobepoweredfromdifferentsources. • PowerforDSP • ConsumerElectronics V IN TPS54283 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 OUTPUT1 OUTPUT2 3 SW1 SW2 12 4 GND BP 11 5 EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 GND UDG-07006 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstruments. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION(1) PARTNUMBER OPERATINGFREQUENCY(kHz) PACKAGE MEDIA UNITS(Pieces) TPS54283PWP Tube 90 300 TPS54283PWPR TapeandReel 2000 Plastic14-PinHTSSOP TPS54286PWP Tube 90 600 TPS54286PWPR TapeandReel 2000 (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT PVDD1,PVDD2,EN1,EN2 30 BOOT1,BOOT2 VSW+7 SW1,SW2 –2to30 Inputvoltagerange SW1,SW2transient(<50ns) –3to31 V BP 6.5 SEQ,ILIM2 –0.3to6.5 FB1,FB2 –0.3to3 SW1,SW2outputcurrent 7 A BPloadcurrent 35 mA Tstg Storagetemperature –55to+165 TJ Operatingtemperature –40to+150 (cid:176)C Solderingtemperature +260 (1) PermanentdevicedamagemayoccurifAbsoluteMaximumRatingsareexceeded.Functionaloperationshouldbelimitedtothe RecommendedDCOperatingConditionsdetailedinthisdatasheet.Exposuretoconditionsbeyondtheoperationallimitsforextended periodsoftimemayaffectdevicereliability. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT V Inputvoltage 4.5 28 V PVDD2 T Operatingjunctiontemperature –40 +125 (cid:176) C J ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN UNIT Humanbodymodel 2k CDM 1.5k V MachineModel 250 PACKAGE DISSIPATION RATINGS(1)(2)(3) THERMALIMPEDANCE JUNTION-TO-THERMALPAD TA=+25(cid:176)C,NOAIRFLOW TA=+85(cid:176)C,NOAIRFLOW PACKAGE ((cid:176)C/W) POWERRATING(W) POWERRATING(W) Plastic14-PinHTSSOP(PWP) 2.07(4) 1.6 1.0 (1) FormoreinformationonthePWPpackage,refertoTITechnicalBrief(SLMA002A). (2) TIdevicepackagesaremodeledandtestedforthermalperformanceusingprintedcircuitboarddesignsoutlinedinJEDECstandards JESD51-3andJESD51-7. (3) Forapplicationinformation,seethePowerDeratingsection. (4) T =+40(cid:176) C/W J-A 2 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 ELECTRICAL CHARACTERISTICS –40(cid:176) C≤T ≤+125(cid:176) C,V =V =12V,unlessotherwisenoted. J PVDD1 PVDD2 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTSUPPLY(PVDD) VPVDD1 Inputvoltagerange 4.5 28 V VPVDD2 IDDSDN Shutdown VEN1=VEN2=VPVDD2 70 150 m A IDDQ Quiescent,non-switching VFB=0.9V,Outputsoff 1.8 3.0 SWnodeunloaded;MeasuredasBPsink mA IDDSW Quiescent,while-switching current 5 VUVLO Minimumturn-onvoltage PVDD2only 3.8 4.1 4.4 V VUVLO(hys) Hysteresis 400 mV tSTART(1)(2) Timefromstartuptosoftstartbegin CsiBmPu=lta1n0emoFus,lEyN1andEN2golow 2 ms ENABLE(EN) VEN1 Enablethreshold 0.9 1.2 1.5 V VEN2 Hysteresis 50 mV IEN1 Enablepull-upcurrent VEN1=VEN2=0V 6 12 m A IEN2 tEN(1) Timefromenabletosoft-startbegin OtherENpin=GND 10 m s BPREGULATOR(BP) BP Regulatorvoltage 8V<PVDD2<28V 5 5.25 5.6 V BPLDO Dropoutvoltage PBVPDD2=4.5V;switching,noexternalloadon 400 mV IBP(1) Regulatorexternalload 2 mA IBPS Regulatorshortcircuit 4.5V<PVDD2<28V 10 20 30 OSCILLATOR TPS54283 255 310 375 fSW Switchingfrequency kHz TPS54286 510 630 750 tDEAD(1) Clockdeadtime 140 ns ERRORAMPLIFIER(EA)andVOLTAGEREFERENCE(REF) VFB1 0(cid:176)C<TJ<+85(cid:176)C 788 800 812 Feedbackinputvoltage mV VFB2 –40(cid:176)C<TJ<+125(cid:176)C 786 812 IFB1 Feedbackinputbiascurrent 3 50 nA IFB2 gM1(1) Transconductance 30 m S gM2(1) SOFTSTART(SS) TSS1 Softstarttime 1.5 2.1 2.7 ms TSS2 OVERCURRENTPROTECTION ICL1 Currentlimitchannel1 2.4 3.0 3.6 VILIM2=VBP 1.15 1.50 1.75 A ICL2 Currentlimitchannel2 VILIM2=(floating) 2.4 3.0 3.6 VILIM2=GND 1.15 1.50 1.75 VUV1 Low-leveloutputthresholdtodeclareafault Measuredatfeedbackpin. 670 mV VUV2 THICCUP(1) Hiccuptimeout 10 ms tON1(oc)(1) Minimumovercurrentpulsewidth 90 150 ns tON2(oc)(1) (1) Ensuredbydesign.Notproductiontested. (2) Whenbothoutputsarestartedsimultaneously,a20-mAcurrentsourcechargestheBPcapacitor.Fastertimesarepossiblewithalower BPcapacitorvalue.MoreinformationcanbefoundintheInputUVLOandStartupsection. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 ELECTRICAL CHARACTERISTICS (continued) –40(cid:176) C≤T ≤+125(cid:176) C,V =V =12V,unlessotherwisenoted. J PVDD1 PVDD2 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT BOOTSTRAP RBOOT1 FromBPtoBOOT1orBPtoBOOT2, Bootstrapswitchresistance 18 Ω RBOOT2 IEXT=50mA OUTPUTSTAGE(Channel1andChannel2) RDS(on)(3) MOSFETonresistanceplusbondwireresistance T–4J0=(cid:176)C+2<5(cid:176)TCJ,<V+PV1D2D52(cid:176)C=,8VVPVDD2=8V 110000 180 mΩ tON(min)(3) Minimumcontrollablepulsewidth ISWxpeakcurrent>1A(4) 100 200 ns DMIN MinimumDutyCycle VFB=0.9V 0 % TPS54283 fSW=300kHz 90 95 % DMAX MaximumDutyCycle TPS54286 fSW=600kHz 85 90 % ISW Switchingnodeleakagecurrent(sourcing) OutputsOFF 2 12 m A THERMALSHUTDOWN TSD(3) Shutdowntemperature 148 TSD(hys)(3) Hysteresis 20 (cid:176)C (3) Ensuredbydesign.Notproductiontested. (4) SeeFigure14forcharacteristicsforI peakcurrent<1A. SWx 4 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 TYPICAL CHARACTERISTICS QUIESCENTCURRENT(NON-SWITCHING) SHUTDOWNCURRENT vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 2.1 140 V =5.25 V V =28 V BP PVDDx 120 2.0 V =12 V PVDDx A m A m 100 -nt 1.9 -nt e e urr urr 80 C C nt 1.8 n e w sc do 60 Quie 1.7 Shut - - 40 DDQ ISD I 1.6 VPVDDx=4.5 V 20 1.5 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 T -Junction Temperature-°C T -Junction Temperature-°C J J Figure1. Figure2. UNDERVOLTAGELOCKOUTTHRESHOLD ENABLETHRESHOLDS vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 4.2 1.25 EN(Off) 4.1 V V 1.23 -ut UVLO(On) -ge o a ck 4.0 olt o V voltage L 3.9 hreshold 1.21 der UVLO(Off) e T 1.19 EN(On) Un 3.8 abl - n E O L - V U N1.17 V 3.7 VE 3.6 1.15 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 T -Junction Temperature-°C T -Junction Temperature-°C J J Figure3. Figure4. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 TYPICAL CHARACTERISTICS (continued) SOFTSTARTTIME SWITCHINGFREQUENCY(300kHz) vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 3.5 350 V =5.25 V BP V =5.25 V BP s 3.0 Hz 330 m k - - y e c m n Ti ue oft Start 2.5 WM Freq 310 S P - - tSS 2.0 WM 290 P f 1.5 270 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 T -Junction Temperature-°C T -Junction Temperature-°C J J Figure5. Figure6. SWITCHINGFREQUENCY(600kHz) FEEDBACKBIASCURRENT vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 680 5 V =5.25 V BP 660 A 3 z n H - -k nt ncy 640 urre 1 e C M Frequ ck Bias W 620 a -1 b P d - e e M F W P - f 600 FB -3 I 580 -5 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 T -Junction Temperature-°C T -Junction Temperature-°C J J Figure7. Figure8. 6 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 TYPICAL CHARACTERISTICS (continued) FEEDBACKVOLTAGE OVERCURRENTLIMIT(CH1,CH2HIGHLEVEL) vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 808 3.4 V =24 V PVDDx V 803 3.2 m A - - ge mit Volta nt Li k 798 re 3.0 ac ur b c d er e v e O F - - VFB 793 ICL 2.8 V =12 V PVDDx V =5 V PVDDx 788 2.6 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 T -Junction Temperature-°C T -Junction Temperature-°C J J Figure9. Figure10. OVERCURRENTLIMIT(CH2LOWLEVEL) SWITCHINGNODELEAKAGECURRENT vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 1.8 5 VPVDDx=24 V Am - nt e -A 1.6 Curr 4 mit ge rent Li Leaka rcur ode 3 e N v O 1.4 ng - hi ICL witc 2 S - VPVDDx=12 V off) V =5 V W( PVDDx S 1.2 I -50 -25 0 25 50 75 100 125 1 -50 -25 0 25 50 75 100 125 T -Junction Temperature-°C J T -JunctionTemperature-°C J Figure11. Figure12. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 TYPICAL CHARACTERISTICS (continued) OVERCURRENTLIMIT MINIMUMCONTROLLABLEPULSEWIDTH vs vs SUPPLYVOLTAGE LOADCURRENT 400 T (°C) OCL=3.0A s A 3.5 n 350 –40 - h T =–40°C 0 mit-A 3.0 seWidt 300 A 2855 Li ul P rent 2.5 ble 250 vercur ntrolla 200 TA=0°C -O 2.0 OCL=1.5A Co C m IO mu 150 1.5 ni Mi - 100 TA=25°C N O 1.0 t TA=85°C 4 8 12 16 20 24 28 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 V -SupplyVoltage-V DD I -LoadCurrent-A L Figure13. Figure14. 8 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 DEVICE INFORMATION PIN CONNECTIONS HTSSOP(PWP) (TopView) PVDD1 1 14 PVDD2 BOOT1 2 13 BOOT2 SW1 3 12 SW2 GND 4 ThermalPad 11 BP (bottomside) EN1 5 10 SEQ EN2 6 9 ILIM2 FB1 7 8 FB2 TERMINALFUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. InputsupplytothehighsidegatedriverforOutput1.Connecta22-nFto82-nFcapacitorfromthispin toSW1.ThiscapacitorischargedfromtheBPpinvoltagethroughaninternalswitch.Theswitchis BOOT1 2 I turnedONduringtheOFFtimeoftheconverter.ToslowdowntheturnONoftheinternalFET,asmall resistor(1Ωto3Ω)maybeplacedinserieswiththebootstrapcapacitor. InputsupplytothehighsidegatedriverforOutput2.Connecta22-nFto82-nFcapacitorfromthispin toSW2.ThiscapacitorischargedfromtheBPpinvoltagethroughaninternalswitch.Theswitchis BOOT2 13 I turnedONduringtheOFFtimeoftheconverter.ToslowdowntheturnONoftheinternalFET,asmall resistor(1Ωto3Ω)maybeplacedinserieswiththebootstrapcapacitor. Regulatedvoltagetochargethebootstrapcapacitors.BypassthispintoGNDwithalowESR(4.7-m F BP 11 - to10-m FX7RorX5Rpreferred)ceramiccapacitor. ActivelowenableinputforOutput1.Ifthevoltageonthispinisgreaterthan1.55V,Output1is disabled(high-sideswitchisOFF).Avoltageoflessthan0.9VenablesOutput1andallowssoftstartof EN1 5 I Output1tobegin.AninternalcurrentsourcedrivesthispintoPVDD2ifleftfloating.Connectthispinto GNDtoforce"alwaysON"operation. ActivelowenableinputforOutput2.Ifthevoltageonthispinisgreaterthan1.55V,Output2is disabled(high-sideswitchisOFF).Avoltageoflessthan0.9VenablesOutput2andallowssoftstartof EN2 6 I Output2tobegin.AninternalcurrentsourcedrivesthispintoPVDD2ifleftfloating.Connectthispinto GNDtoforce"alwaysON"operation. VoltagefeedbackpinforOutput1.TheinternaltransconductanceerroramplifieradjuststhePWMfor Output1toregulatethevoltageatthispintotheinternal0.8-Vreference.Aseriesresistordividerfrom FB1 7 I Output1toground,withthecenterconnectiontiedtothispin,determinesthevalueoftheregulated outputvoltage.Compensationforthefeedbackloopisprovidedinternallytothedevice.SeeFeedback LoopandInductor-Capacitor(L-C)Filtersectionforfurtherinformation. VoltagefeedbackpinforOutput2.TheinternaltransconductanceerroramplifieradjuststhePWMfor Output2toregulatethevoltageatthispintotheinternal0.8-Vreference.Aseriesresistordividerfrom FB2 8 I Output2toground,withthecenterconnectiontiedtothispin,determinesthevalueoftheregulated Outputvoltage.Compensationforthefeedbackloopisprovidedinternallytothedevice.SeeFeedback LoopandInductor-Capacitor(L-C)Filtersectionforfurtherinformation. GND 4 - Groundpinforthedevice.ConnectdirectlytoThermalPad. CurrentlimitadjustpinforOutput2only.Thisfunctionisintendedtoallowauserwithasymmetrical loadcurrents(Output1loadcurrentmuchgreaterthanOutput2loadcurrent)tooptimizecomponent ILIM2 9 I scalingofthelowercurrentoutputwhilemaintainingpropercomponentderatinginaovercurrentfault condition.ThediscretelevelsareavailableasshowninTable2.Note:Aninternal2-resistordivider (150-kΩeach)connectsBPtoILIM2andtoGND. PowerinputtotheOutput1highsideMOSFETonly.ThispinshouldbelocallybypassedtoGNDwitha PVDD1 1 I lowESRceramiccapacitorof10-m Forgreater. ThePVDD2pinprovidespowertothedevicecontrolcircuitry,providesthepull-upfortheEN1andEN2 pinsandprovidespowertotheOutput2high-sideMOSFET.Thispinshouldbelocallybypassedto PVDD2 14 I GNDwithalowESRceramiccapacitorof10-m Forgreater.TheUVLOfunctionmonitorsPVDD2and enablesthedevicewhenPVDD2isgreaterthan4.1V. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 TERMINALFUNCTIONS(continued) TERMINAL I/O DESCRIPTION NAME NO. Thispinconfigurestheoutputstartupmode.IftheSEQpinisconnectedtoBP,thenwhenOutput2is enabled,Output1isallowedtostartafterOutput2hasreachedregulation;thatis,sequentialstartup whereOutput1isslavetoOutput2.IfEN2isallowedtogohighaftertheoutputshavebeenoperating, thenbothoutputsaredisabledimmediately,andtheoutputvoltagesdecayaccordingtotheloadthatis present.Forthissequenceconfiguration,tieEN1toground. IftheSEQpinisconnectedtoGND,thenwhenOutput1isenabled,Output2isallowedtostartafter Output1hasreachedregulation;thatis,sequentialstartupwhereOutput2isslavetoOutput1.IfEN1 isallowedtogohighaftertheoutputshavebeenoperating,thenbothoutputsaredisabledimmediately, SEQ 10 I andtheoutputvoltagesdecayaccordingtotheloadthatispresent.Forthissequenceconfiguration,tie EN2toground. Ifleftfloating,Output1andOutput2startratio-metricallywhenbothoutputsareenabledatthesame time.Theysoftstartataratedeterminedbytheirfinaloutputvoltageandenterregulationatthesame time.IftheEN1andEN2pinsareallowedtooperateindependently,thenthetwooutputsalsooperate independently. NOTE:Aninternaltworesistor(150-kΩeach)dividerconnectsBPtoSEQandtoGND.SeeTable1 SequencingStates. Source(switching)outputforOutput1PWM.Asnubberisrecommendedtoreduceringingonthis SW1 3 O node.SeeSWNodeRingingforfurtherinformation. Source(switching)outputforOutput2PWM.Asnubberisrecommendedtoreduceringingonthis SW2 12 O node.SeeSWNodeRingingforfurtherinformation. ThermalPad - - ThispadmustbetiedexternallytoagroundplaneandtheGNDpin. 10 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 BLOCK DIAGRAM 2 BOOT1 BP CLK1 Level 1 PVDD1 Shift Current f(I )+DC(ofst) Comparator DRAIN1 S Q + GND 4 R R Q + f(I ) FB1 7 DRAIN1 OvercurrentComp 0.8V + 3 SW1 REF RCOMP f(ISLOPE1) f(IMAX1) BP SoftStart Weak SD1 1 CCOMP CLK1 Anti-Cross Pull-Down Conduction MOSFET VDD2 f(I ) SLOPE1 Ramp Gen1 TSD 1.2MHz Divide CLK1 6mA 6mA Oscilator by2/4 f(I ) SLOPE2 EN1 5 SD1 Ramp Gen2 Internal SD2 EN2 6 Control CLK2 UVLO 150kW SEQ 10 BP FB1 Output Undervoltage 150kW 13 BOOT2 FB2 Detect BP CLK2 Level 14 PVDD2 Shift Current Comparator FET f(I )+DC(ofst) DRAIN2 S Q Switch + GND 4 R R Q + f(I ) FB2 8 DRAIN2 OvercurrentComp 0.8V + 12 SW2 REF RCOMP f(ISLOPE2) f(IMAX2) BP SoftStart Weak SD2 2 CCOMP CLK2 Anti-Cross Pull-Down Conduction MOSFET 5.25-V BP 11 PVDD2 Regulator 150kW BP Level ILIM2 9 Select 150kW 0.8V REF References I (Settooneoftwolimits) MAX2 UDG-07007 Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 APPLICATION INFORMATION FUNCTIONAL DESCRIPTION The TPS54283 and TPS54286 are dual output non-synchronous converters. Each PWM channel contains an internally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable, and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, clockoscillator,andoutputvoltagesequencingfunctions. DESIGNHINT The TPS5428x contains internal slope compensation and loop compensation components; therefore, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally selected first, and the compensation network is found afterwards. (See Feedback Loop and L-C Filter Selectionsection.) NOTE: Unless otherwise noted, the term TPS5428x applies to both the TPS54283 and TPS54286.Also,unlessotherwisenoted,alabel with a lowercase x appended implies thetermapplies to both outputs of the two modulator channels. For example, the term ENx implies both EN1 and EN2. Unless otherwise noted, all parametric values given are typical. Refer to the Electrical Characteristics for minimum and maximum values. Calculationsshouldbeperformedwithtolerancevaluestakenintoconsideration. VoltageReference Thebandgapcellcommontobothoutputs,trimmedto800mV. Oscillator The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are internallyconfiguredtooperateonalternatingswitchcycles(thatis,180(cid:176) outofphase). InputUndervoltageLockout(UVLO)andStartup When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startup sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start begins, depending on the SEQmodeofoperationandtheEN1andEN2settings. Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be higherorlowerthanPVDD2.(SeetheDualSupplyOperationsection.) EnableandTimedTurnOnoftheOutputs Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the associatedoutputisenabledandsoftstartisinitiated. If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is shut down and minimal functions are active. The total standby current from both PVDD pins is approximately 70m Aat12-Vinputsupply. 12 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power is applied to PVDDx (see Figure 15). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to PVDD2,thenomitthesetwocomponentsandtietheENxpintoGNDdirectly. If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V / 6m A or 200 kΩ. A suggested value is 51 kΩ. This resistor value allows the ENx voltage to decay below the 1.2-V thresholdwhilethe6-m Abiascurrentflows. Thecapacitorvaluerequiredtodelaythestartuptime(aftertheapplicationofPVDD2)isshowninEquation1. t C= DELAY farads æV -2´I ´Rö R´lnç IN ENx ÷ è VTH-IENx´R ø (1) where: • RandCarethetimingcomponents • V isthe1.2-Venablethresholdvoltage TH • I isthe6m Aenablepinbiasingcurrent ENx Other enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing section.) PVDD2 6mA C ENx PVDDx PVDDx + 1.2-V Threshold 1.2 V R ENx TPS5428x V OUTx 0 t t + t DELAY DELAY SS T-Time Figure15.StartupDelaySchematic Figure16.StartupDelaywithR-ConEnable DESIGNHINT If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to GND. This configuration allows the outputs to start immediately on valid application of PVDD2. If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and the outputdecaysataratedeterminedbytheoutputcapacitorandtheload. The internal pulldown MOSFET remains intheOFFstate.(SeetheBootstrapforN-ChannelMOSFETsection.) Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 OutputVoltageSequencing The TPS5428x allows single-pin programming of output voltage startup sequencing. During power-on, the state of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs behave asdescribedinTable1. Table1.SequenceStates SEQPINSTATE MODE EN1 EN2 IgnoredbythedevicewhenV < EN2 enablethresholdvoltage TieEN1to<enablethresholdvoltage forBPtobeactivewhenV > BP Sequential,Output2thenOutput1 EN2 Active enablethresholdvoltage TieEN1to>enablethresholdvoltage forlowquiescentcurrent(BPinactive) whenV >enablethresholdvoltage EN2 IgnoredbythedevicewhenV < EN1 enablethresholdvoltage TieEN2to<enablethresholdvoltage forBPtobeactivewhenV > GND Sequential,Output1thenOutput2 Active EN1 enablethresholdvoltage TieEN2to>enablethresholdvoltage forlowquiescentcurrent(BPinactive) whenV >enablethresholdvoltage EN1 IndependentorRatiometric,Output1 Active.EN1andEN2mustbetied Active.EN1andEN2mustbetied (floating) andOutput2 togetherforRatiometricstartup. togetherforRatiometricstartup. IftheSEQpinisconnectedtoBP,then when Output 2 is enabled, Output 1 is allowed to start approximately 400 m s after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the outputvoltagesdecayaccordingtotheloadthatispresent. If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start approximately 400 m s after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, andtheoutputvoltagesdecayaccordingtotheloadthatispresent. SEQ=BP SEQ=GND Sequential Sequential CH2thenCH1 CH1thenCH2 5-VVOUT1 (2V/div) 5-VVOUT1 (2V/div) 3.3-VVOUT2 (2V/div) 3.3-VVOUT2 (2V/div) T-Time-1ms/div T-Time-1ms/div Figure17.SEQPinTIedtoBP Figure18.SEQPinTiedtoGND 14 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 DESIGNHINT An R-C network connected to the ENx pin may be used in addition to the SEQ pin in sequential mode to delay the startup of the first output voltage. This approach may be necessary in systems with a large number of output voltages and elaborate voltage sequencingrequirements.SeeEnableandTimedTurnOnoftheOutputs. If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled at the same time. Output 1 and Output 2 soft start at a rate that is determined by the respective final output voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, thenthetwooutputsalsooperateindependently. 5-VVOUT1 (2V/div) 3.3-VVOUT2 (2V/div) T-Time-1ms/div Figure19.SEQPinFloating SoftStart Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft start interval, the TPS5428x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the internal 0.8 V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains atthereferencevoltage. NOTE: To avoid a disturbance in the output voltage during the stepping of the digital soft start, a minimum output capacitance of 50 m F is recommended. Also see Feedback Loop and Inductor-Capacitor (L-C) Filter Selection Once the filter and compensation components have been established, laboratory measurements of the physical design shouldbeperformedtoconfirmconverterstability. During the soft start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the OutputOverloadProtectionsection.)Thereisnopulseskippingifacurrentlimitpulseisnotdetected. DESIGNHINT If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 to support the desired regulation voltage by the time Soft Start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. See Operating Near Maximum Duty Cycleand Maximum Output Capacitance for related information. OutputVoltageRegulation Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (see Figure 20). Assuming the value of the upper voltage setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by Equation2. V REF R2 = R1´ V -V OUT REF (2) where • V istheinternal0.8-Vreferencevoltage REF TPS5428x 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 OUTPUT1 3 SW1 SW2 12 4 GND BP 11 R1 5 EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 R2 UDG-07011 Figure20.FeedbackNetworkforChannel1 DESIGNHINT There is a leakage current of up to 12 m A out of the SW pin when a single output of the TPS5428x is disabled. Keeping the series impedance of R1 + R2 less than 50 kΩ preventstheoutputfromfloatingabovethereferecevoltagewhilethecontrolleroutput isintheOFFstate. 16 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 FeedbackLoopandInductor-Capacitor(L-C)FilterSelection In the feedback signal path, the output voltage setting divider is followed by an internal g -type error amplifier M with a typical transconductance of 30 m S. An internal series connected R-C circuit from the g amplifier output to M ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to drivetheupperMOSFETswitch.AsimplifiedequivalentcircuitofthesignalcontrolpathisdepictedinFigure21. NOTE: Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow pulse width operation, especially at load currents less than 1 A. See SW Node RingingforfurtherinformationonreducingnoiseontheSWxnode. TPS5428x BOOT I -I COMP SLOPE x2 PWMto ErrorAmplifier I Switch SLOPE 0.8V + REF + I FB COMP Offset f(I ) DRAIN R COMP SW 11.5kW C COMP R C COMP COMP (kW) (pF) TPS54283 700 40 TPS54286 700 20 UDG-07012 Figure21.FeedbackLoopEquivalentCircuit A more conventional small signal equivalent block diagram is shown in Figure 22. Here, the full closed loop signal path is shown. Because the TPS5428x contains internal slope compensation and loop compensation components,theexternalL-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally selected first, and the compensation network is found afterwards. To find the appropriate L and C filter combination, the Output-to-Vc signal path plots (see the next section) of gain and phase are used along with otherdesigncriterialtoaidinfindingthecombinationsthatbestresultsinastablefeedbackloop. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 VIN V + C + VOUT VREF Modulator _ _ Filter Current Feedback Network Compensation Network Figure22.SmallSignalEquivalentBlockDiagram Inductor-Capacitor(L-C)Selection The following figures plot the TPS5428x Output-to-Vc gain and phase versus frequency for various duty cycles (10%, 30%, 50%, 70%, 90%) at three (200 mA, 400 mA, 600 mA) peak-to-peak ripple current levels. The loop response curve selected to compensate the loop is based on the duty cycle of the application and the ripple current in the inductor. Once the curve has been selected and the inductor value has been calculated, the output capacitor is found by calculating the L-C resonant frequency required to compensate the feedback loop. A brief examplefollowsthecurves. Note that the internal error amplifier compensation is optimized for output capacitors with an ESR zero frequency between20kHzand60kHz.Seethefollowingsectionsforfurtherdetails. GAINANDPHASE GAINANDPHASE vs vs FREQUENCY FREQUENCY 100 270 100 270 DutyCycle% DutyCycle% Gain Phase 225 Gain Phase 225 80 10 80 10 30 30 50 180 50 180 70 70 60 90 60 90 135 135 B ° B d - d ° ain- 40 90 hase ain- 40 90 ase- G P G h 45 45 P 20 20 0 0 0 0 -45 -45 -20 -90 -20 -90 100 1k 10k 100k 1M 100 1k 10k 100k 1M f-Frequency-Hz Figure23.TPS54283at200-mAp-pRippleCurrent Figure24.TPS54283at400-mAp-pRippleCurrent 18 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 GAINANDPHASE GAINANDPHASE vs vs FREQUENCY FREQUENCY 100 270 100 270 DutyCycle% 85 225 Gain Phase 225 80 10 30 50 180 70 180 70 60 90 135 55 135 dB -° dB °- ain- 40 90 hase -ain 40 90hase G P G P 45 25 45 20 Duty Cycle % 0 10 Gain Phase 0 10 0 30 -45 -5 50 -45 70 -20 -90 90 100 1k 10k 100k 1M -20 -90 f-Frequency-Hz 100 1 k 10 k 100 k 1 M f-Frequency-Hz Figure25.TPS54283at600-mAp-pRippleCurrent Figure26.TPS54286at200-mAp-pRippleCurrent GAINANDPHASE GAINANDPHASE vs vs FREQUENCY FREQUENCY 100 270 100 270 85 225 225 80 70 180 180 60 135 55 135 ain-dB 40 90 hase-° -aindB 40 90°-ase G P G h 45 25 45P 20 DutyCycle% Duty Cycle % Gain10Phase 0 10 Gain 1 0Phase 0 30 0 30 5700 -45 -5 50 -45 70 90 -20 -90 90 100 1k 10k 100k 1M -20 -90 f-Frequency-Hz 100 1 k 10 k 100 k 1 M f-Frequency-Hz Figure27.TPS54286at400-mAp-pRippleCurrent Figure28.TPS54286at600-mAp-pRippleCurrent MaximumOutputCapacitance With internal pulse-by-pulse current limiting and a fixed soft start time, there is a maximum output capacitance which may be used before startup problems begin to occur. If the output capacitance is large enough so that the device enters a current limit protection mode during startup, then there is a possibility that the output will never reach regulation. Instead, the TPS5428x will simply shut down and attempt a restart as if the output were short circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is givenbyEquation3: Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 R1 V (1+ ) ´T C = tSS I -V (1+ R1)(1- REF R2 S + 1 ) OUTmax V CLx REF R2 2´V ´L R REF IN LOAD (3) MinimumOutputCapacitance Ensure the value of capacitance selected for closed loop stability is compatible with the requirements of Soft Start. ModifyingTheFeedbackLoop Within the limits of the internal compensation, there is flexibility in the selection of the inductor and output capacitor values. A smaller inductor increases ripple current, and raises the resonant frequency, thereby increasing the required value of output capacitance. A smaller capacitor could also be used, increasing the resonant frequency, and increasing the overall loop bandwidth—perhaps at the expense of adequate phase margin. The internal compensation of the TPS54x8x is designed for capacitors with an ESR zero frequency between 20kHz and 60kHz. It is possible, with additional feedback compensation components, to use capacitors with higher or lower ESR zero frequencies. For either case, the components C1 and R3 (ref. Figure 29 ) are added to re-compensate the feedback loop for stability. In this configuration a low frequency pole is followed by a higher frequency zero. The placement of this pole-zero pair is dependent on the type of output capacitor used, and the desiredclosedloopfrequencyresponse. TPS5428x 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 OUTPUT1 3 SW1 SW2 12 C2 R1 4 GND BP 11 5 EN1 SEQ 10 C1 6 EN2 ILIM2 9 R2 7 FB1 FB2 8 R3 UDG-07013 Figure29.OptionalLoopCompensationComponents NOTE: Once the filter and compensation components have been established, laboratory measurements of the physical design should be performed to confirm converter stability. UsingHigh-ESROutputCapacitors If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability. To compensate, a small R-C series connected network is placed in parallel with the lower voltage setting divider resistor (Ref Figure 29). The values of the components are determined such that a pole is placed at the same frequency as the ESR zero and a new zero is placed at a frequency location conducive to good loop stability. 20 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 The value of the resistor is calculated using a ratio of impedances to match the ratio of ESR zero frequency to thedesiredzerofrequency. R2 R3= ææf ö ö ZERO(desired) çç ÷-1÷ çç f ÷ ÷ èè ESR(zero) ø ø (4) where • f istheESRzerofrequencyoftheoutputcapacitor ESR(zero) • f isthedesiredfrequencyofthezeroaddedtothefeedback.Thisfrequencyshouldbeplaced ZERO(desired) between20kHzand60kHztoensuregoodloopstability. ThevalueofthecapacitoriscalculatedinEquation5. 1 C1= 2p´R ´f EQ ESR(zero) (5) where: • R isanequivalentimpedancecreatedbytheparallelcombinationofthevoltagesettingdividerresistors(R1 EQ andR2)inserieswithR3. 1 R =R3+ EQ ææ 1 ö æ 1 öö çç ÷+ç ÷÷ R1 R2 èè ø è øø (6) UsingAllCeramicOutputCapacitors With low ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In this case, (Ref Figure 29) resistor R3 is set equal to 1/2 R2. This will lower the gain by 6dB, reduce the crossover frequency,andimprovephasemargin. The value of C1 is found by determining the frequency to place the low frequency pole. The minimum frequency to place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with the internal soft start. (Ref. Soft Start) The upper bound for the pole frequency is determined by the operating frequency of the converter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from Equation 7. Keep componenttolerancesinmindwhenselectingthedesiredpolefrequency. 1 C1= 2p´R ´f EQ POLE(desired) (7) where: • f isthedesiredpolefrequencybetween1kHzand3kHz(TPS54x83)or1kHzand6kHz POLE(desired) (TPS54x86). • R isanequivalentimpedancecreatedbytheparallelcombinationofthevoltagesettingdividerresistors(R1 EQ andR2)inserieswithR3. 1 R =R3+ EQ ææ 1 ö æ 1 öö çç ÷+ç ÷÷ R1 R2 èè ø è øø (8) If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage setting divider resistor(Ref.C2inEquation9). Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 1 R1 C2= ´ 1+ 2p´fC´R1 æ(R2´R3)ö ç ÷ ç(R2+R3)÷ è ø (9) where • f istheunitygaincrossoverfrequency(approximately50kHzformostdesignsfollowingtheseguidelines) C 22 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Example:TPS54286BuckConverterOperatingat12-VInput,3.3-VOutputand400-mAp-pRippleCurrent First, the steady state duty cycle is calculated. Assuming the rectifier diode has a voltage drop of 0.5 V, the duty cycleisapproximatedusingEquation10. V +V 3.3+0.5 OUT DIODE d= = = 30% V +V 12+0.5 IN DIODE (10) Thefilterinductoristhencalculated;seeEquation11. L= VIN-VOUT ´d´T =12-3.3´0.3´ 1 =10.9mH S DI 0.4 600000 L (11) A custom-designed inductor may be used for the application, or a standard value close to the calculated value may be used. For this example, a standard 10-m H inductor is used. Using Figure 27, find the 30% duty cycle curve. The 30% duty cycle curve has a down slope from low frequency and rises at approximately 6 kHz. This curve is the resonant frequency that must be compensated. Any frequency wthin an octave of the peak may be usedincalculatingthecapacitorvalue.Inthisexample,6kHzisused. 1 1 C= = =70mF L´(2´p´f )2 10´10-6´(2´3.14´6000)2 RES (12) A 68-m F capacitor may be used as a bulk capacitor, with 10-m F of ceramic bypass capacitance in parallel. To ensure the ESR zero does not significantly impact the loop response, the ESR of the bulk capacitor should be placedadecadeabovetheresonantfrequency. 1 1 R < = »40mW ESR 2´p´10´fRES´C 2´3.14´10´6000´68´(10)-6 (13) The resulting loop gain and phase are shown in Figure 30. Based on measurement, loop crossover is 45 kHz withaphasemarginof60degrees. GAINANDPHASE vs FREQUENCY 80 180 70 Phase 135 60 90 50 45 40 B ° d - -ain 30 0 hase G 20 P -45 10 -90 0 Gain -135 -10 -20 -180 100 1 k 10 k 100 k 1 M f-Frequency-Hz Figure30.ExampleLoopResult Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 BootstrapfortheN-ChannelMOSFET A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the MOSFETgateisderivedfromthevoltageonthiscapacitor. To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the SWnodetowardgroundandallowthebootstrapcapacitortocharge. Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge requirementoftheMOSFETbeingused. DESIGNHINT For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and 82nF. DESIGNHINT For 5-V input applications, connect PVDDx to BP directly. This connection bypasses the internal control circuit regulator and provides maximum voltage to the gate drive circuitry. In this configuration, shutdown mode IDD will be the same as quiescent SDN IDD . Q LightLoadOperation There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous converter is to operate in the discontinuous conduction mode (DCM) at an average load current less than one-half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of inputvoltage,outputvoltage,inductorvalue,andoperatingfrequency,asshowninEquation14. V -V 1 IN OUT I = ´ ´ d ´T DCM 2 L S (14) During discontinuous comduction mode operation the commanded pulse width may become narrower than the capability of the converter to resolve. To maintain the output voltage within regulation, skipping of switching pulses at light load conditions is a by-product of that mode. This condition may occur if the output capacitor is charged to a value greater than the output regulation voltage, and there is insufficient load to discharge the capacitor.Aby-productofpulseskippingisanincreaseinthepeak-to-peakoutputripplevoltage. 24 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 SWWaveform Skipping SWWaveform V =12V IN V =5V OUT V OUT Ripple RViOppUlTe Inductor Current SteadyState Inductor V =12V IN Current V =5V OUT Figure31.SteadyState Figure32.Skipping DESIGNHINT If additional output capacitance is required to reduce the output voltage ripple during DCM operation, be sure to recheck Feedback Loop and Inductor-Capacitor (L-C) FilterSelectionandMaximumOutputCapacitancesections. SWNodeRinging A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to decrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than 30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of design techniquesforreducingringingandnoise. SWNodeSnubber Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance and capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an R-Csnubbermaybeusedtodampentheringingandensureproperoperationoverthefullloadrange. DESIGNHINT A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 Ω) connectedfromSWtoGNDreducestheringingontheSWnode. BootstrapResistor A small resistor in series with the bootstrap capacitor reduces the turn-on time of the internal MOSFET, thereby reducingtherisingedgeringingoftheSWnode. DESIGNHINT Aresistorwithavaluebetween1Ω and 3Ω may be placed in series with the bootstrap capacitortoreduceringingontheSWnode. DESIGNHINT Placeholders for these components should be placed on the initial prototype PCBs in casetheyareneeded. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 OutputOverloadProtection In the event of an overcurrent during soft start on either output (such as starting into an output short), pulse-by-pulse current limiting and PWM frequency division (see below) are in effect for that output until the internal soft start timer ends. At the end of the soft start time, a UV condition is declared and a fault is declared. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This process ensures that both outputs discharge to GND in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup mode timeout before attempting to restart. "Frequency Division" means if an overcurrent pulse is detected, six clock cycles are skipped before a next PWM pulse is initiated, effectively dividing the operating frequency by six and preventing excessive current buildupintheinductor. In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (that follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the otherisnotloaded.Theconverterthenentersahiccupmodetimeoutbeforeattemptingtorestart. The overcurrent threshold for Output 1 is set nominally at 3.0 A. The overcurrent level of Output 2 is determined by the state of the ILIM2 pin. The ILIM setting of Output 2 is not latched in place and may be changed during operationoftheconverter. Table2.CurrentLimitThresholdAdjustmentfor Output2 ILIM2Connection OCPThresholdforOutput2 BPorGND 1.5Anominalsetting (floating) 3.0Anominalsetting DESIGNHINT The overcurrent protection threshold refers to the peak current in the internal switch. Be sure to add one-half of the peak inductor ripple current to the dc load current in determininghowclosetheactualoperatingpointistotheOCPthreshold. OperatingNearMaximumDutyCycle If the TPS5428x operates at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load current transient), then there is a possibility that the output voltage will fall from regulation and trip the output UV comparator. If this should occur, the TPS5428x protection circuitry will declareafaultandenterashutdown-and-restartcycle. DESIGNHINT Ensure that under ALL conditions of line and load regulation, there is sufficient duty cycletomaintainoutputvoltageregulation. Theoperatingdutycycleundercontinuousconduction(neglectinglosses)isapproximatedusingEquation15. VOUT +VDIODE d = VIN +VDIODE (15) where • V isthevoltagedropoftherectifierdiode DIODE DualSupplyOperation It is possible to operate a TPS5428x from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This level requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 supplies energy to the output. In addition, Output 1 must be held in the disabled state (EN1 high) until there is sufficient voltageonPVDD1tosupportOutput1inregulation.(SeetheOperatingNearMaximumDutyCyclesection.) 26 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Thepreferredsequenceofeventsis: 1. PVDD2risesabovetheinputUVLOvoltage 2. PVDD1riseswithOutput1disableduntilPVDD1risesaboveleveltosupportOutput1regulation. Withthesetwoconditionssatisfied,thereisnorestrictiononPVDD2tobegreaterthan,orlessthanPVDD1. DESIGNHINT An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough periodoftimetoensurethatPVDD1cansupportOutput1load. CascadingSupplyOperation It is possible to source PVDD1 from Output 2 as depicted in Figure 33 and Figure 34. This configuration may be preferrediftheinputvoltageishigh,relativetothevoltageonOutput1. V IN TPS54283 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 OUTPUT1 OUTPUT2 3 SW1 SW2 12 4 GND BP 11 5 EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 UDG-07015 Figure33.SchematicShowingCascadingPVDD1fromOutput2 Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 PVDD2 Output2 PVDD1 Output1 T-Time Figure34.WaveformsResultingfromCascadingPVDD1fromOutput2 Inthisconfiguration,thefollowingconditionsmustbemaintained: 1. Output2mustbeofavoltagehighenoughtomaintainregulationofOutput1underallloadconditions. 2. The sum of the current drawn by Output 2 load plus the current into PVDD1 must be less than the overload protectioncurrentlevelofOutput2. 3. The method of output sequencing must be such that the voltage on Output 2 is sufficient to support Output 1 beforeOutput1isenabled.Thisrequrementmaybeaccomplishedby: a. adelayoftheenablefunction b. selectingsequentialsequencingofOutput1startingafterOutput2isinregulation MultiphaseOperation The TPS5428x is not designed to operate as a two-phase single-output voltage converter. See http://www.power.ti.comforappropriatedeviceselection. BypassandFIltering As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise immunityoftheconverter,ceramicbypasscapacitorsmustbeplacedasclosetothepackageaspossible. 1. PVDD1toGND:Usea10-m Fceramiccapacitor 2. PVDD2toGND:Usea10-m Fceramiccapacitor 3. BPtoGND:Usea4.7-m Fto10-m Fceramiccapacitor Over-TemperatureProtectionandJunctionTemperatureRise Theover-temperaturethermalprotectionlimitsthe maximum power to be dissipated at a given operating ambient temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is limited by the maximum allowable junction operating temperature. The device junction temperature is a function of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature should reach the thermal shutdown level, the TPS5428x shuts off both PWMs and remains in this state until the dietemperaturedropsbelowthehysteresisvalue,atwhichtimethedevicerestarts. The first step to determine the device junction temperature is to calculate the power dissipation. The power dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by each MOSFET is composed of conduction losses and output (switching) losses incurred while driving the externalrectifierdiode.Tofindtheconductionloss,firstfindtheRMScurrentthroughtheupperswitchMOSFET. 28 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 IRMS(outputx) = D´æçç(IOUTPUTx)2 +æçç(DIOU1TP2UTx)2 ö÷÷ö÷÷ ç ÷ è è øø (16) where • Disthedutycycle • I istheDCoutputcurrent OUTPUTx • ΔI isthepeakripplecurrentintheinductorforOutputx OUTPUTx Noticetheimpactoftheoperatingdutycycleontheresult. MultiplyingtheresultbytheR oftheMOSFETgivestheconductionloss. DS(on) P =I 2´R D(cond) RMS(outputx) DS(on) (17) Theswitchinglossisapproximatedby: 2 (V ) ´C ´f IN J S P = D(SW) 2 (18) where • whereC istheparallelcapacitanceoftherectifierdiodeandsnubber(ifany) J • f istheswitchingfrequency S The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal regulator. P =P +P +P +P +V ´Iq D D(cond)output1 D(SW)output1 D(cond)output2 D(SW)output2 IN (19) Thetemperatureriseofthedevicejunctiondependsonthethermalimpedancefromjunctiontothemountingpad (See the Package Dissipation Ratings table), plus the thermal impedance from the thermal pad to ambient. The thermal impedance from the thermal pad to ambient depends on the PCB layout (PowerPAD interface to the PCB,theexposedpadarea)andairflow(ifany).SeethePCBLayoutGuidelines,AdditionalReferencessection. TheoperatingjunctiontemperatureisshowninEquation20. T =T +P ´(q +q ) J A D TH(pkg) TH(pad-amb) (20) PowerDerating The TPS5428x delivers full current at ambient temperatures up to +85(cid:176) C if the thermal impedance from the thermal pad to ambient is sufficiently low enough to maintain the junction temperature below the thermal shutdown level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 35 illustrates the power derating for elevated ambient temperature under various airflow conditions. Note that these curves assume that the PowerPAD is properlysolderedtotherecommendedthermalpad.(SeetheReferencessectionforfurtherinformation.) Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 POWERDISSIPATION vs AMBIENTTEMPERATURE 1.8 LFM=250 1.6 LFM=500 1.4 W LFM=0 n- 1.2 o ati LFM=150 p 1.0 si s Di 0.8 r e w o P 0.6 - D LFM P 0.4 0 150 0.2 250 500 0 0 20 40 60 80 100 120 140 T -AmbientTemperature-°C A Figure35.PowerDeratingCurves 30 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 PowerPADPackage The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package.(SeetheAdditionalReferencessection.) PCBLayoutGuidelines The layout guidelines presented here are illustrated in the printed circuit board layout example given in Figure 36 andFigure37. • The PowerPAD must be connected to a low current (signal) ground plane having a large copper surface area to dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal transfer of heatawayfromtheIC. • ConnecttheGNDpintothePowerPADthrougha10-mil(.010in,or0.0254mm)widetrace. • PlacetheceramicinputcapacitorsclosetoPVDD1andPVDD2;connectusingshort,widetraces. • Maintainatightloopof wide traces from SW1 or SW2 through the switch node, inductor, output capacitor and rectifierdiode.Avoidusingviasinthisloop. • Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the power pathaspossible.Placementdirectlyunderthediodeandtheswitchnodeisrecommended. • LocatethebootstrapcapacitorclosetotheBOOTpintominimizethegatedriveloop. • Locate voltage setting resistors and any feedback components over the ground plane and away from the switchnodeandtherectifierdiodetoinputcapacitorgroundconnection. • Locatesnubbercomponents(ifused)closetotherectifierdiodewithminimallooparea. • LocatetheBPbypasscapacitorveryclosetotheIC;aminimalloopareaisrecommended. • Locate the output ceramic capacitor close to the inductor output terminal between the inductor and any electrolyticcapacitors,ifused. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 L2 VOUT2 C14 R8 C13 D2 C18 C19 C17 R6 GND C11 C12 C15 R7 CR196 U1 VIN 1 C8 R4 C6 R2 C1 C10 D1 R5 GND GND C9 C4 C3 C5 C7 R3 VOUT1 L1 Figure36.TopLayerCopperLayoutandComponentPlacement Figure37.BottomLayerCopperLayout 32 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 DESIGN EXAMPLES Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual non-synchronous buck regulator using the TPS54283 converter. Design Example List of Materials and Table 4, DefinitionofSymbolsisfoundattheendofthissection. PARAMETER NOTESANDCONDITIONS MIN NOM MAX UNIT INPUTCHARACTERISTICS VIN Inputvoltage 6.9 12.0 13.2 V IIN Inputcurrent VIN=nom,IOUT=max 1.6 2.0 A Noloadinputcurrent VIN=nom,IOUT=0A 12 20 mA OUTPUTCHARACTERISTICS VOUT1 Outputvoltage1 VIN=nom,IOUT=nom 4.8 5.0 5.2 V VOUT2 Outputvoltage2 VIN=nom,IOUT=nom 3.2 3.3 3.4 Lineregulation VIN=mintomax 1% Loadregulation IOUT=mintomax 1% VOUT(ripple Outputvoltageripple VIN=nom,IOUT=max 50 mVPP ) IOUT1 Outputcurrent1 VIN=mintomax 0 2.0 IOUT2 Outputcurrent2 VIN=mintomax 0 2.0 IOCP1 O1utputovercurrentchannel VIN=nom,VOUT=VOUT1=5% 2.4 3 3.5 A Outputovercurrentchannel IOCP2 2 VIN=nom,VOUT=VOUT2=5% 2.4 3 3.5 Tfrroamnsloieandtrtreasnpsoiennset ΔVOUT ΔIOUT=1A@3A/m s 200 mV Transientresponsesettling 1 ms time SYSTEMCHARACTERISTICS fSW Switchingfrequency 250 310 370 kHz h Fullloadefficiency 85% TJ Orapnegreatingtemperature 0 25 60 (cid:176)C + + + Figure38.DesignExampleSchematic Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Design Procedure DutyCycleEstimation ThefirststepistoestimatethedutycycleofeachswitchingFET. V +V D » OUT FD max V +V IN(min) FD (21) V +V D » OUT FD min V +V IN(max) FD (22) Using an assumed forward drop of 0.5 V for a schottky rectifier diode, the Channel 1 duty cycle is approximately 40.1% (minimum) to 48.7% (maximum) while the Channel 2 duty cycle is approximately 27.7% (minimum) to 32.2%(maximum). InductorSelection The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current far enoughfromtheminimumovercurrenttripleveltoensurereliableoperation. For both Channel 1 and Channel 2, the maximum inductor ripple current is 600 mA. The inductor size is estimatedinEquation23. VIN(max) -VOUT 1 Lmin » I ´Dmin´ f LRIP(max) SW (23) Theinductorvaluesare • L1=18.3m H • L2=15.3m H Thenexthigherstandardinductorvalueof22m Hisusedforbothinductors. Theresultingripplecurrentsare: VIN(max) -VOUT 1 I » ´D ´ RIPPLE min L f SW (24) Peak-to-peakripplecurrentsof0.498Aand0.416AareestimatedforChannel1andChannel2respectively. TheRMScurrentthroughaninductorisapproximatedbyEquation25. I = (I )2 + 1 (I )2 L(rms) L(avg) 12 RIPPLE (25) andisapproximately2.0Aforbothchannels. Thepeakinductorcurrentisfoundusing: 1 I »I + I L(peak) OUT(max) 2 RIPPLE (26) An inductor with a minimum RMS current rating of 2.0 A and minimum saturation current rating of 2.25 A is required.ACoilcraftMSS1278-223ML22-m H,6.8-Ainductorisselected. RectifierDiodeSelection A schottky diode is selected as a rectifier diode for its low forward voltage drop. Allowing 20% over VIN for ringingontheswitchnode,therequiredminimumreversebreak-downvoltageoftherectifierdiodeis: 34 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 V ³1.2´V (BR)R(min) IN (27) Thediodemusthavereversebreakdownvoltagegreaterthan15.8V,thereforea20-Vdeviceisused. TheaveragecurrentintherectifierdiodeisestimatedbyEquation28. I »I ´(1-D) D(avg) OUT(max) (28) For this design, 1.2-A (average) and 2.25 A (peak) is estimated for Channel 1 and 1.5-A (average) and 2.21-A (peak)forChannel2. An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forward voltagedropof0.4Vat2A. ThepowerdissipationinthediodeisestimatedbyEquation29. P » V ´I D(max) FM D(avg) (29) Forthisdesign,thefullloadpowerdissipationisestimatedtobe480mWinD1,and580mWinD2. OutputCapacitorSelection The TPS54283's internal compensation limits the selection of the output capacitors. From Figure 24, the internal compensationhasadoublezeroresonanceatabout3kHz.TheoutputcapacitorisselectedbyEquation30. 1 C = OUT 4´p2´(f )2´L RES (30) SolvingforC using OUT • f =3kHz RES • L=22m H The resulting is C = 128 m F. The output ripple voltage of the converter is composed of the ripple voltage OUT across the output capacitance and the ripple voltage across the ESR of the output capacitor. To find the maximum ESR allowable to meet the output ripple requirements the total ripple is partitioned, and the equation manipulatedtofindtheESR. VRIPPLE(tot) -VRIPPLE(cap) VRIPPLE(tot) D ESR = = - (max) I I f ´C RIPPLE RIPPLE S OUT (31) Based on 128 m F of capacitance, 300-kHz switching frequency and 50-mV ripple voltage plus rounding up the ripple current to 0.5 A, and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving a maximumallowableESRof87mΩ. To meet the ripple voltage requirements, a low-cost 100-m F electrolytic capacitor with 400 mΩ ESR (C5, C17) and two 10-m F ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-mΩ ESR are selected. From the datasheets for the ceramic capacitors, the parallel combination provides an impedance of 28 mΩ @ 300 kHz for 14mVofripple. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 VoltageSetting The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 kΩ and 50 kΩ to maintainabalancebetweenpowerdissipationandnoisesensitivity.Forthisdesign,20kΩisselected. Thelowerresistors,R4andR7arefoundusingthefollowingequations. V ´R2 R4= FB V -V OUT1 FB (32) V ´R9 R7= FB V -V OUT2 FB (33) • R2=R9=20kΩ • V =0.80V FB • R4=3.80kΩ(3.83kΩstandardvalueisused) • R7=6.40kΩ(6.34kΩstandardvalueisused) CompensationCapacitors CheckingtheESRzerooftheoutputcapacitors: 1 f = ESR(zero) 2´p´C´ESR (34) • C=100m F • ESR=400mΩ • ESR =3980Hz (zero) Since the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4 andR7tocompensatefortheelectrolyticcapacitors'ESRandaddazeroabout40kHz. R4 R5= ææf ö ö ZERO(desired) çç ÷-1÷ çç f ÷ ÷ èè ESR(zero) ø ø (35) • f =4kHz ESR(zero) • f =40kHz ESR(desired) • R4=3.83kΩ • R5=424Ω(422Ωselected) • R7=6.34kΩ • R8=702Ω(698Ωselected) 1 R =R5+ EQ ææ 1 ö æ 1 öö çç ÷+ç ÷÷ R2 R4 èè ø è øø (36) • R2=R9=20kΩ • REQ1=3.63kΩ • REQ2=5.51kΩ 1 C8= 2´p´R ´f EQ ESR(zero) (37) • C8=10.9nF(10nFselected) • C15=7.22nF(6800pFselected) 36 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 InputCapacitorSelection The TPS54283 datasheet recommends a minimum 10-m F ceramic input capacitor on each PVDD pin. These capacitor must be capable of handling the RMS ripple current of the converter. The RMS current in the input capacitorsisestimatedbyEquation38. IRMS(outputx) = D´æçç(IOUTPUTx)2 +æçç(DIOU1TP2UTx)2 ö÷÷ö÷÷ ç ÷ è è øø (38) • I =0.43A RMS(CIN) One 1210 10-m F, 25 V, X5R ceramic capacitor with 2-mΩ ESR and a 2-A RMS current rating are selected for each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensurethecapacitorsmaintainssufficientcapacitanceattheworkingvoltage. BootStrapCapacitor To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 33-nF bootstrapcapacitorisused. ILIM Current limit must be set above the peak inductor current I . Comparing I to the available minimum L(peak) L(peak) currentlimits,ILIMisleftfloatingforthehighestcurrentlimitlevel. SEQ The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied together, the two supplies start-up ratiometrically. Alternatively, SEQ could be connected to BP or GND to providesequentialstart-up. PowerDissipation The power dissipation in the TPS54283 is composed of FET conduction losses, switching losses and internal regulatorlosses.TheRMSFETcurrentisfoundusingEquation39. æ ( )2 ö ç 2 DI(Outputx) ÷ I = D´ç(I ) + ÷ RMS(Outputx) OUTPUT 12 ç ÷ ç ÷ è ø (39) Thisresultsin1.05-ARMSforChannel1and0.87-ARMSforChannel2. Conductionlossesareestimatedby: ( )2 P =R ´ I CON DS(on) QSW(rms) (40) Conductionlossesof198mWand136mWareestimatedforChannel1andChannel2respectively. TheswitchinglossesareestimatedinEquation41. ( )2 V ´(C +C )´f IN(max) DJ OSS SW P » SW 2 (41) From the data sheet of the MBRS320, the junction capacitance is 658 pF. Since this is large compared to the output capacitance of the TPS54x8x the FET capacitance is neglected, leaving switching losses of 17 mW for eachchannel. TheregulatorlossesareestimatedinEquation42. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 ( ) P »I ´V +I ´ V -V REG DD IN(max) BP IN(max) BP (42) WithnoexternalloadonBP(I =0)theregulatorpowerdissipationis66mW. BP Total power dissipation in the device is the sum of conduction and switching for both channels plus regulator losses. ThetotalpowerdissipationisP =0.198+0.136+0.017+0.017+.066=434mW. DISS Design Example Test Results ThefollowingresultsarefromtheTPS54283-001EVM. VIN = 12 V SW 3.3 V SW 5 V t − Time − 40 ns/div Figure39.SwitchingNodeWaveforms 100 100 V =9.6V IN 90 90 80 VIN=9.6V 80 V =12.0V 70 70 IN V =12.0V IN % % V =13.2V - 60 - 60 IN y y c c n n e 50 V =13.2V e 50 ci IN ci Effi 40 Effi 40 - - h V =5.0V h V =3.3V 30 OUT 30 OUT V (V) V (V) 20 IN 20 IN 9.6 9.6 12.0 12.0 10 10 13.2 13.2 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 I -LoadCurrent-A I -LoadCurrent-A LOAD LOAD Figure40.5.0-VOutputEfficiencyvs.LoadCurrent Figure41.3.3-VOutputEfficiencyvs.LoadCurrent 38 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 1.005 1.005 1.004 1.004 V V d)- 1.003 d)- 1.003 e e ormaliz 11..000012 VIN=12.0V VIN=13.2V ormaliz 11..000012 VAollltIangpeust N N ( ( e e g 1.000 g 1.000 a a olt olt V 0.999 V 0.999 Output 0.998 VIN=9.6V VOUT=5.0V Output 0.998 -OUT0.997 VIN9(.V6) -OUT0.997 V 0.996 12.0 V 0.996 13.2 0.995 0.995 0 0.4 0.8 1.2 1.6 2.0 0 0.4 0.8 1.2 1.6 2.0 I -LoadCurrent-A I -LoadCurrent-A OUT OUT Figure42.5.0-VOutputVoltagevs.LoadCurrent Figure43.3.3-VOutputVoltagevs.LoadCurrent 80 180 60 135 40 90 20 45 B ° d - ain- 0 0 hase G P -20 -45 -40 -90 Gain Phase -60 5.0V -135 3.3V -80 -180 1k 10k 100k 300k f-Frequency-Hz Figure44.Example1LoopResponse Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Table3.DesignExampleListofMaterials REFERENCE QTY VALUE DESCRIPTION SIZE PARTNUMBER MANUFACTURER DESIGNATOR 1 C1 100m F Capacitor,Aluminum,25V,(cid:3) 20% E-can EEEFC1E101P Panasonic 2 C10,C11 10m F Capacitor,Ceramic,25V,X5R20% 1210 C3216X5R1E106M TDK 1 C12 4.7m F Capacitor,Ceramic,10V,X5R20% 0805 Std Std 2 C14,C16 470pF Capacitor,Ceramic,25V,X7R,20% 0603 Std Std 1 C15 6.8nF Capacitor,Ceramic,25V,X7R,20% 0603 Std Std 1 C17,C5 100m F Capacitor,Aluminum,10V,20%,FC F-can EEEFC1A101P Panasonic Series 4 C3,C4,C18,C19 10m F Capacitor,Ceramic,6.3V,X5R20% 0805 C2012X5R0J106M TDK 1 C8 10nF Capacitor,Ceramic,25V,X7R,20% 0603 Std Std 2 C9,C13 0.033m F Capacitor,Ceramic,25V,X7R,20% 0603 Std Std 2 D1,D2 MBRS320 Diode,Schottky,3-A,30-V SMC MBRS330T3 OnSemi 2 L1,L2 22m H Inductor,Power,6.8A,0.038Ω 0.484x MSS1278-153ML Coilcraft 0.484 2 R2,R9 20kΩ Resistor,Chip,1/16W,1% 0603 Std Std 1 R5 422Ω Resistor,Chip,1/16W,1% 0603 Std Std 2 R6,R10 10Ω Resistor,Chip,1/16W,5% 0603 Std Std 1 R8 698Ω Resistor,Chip,1/16W,1% 0603 Std Std 1 R4 3.83kΩ Resistor,Chip,1/16W,1% 0603 Std Std 1 R7 6.34kΩ Resistor,Chip,1/16W,1% 0603 Std Std 1 U1 TPS54283DC-DCSwitchingConverter HTSSOP TPS54283PWP TI w/FET -14 40 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Table4.DefinitionofSymbols C Averagejunctioncapacitanceoftherectifierdiodefrom0VtoVIN(max) DJ C AverageoutputcapacitanceoftheswitchingMOSFETfrom0VtoVIN(max) OSS C OutputCapacitor OUT D Maximumsteadystateoperatingdutycycle (max) D Minimumsteadystateoperatingdutycycle (min) ESR MaximumallowableoutputcapacitorESR (max) f Switchingfrequency SW I OutputCurrentofBPregulatorduetoexternalloads BP I SwitchingquiescentcurrentwithnoloadonBP DD I Averagediodeconductioncurrent D(avg) I Peakdiodeconductioncurrent D(peak) I Averageinputcurrent IN(avg) I Rootmeansquared(RMS)inputcurrent IN(rms) I Averageinductorcurrent L(avg) I Rootmeansquared(RMS)inductorcurrent L(rms) I Peakcurrentininductor L(peak) I Maximumallowableinductorripplecurrent LRIP(max) L Minimuminductorvaluetomaintaindesiredripplecurrent (min) I Maximumdesignedoutputcurrent OUT(max) I Rootmeansquared(RMS)currentthroughtheinputcapacitor RMS(cin) I Inductorpeaktopeakripplecurrent RIPPLE I RootmeansquaredcurrentthroughtheswitchingMOSFET QSW(rms) P PowerlossduetoconductionthroughswitchingMOSFET CON P Maximumpowerdissipationindiode D(max) R DraintosourceresistanceoftheswitchingMOSFETwhen“ON” DS(on) P Powerlossduetoswitching SW P Powerlossduetotheinternalregulator REG V OutputVoltageofBPregulator BP V Minimumreversebreakdownvoltageratingforrectifierdiode (BR)R(min) V Regulatedfeedbackvoltage FB V Forwardvoltagedropacrossrectifierdiode FD V Powerstageinputvoltage IN V Regulatedoutputvoltage OUT V PeaktoPeakripplevoltageduetoidealcapacitor(ESR=0(cid:3) ) RIPPLE(cap) V Maximumallowablepeaktopeakoutputripplevoltage RIPPLE(tot) Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Additional Design Examples Example2:24-Vto12-Vand24-Vto5-V For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switch node and a 30 V schottky diode is selected. A higher resistance feedback network is chosen for the 12 V output toreducethefeedbackcurrent. + + Figure45.24-Vto12-Vand24-Vto5-VUsingtheTPS54283 VIN = 24 V VIN = 24 V IOUT = 2 A IOUT = 2 A VOUT VOUT (5 V/div) (5 V/div) T − Time − 10 ns / div T − Time − 10 ns / div Figure46.SwitchNodeRingingWithoutSnubberand Figure47.SwitchNodeRingeingWithSnubberand BoostResistor BoostResistor 42 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 90 80 V =12V 70 OUT % V =5V - 60 OUT y c n e 50 ci Effi 40 - V =24V h IN 30 V (V) OUT 20 5 12 10 0 0 0.5 1.0 1.5 2.0 2.5 I -LoadCurrent-A OUT Figure48.Efficiencyvs.LoadCurrent Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 Example3:5-Vto3.3Vand5-Vto1.2V For a low input voltage application, the TPS54286 is selected for reduced size and all ceramic output capacitors are used. 22-m F input capacitors are selected to reduce input ripple and lead capacitors are placed in the feedbacktoboostphasemargin. Figure49.5-Vto3.3Vand5-Vto1.2V 100 80 180 V =1.2V 90 60 OUT 135 80 40 90 70 V =3.3V OUT 20 45 % - 60 VOUT=1.2V B ° y d - Efficienc 4500 Gain- -200 -045Phase - V =5.0V h IN 30 -40 -90 V (V) 20 OUT Gain Phase 1.2 -60 WIthLead -135 3.3 WithoutLead 10 -80 -180 1k 10k 100k 300k 0 f-Frequency-Hz 0 0.5 1.0 1.5 2.0 2.5 I -LoadCurrent-A OUT Figure50.Efficiencyvs.LoadCurrent Figure51.Example3LoopResponse 44 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54283TPS54286

TPS54283,, TPS54286 www.ti.com SLUS749C–JULY2007–REVISEDOCTOBER2007 ADDITIONAL REFERENCES Related Devices ThefollowingpartshavecharacteristicssimilartotheTPS54283/6andmaybeofinterest. Table5.DevicesRelatedtotheTPS54283andTPS54286 TILITERATURE DEVICE DESCRIPTION NUMBER SLUS642 TPS40222 5-VInput,1.6-ANon-SynchronousBuckConverter TPS54383/ SLUS774 3-ADualNon-SynchronousConverterwithIntegratedHigh-SideMOSFET TPS54386 References These references, design tools and links to additional references, including design software, may be found at http:www.power.ti.com Table6.References TILITERATURE DESCRIPTION NUMBER SLMA002 PowerPADThermallyEnhancedPackageApplicationReport SLMA004 PowerPAD™MadeEasy SLUP206 UnderTheHoodOfLowVoltageDC/DCConverters.SEM1500Topic5,2002SeminarSeries SLVA057 UnderstandingBuckPowerStagesinSwitchmodePowerSupplies SLUP173 DesigningStableControlLoops.SEM1400,2001SeminarSeries Package Outline and Recommended PCB Footprint The following pages outline the mechanical dimensions of the 14-Pin PWP package and provide recommendationsforPCBlayout. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):TPS54283TPS54286

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) HPA00442PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54286 & no Sb/Br) TPS54283PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54283 & no Sb/Br) TPS54283PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54283 & no Sb/Br) TPS54286PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54286 & no Sb/Br) TPS54286PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54286 & no Sb/Br) TPS54286PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54286 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54283PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS54286PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54283PWPR HTSSOP PWP 14 2000 350.0 350.0 43.0 TPS54286PWPR HTSSOP PWP 14 2000 350.0 350.0 43.0 PackMaterials-Page2

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