Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 TPS54233 2A, 28V Input, Step Down DC/DC Converter With Eco-mode™ 1 Features 3 Description • 3.5Vto28VInputVoltageRange The TPS54233 is a 28 V, 2 A non-synchronous buck 1 converter that integrates a low R high side • AdjustableOutputVoltageDownto0.8V DS(on) MOSFET. To increase efficiency at light loads, a • Integrated80mΩ HighSideMOSFETSupports pulse skipping Eco-mode™ feature is automatically upto2AContinuousOutputCurrent activated. Furthermore, the 1 μA shutdown supply • HighEfficiencyatLightLoadswithaPulse current allows the device to be used in battery powered applications. Current mode control with SkippingEco-mode™ internal slope compensation simplifies the external • Fixed300kHzSwitchingFrequency compensation calculations and reduces component • Typical1μAShutdownQuiescentCurrent count while allowing the use of ceramic output • AdjustableSlowStartLimitsInrushCurrents capacitors. A resistor divider programs the Hysteresis of the input under-voltage lockout. An overvoltage • ProgrammableUVLOThreshold transient protection circuit limits voltage overshoots • OvervoltageTransientProtection during startup and transient conditions. A cycle by • CyclebyCycleCurrentLimit,FrequencyFold cycle current limit scheme, frequency fold back and BackandThermalShutdownProtection thermal shutdown protect the device and the load in the event of an overload condition. The TPS54233 is • AvailableinEasy-to-UseSOIC8Package available in an 8-pin SOIC package that has been • Supportedby WEBENCH®SoftwareTool internallyoptimizedtoimprovethermalperformance. (www.TI.com/WEBENCH) DeviceInformation(1) 2 Applications PARTNUMBER PACKAGE BODYSIZE(NOM) • ConsumerApplicationssuchasSet-TopBoxes, TPS54233 SOIC(8) 4.90mmx3.90mm CPEEquipment,LCDDisplays,Peripherals,and (1) For all available packages, see the orderable addendum at BatteryChargers theendofthedatasheet. • IndustrialandCarAudioPowerSupplies • 5V,12Vand24VDistributedPowerSystems 4 Simplified Schematic Ren1 Efficiency EN VIN VIN Ren2 C 100 I V = 3.3 V TPS54233 95 O VIN= 8 V VIN= 12 V V = 15 V C IN BOOT BOOT 90 L O PH VOUT 85 % CSSOMP D1 CO R5 cy - 80 VIN= 18 V n e CSS C7 C6 Effici 75 VSENSE 70 R3 GND R6 65 60 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 IO- Output Current -A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................11 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 12 3 Description............................................................. 1 9.1 ApplicationInformation............................................12 4 SimplifiedSchematic............................................. 1 9.2 TypicalApplication .................................................12 5 RevisionHistory..................................................... 2 10 PowerSupplyRecommendations..................... 22 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 22 11.1 LayoutGuidelines.................................................22 7 Specifications......................................................... 4 11.2 LayoutExample....................................................22 7.1 AbsoluteMaximumRatings .....................................4 11.3 EstimatedCircuitArea..........................................23 7.2 ESDRatings..............................................................4 11.4 ElectromagneticInterference(EMI) 7.3 RecommendedOperatingConditions.......................4 Considerations.........................................................23 7.4 ThermalInformation..................................................4 12 DeviceandDocumentationSupport................. 24 7.5 ElectricalCharacteristics...........................................5 12.1 DeviceSupport......................................................24 7.6 SwitchingCharacteristics..........................................5 12.2 Trademarks...........................................................24 7.7 TypicalCharacteristics..............................................6 12.3 ElectrostaticDischargeCaution............................24 8 DetailedDescription.............................................. 8 12.4 Glossary................................................................24 8.1 Overview...................................................................8 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.........................................8 Information........................................................... 24 8.3 FeatureDescription...................................................9 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(February2011)toRevisionC Page • RemovedSwift™fromthedatasheettitle............................................................................................................................. 1 • AddedESDRatingtable,ThermalInformationtable,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,DeviceandDocumentation Supportsection,andMechanical,Packagingsections. ........................................................................................................ 1 • DeletedFeaturesItem:ForSWIFT™Documentation,SeetheTIWebsiteatwww.ti.com/swift........................................... 1 • ChangedFeaturesitem:SupportedbySwitcherPro™To:SupportedbyWEBENCH®........................................................ 1 • ChangedR To:R5,R ToR6,C ToC6,andC ToC7intheSimplifiedSchematic ..................................................... 1 O1 O2 1 2 • ChangedSwitcherPro™SoftwaretoolTo:WEBENCHSoftwaretoolintheCurrentModeCompensationDesign section.................................................................................................................................................................................. 10 • ChangedR To:R5,R ToR6,C ToC6,andC ToC7intheTable1 ........................................................................ 10 O1 O2 1 2 • ChangedtheOutputVoltageSetPointsection.UpdatedtheparagraphfollowingEquation5........................................... 13 ChangesfromRevisionA(March2010)toRevisionB Page • Figure14,ChangedV =18Vonthetop(blue)curveTo:V =8V................................................................................. 20 IN IN ChangesfromOriginal(October2008)toRevisionA Page • ChangedtheAbsoluteMaximumRatings(1)table,InputVoltage-ENpinmaxvalueFrom:5Vto6V................................. 4 • AddedAtabletotheDescription-withtext"Foradditionaldesignneeds,see.."............................................................... 12 2 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 6 Pin Configuration and Functions DPackage TopView BOOT 1 8 PH VIN 2 7 GND EN 3 6 COMP SS 4 5 VSENSE PinFunctions PIN DESCRIPTION NAME NO. A0.1μFbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitorfallsbelowthe BOOT 1 minimumrequirement,thehigh-sideMOSFETisforcedtoswitchoffuntilthecapacitorisrefreshed. VIN 2 Inputsupplyvoltage,3.5Vto28V. Enablepin.Pullbelow1.25Vtodisable.Floattoenable.Programmingtheinputundervoltagelockoutwithtwo EN 3 resistorsisrecommended. SS 4 Slowstartpin.Anexternalcapacitorconnectedtothispinsetstheoutputrisetime. VSENSE 5 Invertingnodeofthegmerroramplifier. COMP 6 Erroramplifieroutput,andinputtothePWMcomparator.Connectfrequencycompensationcomponentstothispin. GND 7 Ground. PH 8 Thesourceoftheinternalhigh-sidepowerMOSFET. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VIN –0.3 30 EN –0.3 6 BOOT 38 InputVoltage V VSENSE –0.3 3 COMP –0.3 3 SS –0.3 3 BOOT-PH 8 OutputVoltage PH –0.6 30 V PH(10nstransientfromgroundtonegativepeak) –5 EN 100 μA BOOT 100 mA SourceCurrent VSENSE 10 μA PH 6 A VIN 6 A SinkCurrent COMP 100 μA SS 200 OperatingJunctionTemperature –40 150 °C StorageTemperature –65 150 °C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT OperatingInputVoltageon(VINpin) 3.5 28 V Operatingjunctiontemperature,T –40 150 °C J 7.4 Thermal Information D THERMALMETRIC(1) UNIT 8PINS R Junction-to-ambientthermalresistance 116.7 θJA R Junction-to-case(top)thermalresistance 62.4 θJC(top) R Junction-to-boardthermalresistance 57.0 θJB °C/W ψ Junction-to-topcharacterizationparameter 14.5 JT ψ Junction-to-boardcharacterizationparameter 56.5 JB R Junction-to-case(bottom)thermalresistance N/A θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 4 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 7.5 Electrical Characteristics T =–40°Cto150°C,VIN=3.5Vto28V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Internalundervoltagelockoutthreshold RisingandFalling 3.5 V Shutdownsupplycurrent EN=0V,VIN=12V,–40°Cto85°C 1 4 μA Operating–nonswitchingsupplycurrent VSENSE=0.85V 75 110 μA ENABLEANDUVLO(ENPIN) Enablethreshold RisingandFalling 1.25 1.35 V Inputcurrent Enablethreshold–50mV -1 μA Inputcurrent Enablethreshold+50mV -4 μA VOLTAGEREFERENCE Voltagereference 0.772 0.8 0.828 V HIGH-SIDEMOSFET BOOT-PH=3V,VIN=3.5V 115 200 Onresistance mΩ BOOT-PH=6V,VIN=12V 80 150 ERRORAMPLIFIER Erroramplifiertransconductance(gm) –2μA<I <2μA,V =1V 92 μmhos (COMP) (COMP) ErroramplifierDCgain(1) VSENSE=0.8V 800 V/V Erroramplifierunitygainbandwidth(1) 5pFcapacitancefromCOMPtoGNDpins 2.7 MHz Erroramplifiersource/sinkcurrent V =1V,100mVoverdrive ±7 μA (COMP) SwitchcurrenttoCOMPtransconductance VIN=12V 9 A/V PULSESKIPPINGEco-mode™ PulseskippingEco-mode™switchcurrentthreshold 100 mA CURRENTLIMIT Currentlimitthreshold VIN=12V 2.3 3.5 A THERMALSHUTDOWN ThermalShutdown 165 °C SLOWSTART(SSPIN) Chargecurrent V =0.4V 2 μA (SS) SStoVSENSEmatching V =0.4V 10 mV (SS) (1) Specifiedbydesign 7.6 Switching Characteristics T =–40°Cto150°C,VIN=3.5to28V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SWITCHINGFREQUENCY Deviceswitchingfrequency VIN=12V 210 300 390 kHz Minimumcontrollableontime VIN=12V,25°C 105 130 ns Maximumcontrollabledutyratio(1) BOOT-PH=6V 90% 93% (1) Specifiedbydesign. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 7.7 Typical Characteristics 110 4 105 VIN = 12 V T = 150°C J 100 Wesistance - m 899505 wn Current -Am 23 TJ= -40°C R o On 80 utd Rdson - 75 Isd - Sh 1 TJ= 25°C 70 65 60 0 -50 -25 0 25 50 75 100 125 150 3 8 13 18 23 28 TJ- Junction Temperature - °C VI- Input Voltage - V Figure1.OnResistancevsJunctionTemperature Figure2.ShutdownQuiescentCurrentvsInputVoltage 310 0.8240 VIN = 12 V 0.8180 uency - kHz 305 erence - V 00..88016200 w - Oscillator Freq 239050 Vref - Voltage Ref 000...778890840000 s f 0.7820 290 0.7760 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure3.SwitchingFrequencyvsJunctionTemperature Figure4.VoltageReferencevsJunctionTemperature 140 4 ns VIN = 12 V VIN = 12 V e - % n Tim130 atio - 3.75 O R e y bl ut a D ntroll120 able 3.50 Co oll m ntr u o m C ni m min - Mi 110 Minimu 3.25 n o T 100 3 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure5.MinimumControllableOnTimevs Figure6.MinimumControllableDutyRatiovs JunctionTemperature JunctionTemperature 6 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 Typical Characteristics (continued) 2.10 4 A nt -m A TJ= 25°C TJ= -40°C urre old - C h art Charge 2 Limit Thres 3.5 w St ent I- SloSS Curr TJ= 150°C 1.90 3 -50 -25 0 25 50 75 100 125 150 3 8 13 18 23 28 TJ- Junction Temperature - °C VI- Input Voltage - V Figure7.SSChargeCurrentvsJunctionTemperature Figure8.CurrentLimitThresholdvsInputVoltage 30 150 25 125 C Voltage - V 20 IO= 1A mperature - ° 100 ut 15 IO= 2A Te V- OutpO 10 Junction 75 - TJ 50 5 0 25 3 8 13 18 23 28 0 0.2 0.4 0.6 0.8 1 1.2 VI- Input Voltage - V PD- Power Dissipation - W Figure9.TypicalMaximumOutputVoltagevs Figure10.MaximumPowerDissipationvs InputVoltage JunctionTemperature Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 8 Detailed Description 8.1 Overview The TPS54233 is a 28 V, 2 A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54233hasapre-setswitchingfrequencyof300kHz. The TPS54233 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under-voltage lockout (UVLO) with two external resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to operate. The operating current is 75 μA typically when not switching and under no load. When the device is disabled,thesupplycurrentis1 μAtypically. The integrated 80 mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output currentsupto2A. The TPS54233 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference voltage. By adding an external capacitor, the slow start time of the TPS54233 can be adjustable which enables flexible outputfilterselection. To improve the efficiency at light load conditions, the TPS54233 enters a special pulse skipping Eco-modeTM whenthepeakinductorcurrentdropsbelow100mAtypically. The frequency foldback reduces the switching frequency during startup and over current conditions to help controltheinductorcurrent.Thethermalshutdowngivestheadditionalprotectionunderfaultconditions. 8.2 Functional Block Diagram EN VIN 165C Thermal Shutdown 1mA 3mA Shutdown Shutdown Logic 1.25 V Enable Enable Threshold Comparator Boot Charge ™ ECO-MODE Boot Minimum Clamp UVLO BOOT 2.1V Error 9A/V VSENSE Amplifier PWM PWM Current Comparator Latch Sense 2mA gm = 92mA/V Gate R Q 80 mW DC gain = 800 V/V Drive BW = 2.7 MHz Logic S SS Voltage 2 kW Re0fe.8re Vnce Shutdown S ComSpleonpseation Discharge PH Logic VSENSE FreSqhuieftncy Oscillator COMP GND Maximum Clamp 8 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 8.3 Feature Description 8.3.1 FixedFrequencyPWMControl The TPS54233 uses a fixed frequency, peak current mode control. The internal switching frequency of the TPS54233isfixedat300kHz. 8.3.2 VoltageReference(V ) ref The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by scalingtheoutputofatemperaturestablebandgapcircuit.Thetypicalvoltagereferenceisdesignedat0.8V. 8.3.3 BootstrapVoltage(BOOT) TheTPS54233hasanintegratedbootregulatorandrequiresa0.1 μFceramiccapacitorbetweentheBOOTand PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54233 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greaterthan2.1Vtypically. 8.3.4 EnableandAdjustableInputUnder-VoltageLockout(VINUVLO) The EN pin has an internal pull-up current source that provides the default condition of the TPS54233 operating whentheENpinfloats. The TPS54233 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended to use an external VIN UVLO to add Hysteresis unless VIN is greater than (V + 2V). To adjust the VIN UVLO OUT with Hysteresis, use the external circuitry connected to the EN pin as shown in Figure 11. Once the EN pin voltage exceeds 1.25V , an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate the resistor values needed for the desired VIN UVLO threshold voltages. The V is the input start threshold START voltage, the V is the input stop threshold voltage and the V is the enable threshold voltage of 1.25 V. The STOP EN V shouldalwaysbegreaterthan3.5V. STOP VIN Ren1 1mA 3mA + EN Ren2 1.25 V - Figure11. AdjustableInputUndervoltageLockout V -V Ren1= START STOP 3mA (1) V Ren2= EN V -V START EN+1mA Ren1 (2) Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com Feature Description (continued) 8.3.5 ProgrammableSlowStartUsingSSPIN Itisrecommendedtoprogramtheslowstarttimeexternallybecausenoslowstarttimeisimplementedinternally. The TPS54233 effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor (C ) on the SS pin to ground implements a slow start time. The TPS54233 has an internal pull-up current SS source of 2 μA that charges the external slow start capacitor. The equation for the slow start time (10% to 90%) isshowninEquation3.TheV is0.8VandtheI currentis2 μA. ref SS C (nF) ´ V (V) T (ms)= SS ref SS I (mA) SS (3) The slow start time should be set between 1ms to 10ms to ensure good start-up behavior. The slow start capacitorshouldbenomorethan27nF. If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below 1.25V,orathermalshutdowneventoccurs,theTPS54233stopsswitching. 8.3.6 ErrorAmplifier The TPS54233 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation componentsareconnectedbetweentheCOMPpinandground. 8.3.7 SlopeCompensation To prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS54233addsabuilt-inslopecompensationwhichisacompensatingramptotheswitchcurrentsignal. 8.3.8 CurrentModeCompensationDesign To simplify design efforts using the TPS54233, the typical designs for common applications are listed in Table 1. For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases. See the Detailed Design Procedure section for the detailed guidelinesorusetheWEBENCHSoftwaretool(www.TI.com/WEBENCH). Table1.TypicalDesigns(RefertoSection4:SimplifiedSchematic VIN V F L C R5 R6 C7 C6 R3 OUT sw O O (V) (V) (kHz) (μH) (kΩ) (kΩ) (pF) (pF) (kΩ) 12 5 300 22 Ceramic47μF 10 1.91 68 1800 21 12 3.3 300 15 Ceramic47μF 10.2 3.24 47 4700 21 12 1.8 300 10 Ceramic100μFx2 10 8.06 100 4700 21 12 0.9 300 6.8 Ceramic100μFx2 10 80.6 100 4700 21 12 5 300 22 Aluminum330μF/160mΩ 10 1.91 56 220 40.2 12 3.3 300 15 Aluminum470μF/160mΩ 10.2 3.24 220 220 30.9 12 1.8 300 10 SP220μF/12mΩ 10 8.06 100 4700 40.2 12 0.9 300 6.8 SP220μF/12mΩ 10 80.6 100 1800 21 10 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 8.3.9 OvercurrentProtectionandFrequencyShift The TPS54233 implements current mode control that uses the COMP pin voltage to turn off the high-side MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared; when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrentconditionsthatpulltheoutputvoltagelow,theerroramplifierrespondsbydrivingtheCOMPpinhigh, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output current. The TPS54233 provides robust protection during short circuits. There is potential for overcurrent runaway in the output inductor during a short circuit at the output. The TPS54233 solves this issue by increasing the off time during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency andtheVSENSEpinvoltageisshowninTable2. Table2.SwitchingFrequencyConditions SWITCHINGFREQUENCY VSENSEPINVOLTAGE 300kHz VSENSE≥0.6V 300kHz/2 0.6V>VSENSE≥0.4V 300kHz/4 0.4V>VSENSE≥0.2V 300kHz/8 0.2V>VSENSE 8.3.10 OvervoltageTransientProtection The TPS54233 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% × V , the high-side MOSFET will be forced off. When the VSENSE pin voltage falls ref below107%× V ,thehigh-sideMOSFETwillbeenabledagain. ref 8.3.11 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal tripthreshold.Oncethedietemperaturedecreasesbelow165°C,thedevicereinitiatesthepowerupsequence. 8.4 Device Functional Modes 8.4.1 Eco-modeTM The TPS54233 is designed to operate in pulse skipping Eco-modeTM at light load currents to boost light load efficiency. When the peak inductor current is lower than 100 mA typically, the COMP pin voltage falls to 0.5V typically and the device enters Eco-mode™. When the device is in Eco-mode™, the COMP pin voltage is clamped at 0.5V internally which prevents the high side integrated MOSFET from switching. The peak inductor current must rise above 100mA for the COMP pin voltage to rise above 0.5V and exit Eco-mode™. Since the integrated current comparator catches the peak inductor current only, the average load current entering Eco- mode™varieswiththeapplicationsandexternaloutputfilters. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The TPS54233 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 28 V to alowervoltage.WEBENCHsoftwareisavailabletoaidinthedesignandanalysisofcircuits. Foradditionaldesignneeds,seethefollowingdevices. TPS54231 TPS54232 TPS54233 TPS54331 TPS54332 I (Max) 2A 2A 2A 3A 3.5A O InputVoltageRange 3.5V-28V 3.5V-28V 3.5V-28V 3.5V-28V 3.5V-28V SwitchingFreq.(Typ) 570kHz 1000kHz 285kHz 570kHz 1000kHz SwitchCurrentLimit(Min) 2.3A 2.3A 2.3A 3.5A 4.2A Pin/Package 8SOIC 8SOIC 8SOIC 8SOIC 8SOPowerPAD™ 9.2 Typical Application L1 Vout 3.3 V, 15mH Iout Max 2A D1 C4 + C9 0.1mF B230A 470mF R5 Vin 8 - 18 V 10.2 kW C1 R1 R6 10mF 332 kW C6 3.24 kW 220 pF C7 C5 220 pF R2 R3 68.1 kW 0.015mF 30.9 kW Figure12. TypicalApplicationSchematic 9.2.1 DesignRequirements Forthisdesignexample,usetheinputparametersinTable3. Table3.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Inputvoltagerange 8Vto18V Outputvoltage 3.3V Inputripplevoltage 300mV Outputripplevoltage 100mV Outputcurrentrating 2A OperatingFrequency 300kHz 12 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 9.2.2 DetailedDesignProcedure The following design procedure can be used to select component values for the TPS54233. Alternately, the WEBENCH Software can be used to generate a complete design. The WEBENCH Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This sectionpresentsasimplifieddiscussionofthedesignprocess. 9.2.2.1 SwitchingFrequency TheswitchingfrequencyfortheTPS54233isfixedat300kHz. 9.2.2.2 OutputVoltageSetPoint The output voltage of the TPS54233 is externally adjustable using a resistor divider network. In the application circuit of Figure 12, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistordividerisgivenbyEquation4andEquation5: R5 ´ V R6= REF V -V OUT REF (4) éR5 ù V =V ´ +1 OUT REF êëR6 úû (5) Choose R5 to be approximately 10 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage matching when using standard value resistors. In this design, R5 = 10.2 kΩ and R6 = 3.24 kΩ, resulting in a 3.31Voutputvoltage. 9.2.2.3 InputCapacitors The TPS54233 requires an input decoupling capacitor and depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54233 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltageisacceptable.Forthisdesigntwo4.7μFcapacitorsareusedfortheinputdecouplingcapacitor.Theyare X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ, and the current ratingis3A.Additionally,asmall0.01 μFcapacitorisincludedforhighfrequencyfiltering. ThisinputripplevoltagecanbeapproximatedbyEquation6 I ´ 0.25 OUT(MAX) ( ) DV = + I ´ ESR IN OUT(MAX) MAX C ´ f BULK SW (6) Where I is the maximum load current, f is the switching frequency, C is the bulk capacitor value OUT(MAX) SW BULK andESR isthemaximumseriesresistanceofthebulkcapacitor. MAX The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be approximatedbyEquation7 I OUT(MAX) I = CIN 2 (7) In this case, the input ripple voltage would be 143 mV and the RMS ripple current would be 1.5 A. It is also important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in Design Parameters and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both providing ample margin. It is important that the maximum ratings for voltage and current are not exceeded under anycircumstance. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 9.2.2.4 OutputFilterComponents Two components need to be selected for the output filter, L1 and C9. Since the TPS54233 is an externally compensateddevice,awiderangeoffiltercomponenttypesandvaluescanbesupported. 9.2.2.4.1 InductorSelection Tocalculatetheminimumvalueoftheoutputinductor,useEquation8 ( ) V ´ V -V OUT(MAX) IN(MAX) OUT L = MIN V ´ K ´I ´F IN(MAX) IND OUT SW (8) K is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. IND This value is at the discretion of the designer; however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as K = 0.3 may be used. When using higher IND ESRoutputcapacitors,K =0.2yieldsbetterresults. IND For this design example, use K = 0.3 and the minimum inductor value is calculated to be 14.97μH. For this IND design,theclosestvalue15μHwaschosen. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. TheRMSinductorcurrentcanbefoundfromEquation9 æ V ´ (V - V ) ö2 I = I2 + 1 ´ ç OUT IN(MAX) OUT ÷ L(RMS) OUT(MAX) 12 çV ´ L ´ F ´ 0.7÷ IN(MAX) OUT SW è ø (9) andthepeakinductorcurrentcanbedeterminedwithEquation10 ( ) V ´ V - V OUT IN(MAX) OUT I =I + L(PK) OUT(MAX) 1.4 ´ V ´ L ´ F IN(MAX) OUT SW (10) For this design, the RMS inductor current is 2.02 A and the peak inductor current is 2.43 A. The chosen inductor is a Coilcraft MSS1038-153ML 15 μH. It has a saturation current rating of 3.86 A and an RMS current rating of 3.8 A, meeting these requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wishes to allow so long as the other design requirements are met. Larger value inductors will have lower ac current and result in lower output voltage ripple, while smaller inductor values will increase ac current and output voltage ripple. Inductor values for use with the TPS54233 are in the range of 6.8 μHto47 μH. 9.2.2.4.2 CapacitorSelection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With high switching frequencies such as the 300 kHz frequency of this design, internal circuit limitations of the TPS54233 limit the practical maximum crossover frequency to about 25 kHz. In general, the closed loop crossover frequency should be higher than the corner frequency determined by the load impedance and the output capacitor.Thislimitstheminimumcapacitorvaluefortheoutputfilterto: C =1/(2´p´R ´F ) O_min O CO_max (11) Where R is the output load impedance (V /I ) and f is the desired crossover frequency. For a desired O O O CO maximum crossover of 25 kHz the minimum value for the output capacitor is around 3.8μF. This may not satisfy the output ripple voltage requirement. The output ripple voltage consists of two components; the voltage change due to the charge and discharge of the output filter capacitance and the voltage change due to the ripple current timestheESRoftheoutputfiltercapacitor.Theoutputripplevoltagecanbeestimatedby: 14 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 é (D - 0.5) ù V = I + R ê ú OPP LPP ë4´ F ´C ESRû SW O (12) WhereN isthenumberofoutputcapacitorsinparallel. C The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in the initial design parameters; so the maximum specified ESR as listed in the capacitor data sheet is given by Equation13: V (D -0.5) ESRmax = OIPLPPMPAX -4 ´ FSW ´ CO (13) WhereΔV isthedesiredpeak-to-peakoutputripple. p-p To meet the 100 mV p-p ripple requirement, a single 470 μF aluminum electrolytic output capacitor is chosen for C9. This is a Panasonic, EEVFK1A471P rated at 10V with a maximum ESR of 160 mΩ and a ripple current ratingof600mA. ThemaximumRMSoutputripplecurrentcanbecalculatedusingEquation14 I = 1 × æç VOUT × (VIN(MAX) - VOUT) ö÷ COUT(RMS) 12 çV ×L ×F ×N ÷ è IN(MAX) OUT SW C ø (14) The calculated total RMS ripple current is 216 mA and the maximum total ESR required is 43 mΩ. These output capacitors exceed the requirements by a wide margin and will result in a reliable, high-performance design. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus = the ripple voltage.Anyderatingamountmustalsobeincluded. OthercapacitortypesworkwellwiththeTPS54233,dependingontheneedsoftheapplication. 9.2.2.5 CompensationComponents The external compensation used with the TPS54233 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectricoutputcapacitors,butothertypesaresupported. A Type II compensation scheme is recommended for the TPS54233. The compensation components are chosen to set the desired closed loop cross over frequency and phase margin for output filter components. The type II compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency zero/polepair. ThedcgainisdeterminedbyEquation15: V ´ V ggm REF G = DC V O (15) Where: V =800 ggm V =0.8V REF Thelow-frequencypoleisdeterminedbyEquation16: VPO =1/(2 ´ p ´ ROO ´CZ) (16) Themid-frequencyzeroisdeterminedbyEquation17: FZ1 =1/(2 ´ p ´ RZ ´CZ) (17) And,themid-frequencypoleisgivenbyEquation18: FP1 =1/(2 ´ p ´ RZ ´CP) (18) Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency, but for the TPS54233it is recommended that the maximum closed loop crossover frequency be not greater than 25 kHz. Next, the required gain and phase boost ofthecrossovernetworkneedstobecalculated.Bydefinition,thegainofthecompensationnetworkmustbethe inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is less than the closed loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation19: æ R ö æ R ö Gain =20 log ç O ÷-20log ç O ÷ èRSENSE ø èRESR ø (19) Where: R =1Ω/9 SENSE R =V /I O O O R =Equivalentseriesresistanceoftheoutputcapacitor ESR ThephaselossisgivenbyEquation20: PL=a tan(2 ´ p ´ FCO´RESR ´ CO) -a tan(2 ´ p ´ FCO´RO ´ CO) (20) Where: R =Equivalentseriesresistanceoftheoutputcapacitor ESR R =V /I O O O Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement canbedetermined.TherequiredphaseboostisgivenbyEquation21: PB= (PM - 90deg) -PL (21) WherePM=thedesiredphasemargin. A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined byEquation22andtheresultantzeroandpolefrequenciesaregivenbyEquation23 andEquation24 æPB ö k = tanç +45deg÷ è 2 ø (22) F F = CO Z1 k (23) F = F ´k P1 CO (24) Thelow-frequencypoleissetsothatthegainatthecrossoverfrequencyisequaltotheinverseofthegainofthe modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of R canbederiveddirectlybyEquation25: Z V ´ R ´ 0.98 R = O OA Z GM ´ V ´ V ´ R COMP ggm REF ESR (25) Where: V =Outputvoltage O R =8.696MΩ OA GM =9A/V COMP V =800 ggm V =0.8V REF R =Equivalentseriesresistanceoftheoutputcapacitor ESR WithR known,C andC canbecalculatedusingEquation26andEquation27: Z Z P 16 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 1 C = Z 2´p´F ´R Z1 z (26) 1 C = P 2´p ´F ´R P1 z (27) For this design, a singe 470 μF output capacitor is used. The ESR is approximately .160 Ω. The desired closed loopcrossoverfrequencyis22000Hz. UsingEquation19andEquation20,theoutputstagegainandphaselossareequivalentas: Gain=–3.114dB and PL=–4.96degrees For60degreesofphasemargin,Equation21requiresnoadditionalphaseboost,soKcanbesetequalto1. Equation22,Equation23,andEquation24areusedtofindthezeroandpolefrequenciesof: F =22000Hz Z1 And F =22000Hz P1 R ,C ,andC arecalculatedusingEquation25,Equation26,andEquation27: Z Z P 2.5 ´ 8.696 ´ 106 ´ 0.98 Rz= =30.5kW 9 ´ 800 ´ 0.8 ´ 0.160 (28) 1 Cz = =237pF 2 ´ p ´ 22000 ´ 30500 (29) 1 Cp = =237pF 2 ´ p ´ 22000 ´ 30500 (30) UsingstandardvaluesforR3,C6,andC7intheapplicationschematicofFigure12: R3=30.9kΩ C6=220pF C7=220pF The measured overall loop response for the circuit is given in Figure 12. Note that the actual closed loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of lineandloadvariability. 9.2.2.6 BootstrapCapacitor Every TPS54233 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a high- qualityceramictypewithX7RorX5Rgradedielectricfortemperaturestability. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 9.2.2.7 CatchDiode The TPS54233 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is V + 0.5 V. Peak current must be greater than I plus on half the peak INMAX OUTMAX to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of40V,forwardcurrentof3A,andaforwardvoltagedropof0.5V. 9.2.2.8 OutputVoltageLimitations Due to the internal design of the TPS54233, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91% andisgivenbyEquation31: V =0.91× ((V - I ×R )+V ) - (I ×R ) - V Omax INmin Omax DS(on)max D Omax L D (31) Where: V =Minimuminputvoltage INmin I =Maximumloadcurrent O max V =Catchdiodeforwardvoltage D R =Outputinductorseriesresistance L Theequationassumesmaximumonresistancefortheinternalhigh-sideFET. The lower limit is constrained by the minimum controllable on time which may be as high as 160 ns. The approximateminimumoutputvoltageforagiveninputvoltageandminimumloadcurrentisgivenbyEquation32: VOmin =0.051 ´ ((VINmax - IOmin ´ Rin) +VD) - (IOmin ´ RL ) - VD (32) Where: V =Maximuminputvoltage INmax I =Minimumloadcurrent O min V =Catchdiodeforwardvoltage D R =Outputinductorseriesresistance L This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checkedtoassureproperfunctionality. 18 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 9.2.2.9 PowerDissipationEstimate The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or pulseskippingEco-modeTM. Thedevicepowerdissipationincludes: 1)Conductionloss:Pcon=Iout2xR xV /VIN DS(on) OUT 2)Switchingloss:Psw=0.5x10-9xVIN2xI xFsw OUT 3)Gatechargeloss:Pgc=22.8x10-9xFsw 4)Quiescentcurrentloss:Pq=0.075x10-3xVIN Where: I istheoutputcurrent(A). OUT R istheon-resistanceofthehigh-sideMOSFET(Ω). DS(on) V istheoutputvoltage(V). OUT VINistheinputvoltage(V). Fswistheswitchingfrequency(Hz). So Ptot=Pcon+Psw+Pgc+Pq ForgivenT ,T =T +RthxPtot. A J A ForgivenT =150°C,T =T –RthxPtot. JMAX AMAX JMAX Where: Ptotisthetotaldevicepowerdissipation(W). T istheambienttemperature(°C). A T isthejunctiontemperature(°C). J Rthisthethermalresistanceofthepackage(°C/W). T ismaximumjunctiontemperature(°C). JMAX T ismaximumambienttemperature(°C). AMAX Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 9.2.3 ApplicationCurves 100 100 VO= 3.3 V 95 95 VIN= 8 V VIN= 12 V VIN= 15 V 90 VIN= 8 V VIN= 12 V VIN= 15 V 90 85 % 85 % y - VIN= 18 V y - 80 c c en 80 en 75 VIN= 18 V ci ci Effi 75 Effi 70 65 70 60 65 55 60 50 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 20 40 60 80 100 120 140 160 180 200 IO- Output Current -A IO- Output Current - mA Figure13.TPS54233Efficiency Figure14.TPS54233LowCurrentEfficiency 0.05 0.025 0.04 0.020 IO= 1A 0.015 0.03 Output Regulation - %-000...0000112 VIN= 18 VVIN= 12 VVIN= 8 V Output Regulation - % --0000....0000100105500 -0.02 VIN= 15 V -0.015 -0.03 -0.020 -0.04 -0.025 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 8 9 10 11 12 13 14 15 16 17 18 IO- Output Current -A VI- Input Voltage -V Figure15.TPS54233LoadRegulation Figure16.TPS54233LineRegulation 60 180 VOUT Gain hase P IOUT -60 -180 10 1M f - Frequency - Hz Figure18.TPS54233LoopResponse Figure17.TPS54233TransientResponse 20 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 VIN VOUT PH PH Figure20.TPS54233OutputRipple Figure19.TPS54233InputRipple VIN ENA VOUT VOUT Figure21.TPS54233StartUp Figure22.TPS54233Start-upRelativetoEnable VOUT PH Figure23.TPS54233Eco-mode™Operation Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 10 Power Supply Recommendations The device is designed to operate from an input-voltage supply range between 3.5 V and 28 V. This input supply should be well regulated. If the input supply is located more than a few inches from the converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of100μFisatypicalchoice. 11 Layout 11.1 Layout Guidelines The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The typical recommended bypass capacitance is 10 μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 24 for a PCB layout example. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The TPS54233 uses a fused lead frame so that the GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of internal or back side ground plane available, and the top side ground area can be connected to these areas using multiple vias under or adjacent to the device to help dissipate heat. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate layoutschemes,howeverthislayouthasbeenshowntoproducegoodresultsandisintendedasaguideline. 11.2 Layout Example OUTPUT Vout FILTER TOPSIDE CAPACITOR FeedbackTrace GROUND AREA Route BOOTCAPACITOR OUTPUT trace on other layer to provide CATCH INDUCTOR wide path for topside ground DIODE PH INPUT BYPASS CAPACITOR BOOT BOOT PH CAPACITOR Vin VIN GND EN COMP UVLO RESISTOR SS VSENSE DIVIDER COMPENSATION RESISTOR SLOW START NETWORK DIVIDER CAPACITOR Thermal VIA Signal VIA Figure24. TPS54233BoardLayout 22 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

TPS54233 www.ti.com SLUS859C–OCTOBER2008–REVISEDJANUARY2015 11.3 Estimated Circuit Area TheestimatedprintedcircuitboardareaforthecomponentsusedinthedesignofFigure12 is0.72in2.Thisarea doesnotincludetestpointsorconnectors. 11.4 Electromagnetic Interference (EMI) Considerations As EMI becomes a rising concern in more and more applications, the internal design of the TPS54233 takes measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used tolowertheparasiticseffects. To achieve the best EMI performance, external component selection and board layout are equally important. FollowtheDetailedDesignProcedureabovetopreventpotentialEMIissues. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54233

TPS54233 SLUS859C–OCTOBER2008–REVISEDJANUARY2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 DevelopmentSupport FortheWEBENCHSoftwareTool,gotowww.TI.com/WEBENCH. 12.2 Trademarks Eco-mode,PowerPADaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 24 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54233

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54233D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 150 54233 & no Sb/Br) TPS54233DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 150 54233 & no Sb/Br) TPS54233DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 150 54233 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54233 : •Automotive: TPS54233-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54233DR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54233DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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