Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 TPS54232 2-A, 28-V, 1-MHz, Step-Down DC-DC Converter With Eco-Mode™ 1 Features 3 Description • 3.5-Vto28-VInputVoltageRange The TPS54232 is a 28-V, nonsynchronous buck 1 converter that integrates a low R high-side • AdjustableOutputVoltageDownto0.8V DS(on) MOSFET. To increase efficiency at light loads, a • Integrated80-mΩHigh-SideMOSFETSupports pulse-skipping Eco-Mode feature is automatically upto2-AContinuousOutputCurrent activated. Furthermore, the 1-μA shutdown supply • HighEfficiencyatLightLoadswithaPulse- current allows the device to be used in battery- powered applications. Current mode control with SkippingEco-Mode™ internal slope compensation simplifies the external • Fixed1-MHzSwitchingFrequency compensation calculations and reduces component • Typical1-μAShutdownQuiescentCurrent count while allowing the use of ceramic output • AdjustableSlow-StartLimitsInrushCurrents capacitors. A resistor divider programs the hysteresis of the input undervoltage lockout. An overvoltage • ProgrammableUVLOThreshold transient protection circuit limits voltage overshoots • OvervoltageTransientProtection during startup and transient conditions. A cycle-by- • Cycle-by-CycleCurrentLimit,FrequencyFold cycle current limit scheme, frequency fold back, and BackandThermalShutdownProtection thermal shutdown protect the device and the load in the event of an overload condition. The TPS54232 is • Availablein8-PinSOICPackage availableinan8-pinSOICpackage. • Supportedby WEBENCH®SoftwareTool (http://www.ti.com/lsds/ti/analog/webench/overvie DeviceInformation(1) w.page) PARTNUMBER PACKAGE BODYSIZE(NOM) TPS54232 SOIC(8) 4.90mmx3.90mm 2 Applications (1) For all available packages, see the orderable addendum at • ConsumerApplicationssuchasSet-TopBoxes, theendofthedatasheet. CPEEquipment,LCDDisplays,Peripherals,and BatteryChargers • IndustrialandCarAudioPowerSupplies • 5-V,12-V,and24-VDistributedPowerSystems 4 Simplified Schematic Efficiency Ren1 EN VIN VIN 100 Ren2 C V = 3.3 V I O 95 TPS54232 V= 5 V I C 90 BOOT BOOT LO % 85 V= 12 V PH VOUT y - I SS nc 80 COMP D1 CO RO1 Efficie 75 VI= 15 V CSS C1 70 C2 VSENSE R3 65 GND R O2 60 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 IO- Output Current -A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription.................................................11 2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................13 3 Description............................................................. 1 9 ApplicationandImplementation........................ 14 4 SimplifiedSchematic............................................. 1 9.1 ApplicationInformation............................................14 9.2 TypicalApplication .................................................14 5 RevisionHistory..................................................... 2 10 PowerSupplyRecommendations..................... 24 6 PinConfigurationandFunctions......................... 4 11 Layout................................................................... 24 7 Specifications......................................................... 5 11.1 LayoutGuidelines.................................................24 7.1 AbsoluteMaximumRatings .....................................5 11.2 LayoutExample....................................................24 7.2 HandlingRatings......................................................5 11.3 EstimatedCircuitArea..........................................25 7.3 RecommendedOperatingConditions.......................6 11.4 ElectromagneticInterference(EMI) 7.4 ThermalInformation..................................................6 Considerations.........................................................25 7.5 ElectricalCharacteristics...........................................7 12 DeviceAndDocumentationSupport................. 26 7.6 SwitchingCharacteristics..........................................7 12.1 Trademarks...........................................................26 7.7 TypicalCharacteristics..............................................8 12.2 ElectrostaticDischargeCaution............................26 8 DetailedDescription............................................ 10 12.3 Glossary................................................................26 8.1 Overview.................................................................10 13 Mechanical,Packaging,AndOrderable 8.2 FunctionalBlockDiagram.......................................10 Information........................................................... 26 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(October2013)toRevisionD Page • Changedthedatasheettothenewstandardformat............................................................................................................. 1 • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 • AddedtheThermalInformationtable..................................................................................................................................... 6 • DeletedPackageDissipationRatingstable............................................................................................................................ 7 • ChangedEquation7............................................................................................................................................................. 15 • ChangedEquation32........................................................................................................................................................... 20 • ChangedEquation33........................................................................................................................................................... 20 ChangesfromRevisionB(February2011)toRevisionC Page • RemovedSwift™fromthedatasheettitle............................................................................................................................. 1 • ChangedtextFrom:"WhereN isthenumberofoutputcapacitorsinparallel."To:":WhereC isthenumberof C O outputcapacitorsinparallel."FollowingEquation13........................................................................................................... 17 • ChangedEquation26........................................................................................................................................................... 18 • ChangedEquation29........................................................................................................................................................... 19 • Changed:Switchingloss:Paw=0.5x10-9xVIN2xI xFewTo:Switchingloss:Psw=0.5x10-9xVIN2xI x OUT OUT Fsw ...................................................................................................................................................................................... 21 • Changed:Gatechargeloss:P.C.=22.8x10-9xFewTo:Gatechargeloss:Pgc.=22.8x10-9xFsw ............................21 • Deletedgraph"MaximumPowerDissipationvsJunctionTemperature"fromtheSupplementalApplicationCurves.........22 2 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 ChangesfromRevisionA(March2010)toRevisionB Page • DeletedfeatureItem:ForSWIFT™Documentation,SeetheTIWebsiteatwww.ti.com/swift.............................................. 1 • ChangedFigure14x-axisFrom:I -OutputCurrent-mATo:I -OutputCurrent-A....................................................... 22 O O ChangesfromOriginal(November2008)toRevisionA Page • ChangedChangedtheABSOLUTEMAXIMUMRATINGStable,InputVoltage-ENpinmaxvalueFrom:5Vto6V.......... 5 • AddedanewtabletotheDescription-Foradditionaldesignneeds................................................................................... 14 Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 6 Pin Configuration and Functions DPACKAGE (TOPVIEW) BOOT 1 8 PH VIN 2 7 GND EN 3 6 COMP SS 4 5 VSENSE PinFunctions PIN I/O DESCRIPTION NAME NO. BOOT 1 O A0.1-μFbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitorfallsbelow theminimumrequirement,thehigh-sideMOSFETisforcedtoswitchoffuntilthecapacitorisrefreshed. VIN 2 I Inputsupplyvoltage,3.5Vto28V. EN 3 I Enablepin.Pullbelow1.25Vtodisable.Floattoenable.Programmingtheinputundervoltagelockoutwith tworesistorsisrecommended. SS 4 I Slowstartpin.Anexternalcapacitorconnectedtothispinsetstheoutputrisetime. VSENSE 5 I Invertingnodeofthegmerroramplifier. COMP 6 O Erroramplifieroutput,andinputtothePWMcomparator.Connectfrequencycompensationcomponentsto thispin. GND 7 - Ground. PH 8 O Thesourceoftheinternalhigh-sidepowerMOSFET. 4 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VIN –0.3 30 EN –0.3 6 BOOT 38 InputVoltage V VSENSE –0.3 3 COMP –0.3 3 SS –0.3 3 BOOT-PH 8 8 OutputVoltage PH –0.6 30 V PH(10nstransientfromgroundtonegativepeak) –5 EN 100 μA BOOT 100 mA SourceCurrent VSENSE 10 μA PH 6 A VIN 6 A SinkCurrent COMP 100 μA SS 200 OperatingJunctionTemperature,T –40 150 °C J (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 7.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) –2 2 kV V Electrostaticdischarge (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) –500 500 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT OperatingInputVoltageon(VINpin) 3.5 28 V T Operatingjunctiontemperature –40 150 °C J 7.4 Thermal Information TPS54232 THERMALMETRIC(1) D UNIT 8PINS R Junction-to-ambientthermalresistance 116.3 θJA R Junction-to-case(top)thermalresistance 53.7 θJC(top) R Junction-to-boardthermalresistance 57.1 θJB °C/W ψ Junction-to-topcharacterizationparameter 12.9 JT ψ Junction-to-boardcharacterizationparameter 56.5 JB R Junction-to-case(bottom)thermalresistance - θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 7.5 Electrical Characteristics T =–40°Cto150°C,VIN=3.5Vto28V(unlessotherwisenoted) J DESCRIPTION TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Internalundervoltagelockoutthreshold RisingandFalling 3.5 V Shutdownsupplycurrent EN=0V,VIN=12V,–40°Cto85°C 1 4 μA Operating–nonswitchingsupplycurrent VSENSE=0.85V 85 120 μA ENABLEANDUVLO(ENPIN) Enablethreshold RisingandFalling 1.25 1.35 V Inputcurrent Enablethreshold–50mV -1 μA Inputcurrent Enablethreshold+50mV -4 μA VOLTAGEREFERENCE Voltagereference 0.772 0.8 0.828 V HIGH-SIDEMOSFET BOOT-PH=3V,VIN=3.5V 115 200 Onresistance mΩ BOOT-PH=6V,VIN=12V 80 150 ERRORAMPLIFIER Erroramplifiertransconductance(gm) –2μA<I <2μA,V =1V 92 μmhos (COMP) (COMP) ErroramplifierDCgain(1) VSENSE=0.8V 800 V/V Erroramplifierunitygainbandwidth(1) 5pFcapacitancefromCOMPtoGNDpins 2.7 MHz Erroramplifiersource/sinkcurrent V =1.0V,100mVoverdrive ±7 μA (COMP) SwitchcurrenttoCOMPtransconductance VIN=12V 10 A/V PULSE-SKIPPINGECO-MODE Pulse-skippingEco-Modeswitchcurrentthreshold 100 mA CURRENTLIMIT Currentlimitthreshold VIN=12V 2.3 4.9 A THERMALSHUTDOWN ThermalShutdown 165 °C SLOWSTART(SSPIN) Chargecurrent V =0.4V 2 μA (SS) SStoVSENSEmatching V =0.4V 10 mV (SS) (1) Specifiedbydesign 7.6 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT TPS54232SwitchingFrequency VIN=12V,25°C 800 1000 1200 kHz Minimumcontrollableontime VIN=12V,25°C 110 135 ns Maximumcontrollabledutyratio(1) BOOT-PH=6V 90% 93% (1) Specifiedbydesign Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 7.7 Typical Characteristics 110 6 105 VIN = 12 V EN = 0 V 100 Wesistance - m 899505 n Current -Am 4 TJ= 150°C R w dson - On 7850 d - Shutdo 2 R s 70 I 65 TJ=-40°C TJ=25°C 60 0 -50 -25 0 25 50 75 100 125 150 3 8 13 18 23 28 TJ- Junction Temperature - °C VI- Input Voltage - V Figure1.OnResistancevsJunctionTemperature Figure2.ShutdownQuiescentCurrentvsInputVoltage 1020 0.8240 VIN = 12 V 0.8180 w - Oscillator Frequency - kHz 11009019000 Vref - Voltage Reference - V 00000.....77888890018406200000 s f 0.7820 980 0.7760 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure3.SwitchingFrequencyvsJunctionTemperature Figure4.VoltageReferencevsJunctionTemperature 140 14.0 VIN = 12 V On Time - ns130 VIN = 12 V Ratio - %111233...505 able Duty 12.0 m Controll120 ntrollable 1111..05 nimu m Co10.5 Mi 110 mu min - Mini10.0 n 9.5 o T 100 9.0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure5.MinimumControllableOnTimevsJunction Figure6.MinimumControllableDutyRatiosJunction Temperature Temperature 8 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 Typical Characteristics (continued) 2.10 5.5 A m I- Slow Start Charge Current -SS122...900505 Current Limit Threshold -A454...005 TJ= 25°CTJ= 150°C TJ= -40°C 1.90 3.5 -50 -25 0 25 50 75 100 125 150 3 8 13 18 23 28 TJ- Junction Temperature - °C VI- Input Voltage - V Figure7.SSChargeCurrentvsJunctionTemperature Figure8.CurrentLimitThresholdvsInputVoltage Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 8 Detailed Description 8.1 Overview The TPS54232 is a 28-V, 2-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54232hasapre-setswitchingfrequencyof1MHz. The TPS54232 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pull-up current source that can be used to adjust the input-voltage, undervoltage lockout (UVLO) with two external resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to operate. The operating current is 85 μA typically when not switching and under no load. When the device is disabled,thesupplycurrentis1 μAtypically. The integrated 80-mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output currentsupto2A. The TPS54232 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference voltage. By adding an external capacitor, the slow start time of the TPS54232 can be adjustable which enables flexible outputfilterselection. To improve the efficiency at light load conditions, the TPS54232 enters a special pulse-skipping Eco-Mode when thepeakinductorcurrentdropsbelow100mAtypically. The frequency foldback reduces the switching frequency during startup and over current conditions to help controltheinductorcurrent.Thethermalshutdowngivestheadditionalprotectionunderfaultconditions. 8.2 Functional Block Diagram EN VIN 165C Thermal Shutdown 1mA 3mA Shutdown Shutdown Logic 1.25 V Enable Enable Threshold Comparator Boot Charge ™ MEiCniOm-uMmO CDlEamp UBVoLoOt BOOT 2.1V Error 10A/V VSENSE Amplifier PWM PWM Current Comparator Latch Sense 2mA gm = 92mA/V Gate R Q 80 mW DC gain = 800 V/V Drive BW = 2.7 MHz Logic S SS Voltage 2 kW Re0fe.8re Vnce Shutdown S ComSpleonpseation Discharge PH Logic VSENSE FreSqhuieftncy Oscillator COMP GND Maximum Clamp 10 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 8.3 Feature Description 8.3.1 Fixed-FrequencyPWMControl The TPS54232 uses a fixed frequency, peak current mode control. The internal switching frequency of the TPS54232isfixedat1MHz. 8.3.2 VoltageReference(V ) ref The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by scalingtheoutputofatemperaturestablebandgapcircuit.Thetypicalvoltagereferenceisdesignedat0.8V. 8.3.3 BootstrapVoltage(BOOT) TheTPS54232hasanintegratedbootregulatorandrequiresa0.1-μFceramiccapacitorbetweentheBOOTand PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54232 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greaterthan2.1Vtypically. 8.3.4 EnableandAdjustableInputUndervoltageLockout(VINUVLO) The EN pin has an internal pull-up current source that provides the default condition of the TPS54232 operating whentheENpinfloats. The TPS54232 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended to use an external VIN UVLO to add hysteresis unless VIN is greater than (V + 2V). To adjust the VIN UVLO OUT withhysteresis,usetheexternalcircuitryconnectedtotheENpinasshowninFigure9.OncetheENpinvoltage exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate the resistor values needed for the desired VIN UVLO threshold voltages. The V is the input start threshold START voltage, the V is the input stop threshold voltage and the V is the enable threshold voltage of 1.25 V. The STOP EN V shouldalwaysbegreaterthan3.5V. STOP TPS54232 VIN Ren1 1mA 3mA + EN Ren2 1.25 V - Figure9. AdjustableInputUndervoltageLockout V -V Ren1= START STOP 3mA (1) V Ren2= EN V -V START EN+1mA Ren1 (2) 8.3.5 ProgrammableSlow-StartUsingSSPin It is highly recommended to program the slow start time externally because no slow start time is implemented internally. The TPS54232 effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor (C ) on the SS pin to ground implements a slow start time. The TPS54232 has an SS internal pull-up current source of 2 μA that charges the external slow start capacitor. The equation for the slow starttime(10%to90%)isshowninEquation3.TheV is0.8VandtheI currentis2μA. ref SS Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) C (nF) ´ V (V) T (ms)= SS ref SS I (mA) SS (3) The slow start time should be set between 1 ms to 10 ms to ensure good startup behavior. The slow-start capacitorshouldbenomorethan27nF. If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below 1.25V,orathermalshutdowneventoccurs,theTPS54232stopsswitching. 8.3.6 ErrorAmplifier The TPS54232 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation componentsareconnectedbetweentheCOMPpinandground. 8.3.7 SlopeCompensation In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS54232addsabuilt-inslopecompensationwhichisacompensatingramptotheswitchcurrentsignal. 8.3.8 CurrentModeCompensationDesign For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases. For the detailed guidelines, see the Detailed Design Proceduresection. 8.3.9 OvercurrentProtectionandFrequencyShift The TPS54232 implements current mode control that uses the COMP pin voltage to turn off the high-side MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared; when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrentconditionsthatpulltheoutputvoltagelow,theerroramplifierrespondsbydrivingtheCOMPpinhigh, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output current. The TPS54232 provides robust protection during short circuits. There is potential for overcurrent runaway in the output inductor during a short circuit at the output. The TPS54232 solves this issue by increasing the off time during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency andtheVSENSEpinvoltageisshowninTable1. Table1.SwitchingFrequencyConditions SWITCHINGFREQUENCY VSENSEPINVOLTAGE 1MHz VSENSE≥0.6V 1MHz/2 0.6V>VSENSE≥0.4V 1MHz/4 0.4V>VSENSE≥0.2V 1MHz/8 0.2V>VSENSE 8.3.10 OvervoltageTransientProtection The TPS54232 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% × V , the high-side MOSFET will be forced off. When the VSENSE pin voltage falls ref below107%× V ,thehigh-sideMOSFETwillbeenabledagain. ref 12 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 8.3.11 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal tripthreshold.Oncethedietemperaturedecreasesbelow165°C,thedevicereinitiatesthepowerupsequence. 8.4 Device Functional Modes 8.4.1 Eco-Mode TheTPS54232deviceisdesignedtooperateinpulseskippingEco-modeatlightloadcurrentstoboostlightload efficiency. When the peak inductor current is lower than 100 mA (typical), the COMP pin voltage falls to 0.5 V (typical)andthedeviceentersEco-mode.WhenthedeviceisinEco-mode,theCOMPpinvoltageisclampedat 0.5 V internally which prevents the high-side integrated MOSFET from switching. The peak inductor current must rise above 100 mA for the COMP pin voltage to rise above 0.5 V and exit Eco-mode. Because the integrated current comparator catches the peak inductor current only, the average load current entering Eco-mode varies withtheapplicationsandexternaloutputfilters. 8.4.2 OperationWithVIN < 3.5V The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device becomesactivewhentheVINpinpassestheUVLOthreshold.Switchingbeginswhentheslow-startsequenceis initiated. 8.4.3 OperationWithENControl The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the devicebecomesactive.Switchingisenabled,andtheslow-startsequenceisinitiated. Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The TPS54232 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 28 V to alowervoltage.WEBENCH™softwareisavailabletoaidinthedesignandanalysisofcircuits. Foradditionaldesignneeds,see: TPS54231 TPS54232 TPS54233 TPS54331 TPS54332 I (Max) 2A 2A 2A 3A 3.5A O InputVoltageRange 3.5V-28V 3.5V-28V 3.5V-28V 3.5V-28V 3.5V-28V SwitchingFreq.(Typ) 570kHz 1000kHz 285kHz 570kHz 1000kHz SwiitchCurrentLimit(Min) 2.3A 2.3A 2.3A 3.5A 4.2A Pin/Package 8SOIC 8SOIC 8SOIC 8SOIC 8SOPowerPAD™ 9.2 Typical Application Figure10. TypicalApplicationSchematic 9.2.1 DesignRequirements Forthisdesignexample,usethevalueslistedinTable2astheinputparameters Table2.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Inputvoltagerange 5Vto15V Outputvoltage 2.5V Inputripplevoltage 300mV Outputripplevoltage 30mV Outputcurrentrating 2A OperatingFrequency 1MHz 14 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 9.2.2 DetailedDesignProcedure The following design procedure can be used to select component values for the TPS54232. Alternately, the WEBENCH Software may be used to generate a complete design. The WEBENCH™ Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This sectionpresentsasimplifieddiscussionofthedesignprocess. 9.2.2.1 SwitchingFrequency TheswitchingfrequencyfortheTPS54232isfixedat1MHz. 9.2.2.2 OutputVoltageSetPoint The output voltage of the TPS54232 is externally adjustable using a resistor divider network. In the application circuit of Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistordividerisgivenbyEquation4andEquation5. R5 ´ V R6= REF V -V OUT REF (4) éR5 ù V =V ´ +1 OUT REF êëR6 úû (5) Choose R5 to be approximately 10 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage matching when using standard value resistors. In this design, R4 = 10.2 kΩ and R = 4.75 kΩ, resulting in a 2.5 V output voltage. The zero ohm resistor R4 is provided as a convenient place to break the control loop for stability testing. 9.2.2.3 InputCapacitors The TPS54232 requires an input decoupling capacitor and depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54232 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design a 10 μF capacitor issued for the input decoupling capacitor. It isX5R dielectric rated for 25 V. The equivalent series resistance (ESR) is approximately 5 mΩ, and the current rating is 3A. ThisinputripplevoltagecanbeapproximatedbyEquation6. I ´ 0.25 OUT(MAX) ( ) DV = + I ´ ESR IN OUT(MAX) MAX C ´ f BULK SW (6) Where I is the maximum load current, f is the switching frequency, C is the input capacitor value OUT(MAX) SW BULK andESR isthemaximumseriesresistanceoftheinputcapacitor. MAX The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be approximatedbyEquation7. I OUT(MAX) I = CIN 2 (7) In this case, the input ripple voltage would be 60 mV and the RMS ripple current would be 1 A. It is also important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in Table 2 and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen bulk and bypass capacitors are each rated for 25 V and the ripple current capacity is greater than 3 A, both providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded under any circumstance. Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 9.2.2.4 OutputFilterComponents Two components need to be selected for the output filter, L1 and C3. Since the TPS54232 is an externally compensateddevice,awiderangeoffiltercomponenttypesandvaluescanbesupported. 9.2.2.4.1 InductorSelection Tocalculatetheminimumvalueoftheoutputinductor,useEquation8. ( ) V ´ V -V OUT(MAX) IN(MAX) OUT L = MIN V ´ K ´I ´F IN(MAX) IND OUT SW (8) K is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. IND In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as K = 0.4 may be used. When IND usinghigherESRoutputcapacitors,K =0.2yieldsbetterresults. IND For this design example, use K = 0.35 and the minimum inductor value is calculated to be 2.97 μH. For this IND design,alargevaluewaschosen:3.3μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. Thepeak-to-peakinductorcurrentiscalculatedusingEquation9. ( ) VOUT × VIN(MAX) - VOUT I = LPP V ×L ´ ƒ ´ 0.8 IN(MAX) OUT SW (9) TheRMSinductorcurrentcanbefoundfromEquation10. I = I2 + 1 ´ æç VOUT ´ (VIN(MAX) - VOUT) ö÷2 L(RMS) OUT(MAX) 12 çV ´ L ´ F ´ 0.8÷ è IN(MAX) OUT SW ø (10) andthepeakinductorcurrentcanbedeterminedwithEquation11. ( ) V ´ V - V OUT IN(MAX) OUT I =I + L(PK) OUT(MAX) 1.6 ´ V ´ L ´ F IN(MAX) OUT SW (11) For this design, the RMS inductor current is 2.01 A and the peak inductor current is 2.39 A. The chosen inductor is a Coilcraft MSS7341-332NL 3.3 μH. It has a saturation current rating of 3.28 A and an RMS current rating of 3.95 A, meeting these requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wishes to allow so long as the other design requirements are met. Larger value inductors will have lower ac current and result in lower output voltage ripple, while smaller inductor values will increaseaccurrentandoutputvoltageripple.InductorvaluesforusewiththeTPS54232areintherangeof1 μH to47μH. 9.2.2.4.2 CapacitorSelection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With high- switching frequencies such as the 1 MHz frequency of this design, internal circuit limitations of the TPS54232 limit the practical maximum crossover frequency to about 70 kHz. In general, the closed loop crossover frequency should be higher than the corner frequency determined by the load impedance and the output capacitor.Thislimitstheminimumcapacitorvaluefortheoutputfilterto: C =1/(2´p´R ´F ) O_min O CO_max (12) 16 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 Where R is the output load impedance (V /I ) and f is the desired crossover frequency. For a desired O O O CO maximum crossover of 50 kHz the minimum value for the output capacitor is around 2.5 μF. This may not satisfy the output ripple voltage requirement. The output ripple voltage consists of two components; the voltage change due to the charge and discharge of the output filter capacitance and the voltage change due to the ripple current timestheESRoftheoutputfiltercapacitor.Theoutputripplevoltagecanbeestimatedby: é (D - 0.5) ù V = I + R ê ú OPP LPP ë4´ F ´C ESRû SW O (13) The maximum ESR of the output capacitor can be determined from the amount of allowable output ripple as specified in the initial design parameters. The contribution to the output ripple voltage due to ESR is the inductor ripple current times the ESR of the output filter, so the maximum specified ESR as listed in the capacitor data sheetisgivenbyEquation14. V (D -0.5) ESR = OPPMAX - max I 4 ´ F ´ C LPP SW O (14) Where V is the desired maximum peak-to-peak output ripple. The maximum RMS ripple current in the OPPMAX outputcapacitorisgivenbyEquation15. I = 1 × æç VOUT × (VIN(MAX) - VOUT) ö÷ COUT(RMS) 12 çV ×L ×F ×N ÷ è IN(MAX) OUT SW C ø (15) WhereN isthenumberofoutputcapacitorsinparallel. C For this design example, a single 22-μF ceramic output capacitor is chosen for C6. It is rated at 10V with a maximum ESR of 5 mΩ and a ripple current rating in excess of 3 A. The calculated total RMS ripple current is 182 mA and the maximum total ESR required is 51 mΩ. This output capacitor exceeds the requirements by a wide margin and will result in a reliable, high-performance design. it is important to note that the actual capacitance in circuit may be less than the catalog value when the output is operating near the rated voltage for the capacitor. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus ½ the ripple voltage but in this example a 10-V capacitor is used so that the effective capacitance will remain close to the stated value of 22 μF. Other capacitor types work well with the TPS54232, depending on the needsoftheapplication. 9.2.2.5 CompensationComponents The external compensation used with the TPS54232 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses a ceramic X5R dielectricoutputcapacitor,butothertypesaresupported. A Type II compensation scheme is recommended for the TPS54232. The compensation components are chosen to set the desired closed loop cross over frequency and phase margin for output filter components. The type II compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency zero/polepair. TheDCgainisdeterminedbyEquation16. V ´ V ggm REF G = DC V O (16) Where: V =800 ggm V =0.8V REF Thelow-frequencypoleisdeterminedbyEquation17. VPO =1/(2 ´ p ´ ROO ´CZ) (17) Themid-frequencyzeroisdeterminedbyEquation18. Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com FZ1 =1/(2 ´ p ´ RZ ´CZ) (18) And,themid-frequencypoleisgivenbyEquation19. FP1 =1/(2 ´ p ´ RZ ´CP) (19) The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency, but for the TPS54232 it is recommended that the maximum closed loop crossover frequency be not greater than 75 kHz. Next, the required gain and phase boost ofthecrossovernetworkneedstobecalculated.Bydefinition,thegainofthecompensationnetworkmustbethe inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed loop crossover frequency, the gain of the modulator and output filter can be approximated byEquation20. Gain= -20log(2 ´ p ´ R ´F ´C )-2dB SENSE CO O (20) Where: R =1Ω/10 SENSE F =Closed-loopcrossoverfrequency CO C =Outputcapacitance O ThephaselossisgivenbyEquation21. PL=a tan(2 ´ p ´ F ´R ´ C ) -a tan(2 ´ p ´ F ´R ´ C )-10deg CO ESR O CO O O (21) Where: R =Equivalentseriesresistanceoftheoutputcapacitor ESR R =V /I O O O The measured overall loop response for the circuit is given in Figure 20. Note that the actual closed-loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of lineandloadvariability. Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement canbedetermined.TherequiredphaseboostisgivenbyEquation22. PB= (PM - 90deg) -PL (22) WherePM=thedesiredphasemargin. A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined byEquation23andtheresultantzeroandpolefrequenciesaregivenbyEquation24 andEquation25. æPB ö k = tanç +45deg÷ è 2 ø (23) F F = CO Z1 k (24) F = F ´k P1 CO (25) Thelow-frequencypoleissetsothatthegainatthecrossoverfrequencyisequaltotheinverseofthegainofthe modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of R canbederiveddirectlybyEquation26. Z 2×p ×F ×V ×C ×R ×0.754 R = CO O O OA Z GM ×V ×V ICOMP ggm REF (26) Where: 18 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 V =Outputvoltage O C =Outputcapacitance O F =Desiredcrossoverfrequency CO R =8.696MΩ OA GM =10A/V COMP V =800 ggm V =0.8V REF WithR known,C andC canbecalculatedusingEquation27andEquation28. Z Z P 1 C = Z 2´p´F ´R Z1 z (27) 1 C = P 2´p ´F ´R P1 z (28) For this design, a 22-μF output capacitor issued. For ceramic capacitors, the actual output capacitance is less thantheratedvaluewhenthecapacitorshaveadcbiasvoltageapplied.ThisisthecaseinaDC-DCconverter. Forthisdesign,a10-Vcapacitorischosentominimizethiseffect.TheESRisapproximately0.005 Ω. UsingEquation20andEquation21,theoutputstagegainandphaselossareequivalentas: Gain=1.613dB and PL=-92.3degrees For60degreesofphasemargin,Equation22requires62.33degreesofphaseboost. Equation23,Equation24,andEquation25areusedtofindthezeroandpolefrequenciesof: F =12.3kHz Z1 And F =203kHz P1 R ,C ,andC arecalculatedusingEquation26,Equation27,andEquation28. Z Z P 2 ´ p ´ 50000 ´ 2.5 ´ 22 ´ 10-6 ´ 8.696 ´ 106´0.754 Rz= =17.7kW 10 ´ 800 ´ 0.8 (29) 1 Cz = =730pF 2 ´ p ´ 12300 ´ 17700 (30) 1 Cp = =44pF 2 ´ p ´ 203000 ´ 17700 (31) UsingstandardvaluesforR3,C6,andC7intheapplicationschematicofFigure10: R3=17.4kΩ C6=680pF C7=47pF 9.2.2.6 BootstrapCapacitor Every TPS54232 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a high- qualityceramictypewithX7RorX5Rgradedielectricfortemperaturestability. Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 9.2.2.7 CatchDiode The TPS54232 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is VIN + 0.5 V. Peak current must be greater than IOUTMAX plus on half the (MAX) peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B220A is chosen, with a reverse voltage of20V,forwardcurrentof2A,andaforwardvoltagedropof0.5V. 9.2.2.8 OutputVoltageLimitations Due to the internal design of the TPS54232, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 90% andisgivenbyEquation32. V = 0.90 x ((V – I x R ) +V ) – (I x R ) – V O(max) IN(min) O(max) dson(max) D O(max) L D (32) Where: V =Minimuminputvoltage IN(min) I =Maximumloadcurrent O(max) V =Catchdiodeforwardvoltage D R =Outputinductorseriesresistance L Theequationassumesmaximumonresistancefortheinternalhigh-sideFET. The lower limit is constrained by the minimum controllable on time which may be as high as 135 ns. The approximateminimumoutputvoltageforagiveninputvoltageandminimumloadcurrentisgivenbyEquation33. V = 0.162 x ((V – I x R ) + V ) – (I x R ) – V O(min) IN(max) O(min) dson(min) D O(min) L D (33) Where: V =Maximuminputvoltage IN(max) I =Minimumloadcurrent O(min) V =Catchdiodeforwardvoltage D R =Outputinductorseriesresistance L This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checkedtoassureproperfunctionality. 20 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 9.2.2.9 PowerDissipationEstimate The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse-skippingEco-Mode. Thedevicepowerdissipationincludes: 1. Conductionloss:Pcon=I 2xR xV /VIN OUT DS(on) OUT 2. Switchingloss:Psw=0.5x10-9xVIN2xI xFsw OUT 3. Gatechargeloss:Pgc.=22.8x10-9xFsw 4. Quiescentcurrentloss:Pq=0.085x10-3xVIN Where: I istheoutputcurrent(A). OUT R istheon-resistanceofthehigh-sideMOSFET(Ω). DS(on) V istheoutputvoltage(V). OUT VINistheinputvoltage(V). Fswistheswitchingfrequency(Hz). So: Ptot=Pcon+Psw+Pgc+Pq ForgivenT ,T =T +RthxPtot. A J A ForgivenT =150°C,T =T –RthxPtot. JMAX AMAX JMAX Where: Ptotisthetotaldevicepowerdissipation(W). T istheambienttemperature(°C). A T isthejunctiontemperature(°C). J Rthisthethermalresistanceofthepackage(°C/W). T ismaximumjunctiontemperature(°C). JMAX T ismaximumambienttemperature(°C). AMAX Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 9.2.3 ApplicationCurves space 3.75 30 IO= 2A IO= 2A 3.25 25 V V- Output Voltage - O122...727555 V- Output Voltage - VO 112050 1.25 5 0.75 0 3 8 13 18 23 28 3 8 13 18 23 28 VI- Input Voltage - V VI- Input Voltage - V Figure11.TypicalMinimumOutputVoltagevsInput Figure12.TypicalMaximumOutputVoltagevsInput Voltage Voltage 100 100 VO= 3.3 V 95 95 VI= 5 V 90 VI= 8 V 90 85 cy - % 85 VI= 12 V cy - % 80 VI= 12 V n 80 n 75 e e ci ci Effi 75 Effi 70 70 VI= 15 V 65 VI= 15 V 60 65 55 60 50 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 0.020.04 0.060.08 0.1 0.12 0.140.160.18 0.2 IO- Output Current -A IO- Output Current -A Figure13.TPS54232Efficiency Figure14.TPS54232LowCurrentEfficiency 0.1 0.025 0.08 0.02 % 0.06 0.015 put Voltage Regulation - --0000....000040224 VI= 15 V VI= 12 V VI= 5 V Output Regulation - % -00-..0000..000055110 IO= 1A ut O -0.06 -0.015 -0.08 -0.02 -0.1 -0.025 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 5 6 7 8 9 10 11 12 13 14 15 IO- Output Current -A VI- Input Voltage - V Figure15.TPS54232LoadRegulation Figure16.TPS54232LineRegulation 22 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 60 180 50 150 VOUT 40 Gain 120 30 90 20 Phase 60 g. B 10 30e d D IOUT 0.5 - 2ASTEP Gain - -100 -030hase - P -20 -60 -30 -90 -40 -120 -50 -150 -60 -180 t - Time - 2 ms/div 10 100 1k 10k 100k 1M f - Frequency - Hz Figure17.TPS54232TransientResponse Figure18.TPS54232LoopResponse VOUT VIN PH PH t - Time - 1ms/div t - Time - 1ms/div Figure19.TPS54232OutputRipple Figure20.TPS54232InputRipple VOUT VOUT VIN SS t - Time - 2 ms/div t - Time - 2 ms/div Figure21.TPS54232Startup Figure22.TPS54232StartupRelativetoEnable Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 10 Power Supply Recommendations The device is designed to operate from an input-voltage supply range between 3.5 V and 28 V. This input supply should be well regulated. If the input supply is located more than a few inches from the converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of100μFisatypicalchoice. 11 Layout 11.1 Layout Guidelines The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the anode of the catch diode. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The TPS54232 uses a fused lead frame so that the GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of internal or back side ground plane available, and the top side ground area can be connected to these areas using multiple vias under or adjacent to the device to help dissipate heat. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate layout schemes, however this layout has been showntoproducegoodresultsandisintendedasaguideline. 11.2 Layout Example OUTPUT Vout FILTER TOPSIDE CAPACITOR FeedbackTrace GROUND AREA Route BOOTCAPACITOR OUTPUT trace on other layer to provide CATCH INDUCTOR wide path for topside ground DIODE PH INPUT BYPASS CAPACITOR BOOT BOOT PH CAPACITOR Vin VIN GND EN COMP UVLO RESISTOR SS VSENSE DIVIDER COMPENSATION RESISTOR SLOW START NETWORK DIVIDER CAPACITOR Thermal VIA Signal VIA Figure23. TPS54232BoardLayout 24 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

TPS54232 www.ti.com SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 11.3 Estimated Circuit Area TheestimatedprintedcircuitboardareaforthecomponentsusedinthedesignofFigure10 is0.44in2.Thisarea doesnotincludetestpointsorconnectors. 11.4 Electromagnetic Interference (EMI) Considerations As EMI becomes a rising concern in more and more applications, the internal design of the TPS54232 takes measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used tolowertheparasiticseffects. To achieve the best EMI performance, external component selection and board layout are equally important. FollowtheDetailedDesignProcedureabovetopreventpotentialEMIissues. Copyright©2008–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54232

TPS54232 SLVS876D–NOVEMBER2008–REVISEDNOVEMBER2014 www.ti.com 12 Device And Documentation Support 12.1 Trademarks Eco-Mode,WEBENCH,PowerPADaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, And Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 26 SubmitDocumentationFeedback Copyright©2008–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54232

PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54232D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 150 54232 & no Sb/Br) TPS54232DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 150 54232 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2018 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jan-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54232DR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jan-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54232DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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