TPS5420-EP www.ti.com SLVS717–DECEMBER2006 2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT™ CONVERTER FEATURES • Fixed500-kHzSwitchingFrequencyforSmall • ControlledBaseline FilterSize – OneAssembly/TestSite,OneFabrication • ImprovedLineRegulationandTransient Site ResponsebyInputVoltageFeedForward • EnhancedDiminishingManufacturingSources • SystemProtectedbyOvercurrentLimitingand (DMS)Support ThermalShutdown • EnhancedProduct-ChangeNotification • -55(cid:176) Cto125(cid:176) COperatingJunction • QualificationPedigree (1) TemperatureRange • WideInputVoltageRange:5.5Vto35V • AvailableinSmall8-PinSOICPackage • Upto2-AContinuous(3-APeak)Output • ForSWIFT™Documentation,Application Reports,andDesignSoftware,SeetheTI Current Websiteatwww.ti.com/swift • HighEfficiencyupto95%Enabledby110-mW IntegratedMOSFETSwitch APPLICATIONS • WideOutputVoltageRange:AdjustableDown • Consumer:Set-TopBoxes,DVDs,LCD to1.22Vwith1.5%InitialAccuracy Displays • InternalCompensationMinimizesExternal • IndustrialandCarAudioPowerSupplies PartsCount • BatteryChargers,High-PowerLEDSupplies (1) ComponentqualificationinaccordancewithJEDECand • 12-V/24-VDistributedPowerSystems industrystandardstoensurereliableoperationoveran extendedtemperaturerange.Thisincludes,butisnotlimited to,HighlyAcceleratedStressTest(HAST)orbiased85/85, temperaturecycle,autoclaveorunbiasedHAST, electromigration,bondintermetalliclife,andmoldcompound life.Suchqualificationtestingshouldnotbeviewedas justifyinguseofthiscomponentbeyondspecified performanceandenvironmentallimits. DESCRIPTION/ORDERING INFORMATION As a member of the SWIFT™ family of dc/dc regulators, the TPS5420 is a high-output-current PWM converter that integrates a low-resistance high-side N-channel MOSFET. Included on the substrate with the listed features is a high-performance voltage error amplifier that provides tight voltage regulation accuracy under transient conditions, an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 5.5 V, an internally set slow-start circuit to limit inrush currents, and a voltage feed-forward circuit to improve the transient response. Using the ENA pin, shutdown supply current is reduced to 18 m A, typically. Other features include an active high enable, overcurrent protection, and thermal shutdown. To reduce design complexity and external component count,theTPS5420feedbackloopisinternallycompensated. TheTPS5420deviceisavailableinaneasytouse8-pinSOICpackage.TI provides evaluation modules and the SWIFT Designer Software tool to aid in quickly achieving high-performance power-supply designs to meet aggressiveequipmentdevelopmentcycles. Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SWIFTisatrademarkofTexasInstruments. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION T INPUTVOLTAGE OUTPUTVOLTAGE PACKAGE(1) PARTNUMBER J –55(cid:176) Cto125(cid:176) C 5.5Vto35V Adjustableto1.22V SOIC(D)(2) TPS5420MDREP (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) TheDpackageisavailabletapedandreeled.AddanRsuffixtothedevicetype(i.e.,TPS5420DR). SIMPLIFIEDSCHEMATIC Efficiency vs Output Current VIN VOUT 100 VIN PH 95 TPS5420 90 NC BOOT 85 VI= 12 V % 80 NENCA VSENSE Effici−ency 7705 65 GND 60 55 50 0 0.5 1 1.5 2 2.5 3 IO−Output Current−A Absolute Maximum Ratings(1)(2) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT VIN –0.3to38(3) BOOT –0.3to50 PH(steady-state) –0.6to38(3) V Inputvoltagerange EN –0.3to7 V I VSENSE –0.3to3 BOOT-PH 10 PH(transient<10ns) –1.2 I Sourcecurrent PH Internallylimited O I Leakagecurrent PH 10 m A lkg T Operatingvirtualjunctiontemperaturerange –55to150 (cid:176) C J T Storagetemperaturerange –65to150 (cid:176) C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesarewithrespecttonetworkgroundterminal. (3) ApproachingtheabsolutemaximumratingfortheVINpinmaycausethevoltageonthePHpintoexceedtheabsolutemaximumrating. 2 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 Dissipation Ratings(1)(2) THERMALIMPEDANCE PACKAGE JUNCTION-TO-AMBIENT 8-pinD (3) 75(cid:176) C/W (1) Maximumpowerdissipationmaybelimitedbyovercurrentprotection. (2) PowerratingataspecificambienttemperatureT shouldbedeterminedwithajunctiontemperatureof125(cid:176) C.Thisisthepointwhere A distortionstartstosubstantiallyincrease.ThermalmanagementofthefinalPCBshouldstrivetokeepthejunctiontemperatureator below125(cid:176) Cforbestperformanceandlong-termreliability.SeeThermalCalculationsinapplicationssectionofthisdatasheetformore information. (3) Testboardconditions: a. 3in· 3in,twolayers,thickness:0.062in b. 2-ozcoppertraceslocatedonthetopandbottomofthePCB Recommended Operating Conditions MIN MAX UNIT V Inputvoltagerange,VIN 5.5 35 V I T Operatingjunctiontemperature –55 125 (cid:176) C J Electrical Characteristics T =–55(cid:176) Cto125(cid:176) C,VIN=5.5Vto35V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SupplyVoltage(VINPin) VSENSE=2V,Notswitching,PHpinopen 3 4.4 mA I Quiescentcurrent Q Shutdown,ENA=0V 18 50 m A UndervoltageLockout(UVLO) Startthresholdvoltage,UVLO 5.3 5.5 V Hysteresisvoltage,UVLO 330 mV VoltageReference T =25(cid:176) C 1.202 1.221 1.239 J Voltagereferenceaccuracy V I =0A–2A 1.196 1.221 1.245 O Oscillator T =25(cid:176) C 400 500 600 kHz J Internallysetfree-runningfrequency T =-55(cid:176) Cto125(cid:176) C 375 600 kHz J Minimumcontrollableontime 150 200 ns Maximumdutycycle 87% 89% Enable(ENAPin) Startthresholdvoltage,ENA 1.3 V Stopthresholdvoltage,ENA 0.5 V Hysteresisvoltage,ENA 450 mV Internalslow-starttime(0~100%) 6.6 8 10.6 ms CurrentLimit Currentlimit 3 4 5.2 A Currentlimithiccuptime 13 16 22 ms ThermalShutdown Thermalshutdowntrippoint 135 162 (cid:176) C Thermalshutdownhysteresis 14 (cid:176) C OutputMOSFET VIN=5.5V 150 r High-sidepowerMOSFETswitch mW DS(on) VIN=10V–35V 110 230 SubmitDocumentationFeedback 3

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 PIN ASSIGNMENTS DPACKAGE (TOPVIEW) BOOT 1 8 PH NC 2 7 VIN NC 3 6 GND VSENSE 4 5 ENA TERMINALFUNCTIONS TERMINAL DESCRIPTION NAME NO. BOOT 1 Boostcapacitorforthehigh-sideFETgatedriver.Connect0.01-m Flow-ESRcapacitorfromBOOTpintoPHpin. NC 2,3 Notconnectedinternally VSENSE 4 Feedbackvoltagefortheregulator.Connecttooutputvoltagedivider. ENA 5 On/offcontrol.Below0.5V,thedevicestopsswitching.Floatthepintoenable. GND 6 Ground Inputsupplyvoltage.BypassVINpintoGNDpinclosetodevicepackagewithahigh-quality,low-ESRceramic VIN 7 capacitor. PH 8 Sourceofthehigh-sidepowerMOSFET.Connectedtoexternalinductoranddiode. 4 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 TYPICAL CHARACTERISTICS MINIMUMCONTROLLABLE OSCILLATORFREQUENCY OPERATINGQUIESCENTCURRENT ONTIME vs vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 530 3.5 180 520 mA VI= 12 V 170 f−Oscillator Frequency−kHz 455447018900000 IOperat−ing Quiescent Current−Q 32..27553 Minimum Controllable On Time−ns 111156340000 446600 2.5 120 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure1. Figure2. Figure3. VOLTAGEREFERENCE ON-STATERESISTANCE INTERNALSLOWSTARTTIME vs vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 11..2233 180 9 170 VI= 12 V V−V−Voltage Voltage Reference−VReference−Vrefref 1111....112222..212122555522 Wr−On-State Resistance−mDS(on) 11111111569234000000000 tInternal Sl−ow Start Time−msSS 87..558 11..2211-50 -25 0 25 50 75 100 125 80-50 -25 0 25 50 75 100 125 7 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure4. Figure5. Figure6. MINIMUMCONTROLLABLE SHUTDOWNQUIESCENTCURRENT DUTYRATIO vs vs INPUTVOLTAGE JUNCTIONTEMPERATURE 25 8 ENA= 0 V Shutdown Current−Am 1250 TTJJ== 12275oCoC mum Duty Ratio−% 77..55 I−SD 10 Mini7.25 TJ= -40oC 5 7 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125 VI−Input Voltage−V TJ−Junction Temperature−oC Figure7. Figure8. SubmitDocumentationFeedback 5

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 APPLICATION INFORMATION FUNCTIONALBLOCKDIAGRAM VIN VIN UVLO 1.22R1e Vfe Breanncdegap VREF Slow Start SHDN ReBgouolattor BOOT HICCUP 5µA ENA ENABLE SHDN SHDN VSENSE Z1 Thermal Protection SHDN SHDN AmErprolifrier Z2 Ramp NC VIN Generator Feed Forward Gain = 25 NC SHDN PWM HICCUP Comparator GND Overcurrent SHDN Oscillator Protection SHDN Gate Drive Control Gate Driver SHDN BOOT PH VOUT DETAILED DESCRIPTION OscillatorFrequency The internal free-running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching frequency allows less output inductance for the same output ripple requirement, resulting in a smaller output inductor. VoltageReference The voltage reference system produces a precision reference signal by scaling the output of a temperature-stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to anoutputof1.221Vatroomtemperature. Enable(ENA)andInternalSlowStart The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled below the threshold voltage the regulator stops switching and the internal slow start resets. Connecting the pin to ground or to any voltage less than 0.5 V disables the regulator and activates the shutdown mode. The quiescentcurrentoftheTPS5420inshutdownmodeistypically18m A. The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application requires controlling the ENA pin, use open-drain or open-collector output logic to interface with the pin. To limit the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its finalvalue,linearly.Theinternalslowstarttimeis8ms,typically. 6 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 APPLICATION INFORMATION (continued) UndervoltageLockout(UVLO) The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, device start-up begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLOcomparatoris330mV. BoostCapacitor(BOOT) Connect a 0.01-m F low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stablevaluesovertemperature. OutputFeedback(VSENSE) The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage reference1.221V. InternalCompensation The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 uses voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover frequency and a high phase margin for good stability. See the Internal Compensation Network in the applicationssectionformoredetails. VoltageFeedForward The internal voltage feed forward provides a constant dc power stage gain, despite any variations with the input voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constantatthefeedforwardgain: VIN Feed Forward Gain = Ramp pk-pk (1) Thetypicalfeed-forwardgainofTPS5420is25. Pulse-Width-Modulation(PWM)Control The regulator employs a fixed-frequency pulse-width-modulator (PWM) control method. First, the feedback voltage(VSENSEpinvoltage)iscomparedtothe constant voltage reference by the high-gain error amplifier and compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width that is the duty cycle.Finally,thePWMoutputisfedintothegatedrivecircuittocontroltheontimeofthehigh-sideMOSFET. OvercurrentProtection Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to avoidanyturn-onnoiseglitches. Once overcurrent indicator is set true, overcurrent protection is triggered. The high-side MOSFET is turned off for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle currentlimiting. SubmitDocumentationFeedback 7

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 APPLICATION INFORMATION (continued) If the sensed current continues increasing, even with the cycle-by-cycle current limiting that may happen during short circuit or under other circumstances, the hiccup-mode overcurrent protection is triggered instead of the cycle-by-cycle current limiting. During the hiccup-mode overcurrent protection, the voltage reference is grounded and the high-side MOSFET is turned off for the hiccup time. Once the hiccup time is complete, the regulator restarts. ThermalShutdown The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side MOSFETisturnedoff.Thepartisrestarted under control of the slow start circuit automatically when the junction temperaturedrops14(cid:176) Cbelowthethermalshutdowntrippoint. PCBLayout Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this is to extend the top-side ground area from under the device adjacent to the VIN trace, and place the bypass capacitorascloseas possible to the VIN pin. The minimum recommended bypass capacitance is 10-m F ceramic withaX5RorX7Rdielectric. There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground areaunderthedeviceasshowninFigure9. The PH pin should be routed to the output inductor, catch diode, and boot capacitor. Since the PH connection is the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device tominimizetheoutputcurrentlooparea.Connectthebootcapacitorbetweenthephase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placementsandconnectionsshownworkwell,butotherconnectionroutingsmayalsobeeffective. Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the loopformedbythePHpin,L ,C ,andGNDassmallasispractical. out out Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not routethistracetooclosetothePHtrace.DuetothesizeoftheICpackageandthe device pinout, the trace may need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the outputcapacitorisnotdesired. ThegroundingschemeshownisusedviaaconnectiontoadifferentlayertoroutetotheENApin. 8 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 APPLICATION INFORMATION (continued) PH CATCH DIODE BOOT CAPACITOR INPUT INPUT BYPASS BULK BOOT PH CAPACITOR FILTER OUTPUT Vin INDUCTOR NC VIN NC GND RESISTOR VSENSE ENA DIVIDER VOUT OUTPUT FILTER TOPSIDE GROUND AREA CAPACITOR VIA to Ground Plane Route feedback trace under the output Signal VIA filter capacitor or on the other layer. Figure9.DesignLayout SubmitDocumentationFeedback 9

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 APPLICATION INFORMATION (continued) 0 5 0 0.220 0. 6 2 0 0. 0.080 All dimensions in inches Figure10.TPS5420LandPattern ApplicationCircuits Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output currentatanominaloutputvoltageof5V. U1 TPS5420D C2 TP5 L1 VIN 10 V - 35 V 7 VIN 1 0.01mF 33mH 5 V 5 BOOT VOUT ENA ENA C1 C4 2 NC PH 8 D1 + C3 4.7mF 4.7mF 63 NC VSNS 4 B340A 1(S0e0e NmoFteA) R101 kW GND R2 3.24 kW A. C3=TantalumAVXTPSD107M010R0080 Figure11.ApplicationCircuit,10-V–35-VInputto5-VOutput 10 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 APPLICATION INFORMATION (continued) DesignProcedure The following design procedure can be used to select component values for the TPS5420. Alternately, the SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Thissectionpresentsasimplifieddiscussionofthedesignprocess. Tobeginthedesignprocess,afewparametersmustbedetermined.Thedesignermustknowthefollowing: • Inputvoltagerange • Outputvoltage • Inputripplevoltage • Outputripplevoltage • Outputcurrentrating • Operatingfrequency DesignParameters Forthisdesignexample,usethefollowingastheinputparameters: DESIGNPARAMETER(1) EXAMPLEVALUE Inputvoltagerange 10Vto35V Outputvoltage 5V Inputripplevoltage 300mV Outputripplevoltage 30mV Outputcurrentrating 2A Operatingfrequency 500kHz (1) Asanadditionalconstraint,thedesignissetuptobesmallsizeandlowcomponentheight. SwitchingFrequency The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching frequency. InputCapacitors The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The recommended value for the decoupling capacitor is 10 m F. A high-quality ceramic type X5R or X7R is required. For some applications, a smaller value decoupling capacitor may be used, if the input voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage, including ripple. For this design, two 4.7-m F capacitors, C1 and C4, are used to allow for smaller 1812 case size tobeusedwhilemaintaininga50-Vrating. ThisinputripplevoltagecanbeapproximatedbyEquation2: I x 0.25 OUT(MAX) DV = + ( I x E S R ) IN OUT(MAX) MAX C x ƒ BULK SW (2) Where: I =Maximumloadcurrent OUT(MAX) f =Switchingfrequency SW C =Inputcapacitorvalue I ESR =Maximumseriesresistanceoftheinputcapacitor MAX SubmitDocumentationFeedback 11

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 The maximum RMS ripple current also needs to be checked. For worst-case conditions, this is approximated by Equation3: I OUT(MAX) I (cid:1) CIN 2 (3) Inthisexample,thecalculatedinputripplevoltageis 118 mV and the RMS ripple current is 1.0 A. The maximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors areratedfor50V,andtheripplecurrentcapacityforeachis3Aat500kHz,providingamplemargin. The actual measured input ripple voltage may be larger than the calculated value, due to the output impedance of the input voltagesourceandparasiticsassociatedwiththelayout. CAUTION: The maximum ratings for voltage and current are not to be exceeded under any circumstance. Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located within approximately2infrom the input voltage source. The value for this capacitor is not critical, but it should be rated to handle the maximum input voltage, including ripple voltage, and should filter the output so that input ripple voltageisacceptable. OutputFilterComponents Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internally compensateddevice,alimitedrangeoffiltercomponenttypesandvaluescanbesupported. InductorSelection Tocalculatetheminimumvalueoftheoutputinductor,useEquation4: V ´ ( V - V ) OUT IN(MAX) OUT L = MIN V ´ K ´ I ´ F ´ 0.8 IN(max) IND OUT SW (4) K is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. IND Three things need to be considered when determining the amount of ripple current in the inductor: the peak-to-peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current, and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using the TPS5420, K of 0.2 to 0.3 yields good results. Low output ripple voltages are obtained when IND paired with the proper output capacitor, the peak switch current is below the current limit set point, and low load currentscanbesourcedbeforediscontinuousoperation. For this design example, use K = 0.2, and the minimum inductor value is 31 m H. The next highest standard IND valueusedinthisdesignis33m H. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. TheRMSinductorcurrentcanbefoundfromEquation5: (cid:7) 2 2 1 (cid:5) VOUT(cid:1)(cid:5)VIN(MAX)(cid:3)VOUT(cid:6) (cid:6) IL(RMS)(cid:4) IOUT(MAX)(cid:2)12(cid:1) VIN(MAX)(cid:1)LOUT(cid:1)FSW(cid:1)0.8 (5) andthepeakinductorcurrentcanbedeterminedusingEquation6: ( ) V ´ V - V OUT IN(MAX) OUT I = I + L(PK) OUT(MAX) 1.6 ´ V ´ L ´ F IN(MAX) OUT SW (6) For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The chosen inductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 m H. It has a saturation current rating of 2.2 A and an RMS current rating of 2.7 A, which meets the requirements. Inductor values for use with the TPS5420areintherangeof10m Hto100m H. 12 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 CapacitorSelection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. Due to the design of the internal compensation, it is recommended to keep the closed-loop crossover frequency in the range 3 kHz to 30 kHz, as this frequency range has adequate phase boost to allow for stable operation. For this design example, the intended closed-loop crossover frequency is between 2590 Hz and 24 kHz, and below the ESR zero of the output capacitor. Under these conditions, the closed-loop crossover frequency is related to the LCcornerfrequencyas: f 2 f (cid:1) LC CO 85V OUT (7) andthedesiredoutputcapacitorvaluefortheoutputfilterto: C (cid:2) 1 OUT 3357(cid:1)L (cid:1)f (cid:1)V OUT CO OUT (8) For a desired crossover of 18 kHz and a 33-m H inductor, the calculated value for the output capacitor is 100 m F. ThecapacitortypeshouldbechosensothattheESRzeroisabovetheloopcrossover.ThemaximumESRis: ESR (cid:2) 1 MAX 2(cid:1)(cid:1)C (cid:1)f OUT CO (9) The maximum ESR of the output capacitor also determines the amount of output ripple, as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter. Check that the maximum specified ESR as listed in the capacitor data-sheet results in an acceptable output ripplevoltage: ESR ´ V ´ (V - V ) MAX OUT IN(MAX) OUT V (MAX) = PP N ´ V ´ L ´ F ´ 0.8 C IN(MAX) OUT SW (10) Where: D V =Desiredpeak-to-peakoutputripple PP N =Numberofparalleloutputcapacitors C F =Switchingfrequency SW The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and 54kHz. The selected output capacitor must also be rated for a voltage greater than the desired output voltage, plus one-half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the outputcapacitorisgivenbyEquation11: [ ] ( - ) V ´ V - V 1 OUT IN(MAX) OUT I = ´ COUT(RMS) Ö12 V ´ L - F ´ 0.8 ´ N IN(MAX) OUT SW C (11) Where: N =Numberofoutputcapacitorsinparallel C F =Switchingfrequency SW SubmitDocumentationFeedback 13

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 Forthisdesignexample,asingle100-m Foutputcapacitoris chosen for C3. The calculated RMS ripple current is 143 mA, and the maximum ESR required is 88 mW . A capacitor that meets these requirements is an AVX TPSD107M010R0080,ratedat 10 V, with a maximum ESR of 80 mW and a ripple current rating of 1.369 A. This capacitor results in a peak-to-peak output ripple of 26 mV using Equation 10. An additional small 0.1-m F ceramic bypasscapacitormayalsoused,butisnotincludedinthisdesign. OthercapacitortypescanbeusedwiththeTPS5420,dependingontheneedsoftheapplication. OutputVoltageSetpoint The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin. CalculatetheR2resistorvaluefortheoutputvoltageof5VusingEquation12: R2 (cid:3) R1(cid:1)1.221 V (cid:2) 1.221 OUT (12) ForanyTPS5420design,startwithanR1valueof10kW .R2isthen3.24kW . BootCapacitor Thebootcapacitorshouldbe0.01m F. CatchDiode The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diode mustmeettheabsolute maximum ratings for the application—reverse voltage must be higher than the maximum voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus one-half the peak-to-peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward currentof3A,andaforwardvoltagedropof0.5V. AdditionalCircuits Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar to those given for the design example, with a larger-value output inductor and a lower closed-loop crossover frequency. U1 L1 TPS5420D C2 TP5 10 V - 21 V 27mH 7 0.01mF VIN VIN 1 5 V 5 BOOT VOUT ENA ENA C1 2 8 + 10mF NC PH D1 C3 3 R1 6 NC VSNS 4 B340A 1(S0e0e NmoFteA) 10 kW GND R2 3.24 kW A. C3=TantalumAVXTPSD107M010R0080 Figure12. 10-V—21-VInputto5-VOutputApplicationCircuit 14 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 ADVANCED INFORMATION Output Voltage Limitations Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% andisgivenby: VOUTMAX(cid:4)0.87(cid:1)(cid:5)(cid:7)VINMIN(cid:3)IOMAX(cid:1)0.230(cid:8)(cid:2)VD(cid:6)(cid:3)(cid:7)IOMAX(cid:1)RL(cid:8)(cid:3)VD (13) Where: V =Minimuminputvoltage INMIN I =Maximumloadcurrent OMAX V =Catchdiodeforwardvoltage D R =Outputinductorseriesresistance L Thisequationassumesmaximumon-resistancefortheinternalhigh-sideFET. The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The approximateminimumoutputvoltageforagiveninputvoltageandminimumloadcurrentisgivenby: VOUTMIN(cid:4)0.12(cid:1)(cid:5)(cid:7)VINMAX(cid:3)IOMIN(cid:1)0.110(cid:8)(cid:2)VD(cid:6)(cid:3)(cid:7)IOMIN(cid:1)RL(cid:8)(cid:3)VD (14) Where: V =Maximuminputvoltage INMAX I =Minimumloadcurrent OMIN V =Catchdiodeforwardvoltage D R =Outputinductorseriesresistance L This equation assumes nominal on resistance for the high-side FET and accounts for worst-case variation of operating frequency set point. Any design operating near the operational limits of the device should be checked toensureproperfunctionality. Internal Compensation Network The design equations given in the example circuit can be used to generate circuits using the TPS5420. These designs are based on certain assumptions, and always select output capacitors within a limited range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the TPS5420. Equation 15gives the nominal frequency response of the internal voltage-mode type III compensation network: (cid:4)1(cid:2)2(cid:1)(cid:1)sFz1(cid:5)(cid:1)(cid:4)1(cid:2)2(cid:1)(cid:1)sFz2(cid:5) H(s)(cid:3) (cid:4) s (cid:5) (cid:4) s (cid:5) (cid:4) s (cid:5) (cid:4) s (cid:5) 2(cid:1)(cid:1)Fp0 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp1 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp2 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp3 (15) Where: Fp0=2165Hz,Fz1=2170Hz,Fz2=2590Hz Fp1=24kHz,Fp2=54kHz,Fp3=440kHz Fp3representsthenon-idealparasiticseffect. Using this information, along with the desired output voltage, feed-forward gain, and output filter characteristics, theclosed-looptransferfunctioncanbederived. SubmitDocumentationFeedback 15

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 ADVANCED INFORMATION (continued) Thermal Calculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations.Theyshouldnotbeusedifthedeviceisworkingatlightloadsinthediscontinuousconductionmode. Conductionloss:Pcon=I 2· r · V /V OUT DS(on) OUT IN Switchingloss:Psw=V · I · 0.01 IN OUT Quiescentcurrentloss:Pq=V · 0.01 IN Totalloss:Ptot=Pcon+Psw+Pq GivenT =>Estimatedjunctiontemperature:T =T +Rth· Ptot A J A GivenT =125(cid:176) C=>Estimatedmaximumambienttemperature:T =T Rth· Ptot JMAX AMAX JMAX 16 SubmitDocumentationFeedback

TPS5420-EP www.ti.com SLVS717–DECEMBER2006 PERFORMANCE GRAPHS The performance graphs in Figure 13 through Figure 19 are applicable to the circuit in Figure 11. T = 25(cid:176) C A (unlessotherwisespecified). 100 0.3 0.3 VI= 10.8 V 0.2 0.2 95 VI= 12 V VI= 15 V IO= 2A % % Efficiency - % 8950 ut Regulation - 0.01 ut Regulation - 0.01 IO=0A VI= 18 V VI= 19.8 V Outp -0.1 Outp -0.1 IO= 1A 80 -0.2 -0.2 75 -0.3 -0.3 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 IO- Output Current -A IO- Output Current -A VI- Input Voltage - V Figure13.Efficiency Figure14.OutputRegulation% Figure15.InputRegulation% vsOutputCurrent vsOutputCurrent vsInputVoltage VIN= 100 mV/Div (AC Coupled) VOUT= 20 mV/Div (AC Coupled) V = 50 mV/Div (AC Coupled) OUT PH = 5 V/Div PH = 5 V/Div I = 500 mA/Div OUT t- Time - 1ms / Div t- Time - 1ms / Div t - Time = 200μs/Div Figure16.InputVoltageRipple Figure17.OutputVoltageRipple Figure18.TransientResponse,I O andPHNode,I =3A andPHNode,I =3A Step0.5to1.5A O O V = 10 V/Div IN ENA= 2 V/Div V = 2 V/Div OUT V = 2 V/Div OUT t - Time = 5 ms/Div t - Time = 5 ms/Div Figure19.StartupWaveform, Figure20.StartupWaveform, V andV ENAandV IN OUT OUT SubmitDocumentationFeedback 17

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS5420MDREP ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 5420MEP & no Sb/Br) TPS5420MDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 5420MEP & no Sb/Br) V62/07613-01XE ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 5420MEP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS5420-EP : •Catalog: TPS5420 •Automotive: TPS5420-Q1 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS5420MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS5420MDREP SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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