TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 2-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER CheckforSamples:TPS5420 FEATURES APPLICATIONS 1 • WideInputVoltageRange:5.5Vto36V • Consumer:Set-topBox,DVD,LCDDisplays • Upto2-AContinuous(3-APeak)Output • IndustrialandCarAudioPowerSupplies Current • BatteryChargers,HighPowerLEDSupply • HighEfficiencyupto95%Enabledby110-mΩ • 12-V/24-VDistributedPowerSystems IntegratedMOSFETSwitch • WideOutputVoltageRange:AdjustableDown DESCRIPTION to1.22Vwith1.5%InitialAccuracy The TPS5420 is a high-output-current PWM • InternalCompensationMinimizesExternal converter that integrates a low resistance high side PartsCount N-channel MOSFET. Included on the substrate with the listed features is a high performance voltage error • Fixed500-kHzSwitchingFrequencyforSmall amplifier that provides tight voltage regulation FilterSize accuracy under transient conditions; an undervoltage- • ImprovedLineRegulationandTransient lockout circuit to prevent start-up until the input ResponsebyInputVoltageFeedForward voltage reaches 5.5 V; an internally set slow-start circuit to limit inrush currents; and a voltage feed- • SystemProtectedbyOverCurrentLimiting, forward circuit to improve the transient response. OverVoltageProtectionandThermal Using the ENA pin, shutdown supply current is Shutdown reduced to 18 μA typically. Other features include an • –40°Cto125°COperatingJunction active-high enable, overcurrent limiting, overvoltage TemperatureRange protection and thermal shutdown. To reduce design • AvailableinSmall8-PinSOICPackage complexity and external component count, the TPS5420feedbackloopisinternallycompensated. The TPS5420 device is available in an easy to use 8- pin SOIC package. TI provides evaluation modules and the Designer software tool to aid in quickly achieving high-performance power supply designs to meetaggressiveequipmentdevelopmentcycles. Simplified Schematic Efficiency vs Output Current 100 VIN VOUT VIN PH 95 TPS5420 90 NC BOOT % 85 NC cy− 80 VI= 12 V en 75 ci ENA VSENSE Effi 70 GND 65 60 55 50 0 0.5 1 1.5 2 2.5 3 IO-Output Current-A 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION T INPUTVOLTAGE OUTPUTVOLTAGE PACKAGE(1) PARTNUMBER J –40°Cto125°C 5.5Vto36V Adjustableto1.22V SOIC(D)(2) TPS5420D (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) TheDpackageisavailabletapedandreeled.AddanRsuffixtothedevicetype(i.e.,TPS5420DR). ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) (2) VALUE UNIT VIN –0.3to40(3) BOOT –0.3to50 PH(steady-state) –0.6to40(3) V Inputvoltagerange EN –0.3to7 V I VSENSE –0.3to3 BOOT-PH 10 PH(transient<10ns) –1.2 I Sourcecurrent PH InternallyLimited O I Leakagecurrent PH 10 μA lkg T Operatingvirtualjunctiontemperaturerange –40to150 °C J T Storagetemperature –65to150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesarewithrespecttonetworkgroundterminal. (3) ApproachingtheabsolutemaximumratingfortheVINpinmaycausethevoltageonthePHpintoexceedtheabsolutemaximumrating. THERMAL INFORMATION TPS5420 THERMALMETRIC(1)(2)(3) UNITS D(8PINS) θ Junction-to-ambientthermalresistance(customboard) (4) 75 JA θ Junction-to-ambientthermalresistance(standardboard) 105.9 JA ψ Junction-to-topcharacterizationparameter 5.7 JT ψ Junction-to-boardcharacterizationparameter 47.0 °C/W JB θ Junction-to-case(top)thermalresistance 45.0 JC(top) θ Junction-to-case(bottom)thermalresistance n/a JC(bottom) θ Junction-to-boardthermalresistance 47.8 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) Maximumpowerdissipationmaybelimitedbyovercurrentprotection (3) PowerratingataspecificambienttemperatureT shouldbedeterminedwithajunctiontemperatureof125°C.Thisisthepointwhere A distortionstartstosubstantiallyincrease.ThermalmanagementofthefinalPCBshouldstrivetokeepthejunctiontemperatureator below125°Cforbestperformanceandlong-termreliability.SeeThermalCalculationsinapplicationssectionofthisdatasheetformore information. (4) Testboardsconditions: (a)3inx3in,2layers,thickness:0.062inch. (b)2oz.coppertraceslocatedonthetopandbottomofthePCB. 2 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT V Inputvoltagerange,VIN 5.5 36 V I T Operatingjunctiontemperature –40 125 °C J ELECTRICAL CHARACTERISTICS T =–40°Cto125°C,VIN=5.5Vto36V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) VSENSE=2V,Notswitching,PHpin 3 4.4 mA I Quiescentcurrent open Q Shutdown,ENA=0V 18 50 μA UNDERVOLTAGELOCKOUT(UVLO) Startthresholdvoltage,UVLO 5.3 5.5 V Hysteresisvoltage,UVLO 330 mV VOLTAGEREFERENCE T =25°C 1.202 1.221 1.239 J Voltagereferenceaccuracy V I =0A–2A 1.196 1.221 1.245 O OSCILLATOR Internallysetfree-runningfrequency 400 500 600 kHz Minimumcontrollableontime 150 200 ns Maximumdutycycle 87% 89% ENABLE(ENAPIN) Startthresholdvoltage,ENA 1.3 V Stopthresholdvoltage,ENA 0.5 V Hysteresisvoltage,ENA 450 mV Internalslow-starttime(0~100%) 6.6 8 10 ms CURRENTLIMIT Currentlimit 3 4 5 A Currentlimithiccuptime 13 16 20 ms THERMALSHUTDOWN Thermalshutdowntrippoint 135 162 °C Thermalshutdownhysteresis 14 °C OUTPUTMOSFET VIN=5.5V 150 r HighsidepowerMOSFETswitch mΩ DS(on) VIN=10V-36V 110 230 Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com PIN ASSIGNMENTS DPACKAGE (TOPVIEW) BOOT 1 8 PH NC 2 7 VIN NC 3 6 GND VSENSE 4 5 ENA TERMINALFUNCTIONS TERMINAL DESCRIPTION NAME NO. BOOT 1 Boostcapacitorforthehigh-sideFETgatedriver.Connect0.01μFlowESRcapacitorfromBOOTpintoPHpin. NC 2,3 Notconnectedinternally. VSENSE 4 Feedbackvoltagefortheregulator.Connecttooutputvoltagedivider. ENA 5 On/offcontrol.Below0.5V,thedevicestopsswitching.Floatthepintoenable. GND 6 Ground. Inputsupplyvoltage.BypassVINpintoGNDpinclosetodevicepackagewithahighquality,lowESRceramic VIN 7 capacitor. PH 8 SourceofthehighsidepowerMOSFET.Connectedtoexternalinductoranddiode. 4 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 TYPICAL CHARACTERISTICS OSCILLATORFREQUENCY OPERATINGQUIESCENTCURRENT MINIMUMCONTROLLABLEONTIME vs vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 530 3.5 180 520 mA VI= 12 V 170 fOscillator −Frequency−kHz 455447018900000 IOperatin−g Quiescent Current−Q 32..27553 Minimum Controllable On Time−ns 111156340000 446600 2.5 120 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure1. Figure2. Figure3. VOLTAGEREFERENCE ONSTATERESISTANCE INTERNALSLOWSTARTTIME vs vs vs JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE JUNCTIONTEMPERATURE 11..2233 180 9 170 VI= 12 V Wm 160 ms V−V−Voltage ReferVoltage Reference−Vence−Vrefref 1111....112222..212122555522 rO−n-State Resistance−DS(on) 11111115923400000000 tIntern−al Slow Start Time−SS 87..558 11..2211 -50 -25 0 25 50 75 100 125 80-50 -25 0 25 50 75 100 125 7 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure4. Figure5. Figure6. SHUTDOWNQUIESCENTCURRENT MINIMUMCONTROLLABLEDUTYRATIO vs vs INPUTVOLTAGE JUNCTIONTEMPERATURE 25 8 ENA= 0 V −Am 20 TJ= 125oC 7.5 nt % e − Curr atio own 15 TJ= 27oC uty R 7.5 d D Shut mum I−SD 10 Mini 7.25 TJ= -40oC 5 7 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125 VI−Input Voltage−V TJ−Junction Temperature−oC Figure7. Figure8. Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN UVLO 1.22R1e Vfe Breanncdegap VREF Slow Start SHDN ReBgouolattor BOOT HICCUP 5µA ENA ENABLE SHDN SHDN VSENSE Z1 Thermal Protection SHDN SHDN AmErprolifrier Z2 Ramp NC VIN Generator Feed Forward Gain = 25 NC SHDN PWM HICCUP Comparator GND Overcurrent SHDN Oscillator Protection SHDN Gate Drive VSENSE OVP Control 112.5% VREF Gate Driver SHDN BOOT PH VOUT DETAILED DESCRIPTION OscillatorFrequency The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching frequency allows less output inductance for the same output ripple requirement resulting in a smaller output inductor. VoltageReference The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of 1.221Vatroomtemperature. Enable(ENA)andInternalSlowStart The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin to ground or to any voltage less than 0.5 V disables the regulator and activate the shutdown mode. The quiescentcurrentoftheTPS5420inshutdownmodeistypically18 μA. The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0V to its finalvaluelinearly.Theinternalslowstarttimeis8mstypically. 6 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 UndervoltageLockout(UVLO) The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates untilVINfallsbelowtheUVLOstopthresholdvoltage.ThetypicalhysteresisintheUVLOcomparatoris330mV. BoostCapacitor(BOOT) Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable valuesovertemperature. OutputFeedback(VSENSE) The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage reference1.221V. InternalCompensation The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 uses voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover frequency and a high phase margin for good stability. See the Internal Compensation Network in the applications sectionformoredetails. VoltageFeedForward The internal voltage feed forward provides a constant DC power stage gain despite any variations with the input voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constantatthefeedforwardgain,i.e. VIN Feed Forward Gain = Ramp pk-pk (1) ThetypicalfeedforwardgainofTPS5420is25. Pulse-Width-Modulation(PWM)Control The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and compensationnetworktoproduceaerrorvoltage.Then,theerrorvoltageiscomparedtotherampvoltagebythe PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle. Finally,thePWMoutputisfedintothegatedrivecircuittocontroltheon-timeofthehigh-sideMOSFET. OvercurrentLimiting Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system willignoretheovercurrentindicatorfortheleadingedgeblankingtimeatthebeginningofeachcycletoavoidany turn-onnoiseglitches. Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for the rest of the cycle after a propagation delay. The overcurrent limiting scheme is called cycle-by-cycle current limiting. Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup mode overcurrentlimiting.Duringhiccupmodeovercurrentlimiting,thevoltagereferenceisgroundedandthehigh-side MOSFETisturnedoffforthehiccuptime.Oncethehiccuptimedurationiscomplete,theregulatorrestartsunder controloftheslowstartcircuit. Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com OvervoltageProtection The TPS5420 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side MOSFETwillbeenabledagain. ThermalShutdown The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction temperaturedrops14°Cbelowthethermalshutdowntrippoint. PCBLayout Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitorascloseaspossibletotheVINpin.Theminimumrecommendedbypasscapacitanceis4.7μFceramic withaX5RorX7Rdielectric. There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground areaunderthedeviceasshowninFigure9. The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor minimizedtopreventexcessivecapacitivecoupling.Thecatchdiodeshouldalsobeplacedclosetothedeviceto minimizetheoutputcurrentlooparea.ConnectthebootcapacitorbetweenthephasenodeandtheBOOTpinas shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placementsandconnectionsshownworkwell,butotherconnectionroutingsmayalsobeeffective. Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the loopformedbythePHpin,Lout,CoutandGNDassmallasispractical. Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the outputcapacitorisnotdesired. IfthegroundingschemeshownisusedviaaconnectiontoadifferentlayertoroutetotheENApin. 8 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 PH CATCH DIODE BOOT CAPACITOR INPUT INPUT BYPASS BULK BOOT PH CAPACITOR FILTER OUTPUT Vin INDUCTOR NC VIN NC GND RESISTOR VSENSE ENA DIVIDER VOUT OUTPUT FILTER TOPSIDE GROUND AREA CAPACITOR VIA to Ground Plane Route feedback trace under the output Signal VIA filter capacitor or on the other layer. Figure9. DesignLayout Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com 0 5 0 0.220 0. 6 2 0 0. 0.080 All dimensions in inches Figure10. TPS5420LandPattern ApplicationCircuits Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output currentatanominaloutputvoltageof5V. U1 TPS5420D C2 TP5 L1 VIN 10 V - 35 V 7 VIN 1 0.01mF 33mH 5 V 5 BOOT VOUT ENA ENA C1 C4 2 NC PH 8 D1 + C3 4.7mF 4.7mF 3 NC 4 B340A 100mF R1 6 VSNS (See NoteA) 10 kW GND R2 3.24 kW A. C3=TantalumAVXTPSD107M010R0080 Figure11. ApplicationCircuit,10-V —35Vto5-V 10 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 DesignProcedure The following design procedure can be used to select component values for the TPS5420. Alternately, the Designer Software may be used to generate a complete design. The Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presentsasimplifieddiscussionofthedesignprocess. Tobeginthedesignprocess,afewparametersmustbedetermined.Thedesignermustknowthefollowing: • Inputvoltagerange • Outputvoltage • Inputripplevoltage • Outputripplevoltage • Outputcurrentrating • Operatingfrequency DesignParameters Forthisdesignexample,usethefollowingastheinputparameters: DESIGNPARAMETER(1) EXAMPLEVALUE Inputvoltagerange 10Vto36V Outputvoltage 5V Inputripplevoltage 300mV Outputripplevoltage 30mV Outputcurrentrating 2A Operatingfrequency 500kHz (1) Asanadditionalconstraint,thedesignissetuptobesmallsizeandlowcomponentheight. SwitchingFrequency The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching frequency. InputCapacitors The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The recommended value for the decoupling capacitor is 10 μF. A high quality ceramic type X5R or X7R is required. For some applications, a smaller value decoupling capacitor may be used, if the input voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage, including ripple. For this design, two 4.7 μF capacitors, C1 and C4 are used to allow for smaller 1812 case size tobeusedwhilemaintaininga50Vrating. ThisinputripplevoltagecanbeapproximatedbyEquation2: I x 0.25 OUT(MAX) DV = + ( I x E S R ) IN OUT(MAX) MAX C x ƒ BULK SW (2) Where I is the maximum load current, f is the switching frequency, C is the input capacitor value and OUT(MAX) SW I ESR isthemaximumseriesresistanceoftheinputcapacitor. MAX The maximum RMS ripple current also needs to be checked. For worst case conditions, this is approximated by Equation3: I OUT(MAX) I (cid:1) CIN 2 (3) Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com Inthisexample,thecalculatedinputripplevoltageis118mV,andtheRMSripplecurrentis1.0A.Themaximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actual measured input ripple voltage may be larger than the calculated value due to the output impedance of the input voltagesourceandparasiticsassociatedwiththelayout. CAUTION The maximum ratings for voltage and current are not to be exceeded under any circumstance. Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located within approximately 2 inches from the input voltage source. The value for this capacitor is not critical but it should be ratedtohandlethemaximuminputvoltageincludingripplevoltageandshouldfiltertheoutputsothatinputripple voltageisacceptable. OutputFilterComponents Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internally compensateddevice,alimitedrangeoffiltercomponenttypesandvaluescanbesupported. InductorSelection Tocalculatetheminimumvalueoftheoutputinductor,useEquation4: ( ) V x V - V OUT IN(MAX) OUT L = MIN V x K x I x F x 0.8 IN(max) IND OUT SW (4) K is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. IND Three things need to be considered when determining the amount of ripple current in the inductor: the peak to peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current, and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using the TPS5420, K of 0.2 to 0.3 yields good results. Low output ripple voltages is obtained when paired with the IND proper output capacitor, the peak switch current is below the current limit set point, and low load currents can be sourcedbeforediscontinuousoperation. For this design example, use K = 0.2, and the minimum inductor value is 27 μH. The standard value used in IND thisdesignis33μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. TheRMSinductorcurrentcanbefoundfromEquation5: (cid:7) 2 2 1 (cid:5) VOUT(cid:1)(cid:5)VIN(MAX)(cid:3)VOUT(cid:6) (cid:6) IL(RMS)(cid:4) IOUT(MAX)(cid:2)12(cid:1) VIN(MAX)(cid:1)LOUT(cid:1)FSW(cid:1)0.8 (5) andthepeakinductorcurrentcanbedeterminedusingEquation6: ( ) V x V - V OUT IN(MAX) OUT I = I + L(PK) OUT(MAX) 1.6 x V x L x F IN(MAX) OUT SW (6) For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The chosen inductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 μH. It has a saturation current rating of 2.2 A and a RMS current rating of 2.7 A, which meets the requirements. Inductor values for use with the TPS5420areintherangeof10μHto100μH. 12 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 CapacitorSelection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the designoftheinternalcompensation,itisrecommendedtokeeptheclosedloopcrossoverfrequencyintherange 3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design example, the intended closed loop crossover frequency is between 2590 Hz and 24 kHz, and below the ESR zero of the output capacitor. Under these conditions, the closed loop crossover frequency is related to the LC cornerfrequencyas: f 2 f (cid:1) LC CO 85V OUT (7) andthedesiredoutputcapacitorvaluefortheoutputfilterto: C (cid:2) 1 OUT 3357(cid:1)L (cid:1)f (cid:1)V OUT CO OUT (8) For a desired crossover of 18 kHz and a 33-μH inductor, the calculated value for the output capacitor is 100 μF. ThecapacitortypeshouldbechosensothattheESRzeroisabovetheloopcrossover.ThemaximumESRis: ESR (cid:2) 1 MAX 2(cid:1)(cid:1)C (cid:1)f OUT CO (9) The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter. Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output ripplevoltage: ( ) ESR x V x V - V MAX OUT IN(MAX) OUT V (MAX) = PP N x V x L x F x 0.8 C IN(MAX) OUT SW (10) Where: ΔV isthedesiredpeak-to-peakoutputripple. PP N isthenumberofparalleloutputcapacitors. C F istheswitchingfrequency. SW The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and 54kHz. The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the outputcapacitorisgivenbyEquation11: [ ] ( ) V x V - V 1 OUT IN(MAX) OUT I = x COUT(RMS) Ö12 V x L - F x 0.8 x N IN(MAX) OUT SW C (11) Where: N isthenumberofoutputcapacitorsinparallel. C F istheswitchingfrequency. SW Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com For this design example, a single 100-μF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is a AVX TPSD107M010R0080, rated at 10 V with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This capacitor results in a peak-to-peak output ripple of 26 mV using equation 10. An additional small 0.1-μF ceramic bypasscapacitormayalsoused,butisnotincludedinthisdesign. OthercapacitortypescanbeusedwiththeTPS5420,dependingontheneedsoftheapplication. OutputVoltageSetpoint The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin. CalculatetheR2resistorvaluefortheoutputvoltageof5VusingEquation12: R2 (cid:3) R1(cid:1)1.221 V (cid:2) 1.221 OUT (12) ForanyTPS5420design,startwithanR1valueof10kΩ.R2isthen3.24kΩ. BootCapacitor Thebootcapacitorshouldbe0.01 μF. CatchDiode The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak-to-peakinductorcurrent.Forwardvoltagedropshouldbesmallforhigherefficiencies.Itisimportanttonote that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of 3A,andaforwardvoltagedropof0.5V. AdditionalCircuits Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar to those given for the design example, with a larger value output inductor and a lower closed loop crossover frequency. U1 L1 TPS5420D C2 TP5 10 V - 21 V 27mH 7 0.01mF VIN VIN 1 5 V 5 BOOT VOUT ENA ENA C1 2 8 + 10mF NC PH D1 C3 3 R1 6 NC VSNS 4 B340A 1(S0e0e NmoFteA) 10 kW GND R2 3.24 kW A. C3=TantalumAVXTPSD107M010R0080 Figure12. 10-V—21-VInputto5-VOutputApplicationCircuit 14 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 CircuitUsingCeramicOutputFilterCapacitors Figure13showsanapplicationcircuitusingallceramiccapacitorsfortheinputandoutputfilterswhichgenerates a 3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design example, except for the selection of the output filter capacitor values and the design of the additional compensation componentsrequiredtostabilizethecircuit. VIN 10-24 V U1 C2 L1 7 TPS5420D 0.01mF 18mH VIN VIN 1 3.3 V 5 BOOT VOUT EN ENA C1 2 8 NC PH D1 C3 C4 4.7mF 3 MRBS340 47mF 47mF NC 4 VSNS 6 GND PwPd 9 R1 C7 10 kW 0.1mF C4 R2 150 pF 5.9 kW R3 C6 1800 pF 549W Figure13. CeramicOutputFilterCapacitorsCircuit OutputFilterComponentSelection UsingEquation11,theminimuminductorvalueis17.9 μH.Avalueof18μHischosenforthisdesign. When using ceramic output filer capacitors, the recommended LC resonant frequency should be no more than 7kHz.Sincetheoutputinductorisalreadyselectedat18 μH,thislimitstheminimumoutputcapacitorvalueto: 1 C (MIN) ³ O (2p x 7000) 2 x L O (13) The minimum capacitor value is calculated to be 29 μF. For this circuit a larger value of capacitor yields better transient response. Two 47 μF output capacitors are used for C3 and C4. It is important to note that the actual capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to 3.3V,minimizingthiseffect. ExternalCompensationNetwork When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this circuit, the external components are R3, C5, C6, and C7. To determine the value of these components, first calculatetheLCresonantfrequencyoftheoutputfilter: 1 F = LC 2pÖ L x C (EFF) O O (14) Forthisexampletheeffectiveresonantfrequencyiscalculatedas4109Hz The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole andzerolocationsaregivenbythefollowingequations: Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com V O Fp1 = 500000 x F LC (15) Fz1 = 0.7 x F LC (16) Fz2 = 2.5 x F LC (17) The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower. Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as calculated usingEquation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 426 Hz, Fz1 = 2708 Hz and Fz2 = 8898 Hz, the values of R3, C6 and C7 are determined using Equation 18, Equation 19, and Equation20: 1 C7 = 2p x Fp1 x (R1 || R2) (18) 1 R3 = 2p x Fz1 x C7 (19) 1 C6 = 2p x Fz2 x R1 (20) For this design, using the closest standard values, C7 is 0.1 μF, R3 is 590 Ω, and C6 is 1800 pF. C5 is added to improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole frequency, so it should be small in relationship to C6. C5 should be less the 1/10 the value of C6. For this example,150pFworkswell. For additional information on external compensation of the TPS5420 or other wide voltage range devices, see SLVA237 UsingTPS5410/20/30/31WithAluminum/CeramicOutputCapacitors ADVANCED INFORMATION OutputVoltageLimitations Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% andisgivenby: VOUTMAX(cid:4)0.87(cid:1)(cid:5)(cid:5)VINMIN(cid:3)IOMAX(cid:1)0.230(cid:6)(cid:2)VD(cid:6)(cid:3)(cid:5)IOMAX(cid:1)RL(cid:6)(cid:3)VD (21) Where: V =minimuminputvoltage INMIN I =maximumloadcurrent OMAX V =catchdiodeforwardvoltage. D R =outputinductorseriesresistance. L ThisequationassumesmaximumonresistancefortheinternalhighsideFET. The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximateminimumoutputvoltageforagiveninputvoltageandminimumloadcurrentisgivenby: VOUTMIN(cid:4)0.12(cid:1)(cid:5)(cid:5)VINMAX(cid:3)IOMIN(cid:1)0.110(cid:6)(cid:2)VD(cid:6)(cid:3)(cid:5)IOMIN(cid:1)RL(cid:6)(cid:3)VD (22) Where: V =maximuminputvoltage INMAX I =minimumloadcurrent OMIN V =catchdiodeforwardvoltage. D R =outputinductorseriesresistance. L This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be checkedtoassureproperfunctionality. 16 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 InternalCompensationNetwork The design equations given in the example circuit can be used to generate circuits using the TPS5420. These designs are based on certain assumptions, and always select output capacitors within a limited range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the TPS5420. Equation 23 gives the nominal frequency response of the internal voltage-mode type III compensation network: (cid:4)1(cid:2)2(cid:1)(cid:1)sFz1(cid:5)(cid:1)(cid:4)1(cid:2)2(cid:1)(cid:1)sFz2(cid:5) H(s)(cid:3) (cid:4) s (cid:5) (cid:4) s (cid:5) (cid:4) s (cid:5) (cid:4) s (cid:5) 2(cid:1)(cid:1)Fp0 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp1 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp2 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp3 (23) Where Fp0=2165Hz,Fz1=2170Hz,Fz2=2590Hz Fp1=24kHz,Fp2=54kHz,Fp3=440kHz Fp3representsthenon-idealparasiticseffect. Using this information along with the desired output voltage, feed forward gain and output filter characteristics, theclosedlooptransferfunctioncanbederived. ThermalCalculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations.Theyshouldnotbeusedifthedeviceisworkingatlightloadsinthediscontinuousconductionmode. ConductionLoss: Pcon=I 2xR xV /V OUT DS(on) OUT IN SwitchingLoss: Psw=V xI x0.01 IN OUT QuiescentCurrentLoss: Pq=V x0.01 IN TotalLoss:Ptot=Pcon+Psw+Pq GivenT =>EstimatedJunctionTemperature:T =T +RthxPtot A J A GivenT =125°C=> EstimatedMaximumAmbientTemperature: T =T –RthxPtot JMAX AMAX JMAX Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com PERFORMANCE GRAPHS The performance graphs in Figure 14 - Figure 20 are applicable to the circuit in Figure 11. T = 25°C. unless A otherwisespecified. 100 0.3 0.3 VI= 10.8 V 0.2 0.2 95 VI= 12 V VI= 15 V IO= 2A % % ciency - % 90 egulation - 0.01 egulation - 0.01 IO=0A Effi 85 ut R ut R VI= 18 V VI= 19.8 V Outp -0.1 Outp -0.1 IO= 1A 80 -0.2 -0.2 75 -0.3 -0.3 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 IO- Output Current -A IO- Output Current -A VI- Input Voltage - V Figure14.Efficiencyvs.Output Figure15.OutputRegulation% Figure16.InputRegulation%vs. Current vs.OutputCurrent InputVoltage VIN= 100 mV/Div (AC Coupled) VOUT= 20 mV/Div (AC Coupled) V = 50 mV/Div (AC Coupled) OUT PH = 5 V/Div PH = 5 V/Div IOUT= 500 mA/Div t- Time - 1ms / Div t- Time - 1ms / Div t - Time = 200μs/Div Figure17.InputVoltageRipple Figure18.OutputVoltageRipple Figure19.TransientResponse, andPHNode,I =3A andPHNode,I =3A IoStep0.5to1.5A O O 18 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

TPS5420 www.ti.com SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 V = 10 V/Div IN ENA = 2 V/Div V = 2 V/Div OUT V = 2 V/Div OUT t - Time = 5 ms/Div t - Time = 5 ms/Div Figure20.StartupWaveform,V andV Figure21.StartupWaveform,ENAandV IN OUT OUT Copyright©2006–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS5420

TPS5420 SLVS642E–APRIL2006–REVISEDSEPTEMBER2013 www.ti.com REVISION HISTORY ChangesfromOriginal(April2006)toRevisionA Page • AddedNote3totheABSOLUTEMAXIMUMRATINGStable ............................................................................................. 2 ChangesfromRevisionA(August2006)toRevisionB Page • AddedtheCircuitUsingCeramicOutputFilterCapacitorssection .................................................................................... 15 ChangesfromRevisionB(November2006)toRevisionC Page • ChangedFrom:K =0.2,andtheminimuminductorvalueis31μHTo:K =0.2,andtheminimuminductor IND IND valueis27μH ..................................................................................................................................................................... 12 ChangesfromRevisionC(October2007)toRevisionD Page • ReplacedtheDISSIPATIONRATINGSwiththeTHERMALINFORMATIONtable ............................................................. 2 ChangesfromRevisionD(January2013)toRevisionE Page • DeletedSWIFTfromthedatasheetTitle,Features,andDescription .................................................................................. 1 20 SubmitDocumentationFeedback Copyright©2006–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS5420

PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (3) (4/5) TPS5420D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5420 & no Sb/Br) TPS5420DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5420 & no Sb/Br) TPS5420DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5420 & no Sb/Br) TPS5420DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5420 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS5420 : •Automotive: TPS5420-Q1 •Enhanced Product: TPS5420-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS5420DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS5420DR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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