TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 1-A 60-V STEP-DOWN DC/DC CONVERTER WITH LOW QUIESCENT CURRENT CheckforSamples:TPS54162-Q1 FEATURES 1 • AsynchronousSwitchModeRegulator • ProgrammableOvervoltage,Undervoltage • 3.6Vto48VOperatingRange,Withstands OutputMonitor Transientsupto60V • ThermalSensingandShutdown • 1AMaximumLoadCurrent • SwitchCurrentLimitProtection • 50µATypicalQuiescentCurrent • ShortCircuitandOvercurrentProtectionof • 200kHzto2.2MHzSwitchingFrequency FET • 0.8V±1.5%VoltageReference • JunctionTemperatureRange:–40°Cto150°C • HighVoltageTolerantEnableInput • 20-PinHTSSOPPowerPAD™Package • SoftStartonEnableCycle APPLICATIONS • SlewRateControlonInternalPowerSwitch • QualifiedforAutomotiveApplications • Low-PowerModeforLightLoadConditions • AutomotiveTelematics • ProgrammableDelayforPower-OnReset • NavigationSystems • ExternalCompensationforErrorAmplifier • In-DashInstrumentation • ResetFunctionFilterTimeforFastNegative • BatteryPoweredApplications Transients DESCRIPTION The TPS54162 is a step-down switch-mode power supply with a voltage supervisor and an integrated NMOS switching FET. Integrated input voltage line feed forward topology improves line transient regulation of the voltage mode buck regulator. The regulator has a cycle-by-cycle current limit. The device also features low-power mode operation under light load conditons which reduces the supply current to 50 µA (typical). By pullingtheENpinlow,thesupplyshutdowncurrentisreducedto1µA(typical). An open drain reset signal indicates when the nominal output drops below the reset threshold set by an external resistor divider network. The output voltage start up ramp is controlled by a soft start capacitor. There is an internal undervoltage shut down which is activated when the input supply ramps down to 2.6 V. The device is protected during an overload condition on output by frequency fold back operation, and also has a thermal shutdownprotection. TYPICALAPPLICATION TYPICALCONVERTEREFFICIENCY D1 TPS54162 90 VBATT VIN VReg C1 R11 VIN RST R12 RESET 80 VIN = 14 V EN BOOT 70 R10 C3 L PH VReg 60 VIN = 7 V RC76 SRLPYslMNeCw VSENSE D2 RC97 R4 C4 Efficiency - %4500 R8 SRST/CLK COMP C8R6 C5 R5 - h30 VfswRe=g =5 050 V kHz C2 RST_TH R1 20 LC == 2120 0µ HµF CGdNlDy OV_TH R2 10 RTAs=le 2w5 =°C 30 kW R3 0 0.05 0.25 0.5 0.75 1 ILoad- Load Current -A Figure1. Figure2. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) T PACKAGE(2) ORDERABLEPARTNUMBER TOP-SIDEMARKING J –40°Cto150°C TSSOP–PWP Reelof2000 TPS54162QPWPRQ1 54162Q1 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT Inputvoltage EN -0.3to60 V VIN -0.3to60 VReg -0.3to20 LPM -0.3to5.5 OV_TH -0.3to5.5 RST_TH -0.3to5.5 SYNC -0.3to5.5 VSENSE -0.3to5.5 Outputvoltage BOOT -0.3to65 V PH -0.3to60 -2for30ns -1for200ns -0.85atT =-40°C J -0.5atT =125°C J RT -0.3to5.5 RST -0.3to5.5 Cdly -0.3to8 SS -0.3to8 COMP -0.3to7 Temperature Operatingvirtualjunctiontemperaturerange,T -40to150 °C J Storagetemperaturerange,T -55to165 S Electrostaticdischarge(HBM)(2) 2 kV (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Allvoltage valuesarewithrespecttoGND. (2) Thehumanbodymodelisa100-pFcapacitordischargedthrougha1.5-kΩresistorintoeachpin. 2 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT V Unregulatedbucksupplyinputvoltage(VIN,EN) 3.6 48 V I Incontinuousconductionmode(CCM) 0.9 18 V VReg Regulatedoutputvoltage Powerupinlow-powermode(LPM)ordiscontinuousconduction 0.9 5.5 V mode(DCM) Bootstrapcapacitor(BOOT) 3.6 56 V Switchedoutputs(PH) 3.6 48 V Logiclevels(RST,VSENSE,OV_TH,RST_TH,Rslew,SYNC,RT) 0 5.25 V Logiclevels(SS,Cdly,COMP) 0 6.5 V q Thermalresistance,junctiontoambient(1) 35 °C/W JA q Thermalresistance,junctiontocase(2) 10 °C/W JC T Operatingjunctiontemperature(3) –40 150 °C J (1) ThisassumesaJEDECJESD51-5standardboardwiththermalviaswithHighKprofile–SeePowerPADsectionandapplicationnote fromTexasInstruments(SLMA002)formoreinformation. (2) Thisassumesjunctiontoexposedthermalpad. (3) ThisassumesT =T –powerdissipation×q . A J JA Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com DC ELECTRICAL CHARACTERISTICS VIN=7Vto48V,EN=VIN,T =–40°Cto150°C(unlessotherwisenoted) J TEST PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTPOWERSUPPLY Normalmode:afterinitialstartup 3.6 48 V Fallingthreshold 8 V (LPMdisabled) Info VIN SupplyvoltageonVIN Risingthreshold Low-powermode 8.5 V (LPMactivated) Highvoltagethreshold 29 31 34 V (LPMdisabled) Quiescentcurrent, Openlooptest–maximumdutycycle PT I 5 10 mA q-Normal normalmode VIN=7Vto48V T =25°C 50 70 µA A I <1mA,VIN=12V Load Quiescentcurrent, –40<TJ<150°C 75 µA PT I q-LPM low-powermode T =25°C 75 µA A I <1mA,VIN=24V Load –40<T <150°C 75 µA J PT I Shutdowncurrent EN=0V,deviceisoff T =25°C,VIN=12V 1 4 µA SD A TRANSITIONTIMES(LOWPOWER–NORMALMODES) Transitiondelay,normal CT t VIN=12V,V =5V,I =1Ato1mA 100 µs d1 modetolow-powermode Reg Load Transitiondelay,low-power CT t VIN=12V,V =5VI =1mAto1A 5 µs d2 modetonormalmode Reg Load SWITCHMODESUPPLY;V Reg Info V Regulatoroutput VSENSE=0.8V 0.9 18 V Reg ref CT VSENSE Feedbackvoltage V =0.9Vto18V(openloop) 0.788 0.8 0.812 V Reg PT R Internalswitchresistance MeasuredacrossVINandPH,I =500mA 500 mΩ DS(ON) Load Switchcurrentlimit,cycleby Info I VIN=12V 1.3 2.15 3 A CL cycle Info t Dutycyclepulsewidth BenchCHARonly 50 100 150 ON-Min ns Info t BenchCHARonly 100 200 250 OFF-Min PT f Switchingfrequency SetusingexternalresistoronRTpin 0.2 2.2 MHz sw PT Internaloscillatorfrequency f –10 10 % sw tolerance Info I Start-upcondition OV_TH=0V,V =10V 1 mA Sink Reg Info I Preventovershoot 0V<OV_TH<0.8V,V =10V 80 mA Limit Reg PT: Productiontested CT: Characterizationtestedonly,notproductiontested Info: Userinformationonly,notproductiontested 4 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 DC ELECTRICAL CHARACTERISTICS VIN=7Vto48V,EN=VIN,T =–40°Cto150°C(unlessotherwisenoted) J TEST PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ENABLE(EN) PT V Lowinputthresholdvoltage 0.7 V IL PT V Highinputthresholdvoltage 1.7 V IH EN=60V 100 135 µA PT I LeakagecurrentintoENterminal lkg EN=12V 8 15 µA RESETDELAY(Cdly) PT I Externalcapacitorchargecurrent EN=high 1.4 2 2.6 µA O PT V Switchingthresholdvoltage Outputvoltageinregulation 2 V Threshold LOW-POWERMODE(LPM) PT V Lowinputthresholdvoltage VIN=12V 0.7 V IL PT V Highinputthresholdvoltage VIN=12V 1.7 V IH PT I LeakagecurrentintoLPMterminal LPM=5V 65 95 µA lkg RESETOUTPUT(RST) PT t PORdelaytimer BasedonCdlycapacitor 3.6 7 ms/nF rdly PT VReg_RST ResetthresholdvoltageforV CheckRSToutput 0.768 0.832 V Reg PT t Filtertime DelaybeforeRSTisassertedlow 10 20 35 µs nRSTdly SOFTSTART(SS) PT I Soft-startsourcecurrent 40 50 60 µA SS SYNCHRONIZATION(SYNC) PT V Lowinputthresholdvoltage 0.7 V IL PT V Highinputthresholdvoltage 1.7 V IH PT I Leakagecurrent SYNC=5V 65 95 µA lkg VIN=12V,V =5V, CT SYNC(f ) Externalinputclockfrequency Reg 180 2200 kHz ext 180kHz<f <f <2×f <2.2MHz sw ext sw Info SYNC Externalclocktointernalclock Noexternalclock,VIN=12V,V =5V 32 µs trans Reg Externalclock=1MHz,VIN=12V, Info SYNC Internalclocktoexternalclock 2.5 µs trans V =5V Reg CT SYNC Minimumdutycycle 30 % CLK CT SYNC Maximumdutycycle 70 % CLK Rslew CT I Rslew=50kΩ 20 µA Rslew CT I Rslew=10kΩ 100 µA Rslew OVERVOLTAGESUPERVISORS(OV_TH) ThresholdvoltageforV during Reg Internalswitchisturnedoff 0.768 0.832 V PT VReg_OV overvoltage V =5V InternalpulldownonV ,OV_TH=1V 70(1) mA Reg Reg THERMALSHUTDOWN Thermalshutdownjunction CT T 175 °C SD temperature CT T Hysteresis 30 °C HYS PT: Productiontested CT: Characterizationtestedonly,notproductiontested (1) ThisisthecurrentflowingintotheVRegpinwhenvoltageatOV_THpinis1V. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com DEVICE INFORMATION PWPPACKAGE (TOPVIEW) NC 1 20 BOOT NC 2 19 VIN SYNC 3 18 VIN LPM 4 17 PH EN 5 16 VReg RT 6 15 COMP Rslew 7 14 VSENSE RST 8 13 RST_TH Cdly 9 12 OV_TH GND 10 11 SS Figure3. TERMINALFUNCTIONS NAME NO. I/O DESCRIPTION NC 1 NC Connecttoground. NC 2 NC Connecttoground. Externalsynchronizationclockinputtooverridetheinternaloscillatorclock.Aninternalpulldownof SYNC 3 I 62kΩ(typical)isconnectedtoground. Low-powermodecontrolusingdigitalinputsignal.Aninternalpulldownof62kΩ(typical)isconnected LPM 4 I toground. EN 5 I Enablepin,internallypulledup.Mustbeexternallypulledupordowntoenable/disablethedevice. RT 6 O Externalresistortogroundtoprogramtheinternaloscillatorfrequency. Rslew 7 O ExternalresistortogroundtocontroltheslewrateofinternalswitchingFET. Activelow,opendrainresetoutputconnectedtoexternalbiasvoltagethrougharesistor,assertedhigh RST 8 O afterthedevicestartsregulating. Cdly 9 O Externalcapacitortogroundtoprogrampoweronresetdelay. Groundpin,mustbeelectricallyconnectedtotheexposedpadonthePCBforproperthermal GND 10 O performance. SS 11 O Externalcapacitortogroundtoprogramsoftstarttime. Senseinputforovervoltagedetectiononregulatedoutput,anexternalresistornetworkisconnected OV_TH 12 I betweenVRegandgroundtoprogramtheovervoltagethreshold. Senseinputforundervoltagedetectiononregulatedoutput,anexternalresistornetworkisconnected RST_TH 13 I betweenVRegandgroundtoprogramtheresetandundervoltagethreshold. VSENSE 14 I Invertingnodeoferroramplifierforvoltagemodecontrol. COMP 15 O Erroramplifieroutputtoconnectexternalcompensationcomponents. VReg 16 I Internallow-sideFETtoloadoutputduringstartuporlimitovershoot. PH 17 O SourceoftheinternalswitchingFET. VIN 18 I Unregulatedinputvoltage.Pin18andpin19mustbeconnectedexternally. VIN 19 I Unregulatedinputvoltage.Pin18andpin19mustbeconnectedexternally. BOOT 20 O ExternalbootstrapcapacitortoPHtodrivethegateoftheinternalswitchingFET. 6 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 FUNCTIONALBLOCKDIAGRAM BOOT 20 LPM 4 Banredfgap 00..82 VV rreeff 7Rslew R7 D1 VIN Internal Internal 19 VBATT 18 Voltage supply VIN Rail 16 C1 R11 VReg C3 Gate Drive with 5 Over-Current Limit L R10 EN for Internal Switch PH 17 VReg Selectable Thermal RT 6 Oscillator Sensor D2 C4 R8 C7 ref Error R9 SYNC 3 amp - 14 VSENSE R4 Cdly SS R5 9 + 11 C8 C5 0.8 V ref C6 C2 Vreg 15 + 0.82 V ref COMP R6 R12 + 0.8 V ref - RST_TH R1 8 - 13 RST Voltage R2 C10 Reset with comp - 12 OV_TH GND DelayTimer 10 + 0.8 V ref R3 C9 Figure4. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com TYPICAL CHARACTERISTICS Efficiency Data of Power Supply FETSWITCHING FASTSLEWRATEONSWITCHINGFET 90 90 Rslew = 14 kW VIN=14V 80 80 70 70 Rslew = 30 kW % 60 60 - y % enc 50 y- 50 VIN=7V Effici 40 cienc 40 hh- Effi 30 - VReg=5V VIN = 14 V h¸ 30 fsw=500kHz 20 VReg= 5 V L=22µH fsw= 500 kHz 20 C=100µF L= 22 µH Rslew =30k¸W 10 C = 100 µF T = 25°C 10 TA=25°C A 0 0 0 0.25 0.5 0.75 1 0 0.25 0.5 0.75 1 I -LoadCurrent-A Load I -LoadCurrent-A Load Figure5. Figure6. LPM,QUIESCENTCURRENTVARIATION SHUTDOWNCURRENTVARIATION WITHTEMPERATURE WITHTEMPERATURE Figure7. Figure8. 8 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 TYPICAL CHARACTERISTICS (continued) Output Voltage Drop Out V DROPOUT OUTPUTVOLTAGETRACKING Reg Figure9. Figure10. NOTE • Power up (Start up): This curve shows the input voltage required to achieve the 5 V regulation duringpowerupovertherangeofloadcurrents(seeFigure10). • Power down (Tracking): This curve shows the input voltage at which the output voltage drops approximately by 0.7 V from the programmed 5 V regulated voltage (see Figure 10) or for low inputvoltages(trackingfunction)overtherangeofloadcurrents(seeFigure9). • InFigure5andFigure6,LandCareoutputinductorandcapacitorrespectively. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com TYPICAL CHARACTERISTICS (continued) VOLTAGEDROPONRslewFORCURRENTREFERENCE; INTERNALREFERENCEVOLTAGE (SLEWRATE/Rslew) Figure11. Figure12. CURRENTCONSUMPTIONWITHTEMPERATURE Figure13. 10 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 OVERVIEW The TPS54162 is a 60 V, 1 A DC/DC step down (buck) converter using voltage-control mode scheme. The device features supervisory function for power-on-reset during system power on. Once the output voltage has exceeded the threshold set by RST_TH pin, a delay of 1 ms/nF (based on capacitor value on Cdly terminal) is invoked before the RST line is released high. Conversely on power down, once the output voltage falls below the same set threshold, the RST line is pulled low only after a de-glitch filter of approximately 20 µs (typical) expires. This is implemented to prevent reset from being triggered due to fast transient line noise on the regulated output supply. Anovervoltagemonitorfunction,isusedtolimitregulatedoutputvoltagetothethresholdsetbyOV_THpin.Both the RST_TH and OV_TH monitoring voltages are set to be a pre-scale of the output voltage, and thresholds basedontheinternalbiasvoltagesofthevoltagecomparators(0.8Vtypical). DetectionofundervoltageontheregulatedoutputisbasedontheRST_THsettingandwillinvokeRSTlinetobe asserted low. Detection of overvoltage on the output is based on the OV_TH setting and will not invoke the RST linetobeassertedlow.However,theinternalswitchiscommandedtoturnOFF. In systems where power consumption is critical, low-power mode (LPM) is implemented to reduce the non-switchingquiescentcurrentduringlightloadconditions.Afterthedevicehasbeenoperatingindiscontinuous conduction mode (DCM) for at least 100 µs (typ), depending upon the load current, it may enter in pulse skip mode (PSM). The operation of when the device enters DCM is dependent on the selection of the external components. If thermal shutdown is invoked due to excessive power dissipation, the internal switch is disabled and the regulated output voltage starts to decrease. Depending on the load current, the regulated output voltage could decayandtheRST_THthresholdmayasserttheRSToutputlow. DETAILED DESCRIPTION The TPS54162 is a DC/DC converter using a voltage-control mode scheme with an input voltage feed-forward technique. The device can be programmed for a range of output voltages with a wide input voltage range. Below aredetailswithregardtosettingupthedevice,detailedfunctionalityandthemodesofoperation. Unregulated Input Voltage The input voltage is supplied through VIN pins (pin 18 and 19) which must be externally protected against voltage levels greater than 60 V and reverse input polarity. An external diode is connected to protect these pins from reverse input polarity. The input current drawn from this pin is pulsed, with fast rise and fall times. Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an inputfilterinductormayalsoberequired. NOTE For design considerations, VIN/V ratios should always be set such that the minimum Reg required duty cycle pulse (t ) is greater than 150 ns. The minimum off time (t ) is ON-Min OFF-Min 250nsforallconditions. Regulated Output Voltage The regulated output voltage (V ) is fed back to the device through VReg pin (pin 16). Typically, an output Reg capacitor of value within range of 10 µF to 400 µF is connected at this pin. It is also recommended to use a filter capacitor with low ESR characteristics to minimize ripple in regulated output voltage. The VReg pin is also internallyconnectedtoaloadof~100Ω,whichisturnedONinthefollowingconditions: • During startup condition, when the device is powered up with no-load, or whenever EN is toggled, the internal load connected to VReg pin is turned ON to charge the bootstrap capacitor to provide gate drive voltage to theswitchingtransistor. • During normal operating conditions, when the regulated output voltage (V ) exceeds the overvoltage Reg threshold (VReg_OV, preset by external resistors R1, R2, and R3), the internal load is turned ON, and this pinispulleddowntobringtheregulatedoutputvoltagedown. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com • When VIN is less than typical VIN falling threshold level while LPM is disabled. From device specifications, VINtypicalfallingthreshold(LPMdisabled)=8V(seeDCElectricalCharacteristics). • WhenRSTislow. Regulation/Feedback Voltage The regulated output voltage (V ) can be programmed by connecting external resistor network at VSENSE pin Reg (pin14).Theoutputvoltageisselectablebetween0.9Vto18Vaccordingtothefollowingrelationship: (1) Where, R4,R5=feedbackresistors(seeFigure4) V =0.8V(typical) ref TheoveralltoleranceoftheregulatedoutputvoltageisgivenbyEquation2. (2) Where, tol =toleranceofinternalreferencevoltage(tol =±1.5%) Vref Vref tol ,tol =toleranceoffeedbackresistorsR4,R5 R4 R5 For a tighter tolerance on V , lower-value feedback resistors can be selected. However, for proper Reg operation in low-power mode (see Modes of Operation), it is recommended to keep R4 + R5 around 250 kΩ (typical). TheoutputtrackingdependsupontheloadingconditionsandisexplainedinTable1andisshowninFigure10. Table1.LoadConditions LOADCONDITION OUTPUTTRACKING NominalloadinCCM V tracksVINapproximatelyas:V =95%(VIN–I ×0.5) Reg Reg Load Toenablethetrackingfeature,followingconditionsshouldbemet: Noload/lightloadinLPM 1)f <600kHz SW 2)V <8V,typical(relatedtoVINfallingthresholdwhenLPMisdisabled) Reg Modes of Operation TPS54162 operates in the following modes based on the output loading conditions, input voltage and LPM pin configuration.TheseoperatingconditionsandmodesofoperationsareshowninFigure14. Heavy Loading LPM Pin = Don’t care Active Mode CCM d n a ng Conditions PM Pin Status VerLLyPP LLMMiigg hhPPttii nnLL oo==aa HHddiiiingngghgh PSM ActPivSeM M +o dDeC DMCM PSM diL oa Light/ Very Light Loading L LPM Pin = Low LPM V when ~8.5 V ~32 V V when t <t t <t OFF OFF-Min ON ON-Min VIN Figure14. ModesofOperation 12 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 1)ActiveModeContinuousConductionMode(CCM) In this mode of operation the switcher operates in continuous conduction mode, and the inductor current is alwaysnon-zeroifthetotalloadcurrent(internalandexternal)isgreaterthanI showninEquation3. L_DISCONT IL_DISCONT=IL_LPM=(1-2D×fs)×wVR×Leg (3) Where, D=dutycycle L=outputinductor V =outputvoltage Reg f =switchingfrequency sw For VIN < 8.5 V, the device enables an internal ~100 Ω load. This, combined with the external load, can cause the device to enter into CCM even under light external loading conditions (see Figure 14). This mode of operationisshowninFigure15isalsocalledtheNormalmodeofoperation. Figure15.ActiveModeCCM Figure16.ActiveModeDCM 2)ActiveModeDiscontinuousConductionMode(DCM) In this mode of operation the switcher operates in discontinuous conduction mode, and the inductor current becomeszeroifthetotalloadcurrent(internalandexternal)islessthanI showninEquation4. L_DISCONT IL_DISCONT=IL_LPM=(1-2D×fs)×wVR×Leg (4) The device enters in this mode of operation when LPM pin is set high (i.e disabled) and output loading is less thanI .ThismodeofoperationisshowninFigure16. L_DISCONT 3)PulseSkipMode(PSM) In this mode of operation the switcher operates in discontinuous conduction mode, and the inductor current becomeszero.Thedeviceentersinthismodeofoperationinthefollowingconditions: • At low input voltages when V starts losing regulation and the OFF time (t ) of the switching FET tends to Reg OFF be close to or slightly less than the minimum OFF time (t ). If OFF time is much smaller than t , OFF-Min OFF-Min there is a risk that the part stops switching and regulation is lost until power is re-cycled with OFF time greater than t . This mode of operation is shown in Figure 18. Comparing Figure 17 and Figure 18, OFF-Min pulseskippingoccursinFigure18butnotinFigure17undersimilaroutputloadingconditions. VIN-ILoad´RDS(ON)<~VReg and ççæ1-VReg÷÷ö´ 1 >tOFF-Min è VIN ø fsw (5) Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com Figure17.ActiveModeCCM Figure18.PSMatLowVIN • Likewise, at higher input voltages when the ON time (t ) of the switching FET becomes close to or slightly ON less than the minimum ON time (t ) and the V start losing regulation, the device enters in PSM. If ON ON-Min Reg time is much smaller than t , there is a risk that the part stops switching and regulation is lost until power ON-Min isre-cycledwithONtimegreaterthant . ON-Min • At nominal input voltages during very light output loading. This mode of operation is shown in Figure 19. Comparing Figure 16 and Figure 19, in both cases the device is operating in discontinuous conduction mode; however, pulse skipping happens in Figure 19 because of very light output loading for similar input voltage. LPMpinmustbesethigh(i.e.,disabled)forthistohappen. Figure19. PSMatNominalVIN 4)LowPowerMode(LPM) In this mode of operation the device briefly operates in discontinuous conduction mode and then turns off until V < VReg_UV threshold and this cycle is repeated. The LPM pin must be enabled to enable LPM mode of Reg operation. When total load is less than I , the device operates in LPM for VIN ~8.5 V to ~32 V. This L_DISCONT modeofoperationisshowninFigure20andFigure21(zoomedout). 14 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 Figure20.LowPowerMode Figure21.LowPowerMode(ZoomIn) Any transition from low-power mode to active mode CCM occurs within 5 µs (typical). In low-power mode, the converter operates as a hysteretic controller with the threshold limits set by VReg_UV (see Equation 10, Figure 4 andFigure22),forthelowerlimitand~V fortheupperlimit.Toensuretightregulationinthelow-powermode, Reg R2 and R3 values are set accordingly (see discussion on Noise Filter on RST_TH and OV_TH Terminals). The device operates in both automatic (LPM pin is connected to ground) and digitally controlled (status of LPM pin is controlled by an external device, for example by a microcontroller) low-power mode. The digital low-power mode can over-ride the automatic low-power mode function by applying the appropriate signal on the LPM terminal. ThepartgoesintoactivemodeCCMforatleast100µs,wheneverRST_THorVReg_UVistripped. Table2.LPMPinStatus LPMPINSTATUS MODESOFOPERATION Deviceisforcedinnormalmode. Atlightloads,thedeviceoperatesinDCMwithaswitchingfrequencydeterminedbytheexternal High resistorconnectedtoRTpin. Atverylightloads,thedeviceoperatesinPSMwithareducedswitchingfrequency(seeFigure14). Deviceautomaticallychangesbetweennormalmodeandlow-powermodedependingontheload Loworopen current. Table3.ModesofOperation MODESOFOPERATION DESCRIPTION Allcircuitsincludingovervoltagethresholdcircuit(OV_TH)areenabled. Atheavyloads,thedeviceoperatesincontinuousconductionmodeirrespectiveofthestatusofLPM Normalmode(activemode) pin. OR Atlightloads,thedeviceoperatesindiscontinuousconductionmode(DCM)onlyifLPMpinisexternally sethigh. OV_THcircuitisdisabled. Low-powermode ThedeviceisinDCM,andLPMpinshouldbeforcedlow. When the device is operating in low-power mode, and if the output is shorted to ground, a reset is asserted. The thermal shutdown and current limiting circuitry is activated to protect the device. The LPM pin is active low and is internally pulled down; therefore, the low-power mode is automatically enabled unless this pin is driven high externally (for example, by a microcontroller) and the device is in continuous conduction mode. However, the low-power mode operation is initiated only when the device enters discontinuous mode of operation at light loads,andtheLPMpinislow(orconnectedtoground). Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com 5)HystereticMode The device enters in this mode of operation when the main loop fails to respond during line/ load transients and regulate within specified tolerances. The device exits this mode of operation when the main control loop responds,aftertheerroramplifierstabilizes,andcontrolstheoutputvoltagewithintightertolerance. ThepowerupconditionsindifferentmodesofoperationsareexplainedinTable4. Table4.Power-UpConditions MODEOFOPERATION POWER-UPCONDITIONS CCM VIN>3.6V(minimum) LPM/DCM V <5.5Vand(VIN-V )>2.5V(applicableonlyforf >600kHz) Reg Reg sw Output Tolerances in Different Modes of Operation Figure22. Table5. MODEOFOPERATION VRegLOWERLIMIT VRegUPPERLIMIT COMMENTS Hystereticmode VReg_UV VReg_OV Minimumtomaximumrippleonoutput Low-powermode VReg_UV VReg+tolVReg Minimumtomaximumrippleonoutput Activemode(Normal) VReg–tolVReg VReg+tolVReg Minimumtomaximumrippleonoutput Table6. SUPERVISOR VRegTYPICAL TOLERANCE COMMENTS THRESHOLDS VALUE VReg_OV Overvoltagethresholdsetting VReg_RST Resetthresholdsetting 16 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 Enable and Shutdown The EN pin (pin 5) provides electrical ON/OFF control of the regulator. Once the EN pin voltage exceeds the upper threshold voltage (V ), the regulator starts operating and the internal soft start begins to ramp. If the EN IH pin voltage is pulled below the lower threshold voltage (V ), the regulator stops switching and the internal soft IL start resets. Connecting this pin to ground or to any voltage less than V disables the regulator and causes the IL devicetoshutdown.Thispinmusthaveanexternalpulluporpulldowntochangethestateofthedevice. Soft Start An external soft start capacitor is connected to SS pin (pin 11) to set the minimum time to reach the desired regulated output voltage (V ) during power up cycle. This prevents the output voltage from overshooting when Reg the device is powered up. This is also useful when the load requires a controlled voltage slew rate, and also helpstolimitthecurrentdrawnfromtheinputvoltagesupplyline. Forproperoperation,thefollowingconditionsmustbesatisfiedduringpower-upandafterashortcircuitevent: • VIN– V >2.5V Reg • Loadcurrent< 1A,untilRSTgoeshigh Therecommendedvalueofsoftstartcapacitoris100nF(typical)forstartuploadcurrentof1A(maximum). Oscillator Frequency The oscillator frequency can be set by connecting an external resistor (R8 in Figure 4) to RT pin (pin 6) . Figure 23 shows the relation between the resistor value (RT) and switching frequency (f ). The switching sw frequency can be set in the range 200 kHz to 2200 kHz. In addition, the switching frequency can be imposed externallybyaclocksignal(f )attheSYNCpin. ext SelectingtheSwitchingFrequency A power supply switching at a higher switching frequency allows use of lower value inductor and smaller output capacitor compared to a power supply that switches at a lower frequency. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The switching frequencythatcanbeselectedislimitedbythefollowingfactors: • Theinputvoltage • Theminimumtargetregulatedvoltage • Minimumon-timeoftheinternalswitchingtransistor • Frequencyshiftlimitation Selecting lower switching frequency results in using an inductor and capacitor of a larger value, where as selecting higher switching frequency results in higher switching and gate drive power losses. Therefore, a tradeoff has to be made between physical size of the power supply and the power dissipation at the system/ applicationlevel. The minimum and maximum duty cycles can be expressed in terms of input and output voltage as shown in Equation6. (6) Where, D =minimumdutycycle Min D =maximumdutycycle Max VIN =minimuminputvoltage Min VIN =maximuminputvoltage Max V =minimumregulatedoutputvoltage Reg-Min V =maximumregulatedoutputvoltage Reg-Max FromEquation6,maximumswitchingfrequencycanbecalculatedinEquation7. (7) Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com Where, f =maximumswitchingfrequency sw-Max t =minimumon-timeoftheNMOSswitchingtransistor ON-Min Knowing the switching frequency, the value of resistor to be connected at RT pin can be calculated using the graphshowninFigure23. Figure23. SwitchingFrequencyvsResistorValue 18 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 Synchronization With External Clock An external clock signal can be supplied to the device through SYNC pin (pin 3) to synchronize the internal oscillator frequency with an external clock frequency. The synchronization input overrides the internal fixed oscillator signal. The synchronization signal has to be valid for approximately two clock cycles before the transition is made for synchronization with the external frequency input. If the external clock input does not transition low or high for 32 µs (typical), the system defaults to the internal clock set by the resistor connected to theRTpin.TheSYNCinputcanhaveafrequencyaccordingtoEquation8. 180kHz<f <f <2×f <2.2MHz (8) (8) sw ext sw Where, f =oscillatorfrequencydeterminedbyresistorconnectedtotheRTpin sw f =frequencyoftheexternalclockfedthroughSYNCpin ext For example, if the resistor connected at RT pin is selected such that the switching frequency (f ) is 500 kHz, sw then the external clock can have a frequency (f ) between 500 kHz and 1000 kHz. But, if the resistor connected ext at RT pin is selected such that the switching frequency (f ) is 1500 kHz, then the external clock can have a sw frequency(f )between1500kHzand2200kHzonly. ext If the external clock gets struck for less than 32 µs, the NMOS switching FET is turned off and the output voltage starts decreasing. Depending upon the load conditions, the output voltage may hit the under voltage threshold and reset threshold before the external clock appears. The NMOS switching FET stays OFF until the external clock appears again. If the output voltage hits the reset threshold, the RST pin is asserted low after a deglitch timeof20µs(typical). If the external clock gets struck for more than 32 µs, the NMOS switching FET is turned off and the output voltage starts decreasing. Under this condition the default internal oscillator clock set by RT pin overrides the external after 32 µs and the NMOS switching FET resumes switching. When the external clock appears again (such that 180 kHz < f < f < 2 × f < 2.2 MHz), the NMOS switching FET starts switching at the frequency sw ext sw determinedbytheexternalclock. Slew Rate Control TheslewrateoftheNMOSswitchingFETcanbesetbyusinganexternalresistor(R7inFigure4).Therangeof risetimesandfalltimesfordifferentvaluesofslewresistorareshowninFigure24andFigure25. Figure24.FETRiseTime Figure25.FETFallTime Reset The RST pin (pin 8) is an open drain output pin used to indicate external digital devices/ loads if the device has powered up to a programmed regulated output voltage properly. This pin is asserted low until the regulated output voltage (V ) exceeds the programed reset threshold (VREG_RST, see Equation 11) and the reset delay Reg timer (set by Cdly pin) has expired. Additionally, whenever the EN pin is low or open, RST is immediately asserted low regardless of the output voltage. There is a reset filter timer to prevent reset being invoked due to shortnegativetransientsontheoutputline.Ifthermalshutdown occurs due to excessive thermal conditions, this pinisassertedlowwhentheswitchingFETiscommandedOFFandtheoutputfallsbelowtheresetthreshold. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com PowerOnCondition/ResetLine PowerDownCondition/ResetLine VIN VIN Css Css VReg_RST VReg VReg VReg_RST Cdly Cdly t delay RST RST 20ms (Typ-Deglitch Time) Figure26. Figure27. Reset Delay The delay time to assert the RST pin high after the supply has exceeded the programmed VReg_RST voltage (see Equation 11 to calculate VReg_RST) can be set by external capacitor (C2 in Figure 4) connected to the Cdly pin (pin 9). The delay may be programmed in the range of 2.2 ms to 200 ms using a capacitor in the range of2.2nFto200nF.ThedelaytimeiscalculatedusingEquation9: (9) Where, C=capacitoronCdlypin Reset Threshold and Undervoltage Threshold The undervoltage threshold (VReg_UV) level for proper regulation in low-power mode and the reset threshold level(VReg_RST)toinitiatearesetoutputsignalcanbeprogrammedbyconnectinganexternalresistorstringto the RST_TH pin (pin 13). The resistor combination of R1, R2, and R3 is used to program the threshold for detectionofundervoltage.VoltagebiasonR2+R3setstheresetthreshold. Undervoltage threshold for transient and low-power mode operation is given by the Equation 10. The recommendedrangeforVReg_UVis73%to95%ofV . Reg (10) ResetthresholdisgivenbyEquation11.TherecommendedrangeforVReg_RSTis70%to92%ofV . Reg (11) 20 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 Overvoltage Supervisor The overvoltage monitoring of the regulated output voltage, V can be achieved by connecting an external Reg resistor string to the OV_TH pin (pin 12). The resistor combination of R1, R2, and R3 is used to program the threshold for detection of overvoltage. The bias voltage of R3 sets the overvoltage threshold and the accuracy of regulatedoutputvoltageinhystereticmodeduringtransientevents. (12) RecommendedrangeforVReg_OVis106%to110%ofV . Reg Noise Filter on RST_TH and OV_TH Terminals External capacitors may be required to filter the noise added to RST_TH and OV_TH terminals. The noise is more pronounced with fast falling edges on the PH pin. Therefore, selecting a smaller Rslew resistor (R7 in Figure4)forahigherslewratewillrequiremoreexternalcapacitancetofilterthenoise. TheRCtimeconstantdependsonexternalcomponents(R2,R3,C9andC10inFigure4)connectedtoRST_TH and OV_TH pins. For proper noise filtering, improved loop transient response and better short circuit protection, Equation13mustbesatisfied. (R2+R3)×(C9+C10)<2µs (13) (13) To meet this requirement, it is recommended to use lower values of external capacitors and resistors. The value ofthetimeconstantisalsoaffectedbythePCBcapacitanceandtheapplicationsetup.Therefore,insomecases the external capacitors (C9, C10) on RST_TH and OV_TH terminals may not be required. Users can place a footprint on the application PCB and only populate it if necessary. Also, the external resistors (R1, R2, R3) shouldbesizedappropriatelytominimizeanysignificanteffectofboardleakage. For most cases, it is recommended to keep the external capacitors (either from board capacitance or by connecting external capacitors) between 10 pF to 100 pF; therefore, to meet time constant requirement in Equation13,thetotalexternalresistance(R1+R2+R3)shouldbelessthan200kΩ. Boost Capacitor An external boot strap capacitor (C3 in Figure 4) is connected to pin 20 to provide the gate drive voltage for the internal NMOS switching FET. X7R or X5R grade dielectrics are recommended due to their stable values over temperature. The capacitor value may need to be adjusted higher for high V and/or low frequencies Reg applications(e.g.,100nFfor500kHz/5Vand220nFfor500kHz/8V). Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com Loop Control Frequency Compensation Figure28. Type3Compensation Type3Compensation Type 3 compensation has been used in the feedback loop to improve the stability of the convertor and regulation intheoutputinresponsetothechangesininputvoltageorloadconditions.Thisbecomesimportantbecausethe ceramic capacitors used to filter the output have a low Equivalent Series Resistance (ESR). Type 3 compensation is implemented by connecting external resistors and capacitors to the COMP pin (output of the erroramplifier,pin15)ofthedeviceasshowninFigure28. The crossover frequency should be less than 1/5th to 1/10th of the switching frequency, and should be greater thanfivetimesthedoublepolefrequencyoftheLCfilter. f <f ×(0.1to0.2) (14) (14) c sw Where, f =switchingfrequency sw The modulator break frequencies as a function of the output LC filter are derived from Equation 15 and Equation16.TheLCoutputfiltergivesadoublepolethathasa –180°phaseshift. 1 f = LC 2pÖLC (15) Where, L=outputinductor C=outputcapacitor(C4infunctionalblockdiagram) TheESRoftheoutputcapacitorCgivesa"ZERO"thathasa90°phaseshift. 1 f = ESR 2pC × ESR (16) Where, ESR=Equivalentseriesresistanceofacapacitorataspecifiedfrequency Theregulatedoutputvoltage,V isgivenbyEquation17. Reg R4 V =V 1 + Reg ref R5 (17) V Reg (18) 22 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 ForVIN=8Vto50V,theVIN/V modulatorgainisapproximately10andhasatoleranceofabout20%. ramp VIN Gain =A = = 10 mod V ramp (19) Therefore, (20) Also,V isfixedforthefollowingrangeofVIN.V =1VforVIN<8V,andV =5VforVIN> 48V. ramp ramp ramp Thefrequenciesforpolesandzerosaregivenbyfollowingequations. (C5 + C8) fp1 = 2p ´ R6 ´ (C5 ´ C8) (21) 1 fp2= 2π×R9×C7 (22) 1 fz1= 2π×R6×C5 (23) (24) Guidelines for selecting compensation components selection are provided in the Application Information section ofthisdocument. Bode Plot of Converter Gain Open Loop Error Amp Gain fZ1 fZ2 fP1fP2 B d 20log R6(R4+R9)/(R4*R9) n - ai G 20log(R6/R4) 20log(10) Modulator Gain Compensation Gain Closed Loop Gain fLC fESR fC f - Frequency - Hz Figure29. Short-Circuit Protection The TPS54162 features an output short-circuit protection. Short-circuit conditions are detected by monitoring the RST_TH pin, and when the voltage on this node drops below 0.2 V, the switching frequency is decreased to protect the device. The switching frequency is folded back to approximately 25 kHz and the current limit is reducedto30%ofthetypicalcurrentlimitvalue. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com Thermal Shutdown (TSD) The TPS54162 protects itself from overheating with an internal thermal shutdown (TSD) circuit. If the junction temperature exceeds the thermal shutdown trip point, the NMOS switching FET is turned off. The device is automatically restarted under the control of soft-start circuit when the junction temperature drops below the thermal shutdown hysteretic trip point. During low-power mode operation, the thermal shutdown sensing circuitry is disabled for reduced current consumption. If V drops below VReg_UV, thermal shutdown monitoring is Reg activated. Overcurrent Protection The device features overcurrent protection to protect it from load currents greater than 2 A. Overcurrent protection is implemented by sensing the current through the NMOS switching FET. The sensed current is compared to a current reference level representing the overcurrent threshold limit (I ). If the sensed current CL exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches. Once overcurrent indicator is set true, overcurrent protection is triggered. The NMOS switching FET is turned off for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle current limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature ofthepartwillstartrising,theTSDwillkickinandshutdownswitchinguntilthepartcoolsdown. Internal Undervoltage Lockout (UVLO) This device is enabled on power up once the internal bandgap and bias currents are stable; this happens typicallyatVIN=3.4V(minimum).Onpowerdown,theinternalcircuitryisdisabledatVIN=2.6V(maximum). Power Dissipation and Temperature Considerations The power dissipation losses are applicable for continuous conduction mode operation (CCM). The total power dissipatedbythedeviceisthesumofthefollowingpowerlosses. Conductionlosses,P CON (25) Switchinglosses,P SW (26) Gatedrivelosses,P Gate P =V ×Q ×f (27) (27) Gate drive g sw Powersupplylosses,P IC P =VIN×I (28) (28) IC q-Normal Therefore,thetotalpowerdissipatedbythedeviceisgivenbyEquation29. P =P +P +P +P (29) (29) Total CON SW Gate IC Where, VIN=unregulatedinputvoltage I =outputloadcurrent Load t =FETswitchingrisetime(t=40ns(maximum)) r r t =FETswitchingfalltime f f =switchingfrequency sw V =FETgatedrivevoltage(V =6V(typical),V =8V(maximum)) drive drive drive Q =1×10-9C g I =quiescentcurrentinnormalmode(ActiveModeCCM) q-Normal 24 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 For device under operation at a given ambient temperature (T ), the junction temperature (T ) can be calculated A J usingEquation30. T =T +(R ×P ) (30) (30) J A th Total Therefore,theriseinjunctiontemperatureduetopowerdissipationisshowninEquation31. ΔT=T –T =(R ×P ) (31) (31) J A th Total For a given maximum junction temperature (T ), the maximum ambient temperature (T ) in which the J-Max A-Max devicecanoperateiscalculatedusingEquation32. T =T –(R ×P ) (32) (32) A-Max J-Max th Total Where, T =junctiontemperaturein°C J T =ambienttemperaturein°C A R =thermalresistanceofpackageinW/°C th T =maximumjunctiontemperaturein°C J-Max T =maximumambienttemperaturein°C A-Max There are several other factors that also affect the overall efficiency and power losses. Examples of such factors are AC and DC losses in the inductor, voltage drop across the copper traces on PCB, power losses in the flybackcatchdiodeetc.Abovediscussiondoesnotincludesuchfactors. 4.00 3.50 3.00 W) n ( 2.50 o ati sip 2.00 s Di er 1.50 w o P 1.00 0.50 0.00 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperture (°C) Figure30. PowerDissipationvsAmbientTemperature NOTE The output current rating for the regulator may have to be derated for ambient temperatures above 85°C. The derated value will depend on calculated worst-case power dissipationandthethermalmanagementimplementationintheapplication. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com APPLICATION INFORMATION TheseguidelinesaddressthefollowingtopicsindetailforTPS54162-Q1. 1. Componentselection 2. Designexample 3. PCBlayoutguidelines Component Selection This section explains considerations for the external components selection. The following schematic shows the interconnectionbetweenexternalcomponentsandthedeviceforatypicalDC/DCstepdownapplication. D1 VIN C11 + C1 VBATT 1 20 C3 GND NC BOOT 2 19 GND GND NC VIN VReg VReg GND 3 SYNC VIN 18 L1 R11 4 17 GND LPM PH 5 EN VREG 16 VReg GND D2 R9 C12 + C4 R10 GND R8 6 RT COMP 15 C5 R4 VOUT R7 7 14 GND RSLEW VSENSE C8 R6 C7 GND VReg R12 8 RST RST_TH 13 VReg GND C2 9 12 R1 GND CDLY OV_TH 10 11 GND AGND D SS A P C6 R5 21 R2 C10 GND GND GND C9 R3 GND GND GND Figure31. TypicalApplicationSchematic 1)InputCapacitors(C1,C11) Input filter capacitor (C11) is used to filter out high frequency noise in the input line. Typical values of C11 are 0.1µFto0.01µF.Forhigherfrequencynoise,lowcapacitorvaluesarerecommended. To minimize the ripple voltage, input ceramic de-coupling capacitor (C1) of type X5R or X7R should be used. The DC voltage rating for the input decoupling capacitor must be greater than the maximum input voltage. This capacitor must have an input ripple current rating higher than the maximum input ripple current of the converter fortheapplication;andisdeterminedbyEquation33. (33) The input capacitors for power regulators are chosen to have a reasonable capacitance-to-volume ratio and fairly stable over temperature. The value of the input capacitance also determines the input ripple voltage of the regulator,shownbyEquation34. (34) Input ceramic filter capacitors should be located in close proximity to the VIN terminal. Surface mount capacitors arerecommendedtominimizeleadlengthandreducenoisecoupling. 26 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 2)OutputCapacitor(C4,C12) The selection of the output capacitor will determine several parameters in the operation of the converter, for example voltage drop on the output capacitor and the output ripple. The capacitor value also determines the modulator pole and the roll-off frequency due to the LC output filter double pole. This is expressed in Equation15. The minimum capacitance needed to maintain desired output voltage during high to low load transition and preventovershootisgivenbyEquation35. L× (I 2–I 2) Load-Max Load-Min C4 = V 2–V 2 Reg-Max Reg-Min (35) Where, L=outputinductor I =maximumloadcurrent Load-Max I =minimumloadcurrent Load-Min V =maximumtoleranceofregulatedoutputvoltage Reg-Max V =minimumtoleranceofregulatedoutputvoltage Reg-Min During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the output voltage above a certain level for a specified time and not issue a reset, until the main regulator control loop responds to the change. The minimum output capacitance required to allow sufficient drop on the output voltagewithoutissuingaresetisdeterminedbyEquation36. (36) Where, ΔV =transientresponseduringloadstepping Reg TheminimumcapacitanceneededforoutputvoltageripplespecificationisgivenbyEquation37. (37) Additional capacitance de-ratings for temperature, aging, and DC bias have to be factored in, and so a value of 100µFwithESRcalculatedusingEquation38oflessthan100mΩ shouldbeusedontheoutputstage. Maximum ESR of the output capacitor is based on output ripple voltage specification in Equation 38 . The output ripplevoltageisaproductoftheoutputcapacitorESRandripplecurrent. (38) Output capacitor root mean square (RMS) ripple current is given by Equation 39. This is to prevent excess heatingorfailureduetohighripplecurrents.Thisparameterissometimesspecifiedbythemanufacturers. V (VIN –V ) I = Reg Max Reg Load-RMS Ö12 × VINMax× fsw× L1 (39) Filtercapacitor(C12)ofvalue0.1µF(typical)isusedtofilteroutthenoiseintheoutputline. 3)Soft-StartCapacitor(C6) The soft start capacitor determines the minimum time to reach the desired output voltage during a power up cycle. This is useful when a load requires a controlled voltage slew rate, and helps to limit the current draw from theinputvoltagesupplyline.A100nFcapacitorisrecommendedforstartuploadsof1A(max.). 4)BootstrapCapacitor(C3) A 0.1µF ceramic capacitor must be connected between the PH and BOOT terminals for the converter to operate and regulate to the desired output voltage. It is recommended to use a capacitor with X5R or better grade dielectricmaterial,andthevoltageratingonthiscapacitorofatleast25Vtoallowforderating. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com 5)Power-OnResetDelay(PORdly)Capacitor(C2) ThevalueofthiscapacitorcanbecalculatedusingEquation9. 6)OutputInductor(L1) Use a low EMI inductor with a ferrite type shielded core. Other types of inductors may be used; however, they musthavelowEMIcharacteristicsandshouldbelocatedawayfromthelow-powertracesandcomponentsinthe circuit. Tocalculatetheminimumvalueoftheinductor,theripplecurrentshouldbefirstcalculatedusingEquation40. I =K ×I (40) (40) Ripple IND Load Where, I =maximumoutputloadcurrent Load I =allowablepeaktopeakinductorripplecurrent,typ.20%ofmaximumI Ripple Load K = coefficient that represents the amount of inductor ripple current relative to the maximum output IND current. Since, the inductor ripple current is filtered by the output capacitor; therefore K is typically in the IND rangeof0.2to0.3,dependingontheESRandtheripplecurrentratingoftheoutputcapacitor(C4). TheminimumvalueofoutputinductorcanbecalculatedusingEquation41. (VIN –V ) × V Max Reg Reg L = Min f × I × VIN sw Ripple Max (41) Where, VIN =maximuminputvoltage Max V =regulatedoutputvoltage Reg f =switchingfrequency sw TheRMSandpeakcurrentsflowingintheinductoraregivenbyEquation42andEquation43. I 2 I = I 2+ Ripple L,RMS Load 12 (42) I I = I + Ripple L,pk Load 2 (43) 7)FlybackSchottkyDiode(D2) The TPS54162 requires an external Schottky diode connected between the PH and power ground termination. The absolute voltage at PH should not go beyond the values in Absolute Maximum Ratings. The Schottky diode conducts the output current during the off state of the internal power switch. This Schottky diode must have a reverse breakdown voltage higher than the maximum input voltage of the application. A Schottky diode is selected for its lower forward voltage. The Schottky diode is selected based on the appropriate power rating, which factors in the DC conduction losses and the AC losses due to the high switching frequencies; this is determinedbyEquation44. (VIN –V ) × I × V (VIN–V ) × f × C Max Reg Load fd fd sw J P = + diode VINMax 2 (44) Where, P =powerrating diode V =forwardconductingvoltageofSchottkydiode fd C =junctioncapacitanceoftheSchottkydiode J RecommendedpartnumbersarePDS360andSBR8U60P5. 8)ResistortoSetSlewRate(R7) The slew rate setting is asymmetrical; i.e., for a selected value of R7, the rise time and fall time are different. R7 canbeapproximatelydeterminedfromFigure24andFigure25.Theminimumrecommendedvalueis10kΩ. 28 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 9)ResistortoSelectSwitchingFrequency(R8) PleaserefertothesectionSelectingSwitchingFrequency,Figure23andEquation7. 10)ResistorstoSelectOutputVoltage(R4,R5) To minimize the effect of leakage current on the VSENSE terminal, the current flowing through the feedback network should be greater than 5 mA to maintain output accuracy. Higher resistor values help improve the converter efficiency at low output currents, but may introduce noise immunity problems (see Equation 1). It is recommendedtofixR4toastandardvalue(say187kΩ)andcalculateR5. 11)ResistorstoSetUndervoltage,Overvoltage,andResetThresholds(R1,R2,R3) Overvoltageresistorselection UsingEquation12,thevalueofR3canbedeterminedtosettheovervoltagethresholdatupto106%to110%of V .ThesumofR1,R2,andR3resistornetworktogroundshouldbeisapproximately100kΩ. Reg Resetthresholdresistorselection Using Equation 11 the value of R2 + R3 can be calculated, and knowing R3 from the OV_TH setting, R2 can be determined.Suggestedvalueofresetthresholdis92%ofV . Reg Undervoltagethresholdforlow-powermodeandloadtransientoperation This threshold is set above the reset threshold to ensure the regulator operates within the specified tolerances during output load transient of low load to high load and during discontinuous conduction mode. The typical voltage threshold can be determined using Equation 10. Suggested value of undervoltage threshold is 95% of V . Reg Low-PowerMode(LPM)Threshold An approximation of the output load current at which the converter is operating in discontinuous mode can be obtainedfromEquation4with ±30%hysteresis.ThevaluesusedinEquation6forminimumandmaximuminput voltage will affect the duty cycle and the overall discontinuous mode load current. These are the nominal values, andotherfactorsarenottakenintoconsiderationlikeexternalcomponentvariationswithtemperatureandaging. 12)PullupResistorforEnable(R12) Anexternalpullresistorof30.1kΩ isrecommendedtoenablethedeviceforoperation. 13)Type3CompensationComponents(R5,R6,R9,C5,C7,C8) First,makethe'ZEROs'closetodoublepolefrequency,usingEquation15,Equation16,andEquation14. fz1=(50%to70%)f LC fz2=f LC Second,makethe'POLEs'abovethecrossoverfrequency,usingEquation21andEquation22. fp1=f ESR fp2=½f sw Resistors FromEquation1,knowingV andR4(fixtoastandardvalue),R5canbecalculatedasshowninEquation45: Reg (45) UsingEquation14andEquation18,R6canbecalculatedasshowninEquation46: (46) R9canbecalculatedasshowninEquation47: Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com (47) Capacitors UsingEquation23,C5canbecalculatedasshowninEquation48: (48) C7canbecalculatedasshowninEquation49: (49) C8canbecalculatedasshowninEquation50: (50) 14)NoiseFilteronRST_THandOV_THTerminals(C9,C10) These capacitors may be required in some applications to filter the noise on RST_TH and OV_TH pins. Typical capacitor values for RST_TH and OV_TH pins are between 10 pF to 100 pF for total resistance on RST_TH/OV_THdivideroflessthan200kΩ.SeediscussiononNoiseFilteronRST_THandOV_THTerminals. 30 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 DESIGN EXAMPLE The following example demonstrates the design of a high frequency switching regulator using ceramic output capacitors. A few parameters must be known to start the design process. These parameters are typically determinedatthesystemlevel. Forthisexample,wewillstartwiththefollowingknownandtargetparameters: Table7. Known Inputvoltage,VIN Minimum=8V,Maximum=28V,Typical=14V Outputvoltage,V 3.3V±2% Reg Maximumoutputcurrent,I 1A Load-Max Ripple/transientoccurringininputvoltage,ΔVIN 1%ofVIN(minimum) Resetthreshold,VReg_RST 92%ofV Reg Target Overvoltagethreshold,VReg_OV 106%ofV Reg Undervoltagethreshold,VReg_UV 95%ofV Reg Transientresponse0.25Ato2Aloadstep,ΔV 5%ofV Reg Reg Poweronresetdelay,PORdly 2.2ms Step1.CalculatetheSwitchingFrequency(f ) sw Toreducethesizeofoutputinductorandcapacitor,higherswitchingfrequencycanbeselected.Itisimportantto understand that higher switching frequency will result in higher switching losses, causing the device to heat up. This may result in degraded thermal performance. To prevent this, proper PCB layout guidelines must be followed(explainedinthelatersectionofthisdocument). Based upon the discussion in section Selecting the Switching Frequency, calculate the maximum and minimum dutycycle. KnowingV andtoleranceonV ,theV andV arecalculatedtobe: Reg Reg Reg-Max Reg-Min V =102%ofV =3.366VandV =98%ofV =3.324V. Reg-Max Reg Reg-Min Reg UsingEquation6,theminimumdutycycleiscalculatedtobe,D =11.55% Min Knowing t = 150 ns from the device specifications, and using Equation 7, maximum switching frequency is ON-Min calculatedtobe,f =770kHz. sw-Max Since the oscillator can also vary by ±10%, the switching frequency can be further reduced by 10% to add margin. Also, to improve efficiency and reduce power losses due to switching, the switching frequency can be furtherreducedbyabout193kHz.Thereforef =500kHz. sw FromFigure23,R8canbeapproximatelydeterminedtobe,R8=205kΩ. Step2.CalculatetheRippleCurrent(I ) Ripple UsingEquation40,forK =0.2(typical),inductorripplecurrentiscalculatedtobe:I =0.2A. IND Ripple The ripple current is chosen such that the converter enters discontinuous mode (DCM) at 20% of max load. The 20%isatypicalvalue,itcouldgohighertoamaximumofupto40%. Step3.CalculatetheInductorValue(L1) Using Equation 41, the inductor value is calculated to be, L = 29.1 µH. A closest standard inductor value can Min beused. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com Step4.CalculatetheOutputCapacitorandESR(C4) Calculatecapacitance To calculate the capacitance of the output capacitor, minimum load current must be first determined. Typically, in standby mode the load current is 100 µA, however this really depends on the application. With this value of minimumloadcurrentandusingEquation35,Equation36,andEquation37,C4iscalculatedtobe,C4> 34µF. To allow wider operating conditions and improved performance in low-power mode, it is recommended to use a 100µFcapacitor.Highervalueofoutputcapacitorallowsimprovedtransientresponseduringloadstepping. CalculateESR UsingEquation38,ESRiscalculatedtobe,R < 660mΩ. ESR Capacitors with lowest ESR values should be selected. To meet both the requirements, capacitance and low ESR, several low ESR capacitors may be connected in parallel. In this example, we will select a capacitor with ESRvalueas30mΩ. Filtercapacitor(C12)ofvalue0.1µFcanbeaddedtofilteroutthenoiseintheoutputline. Step5.CalculatetheFeedbackResistors(R4,R5) To keep the quiescent current low and avoid instability problems, it is recommended to select R4 and R5 such that,R4+R5~250kΩ. UsingEquation1andusingafixedstandardvalueofR4=187kΩ,R5iscalculatedtobe,R5=59.84kΩ. Step6.CalculateType3CompensationComponents Resistances(R6,R9) UsingEquation19,forVIN =14V,V iscalculatedtobe,V =1.4V. Typ Ramp Ramp UsingEquation15,f iscalculatedtobe,f =2.95kHz. LC LC Using V , f from above, assuming f as 1/10th of f and Equation 46, R6 is calculated to be, R6 = 316.96 Ramp LC c sw kΩ. UsingEquation47,R9iscalculatedtobe,R9=2.23kΩ. Capacitors(C5,C8,C7) UsingEquation48,C5iscalculatedtobe,C5=340.43pF. UsingEquation16,f iscalculatedtobe,f =53.05kHz. ESR ESR UsingEquation50,C8iscalculatedtobe,C8=9.74pF. UsingEquation49,C7iscalculatedtobe,C7=285.1pF. Step7.CalculateSoft-StartCapacitor(C6) Therecommendedvalueofsoft-startcapacitoris100nF(typical). Step8.CalculateBootstrapCapacitor(C3) Therecommendedvalueofbootstrapcapacitoris0.1µF(typical). Step9.CalculatePower-OnResetDelayCapacitor(C2) Toachieve2.2msdelay,theresetdelaycapacitorcanbecalculatedusingEquation9tobeC2=2.2nF. Step10.CalculateInputCapacitor(C1,C11) TypicalvaluesforC11are0.1µFand0.01 µF. Input capacitor (C1) should be rated more than the maximum input voltage (VIN ). The input capacitor should Max be big enough to maintain supply in case of transients in the input line. Using Equation 34, C1 is calculated to be,C1=6.25µF.Forimprovedtransientresponse,ahighervalueofC1suchas220µFisrecommended. 32 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 www.ti.com SLVSA32C–OCTOBER2009–REVISEDMAY2010 Step11.CalculateResistorstoControlSlewRate(R7) The value of slew rate resistor (R7) can be approximately determined from Figure 24 and Figure 25 at different typical input voltages. The minimum recommended value is 10 kΩ. To achieve rise time, t = 20 ns and fall time, r t =35ns,theslewrateresistorisapproximatelyofvalue30kΩ. f Step12.ResistorstoSelectUndervoltage,OvervoltageandResetThresholdValues(R1,R2,R3) Thesumofthesethreeresistorsshouldbeapproximatelyequalto100kΩ.Inthisexample, VReg_OV=106%ofV =3.498V Reg VReg_RST=92%ofV =3.036V Reg VReg_UV=95%ofV =3.135V Reg UsingEquation12,R3=22.87kΩ. UsingEquation11,R2=3.48kΩ. UsingEquation10,R1=73.64kΩ Step13.DiodeD1andD2Selection Diode D1 is used to protect the IC from the reverse input polarity connection. The diode should be rated at maximumloadcurrent.OnlySchottkydiodeshouldbeconnectedatthePHpin.Therecommendedpartnumbers arePDF360andSBR8U60P5. Step14.NoiseFilteronRST_THandOV_THTerminals(C9andC10) Typical capacitor values for RST_TH and OV_TH pins are between 10 pF to 100 pF for total resistance on RST_TH/OV_THdivideroflessthan200kΩ. Step15.PowerBudgetandTemperatureEstimation UsingEquation25,conductionlossesfortypicalinputvoltagearecalculatedtobe,P =0.058W. CON Assuming slew resistance R7 = 30 kΩ, from Figure 24 and Figure 25, rise time, t = 20 ns and fall time, t = 35 r f ns.UsingEquation26,switchinglossesfortypicalinputvoltagearecalculatedtobe,P =0.385W. SW UsingEquation27,gatedrivelossesarecalculatedtobe,P =3mW. Gate UsingEquation28,powersupplylossesarecalculatedtobe,P =1.8mW. IC UsingEquation29,thetotalpowerdissipatedbythedeviceiscalculatedtobe,P =448mW. Total Using Equation 31, and knowing the thermal resistance of package = 35°C/W, the rise in junction temperature duetopowerdissipationiscalculatedtobe,∆T=15.7°C. Using Equation 32, for a given maximum junction temperature 150°C, the maximum ambient temperature at whichthedevicecanbeoperatediscalculatedtobe,T =134°C(approximately). A-Max Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):TPS54162-Q1

TPS54162-Q1 SLVSA32C–OCTOBER2009–REVISEDMAY2010 www.ti.com PCB LAYOUT GUIDELINES ThefollowingguidelinesarerecommendedforPCBlayoutoftheTPS54162device. Traces and Ground Place Routing All power (high current) traces should be thick and as short as possible. The inductor and output capacitors should be as close to each other as possible. This will reduce EMI radiated by the power traces due to high switching currents. In a two sided PCB, it is recommended to have ground planes on both sides of the PCB to help reduce noise and ground loop errors. The ground connection for the input and output capacitors and IC groundshouldbeconnectedtothisgroundplane. In a multilayer PCB, the ground plane is used to separate the power plane (high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance. Also, it is recommended to arrange the components such that the switching current loops curl in the same direction. This can be done by placing the high current components such that during conduction, the current paths are in the same direction. This will prevent magnetic field reversal caused by the traces between the two halfcycles,helpingtoreduceradiatedEMI. Component Routing for the Feedback Loop It is recommended to route the feedback traces such that there is minimum interaction with any noise sources associated with the switching components. Recommended practice is to ensure the inductor is placed away from thefeedbacktracetopreventEMInoisesource. Output Capacitor Topside SupplyArea Ground Input Capacitor Plane Output Catch Diode Inductor NC BOOT NC VIN SYNC VIN LPM PH EN VReg Compensation Network RT COMP Rslew VSENSE Resistor RST RST_TH Supervisor Network Divider Cdly OV_TH GND SS Signal via to Ground Plane Topside GroundArea Thermal Via Signal Via Figure32. PCBLayoutExample 34 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54162-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54162QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 54162Q1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54162QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54162QPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0 PackMaterials-Page2

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