Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 TPS54140A 1.5-A, 42-V Step-Down DC/DC Converter with Eco-mode™ 1 Features 3 Description • 3.5-Vto42-VInputVoltageRange The TPS54140A device is a 42-V, 1.5-A, step-down 1 regulator with an integrated high-side MOSFET. • 200-mΩ High-SideMOSFET Current-mode control provides simple external • HighEfficiencyatLightLoadswithaPulse compensation and flexible component selection. A SkippingEco-mode™ low ripple-pulse skip mode reduces the no-load, • TighterEnableThresholdthanTPS54140for regulated output supply current to 116 μA. Using the enable pin, shutdown supply current is reduced to 1.3 MoreAccurateUVLOVoltage μA. • AdjustableUVLOVoltageandHysteresis Undervoltage lockout is internally set at 2.5 V, but • 116-μAOperatingQuiescentCurrent can be increased using the enable pin. The output • 1.3-μAShutdownCurrent voltage startup ramp is controlled by the slow start • 100-kHzto2.5-MHzSwitchingFrequency pin that can also be configured for • SynchronizestoExternalClock sequencing/tracking. An open drain power good signal indicates the output is within 94% to 107% of • AdjustableSlowStart/Sequencing itsnominalvoltage. • UVandOVPowerGoodOutput A wide switching frequency range allows efficiency • 0.8-VInternalVoltageReference and external component size to be optimized. • MSOP10and3-mm ×3-mmVSON-10Package Frequency fold back and thermal shutdown protects With PowerPAD™ thepartduringanoverloadcondition. • Supportedby WEBENCH®andSwitcherPro™ DeviceInformation(1) SoftwareTool PARTNUMBER PACKAGE BODYSIZE(NOM) 2 Applications VSON(10) 3.00mm×3.00mm TPS54140A • 12-Vand24-VIndustrialandCommercialLow MSOP(10) 3.00mm×3.00mm PowerSystems (1) For all available packages, see the orderable addendum at theendofthedatasheet. • AftermarketAutoAccessories:Video,GPS, Entertainment SPACE SimplifiedSchematic EfficiencyvsLoadCurrent VIN VVIINN PWRGD 90 TPS54140A 85 EN BOOT 80 % 75 SS/TR PH VOUT y - nc 70 RT/CLK e ci COMP Effi 65 VSENSE 60 VI= 12 V, V = 3.3 V, O GND 55 fsw= 1200 kHz 50 0 0.25 0.50 0.75 1 1.25 1.50 1.75 2 Load Current -A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 18 2 Applications........................................................... 1 8.1 ApplicationInformation............................................18 3 Description............................................................. 1 8.2 TypicalApplication .................................................25 4 RevisionHistory..................................................... 2 8.3 SystemExamples...................................................35 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 39 9.1 Sequencing.............................................................39 6 Specifications......................................................... 4 10 Layout................................................................... 43 6.1 AbsoluteMaximumRatings .....................................4 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................43 6.3 RecommendedOperatingConditions.......................5 10.2 LayoutExample....................................................43 6.4 ThermalInformation..................................................5 10.3 PowerDissipationEstimate..................................43 6.5 ElectricalCharacteristics...........................................6 11 DeviceandDocumentationSupport................. 45 6.6 TypicalCharacteristics..............................................8 11.1 DeviceSupport ....................................................45 7 DetailedDescription............................................ 12 11.2 CommunityResources..........................................45 7.1 Overview.................................................................12 11.3 Trademarks...........................................................45 7.2 FunctionalBlockDiagram.......................................13 11.4 ElectrostaticDischargeCaution............................45 7.3 FeatureDescription.................................................13 11.5 Glossary................................................................45 7.4 DeviceFunctionalModes........................................17 12 Mechanical,Packaging,andOrderable Information........................................................... 45 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(January2014)toRevisionC Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection. ................................................................................................ 1 ChangesfromRevisionA(July2012)toRevisionB Page • DeletedSWIFTfromthedatasheetTitleandFeatures........................................................................................................ 1 ChangesfromOriginal(May2012)toRevisionA Page • ChangedDescriptiontextFrom:"within93%to107%ofitsnominalvoltage."To:"within94%to107%ofitsnominal voltage.".................................................................................................................................................................................. 1 • ChangedthevaluesoftheHysteresiscurrentintheElectricalCharacteristicstable............................................................ 6 • ChangedtextintheSlowStartandTrackingPin(SS/TR)sectionFrom:"VINUVLOisexcedded,ENpinpulled below1.25V"To:"VINpinisbelowtheVINUVLO,ENpinpulledbelow1.25V"................................................................ 20 • ChangedStartInputVoltage(risingVIN)voltageFrom:7.25VTo:7.7V........................................................................... 25 • ChangedStartInputVoltage(fallingVIN)voltageFrom:6.25VTo:6.7V.......................................................................... 25 • ChangedEquation11........................................................................................................................................................... 26 • Changed7.25Vto7.7Vand6.25Vto6.7VintheUnderVoltageLockOutSetPointsection............................................ 30 • ChangedEquation29........................................................................................................................................................... 31 • ChangedEquation30andEquation31............................................................................................................................... 31 • ChangedEquation33........................................................................................................................................................... 32 2 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 5 Pin Configuration and Functions DRCPackage DGQPackage 10-PinVSON 10-PinMSOP TopView TopView BOOT 1 10 PH BOOT 1 10 PH VIN 2 9 GND VIN 2 9 GND Thermal Thermal EN 3 Pad 8 COMP EN 3 Pad 8 COMP (11) (11) SS/TR 4 7 VSENSE SS/TR 4 7 VSENSE RT/CLK 5 6 PWRGD RT/CLK 5 6 PWRGD PinFunctions PIN I/O DESCRIPTION NAME NO. AbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitorisbelowthe BOOT 1 O minimumrequiredbythedevice,theoutputisforcedtoswitchoffuntilthecapacitorisrefreshed. Erroramplifieroutput,andinputtotheoutputswitchcurrentcomparator.Connectfrequencycompensation COMP 8 O componentstothispin. Enablepin,internalpull-upcurrentsource.Pullbelow1.2Vtodisable.Floattoenable.Adjusttheinput EN 3 I undervoltagelockoutwithtworesistors. GND 9 – Ground PH 10 O Thesourceoftheinternalhigh-sidepowerMOSFET. Anopendrainoutput,assertslowifoutputvoltageislowduetothermalshutdown,dropout,over-voltageor PWRGD 6 O ENshutdown. ResistorTimingandExternalClock.Aninternalamplifierholdsthispinatafixedvoltagewhenusingan externalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLLupper RT/CLK 5 I threshold,amodechangeoccursandthepinbecomesasynchronizationinput.Theinternalamplifieris disabledandthepinisahighimpedanceclockinputtotheinternalPLL.Ifclockingedgesstop,theinternal amplifierisre-enabledandthemodereturnstoaresistorsetfunction. Slow-startandTracking.Anexternalcapacitorconnectedtothispinsetstheoutputrisetime.Sincethe SS/TR 4 I/O voltageonthispinoverridestheinternalreference,itcanbeusedfortrackingandsequencing. VIN 2 I Inputsupplyvoltage,3.5Vto42V. VSENSE 7 I Invertingnodeofthetransconductance(gm)erroramplifier. GNDpinmustbeelectricallyconnectedtotheexposedpadontheprintedcircuitboardforproper ThermalPad 11 – operation. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) Overoperatingtemperaturerange(unlessotherwisenoted). MIN MAX UNIT VIN –0.3 47 EN(2) –0.3 5 BOOT 55 VSENSE –0.3 3 Inputvoltage V COMP –0.3 3 PWRGD –0.3 6 SS/TR –0.3 3 RT/CLK –0.3 3.6 PH–BOOT 8 Outputvoltage PH –0.6 47 V PH,10-nsTransient –2 47 VoltageDifference PADtoGND ±200 mV EN 100 μA BOOT 100 mA Sourcecurrent VSENSE 10 μA PH CurrentLimit A RT/CLK 100 μA VIN CurrentLimit A COMP 100 μA Sinkcurrent PWRGD 10 mA SS/TR 200 μA Operatingjunctiontemperature –40 150 °C Storagetemperature –65 150 °C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) SeetheEnableandAdjustingUndervoltageLockoutsectionofthisdatasheetfordetails. 6.2 ESD Ratings VALUE UNIT DRCpackage(VSON) Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 DGQpackage(MSOP) Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan500-VHBMispossibleifnecessaryprecautionsaretaken. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan250-VCDMispossibleifnecessaryprecautionsaretaken. 4 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyinputvoltagerange 3.5 42 V IN V Outputvoltagerange 0.8 39 V O 6.4 Thermal Information TPS54140A THERMALMETRIC(1) DGQ(MSOP) DRC(VSON) UNIT 10PINS 10PINS R Junction-to-ambientthermalresistance(standardboard) 52.3 45.1 °C/W θJA R Junction-to-case(top)thermalresistance 46.3 51.9 °C/W θJC(top) R Junction-to-boardthermalresistance 33 20.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 1.6 0.8 °C/W JT ψ Junction-to-boardcharacterizationparameter 32.7 20.7 °C/W JB R Junction-to-case(bottom)thermalresistance 5.9 5.1 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 6.5 Electrical Characteristics T =–40°Cto150°C,VIN=3.5to42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage 3.5 42 V Internalundervoltagelockout Novoltagehysteresis,risingandfalling 2.5 V threshold Shutdownsupplycurrent EN=0V,25°C,3.5V≤VIN≤42V 1.3 4 Operating:nonswitchingsupply μA VSENSE=0.83V,VIN=12V,25°C 116 136 current ENABLEANDUVLO(ENPIN) Enablethresholdvoltage Novoltagehysteresis,risingandfalling 1.11 1.25 1.36 V Enablethreshold+50mV –3.8 Inputcurrent μA Enablethreshold–50mV –0.9 Hysteresiscurrent 1.91 2.95 3.99 μA VOLTAGEREFERENCE T =25°C 0.792 0.8 0.808 J Voltagereference V 0.784 0.8 0.816 HIGH-SIDEMOSFET VIN=3.5V,BOOT-PH=3V 300 On-resistance mΩ VIN=12V,BOOT-PH=6V 200 410 ERRORAMPLIFIER Inputcurrent 50 nA Erroramplifiertransconductance(g ) ±2μA<I <2μA,V =1V 97 μS M (COMP) (COMP) Erroramplifiertransconductance(gM) ±2μA<I(COMP)<2μA,V(COMP)=1V, 26 μS duringslowstart VSENSE=0.4V Erroramplifierdcgain VSENSE=0.8V 10000 V/V Erroramplifierbandwidth 2700 kHz Erroramplifiersource/sink V =1V,100mVoverdrive ±7 μA (COMP) COMPtoswitchcurrent 6 A/V transconductance CURRENTLIMIT Currentlimitthreshold VIN=12V,T =25°C 1.8 2.7 A J THERMALSHUTDOWN Thermalshutdown 182 °C TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) SwitchingFrequencyRangeusing 100 2500 kHz RTmode f Switchingfrequency R =200kΩ 450 581 720 kHz SW T SwitchingFrequencyRangeusing 300 2200 kHz CLKmode MinimumCLKpulsewidth 40 ns RT/CLKhighthreshold 1.9 2.2 V RT/CLKlowthreshold 0.5 0.7 V RT/CLKfallingedgetoPHrising Measuredat500kHzwithRTresistorinseries 60 ns edgedelay PLLlockintime Measuredat500kHz 100 μs SLOWSTARTANDTRACKING(SS/TR) Chargecurrent V =0.4V 2 μA SS/TR SS/TR-to-VSENSEmatching V =0.4V 45 mV SS/TR SS/TR-to-referencecrossover 98%nominal 1.0 V 6 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Electrical Characteristics (continued) T =–40°Cto150°C,VIN=3.5to42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SS/TRdischargecurrent(overload) VSENSE=0V,V(SS/TR)=0.4V 112 μA SS/TRdischargevoltage VSENSE=0V 54 mV POWERGOOD(PWRGDPIN) VSENSEfalling 92% VSENSErising 94% V VSENSEthreshold VSENSE VSENSErising 109% VSENSEfalling 107% Hysteresis VSENSEfalling 2% Outputhighleakage VSENSE=VREF,V =5.5V,25°C 10 nA (PWRGD) Onresistance I =3mA,VSENSE<0.79V 50 Ω (PWRGD) MinimumVINfordefinedoutput V <0.5V,I =100μA 0.95 1.5 V (PWRGD) (PWRGD) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 6.6 Typical Characteristics W 0.816 m 500 nce - VI= 12 V VI= 12 V a st n-Source On-State Resi 235705 BOOT-PH = 3 V BOOT-PH = 6 V Voltage Reference - V 00..880008 ai - c Dr 125 Vref 0.792 ati St N - O S 0 0.784 D R -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure1.ONResistancevsJunctionTemperature Figure2.VoltageReferencevsJunctionTemperature 3.5 610 V= 12 V, V= 12 V I I RT= 200 kW 600 Hz k A 3 cy - 590 nt - uen e q Switch Curr2.5 witching Fre 557800 S - fs 560 2 550 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure3.SwitchCurrentLimitvsJunctionTemperature Figure4.SwitchingFrequencyvsJunctionTemperature 2500 500 V= 12 V, I T = 25°C J kHz 2000 Hz) 400 ching Frequency - 11050000 hing Frequency (k 230000 Swit witc - S 100 fs 500 0 0 200 300 400 500 600 700 800 900 1000 1100 1200 0 25 50 75 100 125 150 175 200 RT/CLK - Resistance - kW RT/CLK Resistance (kW) C006 Figure5.SwitchingFrequencyvsRT/CLKResistanceHigh Figure6.SwitchingFrequencyvsRT/CLKResistanceLow FrequencyRange FrequencyRange 8 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Typical Characteristics (continued) 40 150 V= 12 V I V= 12 V I 130 30 110 V V A/ A/ m m m - m - g g 90 20 70 10 50 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure7.EATransconductanceDuringSlowStartvs Figure8.EATransconductancevsJunctionTemperature JunctionTemperature 1.40 -3.25 VI= 12 V VVI= 12= VT,hreshold +50 mV I(EN) -3.5 V1.30 d - shol Am hre -N)-3.75 T E EN - 1.20 I( -4 1.10 -50 -25 0 25 50 75 100 125 150 -4.25 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C T - Junction Temperature - °C Figure9.ENPinVoltagevsJunctionTemperature J Figure10.ENPinCurrentvsJunctionTemperature -0.8 -1 VI= 12 V, VI= 12 V VI(EN)=Threshold -50 mV -0.85 -1.5 Am Am I-(EN)-0.9 I-(SS/TR) -2 -0.95 -2.5 -1 -3 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure11.ENPinCurrentvsJunctionTemperature Figure12.SS/TRChargeCurrentvsJunctionTemperature Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Typical Characteristics (continued) 120 100 VI= 12 V VI= 12 V, T = 25°C J 80 115 w I-AmI(SS/TR)110 % of Nominal fs 4600 105 20 100 0 -50 -25 0 25 50 75 100 125 150 0 0.2 0.4 0.6 0.8 TJ- Junction Temperature - °C VSENSE- V Figure13.SS/TRDischargeCurrentvsJunction Figure14.SwitchingFrequencyvsVSENSE Temperature 2 2 V= 12 V I T = 25°C J 1.5 1.5 A A m m I-(VIN) 1 I-(VIN) 1 0.5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 0 10 20 30 40 TJ- Junction Temperature - °C VI- Input Voltage - V Figure15.ShutdownSupplyCurrentvsJunction Figure16.ShutdownSupplyCurrentvsInputVoltage(V ) in Temperature 140 140 VI= 12 V, TJ= 25oC, VI(VSENSE)= 0.83 V VI(VSENSE)= 0.83 V 130 130 120 120 A A m m I-(VIN) 110 I-(VIN) 110 100 100 90 90 -50 -25 0 25 50 75 100 125 150 0 20 40 TJ- Junction Temperature - °C VI- Input Voltage - V Figure17.VINSupplyCurrentvsJunctionTemperature Figure18.VINSupplyCurrentvsInputVoltage 10 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Typical Characteristics (continued) 100 115 V= 12 V V= 12 V I I 80 ef110 VSENSE Rising Vr of % 105 VSENSE Falling WDSON - 60 eshold - 100 R 40 Thr GD 95 VSENSE Rising R W 20 P 90 VSENSE Falling 0 -50 -25 0 25 50 75 100 125 150 85 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure19.PWRGDONResistancevsJunctionTemperature Figure20.PWRGDThresholdvsJunctionTemperature 2.5 3 2.3 2.75 V V- I(BOOT-PH) 2 V- VI(VIN) 2.50 1.8 2.25 1.5 2 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure21.BOOT-PHUVLOvsJunctionTemperature Figure22.InputVoltage(UVLO)vsJunctionTemperature 500 60 VTJI== 1225 oVC, 55 VV(IS=S/ T1R)2= V0.2 V 400 50 et - mV 300 set - mV 45 Offs 200 Off 40 100 35 30 0 -50 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 VSENSE - mV TJ- Junction Temperature - °C Figure24.SS/TRtoVSENSEOffsetvsTemperature Figure23.SS/TRtoVSENSEOffsetvsVSENSE Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 7 Detailed Description 7.1 Overview The TPS54140A device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switchturnontoafallingedgeofanexternalsystemclock. TheTPS54140Ahasadefaultstartupvoltageofapproximately2.5V.TheENpinhasaninternalpull-upcurrent source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will operate. The operating current is 116 μA when not switching and under no load. When the device is disabled, thesupplycurrentis1.3μA. The integrated 200 mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering 1.5 amperes of continuous current to a load. The TPS54140A reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the highsideMOSFEToffwhenthebootvoltagefallsbelowapresetthreshold.TheTPS54140Acanoperateathigh duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8 V reference. The TPS54140A has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowingthepintotransitionhighwhenapull-upresistorisused. The TPS54140A minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from turningonuntiltheoutputvoltageislowerthan107%. The SS/TR (slow start and tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor dividercanbecoupledtothepinforcriticalpowersupplysequencingrequirements.TheSS/TRpinisdischarged before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault, UVLOfaultoradisabledcondition. The TPS54140A, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startupandovercurrentfaultconditionstohelpcontroltheinductorcurrent. 12 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 7.2 Functional Block Diagram PWRGD EN VIN 6 3 2 Shutdown Thermal Shutdown UVLO Enable UO Logic Comparator Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Minimum Boot Reference Clamp UVLO Current Pulse Sense ERROR Skip AMPLIFIER PWM VSENSE 7 Comparator 1 BOOT SS/TR 4 Logic And PWM Latch Shutdown Slope Compensation COMP 8 10 PH 11 POWERPAD Frequency Shift Overload Maximum Recovery Clamp Oscillator 9 GND with PLL TPS54140ABlock Diagram 5 RT/CLK 7.3 Feature Description 7.3.1 FixedFrequencyPWMControl The TPS54140A uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the COMP voltage level the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximumlevel.TheEco-mode™isimplementedwithaminimumclampontheCOMPpin. 7.3.2 SlopeCompensationOutputCurrent The TPS54140A adds a compensating ramp to the switch current signal. This slope compensation prevents sub- harmonicoscillations.Theavailablepeakinductorcurrentremainsconstantoverthefulldutycyclerange. 7.3.3 PulseSkipEco-mode The TPS54140A enters the pulse skip mode when the voltage on the COMP pin is the minimum clamp value. The TPS54140A operates in a pulse skip mode at light load currents to improve efficiency. The peak switch current during the pulse skip mode will be the greater value of 50mA or the peak inductor current that is a function of the minimum on time, input voltage, output voltage and inductance value. When the load current is low and the output voltage is within regulation the device will enter a sleep mode and draw only 116 μA input Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Feature Description (continued) quiescentcurrent.Whilethedeviceisinsleepmodetheoutputpowerisdeliveredbytheoutputcapacitor.Asthe load current decreases, the time the output capacitor supplies the load current increases and the switching frequency decreases reducing gate drive and switching losses. As the output voltage drops, the TPS54140A wakes up from the sleep mode and the power switch turns on to recharge the output capacitor, see Figure 25. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip modetheswitchingtransitionsoccursynchronouslywiththeexternalclocksignal. VOUT(ac) IL PH Figure25. PulseSkipModeOperation 7.3.4 BootstrapVoltage(BOOT) TheTPS54140AhasanintegratedbootregulatorandrequiresasmallceramiccapacitorbetweentheBOOTand PHpintoprovidethegatedrivevoltageforthehighsideMOSFET.Thevalueoftheceramiccapacitorshouldbe 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54140A is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high side MOSFET is turned off using an UVLO circuit allowing for the low side diode to conduct which allows refreshing of the BOOT capacitor. Since the supply current sourced from the BOOT capacitor is low, the high side MOSFET can remain on for more switching cycles than it refreshes, thus, the effectivedutycyclelimitationthatisattributedtothebootregulatorsystemishigh. 7.3.5 LowDropoutOperation The duty cycle during dropout of the regulator will be mainly determined by the voltage drops across the power MOSFET, inductor, low side diode and printed circuit board resistance. During operating conditions in which the input voltage drops, the high side MOSFET can remain on for 100% of the duty cycle to maintain output regulationoruntiltheBOOTtoPHvoltagefallsbelow2.1V. Once the high side is off, the low side diode will conduct and the BOOT capacitor will be recharged. During this boot capacitor recharge time, the inductor current will ramp down until the high side MOSFET turns on. The recharge time is longer than the typical high side off time of previous switching cycles, and thus, the inductor current ripple is larger resulting in more ripple voltage on the output. The recharge time is a function of the input voltage,bootcapacitorvalue,andtheimpedanceoftheinternalbootrechargediode. 14 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Feature Description (continued) Attention needs to be taken in maximum duty cycle applications which experience extended time periods without a load current. When the voltage across the BOOT capacitors falls below the 2.1-V threshold in applications that have a difference in the input voltage and output voltage that is less than 3 V, the high side MOSFET will be turned off but there is not enough current in the inductor to pull the PH pin down to recharge the boot capacitor. The regulator will not switch because the boot capacitor is less than 2.1 V and the output capacitor will decay until the difference in the input voltage and output voltage is 2.1 V. At this time the boot under voltage lockout is exceededandthedevicewillswitchuntilthedesiredoutputvoltageisreached. The start and stop voltages are shown in Figure 26 and Figure 27 for 3.3-V and 5-V applications. The voltages are plotted versus the load current. The start voltage is defined as the input voltage needed to regulate within 1%.Thestopvoltageisdefinedastheinputvoltageatwhichtheoutputdropsby5%orstopsswitching. 4 5.6 VO= 3.3 V VO= 5 V 3.8 5.4 V- Input Voltage - VI 33..46 SSttaorpt V- Input Voltage - VI 5.52 Start Stop 3.2 4.8 3 4.6 0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20 IO- Output Current -A IO- Output Current -A Figure26.3.3-VStart/StopVoltage Figure27.5.0-VStart/StopVoltage 7.3.6 ErrorAmplifier The TPS54140A has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8 V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation, thetransconductanceisafractionofthenormaloperatinggm.WhenthevoltageoftheVSENSEpinisbelow0.8 VandthedeviceisregulatingusingtheSS/TRvoltage,thegmis25 μA/V. The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin toground. 7.3.7 VoltageReference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output ofatemperaturestablebandgapcircuit. 7.3.8 OverloadRecoveryCircuit The TPS54140A has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of 100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed,theoutputwillslowstartfromthefaultvoltagetonominaloutputvoltage. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Feature Description (continued) 7.3.9 OvercurrentProtectionandFrequencyShift The TPS54140A implements current mode control which uses the COMP pin voltage to turn off the high side MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high input voltages the TPS54140A implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSEpin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum inputvoltagelimitinwhichthedeviceoperatesandstillhavefrequencyshiftprotection. Duringshort-circuitevents(particularlywithhighinputvoltageapplications),thecontrolloophasafiniteminimum controllable on time and the output has a very low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp upamount.Thefrequencyshifteffectivelyincreasestheofftimeallowingthecurrenttorampdown. 7.3.10 PowerGood(PWRGDPin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10 and 100kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD will achievefullcurrentsinkingcapabilityasVINinputvoltageapproaches3V. ThePWRGDpinispulledlowwhentheVSENSEislowerthan92%orgreaterthan109%ofthenominalinternal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulledlow. 7.3.11 OvervoltageTransientProtection The TPS54140A incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high side MOSFET is allowed toturnonatthenextclockcycle. 7.3.12 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence bydischargingtheSS/TRpin. 16 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 7.4 Device Functional Modes 7.4.1 OperationwithVIN <3.5V(MinimumV ) IN Thedeviceisrecommendedtooperatewithinputvoltagesabove3.5V.ThetypicalVINUVLOthresholdis2.5V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device will not switch. The PWRGD output will be controlled once VIN is above 1.5 V maximum. If EN is externally pulled up to VIN or left floating, when VIN passes the UVLO threshold the device will become active. Switching is enabled the soft start sequence is initiated. The TPS54140 will start at the soft starttimedeterminedbytheexternalsoftstartcapacitorattheSS/TRpin. 7.4.2 OperationwithENControl The enable threshold voltage is 1.25 V typical. With EN held below that voltage the device is disabled and switchingisinhibitedevenifVINisaboveitsUVLOthreshold.TheICquiescentcurrentisreducedinthisstate.If the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes active.Switchingisenabled,andthesoftstartsequenceisinitiated.TheTPS54140willstartatthesoftstarttime determinedbytheexternalslowstartcapacitorattheSS/TRpin. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54140A is a 42-V, 1.5-A, step-down regulator with an integrated high-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 1.5 A. Example applications are 12-V, 24-V and 48-V Industrial, Automotive and Commercial power systems. Use the following design procedure to select component values for the TPS54140A. This procedure illustrates the design of a high-frequency switching regulator. The Excel® spreadsheet (SLVC432) located on the product page can help on all calculations. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of componentswhengeneratingadesign. 8.1.1 AdjustingtheOutputVoltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable æ(VOUT -0.8V)ö R1=R2´ç ÷ ç 0.8V ÷ è ø (1) 8.1.2 EnableandAdjustingUndervoltageLockout The TPS54140A is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation providing a consistent power up behavior is recommended. The EN pin has an internal pull-up current source, I1, of 0.9 μA that provides the default condition of the TPS54140A operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the input startvoltage. TPS54140A VIN Ihys I1 R1 0.9mA 2.9mA + R2 EN 1.25 V - Figure28. AdjustableUndervoltageLockout(UVLO) V -V R1= START STOP I HYS (2) 18 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Application Information (continued) V R2= ENA V -V START ENA +I R1 1 (3) Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sourcesadditionalhysteresiscurrentintotheENpin. TPS54140A VIN Ihys R1 I1 2.9mA 0.9mA + R2 EN 1.25 V - VOUT R3 Figure29. AddingAdditionalHysteresis V -V R1= START STOP V I + OUT HYS R3 (4) V R2= ENA V -V V START ENA +I - ENA R1 1 R3 (5) Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if V > 5 V when using a voltage divider to adjust the start and stop voltage. EN The node voltage, (see Figure 30) must remain equal to or less than 5.8 V. The zener diode can sink up to 100 µA. The EN pin voltage can be greater than 5 V if the V voltage source has a high impedance and does not IN sourcemorethan100µAintotheENpin. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Application Information (continued) VIN R1 ENA Node 10kohm R2 5.8V Figure30. NodeVoltage 8.1.3 SlowStart/TrackingPin(SS/TR) The TPS54140A effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to groundimplementsaslowstarttime.TheTPS54140Ahasaninternalpull-upcurrentsourceof2 μAthatcharges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6. The voltage reference (V ) is 0.8 V and the slow start current (I ) is 2 μA. The slow start capacitor should REF SS remainlowerthan0.47μFandgreaterthan0.47nF. CSS(nF)= tSSVR(mEFs()V´I)S´S0(.m8A) (6) At power up, the TPS54140A will not start switching until the slow start pin is discharged to less than 40 mV to ensureaproperpowerup,seeFigure31. Also, during normal operation, the TPS54140A stops switching and the SS/TR must be discharged to 40 mV when the voltage at the VIN pin is below the VIN UVLO, EN pin pulled below 1.25 V, or a thermal shutdown eventoccurs. The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure23).TheSS/TRvoltagewillramplinearlyuntilclampedat1.7V. 20 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Application Information (continued) EN SS/TR V SENSE VOUT Figure31. OperationofSS/TRPinwhenStarting 8.1.4 ConstantSwitchingFrequencyandTimingResistor(RT/CLKPin) The switching frequency of the TPS54140A is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 7 or the curves in Figure 32 or Figure 33. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimumcontrollableontimeshouldbeconsidered. Theminimumcontrollableontimeistypically130nsandlimitsthemaximumoperatinginputvoltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of themaximumswitchingfrequencyislocatedbelow. 206033 RRT(kW)= 1.0888 f (kHz) SW (7) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Application Information (continued) 2500 500 V= 12 V, I T = 25°C J Hz 2000 z) 400 k H Frequency - 1500 equency (k 300 witching 1000 ching Fr 200 f- Ss 500 Swit 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK - Clock Resistance - kW RT/CLK Resistance (kW) Figure32.SwitchingFrequencyvsRT/CLKResistance C006 Figure33.SwitchingFrequencyvsRT/CLKResistance HighFrequencyRange LowFrequencyRange 8.1.5 SelectingtheSwitchingFrequency The switching frequency that is selected should be the lower value of the two equations, Equation 8 and Equation 9. Equation 8 is the maximum switching frequency limitation set by the minimum controllable on time. Settingtheswitchingfrequencyabovethisvaluewillcausetheregulatortoskipswitchingpulses. Equation 9 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the fsw(maxshift) frequency. In Equation 9, to calculate the maximum switching frequency one must take into accountthattheoutputvoltagedecreasesfromthenominalvoltageto0volts,thefdivintegerincreasesfrom1to 8correspondingtothefrequencyshift. In Figure 34, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.1 Ω, FET on resistance of 0.2Ω and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching frequency. æ ö 1 I ´R +V +V f = ´ç L dc OUT d ÷ SW(maxskip) t çV -I ´R +V ÷ ON è IN L DS(on) d ø (8) fSWshift = fDIV ´æçIL´Rdc +VOUT(sc)+Vd ö÷ tON ç VIN-IL´RDS(on)+Vd ÷ è ø (9) I inductorcurrent L Rdc inductorresistance V maximuminputvoltage IN V outputvoltage OUT V outputvoltageduringshort OUTSC Vc diodevoltagedrop R switchonresistance DS(on) t minimumcontrollableontime ON(min) ƒ frequencydivideequals(1,2,4,or8) DIV 22 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Application Information (continued) 2500 V = 3.3 V O Hz 2000 y - k Shift c n ue 1500 q Fre Skip g n hi 1000 c wit S - fs 500 0 10 20 30 40 VI- Input Voltage - V Figure34. MaximumSwitchingFrequencyvs.InputVoltage 8.1.6 HowtoInterfacetoRT/CLKPin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 35. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended to use a frequency set resistor connected as shown in Figure 35 through a 50Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLKthresholdthedeviceswitchesfromtheRTresistorfrequencytoPLLmode.Theinternal0.5Vvoltagesource is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decreasetheswitchingfrequencyuntilthePLLlocksontotheCLKfrequencywithin100microseconds. When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5 V voltage and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 36, Figure 37 and Figure 38 show the device synchronized to an external system clockincontinuousconductionmode(ccm)discontinuousconduction(dcm)andpulseskipmode(psm). TPS54140A 10 pF 4 kW PLL R fset EXT RT/CLK Clock 50W Source Figure35. SynchronizingtoaSystemClock Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Application Information (continued) EXT EXT VOUT IL PH PH IL Figure36.PlotofSynchronizinginCCM Figure37.PlotofSynchronizinginDCM EXT IL PH Figure38.PlotofSynchronizinginPSM 24 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 8.2 Typical Application L1 10mH C1 0.1mF 3.3 V at 1.5A U1 D1 + COUT TPS54140ADGQ B220A 47mF/6.3 V 8 - 18 V BOOT PH VIN GND C2 C3 C4 R3 EN COMP 2.2mF 2.2mF 0.1mF 332 kW RSTS//CTLRKPwPdPWVRSGNDS 6.8 CpFF 7R6C.8 kW 3R11.6 kW CSS RT R4 0.01mF 90.9 kW CC R2 61.9 kW 2700 pF 10 kW Figure39. HighFrequency,3.3VOutputPowerSupplyDesignwithAdjustedUVLO 8.2.1 DesignRequirements This example details the design of a high frequency switching regulator design using ceramic output capacitors. Afewparametersmustbeknowninordertostartthedesignprocess.Theseparametersaretypicallydetermined atthesystemlevel.Forthisexample,wewillstartwiththefollowingknownparameters: Table1.DesignParameters DESIGNPARAMETER EXAMPLEVALUE OutputVoltage 3.3V TransientResponse0to1.5-A ΔVout=4% loadstep MaximumOutputCurrent 1.5A InputVoltage 12Vnom.8Vto18V OutputVoltageRipple <33mV pp StartInputVoltage(risingVIN) 7.7V StopInputVoltage(fallingVIN) 6.7V 8.2.2 DetailedDesignProcedure 8.2.2.1 SelectingtheSwitchingFrequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switchesatalowerfrequency.Theswitchingfrequencythatcanbeselectedislimitedbytheminimumon-timeof theinternalpowerswitch,theinputvoltageandtheoutputvoltageandthefrequencyshiftlimitation. Equation 8 and Equation 9 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping or thelackofovercurrentprotectionduringashortcircuit. The typical minimum on time, t , is 130 ns for the TPS54140A. For this example, the output voltage is 3.3 V onmin and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz when including the inductor resistance, on resistance and diode voltage in Equation 8. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 9 or the solid curve in Figure 34 to determine the maximum switching frequency. With an maximum input voltage of 20 V, assuming a diode voltage of 0.5V, inductor resistance of 100 mΩ, switch resistance of 200 mΩ, an output current of 2.8 A, the maximum switching frequencyisapproximately1600kHz. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Choosing the lower of the two values and adding some margin a switching frequency of 1200kHz is used. To determinethetimingresistanceforagivenswitchingfrequency,useEquation7 orthecurveinFigure32. TheswitchingfrequencyissetbyresistorR showninFigure39. t 8.2.2.2 OutputInductorSelection(L ) O Tocalculatetheminimumvalueoftheoutputinductor,useEquation10. K isacoefficientthatrepresentstheamountofinductorripplecurrentrelativetothemaximumoutputcurrent. IND The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion ofthedesigner;however,thefollowingguidelinesmaybeused. For designs using low ESR output capacitors such as ceramics, a value as high as K = 0.3 may be used. IND When using higher ESR output capacitors, K = 0.2 yields better results. Since the inductor ripple current is IND part of the PWM control system, the inductor ripple current should always be greater than 100 mA for dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use K = 0.2 and the minimum inductor value is calculated to be 7.6 μH. For this IND design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation12andEquation13. For this design, the RMS inductor current is 1.506 A and the peak inductor current is 1.62 A. The chosen inductorisaMSS6132-103.Ithasasaturationcurrentratingof1.64AandanRMScurrentratingof1.9A. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of theregulatorbutallowforalowerinductancevalue. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitchcurrentlimitratherthanthepeakinductorcurrent. L = VIN(max)-VOUT ´ VOUT O(min) IOUT´KIND VIN(max)´ fSW (10) V ´(V -V ) OUT IN(max) OUT I = RIPPLE V ´L ´ f IN(max) O SW (11) 2 2 1 æçVOUT´(VIN(max)-VOUT)ö÷ IL(rms)= (IOUT) +12´çç VIN(max)´LO´ fSW ÷÷ è ø (12) I I =I + RIPPLE L(peak) OUT 2 (13) 8.2.2.3 OutputCapacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in loadcurrent.Theoutputcapacitanceneedstobeselectedbasedonthemorestringentofthesethreecriteria. 26 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance necessarytoaccomplishthis. Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no load) to 1.5 A (full load). For this example, ΔIout = 1.5-0 = 1.5 A and ΔVout = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 18.9 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higherESRthatshouldbetakenintoaccount. The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 40. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 15 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, I is the output current under heavy load, I is the output under light load, Vƒ is the OH OL final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 1.5 A to 0 A. The output voltage will increase during this load transition and the stated maximum in our specification is 4% of the output voltage. This will make Vƒ = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 15 yields a minimum capacitance of25.3 μF. Equation 16 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, V is the maximum allowable output voltage ripple, and I is the oripple ripple inductorripplecurrent.Equation17yields0.7 μF. Equation 17 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.Equation17indicatestheESRshouldbelessthan144mΩ. The most stringent criteria for the output capacitor is 25.3 μF of capacitance to keep the output voltage in regulationduringanunloadtransient. Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase thisminimumvalue.Forthisexample,a47 μF6.3VX7Rceramiccapacitorwith5mΩ ofESRwillbeused. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRootMeanSquare(RMS)valueofthemaximumripplecurrent.Equation18 canbeused to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 18 yields 66mA. 2´DI C > OUT OUT fSW ´DVOUT (14) ((I )2-(I )2) OH OL C >L ´ OUT O ((V )2-(V)2) f i (15) 1 1 C > ´ OUT 8´ fSW æVOUT(ripple)ö ç ÷ ç I ÷ è RIPPLE ø (16) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com V OUT(ripple) R = ESR I RIPPLE (17) ( ) V ´ V -V OUT IN(max) OUT I = COUT(rms) 12´V ´L ´ f IN(max) O SW (18) 8.2.2.4 CatchDiode The TPS54140A requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode,thehighertheefficiencyoftheregulatorwillbe. Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since the design example has an input voltage up to 18 V, a diode with a minimum of 20 V reverse voltage will be selected. For the example design, the B220A Schottky diode is selected for its lower forward voltage and it comes in a largerpackagesizewhichhasgoodthermalcharacteristicsoversmalldevices.Thetypicalforwardvoltageofthe B220Ais0.50volts. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 19 is used to calculate the total power dissipation,conductionlossesplusaclosses,ofthediode. The B220A has a junction capacitance of 120 pF. Using Equation 19, the selected diode will dissipate 0.632 Watts. This power dissipation, depending on mounting techniques, should produce a 16°C temperature rise in thediodewhentheinputvoltageis18Vandtheloadcurrentis1.5A. If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diodewhichhasalowleakagecurrentandslightlyhigherforwardvoltagedrop. ( ) VIN(max)-VOUT ´ IOUT´Vfd Cj´ fSW ´(VIN+Vfd)2 P = + D V 2 IN(max) (19) 8.2.2.5 InputCapacitor The TPS54140A requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitormustalsohavearipplecurrentratinggreaterthanthemaximuminputcurrentrippleoftheTPS54140A. TheinputripplecurrentcanbecalculatedusingEquation20. The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreasesasthedcbiasacrossacapacitorincreases. 28 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 For this example design, a ceramic capacitor with at least a 20 V voltage rating is required to support the maximuminputvoltage.Commonstandardceramiccapacitorvoltageratingsinclude4V,6.3V,10V,16V,25V, 50 V or 100V so a 25 V capacitor should be selected. For this example, two 2.2 μF, 25 V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value determinestheinputripplevoltageoftheregulator.TheinputvoltageripplecanbecalculatedusingEquation21. Using the design example values, Ioutmax = 1.5 A, Cin = 4.4 μF, ƒsw = 1200 kHz, yields an input voltage ripple of71mVandarmsinputripplecurrentof0.701A. ( ) V VIN(min)-VOUT ICI(rms)=IOUT´ V OUT ´ V IN(min) IN(min) (20) I ´0.25 OUT(max) DVIN = CIN´ fSW (21) Table2.CapacitorTypes VENDOR VALUE(μF) EIASize VOLTAGE DIALECTRIC COMMENTS 1.0to2.2 100V 1210 GRM32series 1.0to4.7 50V Murata 1.0 100V 1206 GRM31series 1.0to2.2 50V 1.0101.8 50V 2220 1.0to1.2 100V Vishay VJX7Rseries 1.0to3.9 50V 2225 1.0to1.8 100V X7R 1.0to2.2 100V 1812 CseriesC4532 1.5to6.8 50V TDK 1.0.to2.2 100V 1210 CseriesC3225 1.0to3.3 50V 1.0to4.7 50V 1210 1.0 100V AVX X7Rdielectricseries 1.0to4.7 50V 1812 1.0to2.2 100V 8.2.2.6 SlowStartCapacitor The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54140A reach the current limit or excessive current draw from the input power supply may cause the input voltagerailtosag.Limitingtheoutputvoltageslewratesolvesbothoftheseproblems. The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 22 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the 47 μF output capacitor up to 3.3 V while only allowing theaverageinputcurrenttobe0.125Awouldrequirea1msslowstarttime. Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical since the output capacitor value is 47 μF which does not require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of 1mswhichrequiresa3.3nFcapacitor. C ´V ´0.8 t > OUT OUT SS I SS(avg) (22) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 8.2.2.7 BootstrapCapacitorSelection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V orhighervoltagerating. 8.2.2.8 UndervoltageLockOutSetPoint The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54140A. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power downorbrownoutswhentheinputvoltageisfalling.Fortheexampledesign,thesupplyshouldturnonandstart switching once the input voltage increases above 7.7 V (enabled). After the regulator starts switching, it should continuetodosountiltheinputvoltagefallsbelow6.7V(UVLOstop). TheprogrammableUVLOandenablevoltagesaresetusingaresistordividerbetweenVinandgroundtotheEN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 332 kΩ between Vin and EN and a 61.9 kΩ between EN and ground are required to produce the 7.7and6.7voltstartandstopvoltages. 8.2.2.9 OutputVoltageandFeedbackResistorsSelection For the example design, 10.0 kΩ was selected for R2. Using Equation 1, R1 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease quiescentcurrentandimproveefficiencyatlowoutputcurrentsbutmayintroducenoiseimmunityproblems. 8.2.2.10 Compensation There are several industry techniques used to compensate DC/DC regulators. The method presented here yields high phase margins. For most conditions, the regulator will have a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54140A. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequencyusedinthecalculations. UseSwitcherProsoftwareforamoreaccuratedesign. The uncompensated regulator will have a dominant pole, typically located between 300 Hz and 3 kHz, due to the output capacitor and load resistance and a pole due to the error amplifier. One zero exists due to the output capacitorandtheESR.Thezerofrequencyishigherthaneitherofthetwopoles. Ifleftuncompensated,thedoublepolecreatedbytheerroramplifierandthemodulatorwouldleadtoanunstable regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a compensating zero at the modulator pole. Then select a cross over frequency that is higher than the modulator pole.Thegainoftheerroramplifiercanbecalculatedtoachievethedesiredcrossoverfrequency.Thecapacitor used to create the compensation zero along with the output impedance of the error amplifier form a low frequency pole to provide a minus one slope through the cross over frequency. Then a compensating pole is added to cancel the zero due to the output capacitors ESR. If the ESR zero resides at a frequency higher than theswitchingfrequencythenitcanbeignored. TocompensatetheTPS54140Ausingthismethod,firstcalculatethemodulatorpoleandzerousingthefollowing equations: I OUT(max) f = P(mod) 2´p´VOUT´COUT where • I isthemaximumoutputcurrent OUT(max) • C istheoutputcapacitance OUT • V isthenominaloutputvoltage (23) OUT 1 f = Z(mod) 2´p´RESR´COUT (24) 30 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Fortheexampledesign,themodulatorpoleislocatedat1.5kHzandtheESRzeroislocatedat338kHz. Next, the designer needs to select a crossover frequency which will determine the bandwidth of the control loop. The cross over frequency must be located at a frequency at least five times higher than the modulator pole. The cross over frequency must also be selected so that the available gain of the error amplifier at the cross over frequencyishighenoughtoallowforpropercompensation. Equation29isusedtocalculatethemaximumcrossoverfrequencywhentheESRzeroislocatedatafrequency that is higher than the desired cross over frequency. This will usually be the case for ceramic or low ESR tantalum capacitors. Aluminum Electrolytic and Tantalum capacitors will typically produce a modulator zero at a lowfrequencyduetotheirhighESR. TheexampleapplicationisusingalowESRceramiccapacitorwith10mΩ ofESRmakingthezeroat338kHz. This value is much higher than typical crossover frequencies so the maximum crossover frequency is calculated usingbothEquation25andEquation28. Using Equation 28 gives a minimum crossover frequency of 7.6 kHz and Equation 25 gives a maximum crossoverfrequencyof45.3kHz. Acrossoverfrequencyof45kHzisarbitrarilyselectedfromthisrange. ForceramiccapacitorsuseEquation25: f P(mod) f £2100 C(max) V OUT (25) FortantalumoraluminumcapacitorsuseEquation26: 51442 f £ C(max) V OUT (26) ForallcasesuseEquation27andEquation28: fSW f £ C(max) 5 (27) f ³5´ f C(min) P(mod) (28) Once a cross over frequency, ƒc, has been selected, the gain of the modulator at the cross over frequency is calculated.ThegainofthemodulatoratthecrossoverfrequencyiscalculatedusingEquation29. gm ´R ´(2p´ f ´C ´R +1) (PS) LOAD C OUT ESR G = MOD(fc) 2p´ f ´C ´(R +R )+1 C OUT LOAD ESR (29) Fortheexampleproblem,thegainofthemodulatoratthecrossoverfrequencyis0.542.Next,thecompensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on if the ESR zero is located above or below the cross over frequency. For ceramic or low ESR tantalum output capacitors, the zero will usually be located above the cross over frequency. For aluminum electrolytic and tantalum capacitors, the modulator zero is usually located lower in frequency than the cross over frequency. For cases where the modulator zero is higher than the cross over frequency (ceramic capacitors). V R = OUT C G ´gm ´V MOD(fc) (EA) REF (30) 1 CC = 2p´RC´ fP(mod) (31) C ´R Cf = OUT ESR R C (32) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com For cases where the modulator zero is less than the cross over frequency (Aluminum or Tantalum capacitors), theequationsare: V R = OUT C G ´ f ´gm ´V MOD(fc) Z(mod) (EA) REF (33) 1 CC = 2p´RC´ fP(mod) (34) 1 Cf = 2p´RC´ fZ(mod) (35) For the example problem, the ESR zero is located at a higher frequency compared to the cross over frequency so Equation 32 through Equation 35 are used to calculate the compensation components. For the example problem,thecomponentsarecalculatedtobe:R =76.2kΩ,C =2710pF,andCƒ=6.17pF. C C The calculated value of the Cƒ capacitor is not a standard value so a value of 2700 pF will be used. 6.8 pF is used for C . Rc resistor sets the gain of the error amplifier which determines the cross over frequency. The C calculatedR resistorisnotastandardvalue,so76.8kΩ willbeused. C 8.2.3 ApplicationCurves VIN VO VOUT IO EN IL Figure40.LoadTransmit Figure41.StartupWithEN VOUT VOUT IL PH VIN IL Figure42.VINPowerUp Figure43.OutputRippleCCM 32 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 VOUT VOUT IL IL PH PH Figure44.OutputRipple,DCM Figure45.OutputRipple,PSM VIN VIN IL IL PH PH Figure46.InputRippleCCM Figure47.InputRippleDCM 95 VI= 8 V VO= 3.3 V, 90 fsw= 1200 kHz VIN 85 80 IL cy - % 75 VI= 12 V VI= 16 V n e ci 70 Effi 65 PH 60 55 50 0 0.25 0.50 0.75 1 1.25 1.5 1.75 2 IL- Load Current -A Figure48.InputRipplePSM Figure49.EfficiencyvsLoadCurrent Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com 60 1.015 150 V= 12 V I 1.010 40 100 Phase 1.005 20 50 %) Gain - dB 0 Gain 0 oPhase - egulation ( 1.000 -50 R 0.995 -20 -100 0.990 -150 0.985 -40 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 100 1-103 1-104 1-105 1-106 f - Frequency - Hz Load Current -A Figure50.OverallLoopFrequencyResponse Figure51.RegulationvsLoadCurrent 1.015 I = 0.5A O 1.010 1.005 %) n ( atio 1.000 ul g e R 0.995 0.990 0.985 5 10 15 20 VI- Input Voltage - V Figure52.RegulationvsInputVoltage 34 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 8.3 System Examples 8.3.1 SimpleSmallSignalModelforPeakCurrentModeControl Figure 53 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54140A power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 36 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 56) is the power stage transconductance. The gm for the TPS54140A is 6 A/V. The low-frequency gain of the power stage frequency PS responseistheproductofthetransconductanceandtheloadresistanceasshowninEquation37. Astheloadcurrentincreasesanddecreases,thelow-frequencygaindecreasesandincreases,respectively.This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 38). The combined effect is highlighted by the dashed line in the right half of Figure 53. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases fromtheESRzeroatthelowerfrequencies(seeEquation39). V O VC Adc R ESR fp R L gm ps C OUT fz Figure53. SimpleSmallSignalModelandFrequencyResponseforPeakCurrentModeControl æ s ö ç1+ ÷ VOUT = Adc´è 2p´ fZ ø V æ s ö C ç1+ ÷ è 2p´ fP ø (36) Adc=gm ´ R ps L (37) 1 fP = C ´R ´2p OUT L (38) 1 fZ = C ´R ´2p OUT ESR (39) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com System Examples (continued) 8.3.2 SmallSignalModelforFrequencyCompensation The TPS54140A uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 54. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors.. Equation 40 and Equation 41 show how to relate the frequency response of theamplifiertothesmallsignalmodelinFigure54.Theopen-loopgainandbandwidtharemodeledusingtheR O and C shown in Figure 54. See Figure 39 for a design example using a Type 2A network with a low ESR output O capacitor. Equation 40 through Equation 49 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application sectionoruseswitchedinformation. V O R1 VSENSE gm Type 2A Type 2B Type 1 ea COMP Vref R3 C2 R3 R2 RO CO C2 C1 C1 Figure54. TypesofFrequencyCompensation Aol P1 A0 Z1 P2 A1 BW Figure55. FrequencyResponseoftheType2AandType2BFrequencyCompensation 36 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 System Examples (continued) Aol(V/V) Ro= gm ea (40) gm C = ea OUT 2p ´ BW (Hz) (41) æ s ö ç1+ ÷ è 2p´fZ1ø EA = A0´ æ s ö æ s ö ç1+ ÷´ç1+ ÷ è 2p´fP1ø è 2p´fP2 ø (42) R2 A0=gm ´ Ro ´ ea R1+R2 (43) R2 A1=gm ´ Ro||R3 ´ ea R1+R2 (44) 1 P1= 2p´Ro´C1 (45) 1 Z1= 2p´R3´C1 (46) 1 P2= type2a 2p ´ R3||R ´ (C2+C ) OUT (47) 1 P2= type2b 2p ´ R3||R ´ C OUT (48) 1 P2= type1 2p ´ R ´ (C2+C ) OUT (49) 8.3.3 SmallSignalModelforLoopResponse Figure 56 shows an equivalent model for the TPS54140A control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 97 μA/V. The error amplifier can be modeled using an ideal voltage EA controlled current source. The resistor R and capacitor C model the open loop gain and frequency response of o o the amplifier. The 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequencyresponsemeasurements.Plottingc/ashowsthesmallsignalresponseofthefrequencycompensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing R with a current source with the appropriate load step amplitude and step rate in a time domain L analysis.Thisequivalentmodelisonlyvalidforcontinuousconductionmodedesigns. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com System Examples (continued) PH Power Stage VO gmps6A/V a b R1 RESR COMP RL c 0.8 V VSENSE COUT R3 CO RO gmea C2 97mA/V R2 C1 Figure56. SmallSignalModelforLoopResponse 38 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 9 Power Supply Recommendations The devices are designed to operate from an input voltage supply range between 3.5 V and 60 V. This input supply should be well regulated. If the input supply is located more than a few inches from the TPS54160 converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolyticcapacitorwithavalueof100μFisatypicalchoice 9.1 Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of anotherdevice.ThesequentialmethodisillustratedinFigure57usingtwoTPS54140Adevices.Thepowergood is coupled to the EN pin on the TPS54140A which will enable the second power supply once the primary supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply will provide a 1msstartupdelay.Figure58showstheresultsofFigure57. SPACE TPS54140A PWRGD EN EN EN1 SS/TR SS/TR PWRGD1 PWRGD VOUT1 VOUT2 Figure57.SchematicforSequentialStart-Up Figure58.SequentialStartupusingENand Sequence PWRGD Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Sequencing (continued) TPS54140A 3 EN EN1, EN2 4 SS/TR 6 PWRGD VOUT1 VOUT2 TPS54140A 3 EN 4 SS/TR 6 PWRGD Figure59.SchematicforRatiometricStart-Up Figure60.Ratio-MetricStartupusingCoupled Sequence SS/TRpins Figure 59 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pullupcurrentsourcemustbedoubledinEquation6.Figure60showstheresultsofFigure59. 40 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 Sequencing (continued) TPS54140A EN VOUT1 SS/TR PWRGD TPS54140A EN VOUT2 R1 SS/TR R2 PWRGD R3 R4 Figure61. SchematicforRatiometricandSimultaneousStart-UpSequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 61 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 50 and Equation 51, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 52 is the voltage difference between Vout1 andVout2atthe95%ofnominaloutputregulation. The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and trackingresistors,theVssoffsetandIssareincludedasvariablesintheequations. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 50 through Equation 52 for deltaV. Equation 52 will result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 50 is greater than the value calculated in Equation 53 to ensure the device canrecoverfromafault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure23. V R1= VOUT2 +DV + SS(offset) V I REF SS (50) V ´R1 R2= REF V +DV-V OUT2 REF (51) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Sequencing (continued) DV = V -V OUT1 OUT2 (52) R1>2800´V -180´DV OUT1 (53) EN EN VOUT1 VOUT1 VOUT2 VOUT2 Figure62.Ratio-metricStartupwithTrackingResistors Figure63.RatiometricStartupwithTrackingResistors EN VOUT1 VOUT2 Figure64.SimultaneousStartupWithTrackingResistor 42 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the ICandthepowerpad. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good resultsandismeantasaguideline. 10.2 Layout Example Vout Output Capacitor Output Topside Inductor Ground Route Boot Capacitor Catch Area Trace on another layer to Diode provide wide path for topside ground Input Bypass Capacitor BOOT PH Vin VIN GND EN COMP UVLO Adjust SS/TR VSENSE Compensation Resistor Resistors Network RT/CLK PWRGD Divider Slow Start Frequency Thermal VIA Capacitor Set Resistor Signal VIA Figure65. PCBLayoutExample 10.3 Power Dissipation Estimate The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:TPS54140A

TPS54140A SLVSB55C–MAY2012–REVISEDOCTOBER2015 www.ti.com Power Dissipation Estimate (continued) The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) andsupplycurrent(Pq). PCOND =(IOUT)2´RDS(on)´æçVVOUT ö÷ è IN ø (54) PSW =(VIN)2´ fSW ´IOUT´0.25´10-9 (55) PGD = VIN´3´10-9´ fSW (56) P =116´10-6´V Q IN where • I istheoutputcurrent(A) OUT • R istheon-resistanceofthehigh-sideMOSFET(Ω) DS(on) • V istheoutputvoltage(V) OUT • V istheinputvoltage(V) IN • ƒ istheswitchingfrequency(Hz) (57) SW P =P ´P ´P ´P TOT COND SW GD Q (58) ForgivenT , A T =T +R ´P J A TH TOT (59) ForgivenT =150°C JMAX TA(max)=TJ(max)-RTH´PTOT where • P sthetotaldevicepowerdissipation(W) TOT • T istheambienttemperature(°C) A • T isthejunctiontemperature(°C) J • R isthethermalresistanceofthepackage(°C/W) TH • T ismaximumjunctiontemperature(°C) J(max) • T ismaximumambienttemperature(°C). (60) A(max) There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode andtraceresistancethatwillimpacttheoverallefficiencyoftheregulator. 44 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54140A

TPS54140A www.ti.com SLVSB55C–MAY2012–REVISEDOCTOBER2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks Eco-mode,PowerPAD,SwitcherPro,E2EaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:TPS54140A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54140ADGQ ACTIVE HVSSOP DGQ 10 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 5414A & no Sb/Br) TPS54140ADGQR ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 5414A & no Sb/Br) TPS54140ADRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 5414A & no Sb/Br) TPS54140ADRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 5414A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54140ADGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54140ADGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS54140ADRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS54140ADRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54140ADRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS54140ADRCT VSON DRC 10 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54140ADGQR HVSSOP DGQ 10 2500 346.0 346.0 35.0 TPS54140ADGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0 TPS54140ADRCR VSON DRC 10 3000 346.0 346.0 35.0 TPS54140ADRCR VSON DRC 10 3000 338.0 355.0 50.0 TPS54140ADRCT VSON DRC 10 250 203.0 203.0 35.0 TPS54140ADRCT VSON DRC 10 250 338.0 355.0 50.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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