Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 TPS5410 1-A, Wide Input Range, Step-Down Converter 1 Features 3 Description • WideInputVoltageRange:5.5Vto36V The TPS5410 is a high-output-current PWM 1 converter that integrates a low-resistance, high-side, • Upto1-AContinuous(1.2-APeak)OutputCurrent N-channel MOSFET. Included on the substrate with • HighEfficiencyUpto95%Enabledby110-mΩ the listed features is a high performance voltage error IntegratedMOSFETSwitch amplifier that provides tight voltage regulation • WideOutputVoltageRange:AdjustableDownto accuracy under transient conditions; an undervoltage- lockout circuit to prevent start-up until the input 1.22Vwith1.5%InitialAccuracy voltage reaches 5.5 V; an internally set slow-start • InternalCompensationMinimizesExternalParts circuit to limit inrush currents; and a voltage feed- Count forward circuit to improve the transient response. • Fixed500-kHzSwitchingFrequencyforSmall Using the ENA pin, shutdown supply current is FilterSize reduced to 18 μA typically. Other features include an active high enable, overcurrent limiting, overvoltage • ImprovedLineRegulationandTransient protection and thermal shutdown. To reduce design ResponsebyInputVoltageFeed-Forward complexity and external component count, the • SystemProtectedbyOvercurrentLimiting, TPS5410feedbackloopisinternallycompensated. OvervoltageProtectionandThermalShutdown The TPS5410 device is available in an easy to use 8- • –40°Cto125°COperatingJunctionTemperature pin SOIC package. TI provides evaluation modules Range and software tools to aid in quickly achieving high- • AvailableinSmall8-PinSOICPackage performance power supply designs to meet aggressiveequipmentdevelopmentcycles. 2 Applications DeviceInformation(1) • Consumer:Set-TopBox,DVD,LCDDisplays PARTNUMBER PACKAGE BODYSIZE(NOM) • IndustrialandCarAudioPowerSupplies TPS5410D SOIC(8) 3.91mmx4.90mm • BatteryChargers,High-PowerLEDSupply (1) For all available packages, see the orderable addendum at • 12-V/24-VDistributedPowerSystems theendofthedatasheet. Simplified Schematic Efficiency vs Output Current 100 VIN VOUT VIN PH TPS5410 95 NC BOOT % − 90 NC cy n e ci ENA VSENSE Effi 85 GND VI= 20 V V = 12 V O 80 f = 500 kHz s T = 25oC A 75 0 0.2 0.4 0.6 0.8 1 1.2 1.4 IO-Output Current-A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription...................................................9 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................10 3 Description............................................................. 1 8 ApplicationsandImplementation...................... 11 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................11 8.2 TypicalApplications................................................11 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 21 6 Specifications......................................................... 3 10 Layout................................................................... 21 6.1 AbsoluteMaximumRatings......................................3 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................21 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................22 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 23 6.5 ElectricalCharacteristics...........................................4 11.1 DocumentationSupport .......................................23 6.6 TypicalCharacteristics..............................................6 11.2 Trademarks...........................................................23 7 DetailedDescription.............................................. 8 11.3 ElectrostaticDischargeCaution............................23 7.1 Overview...................................................................8 11.4 Glossary................................................................23 7.2 FunctionalBlockDiagram.........................................8 12 Mechanical,Packaging,andOrderable Information........................................................... 23 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(September2013)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 ChangesfromRevisionB(January2013)toRevisionC Page • DeletedSWIFTfromthedatasheetTitle,Features,andDescription.................................................................................. 1 ChangesfromRevisionA(November2006)toRevisionB Page • ReplacedtheDISSIPATIONRATINGSwiththeTHERMALINFORMATIONtable............................................................... 4 ChangesfromOriginal(August2006)toRevisionA Page • ChangedtheEfficiencyvsOutputCurrentgraph................................................................................................................... 1 • ChangedtheFunctionalBlockDiagram................................................................................................................................. 8 2 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 5 Pin Configuration and Functions DPACKAGE 8PINS TOPVIEW BOOT 1 8 PH NC 2 7 VIN NC 3 6 GND VSENSE 4 5 ENA PinFunctions PIN I/O DESCRIPTION NAME NO. Boostcapacitorforthehigh-sideFETgatedriver.Connect0.01μFlowESRcapacitorfromBOOTpinto BOOT 1 O PHpin. NC 2,3 — Notconnectedinternally. VSENSE 4 I Feedbackvoltagefortheregulator.Connecttooutputvoltagedivider. ENA 5 I On/offcontrol.Below0.5V,thedevicestopsswitching.Floatthepintoenable. GND 6 — Ground. Inputsupplyvoltage.BypassVINpintoGNDpinclosetodevicepackagewithahighquality,lowESR VIN 7 I ceramiccapacitor. PH 8 O SourceofthehighsidepowerMOSFET.Connectedtoexternalinductoranddiode. 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) (2) MIN MAX UNIT VIN –0.3 40(3) PH(steady-state) –0.6 40(3) EN –0.3 7 V Inputvoltagerange I VSENSE –0.3 3 V BOOT-PH –0.3 10 PH(transient<10ns) –1.2 I Sourcecurrent PH InternallyLimited O I Leakagecurrent PH 10 μA lkg T Operatingvirtualjunctiontemperature –40 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesarewithrespecttonetworkgroundterminal. (3) ApproachingtheabsolutemaximumratingfortheVINpinmaycausethevoltageonthePHpintoexceedtheabsolutemaximumrating. Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±1500 V C101(2) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions MIN NOM MAX UNIT V Inputvoltagerange 5.5 36 V VIN T Operatingjunctiontemperature –40 125 °C J 6.4 Thermal Information TPS5410 THERMALMETRIC(1) D UNIT 8PINS R Junction-to-ambientthermalresistance(customboard) (2) 75 θJA R Junction-to-ambientthermalresistance(standardboard) 105.9 θJA R Junction-to-case(top)thermalresistance 45.0 θJC(top) R Junction-to-boardthermalresistance 47.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 5.7 JT ψ Junction-to-boardcharacterizationparameter 47.0 JB R Junction-to-case(bottom)thermalresistance N/A θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) Testboardsconditions: (a)3inx3in,2layers,thickness:0.062inch. (b)2oz.coppertraceslocatedonthetopandbottomofthePCB. 6.5 Electrical Characteristics T =–40°Cto125°C,VIN=5.5Vto36V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) VSENSE=2V,Notswitching,PHpin 3 4.4 mA I Quiescentcurrent open Q Shutdown,ENA=0V 18 50 μA UNDERVOLTAGELOCKOUT(UVLO) Startthresholdvoltage,UVLO 5.3 5.5 V Hysteresisvoltage,UVLO 330 mV VOLTAGEREFERENCE T =25°C 1.202 1.221 1.239 J Voltagereferenceaccuracy V I =0A–1A 1.196 1.221 1.245 O OSCILLATOR Internallysetfree-runningfrequency 400 500 600 kHz Minimumcontrollableontime 150 200 ns Maximumdutycycle 87% 89% ENABLE(ENAPIN) Startthresholdvoltage,ENA 1.3 V Stopthresholdvoltage,ENA 0.5 V Hysteresisvoltage,ENA 450 mV Internalslow-starttime(0~100%) 6.6 8 10 ms 4 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 Electrical Characteristics (continued) T =–40°Cto125°C,VIN=5.5Vto36V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT Currentlimit 1.2 1.5 1.8 A Currentlimithiccuptime 13 16 20 ms THERMALSHUTDOWN Thermalshutdowntrippoint 135 162 °C Thermalshutdownhysteresis 14 °C OUTPUTMOSFET VIN=5.5V 150 r High-sidepowerMOSFETswitch mΩ DS(on) VIN=10V-36V 110 230 Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com 6.6 Typical Characteristics 530 3.5 520 mA VI= 12 V f−Oscillator Frequency−kHz 554401890000 Operating Quiescent Current− 32..27553 − 470 Q I 446600 2.5 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure1.OscillatorFrequencyvsJunctionTemperature Figure2.OperatingQuiescentCurrentvsJunction Temperature 180 11..2233 170 Controllable On Time−ns 111564000 Volta−Volta−ge Referencge Reference−Ve−V 11..1122..22225522 mum VVrefref 11..221155 Mini 130 120 11..2211 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure3.MinimumControllableOnTimevsJunction Figure4.VoltageReferencevsJunctionTemperature Temperature 180 9 170 VI= 12 V Wm 160 ms − − 8.5 r−On-State ResistanceDS(on) 111111152340000000 tInternal Slo−w Start TimeSS 7.58 90 80 7 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TJ−Junction Temperature−oC TJ−Junction Temperature−oC Figure5.OnStateResistancevsJunctionTemperature Figure6.InternalSlow-StartTimevsJunctionTemperature 6 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 Typical Characteristics (continued) 25 8 ENA= 0 V −Am 20 TJ= 125oC % 7.5 ent − utdown Curr 15 TJ= 27oC m Duty Ratio 7.5 h u S m − ni ISD 10 Mi 7.25 TJ= -40oC 7 5 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125 VI−Input Voltage−V TJ−Junction Temperature−oC Figure7.ShutdownQuiescentCurrentvsInputVoltage Figure8.MinimumControllableDutyRatiovsJunction Temperature Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com 7 Detailed Description 7.1 Overview The TPS5410 is a 36-V, 1-A step-down (buck) regulator with an integrated, high-side, N-channel MOSFET. These devices implement constant-frequency voltage-mode control with voltage feed-forward for improved line regulationandlinetransientresponse.Internalcompensationreducesdesigncomplexityandexternalcomponent count. The integrated 110-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering 1-A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied by a bootstrap capacitor connected from the BOOT to PH pins. The TPS5410 reduces the external component countbyintegratingthebootstraprechargediode. The TPS5410 has a default input start-up voltage of 5.3 V typical. The ENA pin can be used to disable the TPS5410 reducing the supply current to 18 µA. An internal pullup current source enables operation when the ENA pin is floating. The TPS5410 includes an internal slow-start circuit that slows the output rise time during startuptoreduceinrushcurrentandoutputvoltageovershoot. The minimum output voltage is the internal 1.221-V feedback reference. Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP comparator is activated, the high- side MOSFET is turned off and remains off until the output voltage is less than 112.5% of the desired output voltage. Internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side MOSFET. For continuous overcurrent fault conditions the TPS5410 will enter hiccup mode overcurrent limiting. Thermal protectionprotectsthedevicefromoverheating. 7.2 Functional Block Diagram VIN VIN UVLO 1.22R1e Vfe Breanncdegap VREF Slow Start SHDN ReBgouolattor BOOT HICCUP 5µA ENA ENABLE SHDN SHDN VSENSE Z1 Thermal Protection SHDN SHDN AmErprolifrier Z2 Ramp NC VIN Generator Feed Forward Gain = 25 NC SHDN PWM HICCUP Comparator GND Overcurrent SHDN Oscillator Protection SHDN Gate Drive VSENSE OVP Control 112.5% VREF Gate Driver SHDN BOOT PH VOUT 8 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 7.3 Feature Description 7.3.1 OscillatorFrequency The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500-kHz switching frequency allows less output inductance for the same output ripple requirement resulting in a smaller output inductor. 7.3.2 VoltageReference The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of 1.221Vatroomtemperature. 7.3.3 Enable(ENA)andInternalSlow-Start The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold voltage, the regulator starts operation and the internal slow-start begins to ramp. If the ENA pin voltage is pulled below the threshold voltage, the regulator stops switching and the internal slow-start resets. Connecting the pin to ground or to any voltage less than 0.5 V disables the regulator and activate the shutdown mode. The quiescentcurrentoftheTPS5410inshutdownmodeistypically18 μA. The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0V to its finalvaluelinearly.Theinternalslow-starttimeis8mstypically. 7.3.4 UndervoltageLockout(UVLO) The TPS5410 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow-start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow-start is released and device start-up begins. The device operates untilVINfallsbelowtheUVLOstopthresholdvoltage.ThetypicalhysteresisintheUVLOcomparatoris330mV. 7.3.5 BoostCapacitor(BOOT) Connect a 0.01-μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable valuesovertemperature. 7.3.6 OutputFeedback(VSENSE) The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage reference1.221V. 7.3.7 InternalCompensation The TPS5410 implements internal compensation to simplify the regulator design. Since the TPS5410 uses voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover frequencyandahighphasemarginforgoodstability.SeetheInternalCompensationNetworkintheApplications sectionformoredetails. 7.3.8 VoltageFeed-Forward The internal voltage feed-forward provides a constant DC power stage gain despite any variations with the input voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed-forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constantatthefeed-forwardgain,forexample: VIN Feed Forward Gain = Ramp pk-pk (1) Thetypicalfeed-forwardgainofTPS5410is25. Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com Feature Description (continued) 7.3.9 Pulse-Width-Modulation(PWM)Control The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and compensationnetworktoproduceaerrorvoltage.Then,theerrorvoltageiscomparedtotherampvoltagebythe PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle. Finally,thePWMoutputisfedintothegatedrivecircuittocontroltheon-timeofthehigh-sideMOSFET. 7.3.10 OvercurrentLiming Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system willignoretheovercurrentindicatorfortheleadingedgeblankingtimeatthebeginningofeachcycletoavoidany turn-onnoiseglitches. Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for the rest of the cycle after a propagation delay. The overcurrent limiting scheme is called cycle-by-cycle current limiting. Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen when using cycle-by-cycle current limiting. A second mode of current limiting is used, for example hiccup mode overcurrentlimiting.Duringhiccupmodeovercurrentlimiting,thevoltagereferenceisgroundedandthehigh-side MOSFETisturnedoffforthehiccuptime.Oncethehiccuptimedurationiscomplete,theregulatorrestartsunder controloftheslow-startcircuit. 7.3.11 OvervoltageProtection The TPS5410 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side MOSFETwillbeenabledagain. 7.3.12 ThermalShutdown The TPS5410 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side MOSFET is turned off. The part is restarted under control of the slow-start circuit automatically when the junction temperaturedrops14°Cbelowthethermalshutdowntrippoint. 7.4 Device Functional Modes 7.4.1 MinimumInputVoltage Confid The TPS5410 is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO threshold is 5.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage the device will not switch. If ENA is floating or externally pulled up to greater up than 1.3 V, when V passes the UVLO threshold the TPS5410 will become active. Switching is enabled and (VIN) the slow-start sequence is initiated. The TPS5410 starts linearly ramping up the internal reference voltage from 0 Vtoitsfinalvalueovertheinternalslow-starttimeperiod. 7.4.2 ENAControl T The enable start threshold voltage is 1.3 V max. With ENA held below the 0.5 V minimum stop threshold voltage the TPS5410 is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent current is reduced in this state. If the ENA voltage is increased above the max start threshold while V is above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start (VIN) sequence is initiated. The TPS5410 starts linearly ramping up the internal reference voltage from 0 V to its final valueovertheinternalslow-starttimeperiod. 10 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS5410 is a 1-A, step down regulator with an integrated high-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 1 A. Example applications are: High Density Point-of-Load Regulators for Set-top Box, DVD, LCD and Plasma Displays, High Power LED Supply, Car Audio, Battery Chargers, and other 12-V and 24-V Distributed Power Systems. Use the following design procedure to select component values for the TPS5410. This procedure illustrates the design of a high frequency switching regulator. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of componentswhengeneratingadesign. 8.2 Typical Applications 8.2.1 ApplicationCircuit Figure 9 shows the schematic for a typical TPS5410 application. The TPS5410 can provide up to 1-A output currentatanominaloutputvoltageof12V. U1 C2 L1 TPS5410D 14.5 V-36 V 7 0.01mF 68mH VIN VIN 1 12 V 5 ENA BOOT VOUT ENA 2 NC PH 8 + C3 R1 C4.17mF 3 NC VSNS 4 D1 4(S7emeF NoteA) 10 kW 6 GND B340A R2 1.13 kW A. C3=TantalumAVXTPSE476M020R0150 Figure9. ApplicationCircuit,14.5-V —36Vto12-V Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com Typical Applications (continued) 8.2.1.1 DesignRequirements Forthisdesignexample,usethefollowingastheinputparameters: Table1.DesignRequirements DESIGNPARAMETER(1) EXAMPLEVALUE Inputvoltagerange 14.5Vto36V Outputvoltage 12V Inputripplevoltage 300mV Outputripplevoltage 50mV Outputcurrentrating 1A Operatingfrequency 500kHz (1) Asanadditionalconstraint,thedesignissetuptobesmallsizeandlowcomponentheight. 8.2.1.2 DetailedDesignProcedure 8.2.1.2.1 SwitchingFrequency The switching frequency for the TPS5410 is internally set to 500 kHz. It is not possible to adjust the switching frequency. 8.2.1.2.2 InputCapacitors The TPS5410 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The minimum recommended value for the decoupling capacitor is 4.7 μF. A high quality ceramic type X5R or X7R is required. For some applications, a smaller value decoupling capacitor may be used, if the input voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage, including ripple. For this design, a 4.7 μF capacitor, C1 issued to allow for smaller 1812 case size to be used whilemaintaininga50Vrating. ThisinputripplevoltagecanbeapproximatedbyEquation2: I x 0.25 OUT(MAX) DV = + ( I x E S R ) IN OUT(MAX) MAX C x ƒ BULK SW (2) Where I is the maximum load current, f is the switching frequency, C is the input capacitor value and OUT(MAX) SW I ESR isthemaximumseriesresistanceoftheinputcapacitor. MAX The maximum RMS ripple current also needs to be checked. For worst case conditions, this is approximated by Equation3: I OUT(MAX) I (cid:1) CIN 2 (3) Inthisexample,thecalculatedinputripplevoltageis137mV,andtheRMSripplecurrentis0.5A.Themaximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actual measured input ripple voltage may be larger than the calculated value due to the output impedance of the input voltagesource,decreaseinactualcapacitanceduetobiasvoltageandparasiticsassociatedwiththelayout. CAUTION The maximum ratings for voltage and current are not to be exceeded under any circumstance. 12 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 Additionally, some bulk capacitance may be needed, especially if the TPS5410 circuit is not located within approximately 2 inches from the input voltage source. The value for this capacitor is not critical but it should be ratedtohandlethemaximuminputvoltageincludingripplevoltageandshouldfiltertheoutputsothatinputripple voltageisacceptable. 8.2.1.2.3 OutputFilterComponents Two components need to be selected for the output filter, L1 and C3. Since the TPS5410 is an internally compensateddevice,alimitedrangeoffiltercomponenttypesandvaluescanbesupported. 8.2.1.2.3.1 InductorSelection Tocalculatetheminimumvalueoftheoutputinductor,useEquation4: ( ) V x V - V OUT IN(MAX) OUT L = MIN V x K x I x F x 0.8 IN(max) IND OUT SW (4) K is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. IND Three things need to be considered when determining the amount of ripple current in the inductor: the peak to peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current, and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using the TPS5410, K of 0.2 to 0.3 yields good results. Low output ripple voltages is obtained when paired with the IND proper output capacitor, the peak switch current is below the current limit set point, and low load currents can be sourcedbeforediscontinuousoperation. For this design example, use K = 0.3, and the minimum inductor value is 66 μH. The next highest standard IND valueusedinthisdesignis68μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. TheRMSinductorcurrentcanbefoundfromEquation5: (cid:7) 2 2 1 (cid:5) VOUT(cid:1)(cid:5)VIN(MAX)(cid:3)VOUT(cid:6) (cid:6) IL(RMS)(cid:4) IOUT(MAX)(cid:2)12(cid:1) VIN(MAX)(cid:1)LOUT(cid:1)FSW(cid:1)0.8 (5) andthepeakinductorcurrentcanbedeterminedusingEquation6: ( ) V x V - V OUT IN(MAX) OUT I = I + L(PK) OUT(MAX) 1.6 x V x L x F IN(MAX) OUT SW (6) For this design, the RMS inductor current is 1.004 A, and the peak inductor current is 1.147 A. The chosen inductor is a Coilcraft MSS1260-683 type. The nominal inductance is 68μH. It has a saturation current rating of 2.3 A and a RMS current rating of 2.3 A, which meets the requirements. Inductor values for use with the TPS5410areintherangeof10μHto100μH. 8.2.1.2.3.2 CapacitorSelection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the designoftheinternalcompensation,itisrecommendedtokeeptheclosedloopcrossoverfrequencyintherange 3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design example, the intended closed loop crossover frequency is between 2590 Hz and 24 kHz, and below the ESR zero of the output capacitor. Under these conditions, the closed loop crossover frequency is related to the LC cornerfrequencyas: f 2 f (cid:1) LC CO 85V OUT (7) Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com andthedesiredoutputcapacitorvaluefortheoutputfilterto: C (cid:2) 1 OUT 3357(cid:1)L (cid:1)f (cid:1)V OUT CO OUT (8) For a desired crossover of 10 kHz and a 68-μH inductor, the calculated value for the output capacitor is 36.5 μF. ThecapacitortypeshouldbechosensothattheESRzeroisabovetheloopcrossover.ThemaximumESRis: ESR (cid:2) 1 MAX 2(cid:1)(cid:1)C (cid:1)f OUT CO (9) The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter. Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output ripplevoltage: ( ) ESR x V x V - V MAX OUT IN(MAX) OUT V (MAX) = PP N x V x L x F x 0.8 C IN(MAX) OUT SW (10) Where: ΔV isthedesiredpeak-to-peakoutputripple. PP N isthenumberofparalleloutputcapacitors. C F istheswitchingfrequency. SW The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and 54kHz. The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the outputcapacitorisgivenbyEquation11: [ ] ( ) V x V - V 1 OUT IN(MAX) OUT I = x COUT(RMS) Ö12 V x L - F x 0.8 x N IN(MAX) OUT SW C (11) Where: N isthenumberofoutputcapacitorsinparallel. C F istheswitchingfrequency. SW For this design example, a single 47-μF output capacitor is chosen for C3. This value is close to the calculated value of 36.5 μF and yields an actual closed loop cross over frequency of 10.05 kHz. The calculated RMS ripple current is 84.9 mA and the maximum ESR required is 339 mΩ. A capacitor that meets these requirements is a AVXTPSE476M020R0150,ratedat20VwithamaximumESRof150mΩ andaripplecurrentratingof1.369A. This capacitor results in a peak-to-peak output ripple of 44 mV using equation 10. An additional small 0.1-μF ceramicbypasscapacitormayalsoused,butisnotincludedinthisdesign. OthercapacitortypescanbeusedwiththeTPS5410,dependingontheneedsoftheapplication. 8.2.1.2.4 OutputVoltageSetpoint The output voltage of the TPS5410 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin. CalculatetheR2resistorvaluefortheoutputvoltageof12VusingEquation12: R2 (cid:3) R1(cid:1)1.221 V (cid:2) 1.221 OUT (12) ForanyTPS5410design,startwithanR1valueof10kΩ.R2isthen1.13kΩ. 8.2.1.2.5 BootCapacitor Thebootcapacitorshouldbe0.01 μF. 14 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 8.2.1.2.6 CatchDiode The TPS5410 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak-to-peakinductorcurrent.Forwardvoltagedropshouldbesmallforhigherefficiencies.Itisimportanttonote that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of 3A,andaforwardvoltagedropof0.5V. 8.2.1.2.7 AdvancedInformation 8.2.1.2.7.1 OutputVoltageLimitations Due to the internal design of the TPS5410, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% andisgivenby: VOUTMAX(cid:4)0.87(cid:1)(cid:5)(cid:5)VINMIN(cid:3)IOMAX(cid:1)0.230(cid:6)(cid:2)VD(cid:6)(cid:3)(cid:5)IOMAX(cid:1)RL(cid:6)(cid:3)VD (13) Where: V =minimuminputvoltage INMIN I =maximumloadcurrent OMAX V =catchdiodeforwardvoltage. D R =outputinductorseriesresistance. L ThisequationassumesmaximumonresistancefortheinternalhighsideFET. The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximateminimumoutputvoltageforagiveninputvoltageandminimumloadcurrentisgivenby: VOUTMIN(cid:4)0.12(cid:1)(cid:5)(cid:5)VINMAX(cid:3)IOMIN(cid:1)0.110(cid:6)(cid:2)VD(cid:6)(cid:3)(cid:5)IOMIN(cid:1)RL(cid:6)(cid:3)VD (14) Where: V =maximuminputvoltage INMAX I =minimumloadcurrent OMIN V =catchdiodeforwardvoltage. D R =outputinductorseriesresistance. L This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be checkedtoassureproperfunctionality. 8.2.1.2.7.2 InternalCompensationNetwork The design equations given in the example circuit can be used to generate circuits using the TPS5410. These designs are based on certain assumptions, and always select output capacitors within a limited range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the TPS5410. Equation 15 gives the nominal frequency response of the internal voltage-mode type III compensation network: (cid:4)1(cid:2)2(cid:1)(cid:1)sFz1(cid:5)(cid:1)(cid:4)1(cid:2)2(cid:1)(cid:1)sFz2(cid:5) H(s)(cid:3) (cid:4) s (cid:5) (cid:4) s (cid:5) (cid:4) s (cid:5) (cid:4) s (cid:5) 2(cid:1)(cid:1)Fp0 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp1 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp2 (cid:1) 1(cid:2)2(cid:1)(cid:1)Fp3 (15) Where Fp0=2165Hz,Fz1=2170Hz,Fz2=2590Hz Fp1=24kHz,Fp2=54kHz,Fp3=440kHz Fp3representsthenon-idealparasiticseffect. Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com Using this information along with the desired output voltage, feed-forward gain and output filter characteristics, theclosedlooptransferfunctioncanbederived. 8.2.1.2.7.3 ThermalCalculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations.Theyshouldnotbeusedifthedeviceisworkingatlightloadsinthediscontinuousconductionmode. ConductionLoss: Pcon=I 2xRds(on)xV /V OUT OUT IN SwitchingLoss: Psw=V xI x0.01 IN OUT QuiescentCurrentLoss: Pq=V x0.01 IN TotalLoss:Ptot=Pcon+Psw+Pq GivenT =>EstimatedJunctionTemperature:T =T +RthxPtot A J A GivenT =125°C=> EstimatedMaximumAmbientTemperature: T =T –RthxPtot JMAX AMAX JMAX 8.2.1.3 ApplicationCurves The performance graphs in Figure 10 to Figure 17 are applicable to the circuit in Figure 9. T = 25 °C. unless A otherwisespecified. 100 0.03 VI= 14.5 V VI= 20 V VI= 14.5 V 0.02 95 % VI= 20 V n - ncy - % 90 VI= 35 V Regulatio 0.01 VI= 25 V Efficie 85 VI= 30 V oltage 0 VI= 30 V VI= 25 V utput V-0.01 VI= 36 V 80 O -0.02 75 -0.03 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 IO- Output Current -A IO- Output Current -A Figure10.Efficiencyvs.OutputCurrent Figure11.OutputVoltageRegulation%vs.OutputCurrent 0.03 AC Coupled VIN= 100 mV/div (AC Coupled) 20 MHz BWL 0.02 % n - IO= 0.5A o 0.01 ulati IO= 0A Reg 0 V(PH)= 10 V/div e g a olt V-0.01 put IO= 1A ut O -0.02 -0.03 14 16 18 20 22 24 26 28 30 32 34 36 VI- Input Voltage - V t- Time - 1ms / Div Figure12.OutputVoltageRegulation%vs.InputVoltage Figure13.InputVoltageRippleandPHNode,IO=1A 16 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 AC Coupled VIN= 20 mV/div (AC Coupled) A20C M CHozu pBlWedL 20 MHz BWL VO= 100 mV/div V(PH)= 10 V/div IO= 500 mA/div t- Time - 1ms / Div t- Time - 200ms / Div Figure14.OutputVoltageRippleandPHNode,I =1A Figure15.TransientResponse,I Step0.25to0.75A O O V= 10 V/div I ENA= 2 V/div V = 5 V/div O V = 5 V/div O t- Time - 5 ms / Div t- Time - 5 ms / Div Figure16.StartupWaveform,V andV Figure17.StartupWaveform,ENAandV I O O Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com 8.2.2 UsingAllCeramicCapacitors Figure 18 shows an application circuit using all ceramic capacitors for the input and output filters. The design procedure is similar to those given for the design example, except for the selection of the output filter capacitor valuesandthedesignoftheadditionalcompensationcomponentsrequiredtostabilizethecircuit. U1 C2 L1 TPS5410D 7 V-36 V 7 0.01mF 68mH VIN VIN 1 5 V 5 ENA BOOT VOUT ENA 2 NC PH 8 R1 C6 C4.17mF 3 NC VSNS 4 D1 C473mF C474mF 10 kW 2700 pF 6 GND B340A (NoteA) (NoteA) R3 1.78 kW C5 R2 C7 150 pF 3.24 kW 0.056mF A. C3,C4=CeramicTDKC4532X5R1A476MT Figure18. 7-V—36-VInputto5-VOutputApplicationCircuitwithCeramicCapacitors 8.2.2.1 DesignRequirements Forthisdesignexample,useTable1astheinputparameters. 8.2.2.2 DetailedDesignProcedure 8.2.2.2.1 OutputFilterCapacitorSelection When using ceramic output filer capacitors, the recommended LC resonant frequency should be no more than 7 kHz.Sincetheoutputinductorisalreadyselectedat68μH,thislimitstheminimumoutputcapacitorvalueto: 1 C (MIN) ³ O (2p x 7000) 2 x L O (16) Theminimumcapacitorvalueiscalculatedtobe7.6μF.Forthiscircuitalargervalueofcapacitorwillyieldbetter transient response. Two output capacitors are used for C3 and C4 with a value of 47 uF each. It is important to note that the actual capacitance of ceramic capacitors decreases with applied voltage. In this case the effective valueusedforthecalculationsisapproximately70%oftheratedvalueor70 μF. 8.2.2.2.2 ExternalCompensationNetwork When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this circuit the external components are R3, C5, C6 and C7. To determine the value of these components, first calculatetheLCresonantfrequencyoftheoutputfilter: 1 F = LC 2pÖ L x C (EFF) O O (17) Forthisexampletheeffectiveresonantfrequencyiscalculatedas2306Hz The network composed of R1, R2, R3, C5, C6 and C7 has two poles and two zeros that are used to tailor the overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole andzerolocationsaregivenbythefollowingequations: V O Fp1 = 500000 x F LC (18) 18 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 Fz1 = 0.7 x F LC (19) Fz2 = 2.5 x F LC (20) The final pole is located at a frequency too high to be of concern. The values for R1 and R2 are fixed by the 5-V output voltage as calculated using Equation 12. Now the values of R3, C5, C6 and C7 are determined using Equation21,Equation22,andEquation23: 1 C7 = 2p x Fp1 x (R1 || R2) (21) 1 R3 = 2p x Fz1 x C7 (22) 1 C6 = 2p x Fz2 x R1 (23) For this design, using the closest standard values, C7 is 0.056 μF, R3 is 1.76 kΩ and C6 is 2700 pF. C5 is added to improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole frequency, so it should be small in relationship to C6. C5 should be less the 1/10 the value of C6. For this example,150pFworkswell. For additional information on external compensation of the TPS5410 or other wide voltage range devices, see UsingTPS5410/20/30/31WithAluminum/CeramicOutputCapacitors,SLVA237. 8.2.2.3 ApplicationCurves The performance graphs in Figure 19 to Figure 24 are applicable to the circuit in Figure 18. T = 25 °C. unless A otherwisespecified. 100 0.1 VI= 7 V VI= 10 V VI= 15 V 0.08 VI= 10 V 95 % 0.06 VI= 15 V n - 0.04 o y - % 90 gulati 0.02 VI= 7 V Efficienc 85 oltage Re-0.020 80 VI= 30 VVI= 35 V Output V--00..0046 VI= 25 VVI= 30 VVI= 36 V VI= 25 V VI= 20 V -0.08 VI= 20 V 75 -0.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 IO- Output Current -A IO- Output Current -A Figure19.Efficiencyvs.OutputCurrent Figure20.OutputVoltageRegulation%vs.OutputCurrent Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com 0.03 AC Coupled VIN= 100 mV/div (AC Coupled) 20 MHz BWL 0.02 % n - IO= 0.5A ulatio0.01 IO= 0A Reg V(PH)= 10 V/div e 0 g a olt V ut -0.01 utp IO= 1A O -0.02 -0.03 14 16 18 20 22 24 26 28 30 32 34 36 VI- Input Voltage - V t- Time - 1ms / Div Figure21.OutputVoltageRegulation%vs.InputVoltage Figure22.InputVoltageRippleandPHNode,IO=1A AC Coupled VIN= 20 mV/div (AC Coupled) A20C M CHozu pBlWedL 20 MHz BWL VO= 100 mV/div V(PH)= 10 V/div IO= 500 mA/div t- Time - 1ms / Div t- Time - 200ms / Div Figure23.OutputVoltageRippleandPHNode,IO=1A Figure24.TransientResponse,IOStep0.25to0.75A 20 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 9 Power Supply Recommendations The TPS5410 is designed to operate from an input voltage supply range between 5.5 V and 36 V. This input supply should remain within the input voltage supply range. If the input supply is located more than a few inches from the TPS5410 converter bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolyticcapacitorwithavalueof100μFisatypicalchoice. 10 Layout 10.1 Layout Guidelines Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the TPS5410 ground pin. The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7μF ceramic withaX5RorX7Rdielectric. There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground areaunderthedeviceasshowninFigure25. The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor minimizedtopreventexcessivecapacitivecoupling.Thecatchdiodeshouldalsobeplacedclosetothedeviceto minimizetheoutputcurrentlooparea.ConnectthebootcapacitorbetweenthephasenodeandtheBOOTpinas shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placementsandconnectionsshownworkwell,butotherconnectionroutingsmayalsobeeffective. Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the loopformedbythePHpin,Lout,CoutandGNDassmallasispractical. Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the outputcapacitorisnotdesired. IfthegroundingschemeshownisusedviaaconnectiontoadifferentlayertoroutetotheENApin. Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS5410

TPS5410 SLVS675D–AUGUST2006–REVISEDDECEMBER2014 www.ti.com 10.2 Layout Example PH CATCH DIODE BOOT CAPACITOR INPUT INPUT BYPASS BULK BOOT PH CAPACITOR FILTER OUTPUT Vin INDUCTOR NC VIN NC GND RESISTOR VSENSE ENA DIVIDER VOUT OUTPUT FILTER TOPSIDE GROUND AREA CAPACITOR VIA to Ground Plane Route feedback trace under the output Signal VIA filter capacitor or on the other layer. Figure25. DesignLayout 0 5 0 0.220 0. 6 2 0 0. 0.080 All dimensions in inches Figure26. TPS5410LandPattern 22 SubmitDocumentationFeedback Copyright©2006–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS5410

TPS5410 www.ti.com SLVS675D–AUGUST2006–REVISEDDECEMBER2014 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation UsingTPS5410/20/30/31/50WithAluminum/CeramicOutputCapacitors,applicationreport,SLVA237 11.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 11.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2006–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS5410

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS5410D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5410 & no Sb/Br) TPS5410DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5410 & no Sb/Br) TPS5410DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5410 & no Sb/Br) TPS5410DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5410 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS5410 : •Automotive: TPS5410-Q1 •Enhanced Product: TPS5410-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS5410DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS5410DR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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