Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 TPS54062 4.7-V to 60-V Input, 50-mA Synchronous Step-Down Converter With Low IQ 1 Features 3 Description • IntegratedHigh-SideandLow-SideMOSFET TheTPS54062deviceisa60-V,50-mA,synchronous 1 step-down converter with integrated high-side and • PeakCurrentModeControl low-side MOSFETs. Current mode control provides • DiodeEmulationforImprovedLight-Load simple external compensation and flexible component Efficiency selection. The non-switching supply current is 89 µA. • 89µA(typical)OperatingQuiescentCurrent Using the enable pin, shutdown supply current is reducedto1.7µA. • 100-kHzto400-kHzAdjustableSwitching Frequency Undervoltage lockout is internally set at 4.5 V, but can be increased using the accurate enable pin • SynchronizestoExternalClock threshold. The output voltage start-up ramp is • InternalSlow-Start controlledbytheinternalslow-starttime. • 0.8V±2%VoltageReference Adjustable switching frequency range allows • StablewithCeramicOutputCapacitorsorLow- efficiency and external component size to be CostAluminumElectrolytic optimized. Frequency foldback and thermal shutdown • Cycle-by-CycleCurrentLimit,Thermaland protectsthepartduringanoverloadcondition. FrequencyFoldbackProtection DeviceInformation(1) • MSOP-8and3mm×3mmVSON-8Packages PARTNUMBER PACKAGE BODYSIZE(NOM) 2 Applications MSOP(8) TPS54062 3.00mm×3.00mm VSON(8) • Low-PowerStandbyorBiasVoltageSupplies • 4-20mACurrent-LoopPoweredSensors (1) For all available packages, see the orderable addendum at theendofthedatasheet. • IndustrialProcessControl,Metering,andSecurity Systems • HighVoltageLinearRegulatorReplacement SPACER SPACER SimplifiedSchematic Efficiency 100 VIN= 10 V 90 80 70 %) y ( 60 nc 50 e Effici 40 30 20 10 VO= 5 V, fsw = 100 kHz, EN Floating Copyright © 2016,Texas Instruments Incorporated VO= 3.3 V, fsw = 400 kHz 0 0.001 0.01 0.05 Output Current (A) G000 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................16 2 Applications........................................................... 1 8 ApplicationsandImplementation...................... 17 3 Description............................................................. 1 8.1 ApplicationInformation............................................17 4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................17 5 PinConfigurationandFunctions......................... 4 9 PowerSupplyRecommendations...................... 31 6 Specifications......................................................... 5 10 Layout................................................................... 31 6.1 AbsoluteMaximumRatings......................................5 10.1 LayoutGuidelines.................................................31 6.2 ESDRatings..............................................................5 10.2 LayoutExample....................................................31 6.3 RecommendedOperatingConditions.......................5 11 DeviceandDocumentationSupport................. 32 6.4 ThermalInformation..................................................6 11.1 ReceivingNotificationofDocumentationUpdates32 6.5 ElectricalCharacteristics...........................................6 11.2 CommunityResources..........................................32 6.6 TypicalCharacteristics..............................................8 11.3 Trademarks...........................................................32 7 DetailedDescription............................................ 11 11.4 ElectrostaticDischargeCaution............................32 7.1 Overview.................................................................11 11.5 Glossary................................................................32 7.2 FunctionalBlockDiagram.......................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 32 7.3 FeatureDescription.................................................12 4 Revision History ChangesfromRevisionC(December2014)toRevisionD Page • AddedtexttotheLayoutGuidelinessection"Allsensitiveanalogtracesandcomponents..."........................................... 31 ChangesfromRevisionB(August2012)toRevisionC Page • AddedHandlingRatingtable,FeatureDescriptionsection,DeviceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation Supportsection,andMechanical,Packaging,andOrderableInformationsection. .............................................................. 1 ChangesfromRevisionA(October2011)toRevisionB Page • AddedfeaturesItem:DiodeEmulationforImprovedLight-LoadEfficiency........................................................................... 1 • ChangedFeaturesItemFrom:100kHzto400kHzSwitchingFrequencyTo:100kHzto400kHzAdjustable SwitchingFrequency.............................................................................................................................................................. 1 • ChangedtheEfficiencyGraph................................................................................................................................................ 1 • ChangedVSON-8packagegraphictoclarifyThermalPADarea........................................................................................... 4 • ChangedtheENpinMAXvalueFrom:5VTo:8V............................................................................................................... 5 • ChangedtheEnableandAdjustingUndervoltageLockoutsection..................................................................................... 13 • ChangedEquation22throughEquation25......................................................................................................................... 21 2 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 ChangesfromOriginal(May2011)toRevisionA Page • ChangedFeaturesItemFrom:MSOP8andWSON8PackagesTo:MSOP-8and3mmx3mmVSON-8Packages......... 1 • ChangedtheEfficiencyGraph................................................................................................................................................ 1 • AddedtheVSON(DRB-8Pin)Package................................................................................................................................ 4 • ChangedtheRT/CLKpinDescription.................................................................................................................................... 4 • AddedVSON-8PinsvaluestotheThermalInformationtable............................................................................................... 6 • ChangedthePLLlockintimeUnitofMeasureFrom:µATo:µs........................................................................................... 7 • ChangedEquation22........................................................................................................................................................... 21 • ChangedtheEfficiencyvsOutputCurrentGraphs,Figure21andFigure22..................................................................... 22 Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com 5 Pin Configuration and Functions MSOPPACKAGE 8PINS TOPVIEW BOOT 1 8 PH VIN 2 7 GND EN 3 6 COMP RT/CLK 4 5 VSENSE VSONPACKAGE 8PINS BOTTOMVIEW PH 8 1 BOOT Thermal Pad (9) GND 7 2 VIN COMP 6 See appended 3 EN Mechanical Data for VSENSE 5 size and shape 4 RT/CLK PinFunctions PIN I/O DESCRIPTION NAME NUMBER O AbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitoris BOOT 1 belowtheminimumrequiredbytheoutputdevice,theoutputisforcedtoswitchoffuntilthe capacitorisrefreshed. VIN 2 I Inputsupplyvoltage,4.7Vto60V. I Enablepin,internalpull-upcurrentsource.Pullbelow1.14Vtodisable.Floattoenable.Adjust EN 3 theinputundervoltagelockoutwithtworesistors,seetheEnableandAdjustingUndervoltage Lockoutsection. I ResistorTimingandExternalClock.Aninternalamplifierholdsthispinatafixedvoltagewhen usinganexternalresistortogroundtosettheswitchingfrequency.Ifthepinispulledabovethe PLLupperthreshold,amodechangeoccursandthepinbecomesasynchronizationinput.The RT/CLK 4 internalamplifierisdisabledandthepinisahighimpedanceclockinputtotheinternalPLL.If clockingedgesstop,theinternalamplifierisre-enabledandthemodereturnstoaresistor frequencyprogramming. VSENSE 5 I Invertinginputofthetransconductance(gm)erroramplifier. O Erroramplifieroutput,andinputtotheoutputswitchcurrentcomparator.Connectfrequency COMP 6 compensationcomponentstothispin. GND 7 – Ground PH 8 O Thesourceoftheinternalhigh-sidepowerMOSFETanddrainoftheinternallowsideMOSFET – GNDpinmustbeelectricallyconnectedtotheexposedpadontheprintedcircuitboardfor ThermalPad 9 properoperation.VSON-8packageonly. 4 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VIN –0.3 62 V EN –0.3 8 V BOOT-PH –0.3 8 V VSENSE –0.3 6 V Voltage COMP –0.3 3 V PH –0.6 62 V PH,10nsTransient –2 62 V RT/CLK –0.3 6 V VIN InternallyLimited A EN 100 µA BOOT 100 mA Current VSENSE 10 µA COMP 100 µA PH InternallyLimited A RT/CLK 200 µA Operatingjunctiontemperature –40 125 ºC Storagetemperature,T –65 150 °C sg (1) TheAbsoluteMaximumRatingsspecifiedinthissectionwillapplytoallspecificationsofthisdocumentunlessotherwisenoted.These specificationswillbeinterpretedastheconditionswhichmaydamagethedevicewithasingleoccurrence. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Inputcoltage 4.7 60 V Outputcurrent 50 mA SwitchingfrequencysetbyRT/CLKresistor 100 400 kHz Switchingfrequencysynchronizedtoexternalclock 300 400 kHz Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com 6.4 Thermal Information TPS54062 THERMALMETRIC(1) MSOP VSON UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 127.1 40.2 θJA R Junction-to-case(top)thermalresistance 33.4 49.7 θJC(top) R Junction-to-boardthermalresistance 80 15.7 θJB °C/W ψ Junction-to-topcharacterizationparameter 1 0.6 JT ψ Junction-to-boardcharacterizationparameter 79 15.9 JB R Junction-to-case(bottom)thermalresistance N/A 4.1 θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics(1) T =–40°Cto125°C,VIN=4.7to60V(unlessotherwisenoted) J PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage VIN 4.7 60 V Shutdownsupplycurrent EN=0V 1.7 µA IqOperating–Non-switching VSENSE=0.9V,VIN=12V 89 110 µA ENABLEANDUVLO(ENPIN) Rising 1.24 1.4 V Enablethreshold Falling 1 1.14 V Enablethreshold+50mV –4.7 µA Inputcurrent Enablethreshold–50mV –1.2 µA Hysteresis 3.5 µA Enabletostartswitchingtime 450 µs VIN VINstartvoltage VINrising 4.53 V VOLTAGEREFERENCE Voltagereference 1mA<I <MinimumCurrentLimit 0.784 0.8 0.816 V OUT HIGH-SIDEMOSFET Switchresistance BOOT-PH=5.7V 1.5 2.8 Ω LOW-SIDEMOSFET Switchresistance VIN=12V 0.8 1.5 Ω ERRORAMPLIFIER InputCurrent VSENSEpin 20 nA Errorampgm –2µA<I <2µA,V =1V 102 µS (COMP) (COMP) EAgmduringslow-start –2µA<I <2µA,V =1V,VSENSE=0.4V 26 µS (COMP) (COMP) ErrorampDCgain VSENSE=0.8V 1000 V/V Minunitygainbandwidth 0.5 MHz Errorampsource/sink V =1V,100-mVOverdrive ±8 µA (COMP) StartSwitchingThreshold 0.57 V COMPtoIswitchgm 0.65 A/V CURRENTLIMIT High-sidesourcingcurrentlimit VIN=12V,BOOT-PH=5.7V 75 134 mA threshold Zerocrossdetectcurrent –0.7 mA (1) TheElectricalRatingsspecifiedinthissectionwillapplytoallspecificationsinthisdocumentunlessotherwisenoted.These specificationswillbeinterpretedasconditionsthatwillnotdegradethedevice’sparametricorfunctionalspecificationsforthelifeofthe productcontainingit. 6 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Electrical Characteristics(1) (continued) T =–40°Cto125°C,VIN=4.7to60V(unlessotherwisenoted) J PARAMETER CONDITIONS MIN TYP MAX UNIT THERMALSHUTDOWN Thermalshutdown 146 C RT/CLK OperatingfrequencyusingRTmode 100 400 kHz Switchingfrequency R =510kΩ 192 240 288 kHz (RT/CLK) MinimumCLKpulsewidth 40 ns RT/CLKvoltage R =510kΩ 0.53 V (RT/CLK) RT/CLKhighthreshold 1.3 V RT/CLKlowthreshold 0.5 V RT/CLKfallingedgetoPHrising Measureat240kHzwithRTresistorinseries 100 200 ns edgedelay PLLlockintime Measureat240kHz 100 µs PLLfrequencyrange 300 400 kHz PH MinimumOn-time Measuredat50%to50%ofVINI =50mA 120 ns OUT Deadtime VIN=12V,I =50mA,Onetransition 30 ns OUT BOOT BOOT-PHregulationvoltage VIN=12V 5.7 V BOOT-PHUVLO 2.9 V INTERNALSLOW-STARTTIME Slow-starttime f =240kHz,RT=510kΩ,10%to90% 4.1 ms SW Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com 6.6 Typical Characteristics 3.0 1.6 VIN = 4.7V VIN = 4.7V VIN = 12V 1.4 VIN = 12V 2.5 VIN = 60V VIN = 60V 1.2 ) ) 1.0 We ( 2.0 We ( c c an an 0.8 st st esi 1.5 esi 0.6 R R 0.4 1.0 0.2 0.5 0.0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) G001 G002 Figure1.High-SideR vsTemperature Figure2.Low-SideR vsTemperature DS(on) DS(on) 0.808 100.0 VIN = 12V VSENSE Rising 0.806 87.5 VSENSE Falling V) 0.804 75.0 ge Reference ( 000...788900802 of Normal Fsw 356702...505 Volta 0.796 % 25.0 0.794 12.5 0.792 0.0 VIN= 12V −50 −25 0 25 50 75 100 125 0 100 200 300 400 500 600 700 800 900 Temperature (°C) Feedback Voltage (mV) G003 G005 Figure3.VREFVoltagevsTemperature Figure4.FrequencyvsVSENSEVoltage 280 400 VIN = 12V VIN = 12V 270 RT = 510kW 350 z) z) H 260 H 300 k k y ( y ( nc 250 nc 250 e e u u eq 240 eq 200 Fr Fr or 230 or 150 at at cill 220 cill 100 s s O O 210 50 200 0 −50 −25 0 25 50 75 100 125 300 425 550 675 800 925 1050 1175 1300 Temperature (°C) Timing Resistance (kW ) G004 G006 Figure5.FrequencyvsTemperature Figure6.FrequencyvsRT/CLKResistance 8 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Characteristics (continued) 140 1.26 VIN= 12V 120 1.24 S) nductance (µ 1680000 e Voltage (V) 111...122802 VIN = 1VV2EEVNNAA RFaislliinngg ansco 40 Enabl 1.16 Tr 20 1.14 0 1.12 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Temperature (°C) Junction Temperature (°C) G007 G013 Figure7.ErrorAmpTransconductancevsTemperature Figure8.EnablePinVoltagevsTemperature −3.20 4.50 VIN = 12V A) −3.25 4.45 µ Current ( −−33..3350 e (V) 44..3450 UUVVLLOO SSttaorpt esis −3.40 oltag 4.30 ster −3.45 ut V 4.25 Hy np 4.20 ble −3.50 I 4.15 a n E −3.55 4.10 −3.60 4.05 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) G015 G012 Figure9.EnablePinHysteresisCurrent Figure10.InputVoltage(UVLO)vsTemperature vsTemperature 0.0 3.0 −0.2 2.5 −0.4 A) −0.6 µA) nt (µ −0.8 ent ( 2.0 urre −1.0 Curr 1.5 e C −1.2 wn nabl −1.4 utdo 1.0 E h −−11..86 S 0.5 TTTJJJ === 12−254(cid:176)50C(cid:176)(cid:176)CC −2.0 0.0 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 Input Voltage (V) Input Voltage (V) G016 G009 Figure11.EnablePinPullupCurrentvsInputVoltage Figure12.ShutdownSupplyCurrent(VIN)vsInputVoltage Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Characteristics (continued) 98 2.50 96 Non−Switching 2.25 TTJJ == 12255(cid:176)C(cid:176)C 2.00 TJ = −40(cid:176)C A) 94 A) 1.75 µ µ ent ( 92 ent ( 1.50 urr urr 1.25 C C y 90 y 1.00 pl pl p p Su 88 Su 0.75 TJ = 125(cid:176)C 0.50 86 TTJJ == −254(cid:176)0C(cid:176)C 0.25 84 0.00 0 5 10 15 20 25 30 35 40 45 50 55 60 0 1 2 3 4 5 Input Voltage (V) Input Voltage (V) G008 G011 Figure13. SupplyCurrent(VINpin)vsInputVoltage Figure14.SupplyCurrent(VINpin) vsInputVoltage(0VtoVSTART)ENPinLow 140 4.21 TJ = 125(cid:176)C FSW = 240KHz 120 TJ = 25(cid:176)C 4.20 TJ = −40(cid:176)C 4.19 A) 100 urrent (µ 80 me (ms) 44..1178 pply C 60 SS Ti 44..1156 Su 40 4.14 20 4.13 0 4.12 0 1 2 3 4 5 −50 −25 0 25 50 75 100 125 Input Voltage (V) Junction Temperature (°C) G010 G025 Figure15.SupplyCurrent(VINpin)vs Figure16.Slow-StartTimevsTemperature InputVoltage(0VtoV )ENPinOpen START 170 A) 160 m d ( 150 ol h es 140 hr T mit 130 Li nt 120 e urr TJ = −40(cid:176)C C 110 TJ = 25(cid:176)C TJ = 125(cid:176)C 100 0 5 10 15 20 25 30 35 40 45 50 55 60 Input Voltage (V) G018 Figure17.CurrentLimitvs InputVoltage 10 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 7 Detailed Description 7.1 Overview The TPS54062 device is a 60-V, 50-mA, step-down (buck) regulator with an integrated high-side and low-side n- channel MOSFET. To improve performance during line and load transients the device implements a constant- frequency, current mode control, which reduces output capacitance and simplifies external frequency compensationdesign. The switching frequency of 100 kHz to 400 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor-to-ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turnontoafallingedgeofanexternalsystemclock. The TPS54062 has a default start-up voltage of approximately 4.5 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating the device will operate. The operating current is 89 µA when not switching and under no load. When the device is disabled, the supplycurrentis1.7µA. The integrated 1.5-Ω high-side MOSFET and 0.8-Ω low-side MOSFET allows for high efficiency power supply designscapableofdelivering50-mAofcontinuouscurrenttoaload. The TPS54062 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54062 can operate at high duty cycles because of the boot UVLO. The output voltagecanbesteppeddowntoaslowasthe0.8-Vreference. The TPS54062 has an internal output OV protection that disables the high-side MOSFET if the output voltage is 109%ofthenominaloutputvoltage. The TPS54062 reduces external component count by integrating the slow-start time using a reference DAC system. The TPS54062 resets the slow-start times during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during start-up and overcurrentfaultconditionstohelpcontroltheinductorcurrent. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com 7.2 Functional Block Diagram EN VIN Thermal Shutdown UVLO Enable Comparator Shutdown Shutdown Logic Enable Threshold Boot VSENSE OV Charge Boot Minimum UVLO Current Clamp Sense ERROR AMPLIFIER PWM Comparator BOOT Deadtime Control Logic Shutdown REFERENCE DAC Slope Compensation COMP PH Frequency DRV Shift REG Maximum Clamp ZX detect Oscillator with PLL GND RT/CLK Copyright © 2016,Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Fixed-FrequencyPWMControl The TPS54062 uses an adjustable fixed-frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximumlevel. 7.3.2 SlopeCompensationOutputCurrent The TPS54062 adds a compensating ramp to the switch current signal. This slope compensation prevents sub- harmonicoscillations. 12 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Feature Description (continued) 7.3.3 ErrorAmplifier The TPS54062 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the internal slow-start voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 102 µS during normal operation. During the slow-start operation, the transconductance is a fraction of the normal operating gm. The frequency compensation components (capacitor,seriesresistorandcapacitor)areaddedtotheCOMPpin-to-ground. 7.3.4 VoltageReference The voltage reference system produces a precise ±2 voltage reference over temperature by scaling the output of atemperaturestableband-gapcircuit 7.3.5 AdjustingtheOutputVoltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using 1% tolerance or better divider resistors. Start with a 10-kΩ for the R resistor and use the Equation 1 to LS calculateR . HS æV - 0.8Vö OUT R =R ´ ç ÷ HS LS ç 0.8V ÷ è ø (1) 7.3.6 EnableandAdjustingUndervoltageLockout The TPS54062 is enabled when the VIN pin voltage rises above 4.53 V and the EN pin voltage exceeds the EN rising threshold of 1.24 V. The EN pin has an internal pullup current source, I1, of 1.2 µA that provides the defaultenabledconditionwhentheENpinfloats. If an application requires a higher input undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 18 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.24 V, an additional 3.5 µA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.14 V, the 3.5-µA Ihys current is removed. This additional current facilitates adjustable input voltage hysteresis. Use Equation 2 to calculate R for the desired input start and stop voltages . Use Equation 3 to similarly UVLO1 calculateR . UVLO2 In applications designed to start at relatively low input voltages (for example, from 4.7 V to 10 V) and withstand high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8 V during the high input voltage condition. TI recommends using a zener diode to clampthepinvoltagebelowtheabsolutemaximumrating. VIN TPS54062 i1 ihys R 1 UVLO EN Optional V EN R 2 UVLO Copyright © 2016,Texas Instruments Incorporated Figure18. AdjustableUndervoltageLockOut Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Feature Description (continued) æV ö V ç ENAFALLING ÷- V START V STOP R 1= è ENARISING ø UVLO æ V ö I1× ç1- ENAFALLING ÷+I V HYS è ENARISING ø (2) R 1 ´ V R 2= UVLO ENAFALLING UVLO V - V +R 1 ´ (I +I ) STOP ENAFALLING UVLO 1 HYS (3) 7.3.7 ConstantSwitchingFrequencyandTimingResistor(RT/CLKPin) The switching frequency of the TPS54062 is adjustable over a wide range from approximately 100 kHz to 400 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.53 V and must have a resistor-to-ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 4. To reduce the solution size, one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 130 ns and limits the maximum operating input voltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on thedetailsofthemaximumswitchingfrequencyislocatedbelow. 116720 R (kW)= T f (kHz)0.9967 SW (4) 7.3.8 SelectingtheSwitchingFrequency The TPS54062 implements current mode control which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high input voltages the TPS54062 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal start-up and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still have frequency shift protection. During short- circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on time and the output has a low voltage. During the switch on-time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off-time, the inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the ramp up amount.Thefrequencyshifteffectivelyincreasestheofftimeallowingthecurrenttorampdown. æ 1 ö æV +R ´ I +R ´ I ö f (maxskip)= ç ÷ ´ ç OUT LS O DC O÷ SW èt ø è V - I ´ R +I ´ R ø ON IN O HS O LS (5) æ fdivö æV +R ×I +R ´ I ö f (shift)= ç ÷ × ç OUTSC LS CL DC CL ÷ SW è t ø è V - I ´ R +I ´ R ø ON IN CL HS CL LS (6) Where: I =Outputcurrent O I =CurrentLimit CL V =InputVoltage IN V =OutputVoltage OUT V OutputVoltageduringshort OUTSC R =Inductorresistance DC R =High-sideMOSFETresistance HS R =Low-sideMOSFETresistance LS 14 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Feature Description (continued) t =Controllableon-time on fdiv=Frequencydivide(equals1,2,4,or8) 7.3.9 HowtoInterfacetoRT/CLKPin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in Figure 19. The square wave amplitude must transition lower than 0.5 V and higher than 1.3 V on the RT/CLK pin andhaveanon-timegreaterthan40nsandanoff-timegreaterthan40ns.Thesynchronizationfrequencyrange is 300 kHz to 400 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin-to-ground should the synchronization signal turn off. TI recommends using a frequency set resistor connected as shown in Figure 19 through another resistor-to-ground (for example, 50 Ω) for clock signal that are not Hi-Z or 3-state during the off-state. The sum of the resistance should set the switching frequency close to the external CLK frequency. TI recommends to AC couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK threshold, the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator, the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds. When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal start-up andfaultconditions. TPS54062 TPS54062 RT/CLK RT/CLK PLL PLL RT Hi-Z Clock Clock RT Source Source Copyright © 2016,Texas Instruments Incorporated Figure19. SynchronizingtoaSystemClock 7.3.10 OvervoltageTransientProtection The TPS54062 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low-value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actualityleadstothepossibilityofanoutputovershoot. The OVTP feature minimizes the output overshoot, when using a low-value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than theOVTPthreshold,thehigh-sideMOSFETisallowedtoturnonatthenextclockcycle. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Feature Description (continued) 7.3.11 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 146°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 146°C, the device reinitiates the power-up sequence byrestartingtheinternalslow-start. 7.4 Device Functional Modes 7.4.1 OperationNearMinimumInputVoltage The TPS54062 is recommended to operate with input voltages above 4.7 V. The typical VIN UVLO threshold is 4.53 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device will not switch. If EN is floating or externally pulled up to greater up than the typical 1.24-V rising threshold, when V passes the UVLO threshold the TPS54062 will become active. (VIN) Switching is enabled and the slow-start sequence is initiated. The TPS54062 starts linearly ramping up the internal reference DAC from 0 V to the reference voltage over the internal slow-start time period set by the switchingfrequency. 7.4.2 OperationWithEnableControl The enable start threshold voltage is 1.24 V typical. With EN held below the 1.24-V typical rising threshold voltage the TPS54062 is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent current is reduced in this state. If the EN voltage is increased above the rising threshold voltage while V is above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start (VIN) sequence is initiated. The TPS54062 starts linearly ramping up the internal reference DAC from 0 V to the referencevoltageovertheinternalslow-starttimeperiodsetbytheswitchingfrequency.IfENispulledbelowthe 1.14-VtypicalfallingthresholdtheTPS54062willenterthereducedquiescentcurrentstateagain. 16 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54062 is a 60-V, 50-mA step-down regulator with an integrated high-side and low-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 50 mA. Example applications are: Low Power Standby or Bias Voltage Supplies, 4-20 mA Current- Loop Powered Sensors, Industrial Process Control, Metering, and Security Systems or an efficient high voltage linear regulator replacement. Use the following design procedure to select component values for the TPS54062. This procedure illustrates the design of a high frequency switching regulator. These calculations can be done with the aid of the excel spreadsheet tool SLVC364. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive databaseofcomponentswhengeneratingadesign. 8.2 Typical Applications 8.2.1 ContinuousConductionMode(CCM)SwitchingRegulator + Copyright © 2016,Texas Instruments Incorporated Figure20. ApplicationSchematic 8.2.1.1 DesignRequirements This example details the design of a continuous conduction mode (CCM) switching regulator design using ceramic output capacitors. If a low-output current design is needed, see DCM Application. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level.Forthisexample,wewillstartwiththefollowingknownparameters: OutputVoltage 3.3V TransientResponse0to50-mAloadstep ΔV =4% OUT MaximumOutputCurrent 50mA InputVoltage 24Vnom.8Vto60V OutputVoltageRipple 0.5%ofV OUT StartInputVoltage(risingVIN) 7.88V StopInputVoltage(fallingVIN) 6.66V Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) 8.2.1.2 DetailedDesignProcedure 8.2.1.2.1 SelectingtheSwitchingFrequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high-switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switchesatalowerfrequency.Theswitchingfrequencythatcanbeselectedislimitedbytheminimumon-timeof theinternalpowerswitch,theinputvoltageandtheoutputvoltageandthefrequencyshiftlimitation. Equation 5 and Equation 6 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse-skipping or the lack of overcurrent protection during a short circuit. The typical minimum on time, t min, is 130 ns for the on TPS54062.Forthisexample,theoutputvoltageis3.3Vandthemaximuminputvoltageis60V,whichallowsfor a maximum switch frequency up to 400 kHz when including the inductor resistance, on resistance and diode voltage in Equation 5 or Equation 6. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 6 to determine the maximum switching frequency. With a maximum input voltage of 60 V, inductor resistance of 3.7 Ω, high-side switch resistance of 2.3 Ω, low-side switch resistance of 1.1 Ω, a current limitvalueof120mAandashortcircuitoutputvoltageof0.1V. The maximum switching frequency is 400 kHz in both cases and a switching frequency of 400 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 4. The switching frequency is set byresistorR3showninFigure20.R3iscalculatedtobe298kΩ.Astandardvalueof301kΩisused. 8.2.1.2.2 OutputInductorSelection(LO) To calculate the minimum value of the output inductor, use Equation 7. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. Typically, TI recommends using KIND values in the range of 0.2 to 0.4; however, for designsusinglow-ESRoutputcapacitorssuchasceramicsandlowoutputcurrents,avalueashighasKIND=1 may be used. In a wide-input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND = 0.8 and the minimum inductor value is calculated to be 195 µH. For this design, a near standard value was chosen: 220 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 9 andEquation10. For this design, the RMS inductor current is 50 mA and the peak inductor current is 68 mA. The chosen inductor isaCoilcraftLPS4018-224ML.Ithasasaturationcurrentratingof235mAandanRMScurrentratingof200mA. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit ratherthanthepeakinductorcurrent. æV max - V ö V L min ³ç IN OUT ÷ ´ OUT O è Kind ´ IO ø VINmax ´ fSW (7) V ´ (V max - V ) I ³ OUT IN OUT RIPPLE V max ´ L ´ f IN O SW (8) 2 1 æV ´ (V max - V )ö ILrms= IO2 + 12 ´ çç OUVT max I´N L ´ f OUT ÷÷ è IN O SW ø (9) 18 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Applications (continued) I I peak=I + RIPPLE L OUT 2 (10) 8.2.1.2.3 OutputCapacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance necessary to accomplish this. Where ΔIout is the change in output current, ƒ is the regulators switching sw frequencyandΔVoutistheallowablechangeintheoutputvoltage. For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no load)to50mA(fullload).Forthisexample, ΔI =0.05-0=0.05and ΔV =0.04 × 3.3=0.132. OUT OUT Using these numbers gives a minimum capacitance of 1.89 µF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The low-side FET of the regulator emulates a diode so it can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 26. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 13 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, I is the output current under heavy load, O OH I is the output under light-load, VF is the final peak output voltage, and Vi is the initial capacitor voltage. For OL this example, the worst case load step will be from 50 mA to 0A. The output voltage will increase during this load transitionandthestatedmaximuminourspecificationis4%oftheoutputvoltage.ThiswillmakeVF=1.04 ×3.3 = 3.432 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation14yieldsaminimumcapacitanceof0.619 µF. Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where f is the switching frequency, V is the maximum allowable output voltage ripple, and I is the SW RIPPLE RIPPLE inductor ripple current. Equation 13 yields 0.671 µF. Equation 15 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 15 indicates the ESR should be less than0.466Ω. The most stringent criteria for the output capacitor is 1.89 µF of capacitance to keep the output voltage in regulationduringanloadtransient. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which will increase this minimum value. For this example, 10-µF, 10V X5R ceramic capacitor with 0.003 Ω of ESR will be used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRootMeanSquare(RMS)valueofthemaximumripplecurrent. Equation 11 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application,Equation11yields10.23mA. 1 æV ´ (V max - V )ö ICOrms= 12 ´ çç OUVT max I´N L ´ f OUT ÷÷ è IN O SW ø (11) Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) I æ 1 ö C 1 ³ RIPPLE ´ ç ÷ O VRIPPLE è8 ´ fSW ø (12) (I 2 - I 2) OH OL C 2 ³ L ´ O O VF2-Vi2 (13) I 2 C 3 ³ O O DV f SW (14) V R £ RIPPLE C I RIPPLE (15) 8.2.1.2.4 Inputcapacitor The TPS54062 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1µF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a RMS current rating greater than the maximum RMS input current of the TPS54062. The input RMS current can be calculated using Equation 16. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias takenintoaccount.ThecapacitancevalueofacapacitordecreasesastheDCbiasacrossacapacitorincreases. For this example design, a ceramic capacitor with at least a 100-V voltage rating is required to support the maximum input voltage. The input capacitance value determines the input ripple voltage of the regulator. The inputvoltageripplecanbecalculatedusingrearrangingEquation17. Using the design example values, Ioutmax = 50 mA, C = 2.2 µF, ƒ = 400 kHz, yields an input voltage ripple IN SW of14.2mVandaRMSinputripplecurrentof24.6mA. V (V min - V ) IC rms=I ´ OUT ´ IN OUT IN OUT V min V Min IN IN (16) I æ0.25ö C ³ O ´ ç ÷ IN V ripple è f ø IN SW (17) 8.2.1.2.5 BootstrapCapacitorSelection A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or highervoltagerating. 8.2.1.2.6 UnderVoltageLockOutSetPoint The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54062. The UVLO has two thresholds, one for power-up when the input voltage is rising and one for power- down or brownouts when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.88 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.66 V (UVLO stop). The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 174-kΩ resistor between Vin and EN and a 31.6-kΩ resistor between EN and ground are required to produce the 7.88 and 6.66 voltstartandstopvoltages. 8.2.1.2.7 OutputVoltageandFeedbackResistorsSelection For the example design, 10-kΩ was selected for R . Using Equation 1, R is calculated as 31.25 kΩ. The LS HS neareststandard1%resistoris31.6kΩ. 20 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Applications (continued) 8.2.1.2.8 ClosingtheLoop There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensationisignored,theactualcrossoverfrequencywillusuallybelowerthanthecrossoverfrequencyused in the calculations. This method assume the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro™ software for a more accuratedesign. To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 18 and Equation 19. For Cout, use a derated value of 8.9 µF. Use Equation 20 and Equation 21, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 271 Hz and fzerois5960kHz. Equation 20 is the geometric mean of the modulator pole and the ESR zero and Equation 21 is the mean of modulator pole and the switching frequency. Equation 20 yields 40.29 kHz and Equation 21 gives 7.36 kHz. Use afrequencynearthelowervalueofEquation20orEquation21foraninitialcrossoverfrequency. For this example, fco is 7.8 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensatingpole. To determine the compensation resistor, R4, use Equation 22. Assume the power stage transconductance, gmps, is 0.65 A/V. The output voltage, Vo, reference voltage, V , and amplifier transconductance, gmea, are REF 3.3V,0.8Vand102µS,respectively. R4 is calculated to be 27.1 kΩ, use the nearest standard value of 27.4 kΩ. Use Equation 23 to set the compensation zero to the modulator pole frequency. Equation 23 yields 0.0214 µF for compensating capacitor C5, a 0.022 µF is used on the board. Use the larger value of Equation 24 and Equation 25 to calculate the C6 value,tosetthecompensationpole.Equation25yields29pFsotheneareststandardof27pFisused. 1 fpole(Hz)= V O ´ C ´ 2 ´ p I O O (18) 1 fzero(Hz)= R ´ C ´ 2 ´ p C O (19) fco1(Hz)= (fzero ´ fpole)0.5 (20) æ fsw ö0.5 fco2(Hz)= ç ´ fpole÷ è 2 ø (21) 2 ´ p ´ f ´C V R4= CO O ´ O gmps V ´ gmea REF (22) 1 C5= 2 ´ p ´ R4 ´ f POLE (23) R ´ C C6= C O R4 (24) 1 C6= R4 ´ f ´ p SW (25) Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) 8.2.1.3 ApplicationCurves 100 100 90 VOUT = 3.3V 90 VOUT = 3.3V fSW = 400kHz fSW = 400kHz 80 80 70 70 %) %) y ( 60 y ( 60 nc 50 nc 50 e e Effici 3400 VIN = 10V Effici 3400 VIN = 10V VIN = 24V VIN = 24V 20 VIN = 36V 20 VIN = 36V 10 VIN = 48V 10 VIN = 48V VIN = 60V VIN = 60V 0 0 0 0.01 0.02 0.03 0.04 0.05 0.001 0.01 0.1 Output Current (A) Output Current (A) G040 G041 Figure21.EfficiencyvsOutputCurrent Figure22.EfficiencyvsOutputCurrent 60 180 0.10 50 150 0.08 IOUT = 25mA 40 120 %) 30 90 ed ( 0.06 z 0.04 20 60 ali Gain (dB) −−2110000 −−0306300 Phase (°) Voltage Norm −−0000....00004202 −30 −90 ut −40 −120 utp −0.06 Gain O −50 Phase −150 −0.08 −60 −180 −0.10 10 100 1000 10000 100000 1000000 8 12 16 20 24 28 32 36 40 44 48 52 56 60 Frequency (Hz) Input Voltage (V) G031 G035 Figure23.GainvsPhase Figure24.OutputVoltagevsInputVoltage 0.20 VIN = 24V %) 0.15 ed ( 0.10 z mali 0.05 VOUT= 50 mV / div (ac coupled) or e N 0.00 g a olt−0.05 V utput −0.10 IOUT= 20 mA/ div O−0.15 −0.20 0 0.01 0.02 0.03 0.04 0.05 Output Current (A) Time = 1 msec / div G033 Figure26. LoadTransient Figure25.OutputVoltagevsOutputCurrent 22 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Applications (continued) V= 10 V / div IN V = 100 mV / div (ac coupled) OUT EN= 2 V / div V= 10 V / div IN V = 2 V / div OUT Time = 20 msec / div Time = 2 msec / div Figure27.LineTransient Figure28.Start-UpWithENA V= 10 mV / div (ac coupled) IN V= 10 V / div IN PH= 20 V / div EN= 2 V / div Inductor Current= 100 mA/ div V = 2 V / div OUT Time = 2 msec / div Time = 2 µsec / div Figure29.Start-UpWithVIN Figure30.InputRippleinDCM VIN= 10 mV / div (ac coupled) VIN= 10 mV / div (ac coupled) PH= 20 V / div PH= 20 V / div Inductor Current= 100 mA/ div Inductor Current= 100 mA/ div Time = 2 µsec / div Time = 50 µsec / div Figure31.InputRippleinCCM Figure32.InputRippleSkip Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) V = 10 mV / div (ac coupled) V = 10 mV / div (ac coupled) OUT OUT PH= 20 V / div PH= 20 V / div Inductor Current= 100 mA/ div Inductor Current= 100 mA/ div Time = 2 µsec / div Time = 2 µsec / div Figure33.OutputRippleinDCM Figure34.OutputRippleinCCM V = 10 mV / div (ac coupled) OUT PH= 20 V / div Inductor Current= 100 mA/ div Time = 50 µsec / div Figure35.OutputRippleSkip 24 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Applications (continued) 8.2.2 DCMApplication Copyright © 2016,Texas Instruments Incorporated Figure36. DCMApplicationSchematic 8.2.2.1 DesignRequirements This example details the design of a low output current, fixed switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determinedatthesystemlevel.Forthisexample,wewillstartwiththefollowingknownparameters: OutputVoltage 3.3V TransientResponse0to15mAload-step ΔV =4% OUT MaximumOutputCurrent 10mA MinimumOutputCurrent 3mA InputVoltage 24Vnom.10Vto40V OutputVoltageRipple 0.5%ofV OUT SwitchingFrequency 100kHz StartInputVoltage(risingVIN) 9V StopInputVoltage(fallingVIN) 8V 8.2.2.2 DetailedDesignProcedure It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output currents. A fixed frequency power supply will have a predictable output voltage ripple and noise. Using a traditional continuous conduction mode (CCM) design method to calculate the output inductor will yield a large inductance for a low output current supply. Using a CCM inductor will result in a large sized supply or will affect efficiency from the large DC resistance an alternative is to operate in discontinuous conduction mode (DCM). Use the procedure below to calculate the components values for designing a power supply operating in discontinuous conduction mode. The advantage of operating a power supply in DCM for low-output current is the fixed switching frequency, lower output inductance, and lower DC resistance on the inductor. Use the frequency shiftandskipequationstoestimatethemaximumswitchingfrequency. The TPS54062 is designed for applications which require a fixed operating frequency and low-output voltage ripple at low output currents, thus, the TPS54062 does not have a pulse skip mode at light loads. Since the device has a minimum controllable on-time, there is an output current at which the power supply will pulse skip. To ensure that the supply does not pulse skip at output current of the application, the inductor value will be need to be selected greater than a minimum value. The minimum inductance needed to maintain a fixed switching Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) frequency at the minimum load is calculated to be 0.9 mH using Equation 26. Since the equation is ideal and was derived without losses, assume the minimum controllable light-load on-time, tonminll, is 350 ns. To maintain DCM operation the inductor value and output current need to stay below a maximum value. The maximum inductance is calculated to be 1.42 mH using Equation 27. A 744062102 inductor from Wurth Elektronik is selected.IfCCMoperationisnecessary,usethepreviousdesignprocedure. Use Equation 28, to make sure the minimum current limit on the high-side power switch is not exceeded at the maximum output current. The peak current is calculated as 23.9 mA and is lower than the 134 mA current limit. To determine the RMS current for the inductor and output capacitor, it is necessary to calculate the duty cycle. The duty cycle, D1, for a step-down regulator in DCM is calculated in Equation 29. D1 is the portion of the switching cycle the high-side power switch is on, and is calculated to be 0.1153. D2 is the portion of the switchingcyclethelow-sidepowerswitchison,andiscalculatedtobe0.7253. Using the Equation 31 and Equation 32, the RMS current of the inductor and output capacitor are calculated, to be 12.8 mA and 7.6 mA respectively. Select components that ratings exceed the calculated RMS values. Calculate the output capacitance using the Equation 33 to Equation 35 and use the largest value, V is the RIPPLE steady-state voltage ripple and ΔV is voltage change during a transient. A minimum of 1.5-µF capacitance is calculated. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 22-µF, 6.3-V X7R ceramic capacitor with 5-mΩ ESR is used. To have a low output ripple power supply use a low-ESR capacitor. Use Equation 36 to estimate the maximum esr for the output capacitor. Equation 37 and Equation 38 estimate the RMS current and capacitance for the input capacitor. An RMS current of 3.7 mA and capacitance of 0.2 µF is calculated. A 1-µF 100V/X7R ceramic is usedforthisexample. æV max - V ö æV maxö t nmin2 LOmin ³ çè S VO O ÷ø ´ çè S2 ÷ø ´ OIOmin x fSW (26) æV min - V ö æ V ö 1 LOmax £ çè S 2 O ÷ø ´ çèVSmOin÷ø ´ fSW ´ IO (27) æ2 ´ V ´ I max ´ (V max - V )ö0.5 I peak= ç O O S O ÷ L ç V max ´ L ´ f ÷ è S O SW ø (28) 0.5 æ2 ´ V ´ I ´ L ´ f ö D1= ç O O O SW ÷ ç V ´ (V - V ) ÷ è S S O ø (29) æV - V ö D2= ç S O ÷ ´ D1 V è O ø (30) æD1+D2ö0.5 I rms=I peak ´ ç ÷ L L è 3 ø (31) ææD1+D2ö æD1+D2ö2ö0.5 I rms=I peak ´ çç ÷ - ç ÷ ÷ CO L çè 3 ø è 4 ø ÷ è ø (32) I peak æD1+D2ö C 1 £ L ´ ç ÷ O V è8 ´ f ø RIPPLE SW (33) (Io2 - 02) C 2 ³ L ´ O O (VO +DV)2 - VO2 (34) I 1 C 3 ³ O O DV f CO (35) V R £ RIPPLE C I peak L (36) 26 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Applications (continued) ææD1ö æD1ö2ö0.5 I rms=I peak ´ çç ÷ - ç ÷ ÷ CIN L çè 3 ø è 4 ø ÷ è ø (37) I æ0.25ö C ³ O ´ ç ÷ IN VINRIPPLE è fSW ø (38) 8.2.2.2.1 ClosingtheFeedbackLoop The method presented here is easy to calculate and includes the effect of the slope compensation that is internal to the device. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Once the output components are determined, use the equations below to close the feedback loop. A current mode controlled power supply operating in DCM has a transfer function which has an ESR zero and pole as shown in Equation 39. To calculate the current mode power stage gain, first calculate, Kdcm, DCM gain, and Fm, modulator gain, in Equation 40 and Equation 41. Kdcm and Fm are 26.3 and 1.34 respectively. The location of the pole and ESR zero are calculated using Equation 42 and Equation 43 . The pole and zero are 67 Hz and 2 MHz, respectively. Use the lower value of Equation 44 and Equation 45 as a starting point for the crossover frequency. Equation 44 is the geometric mean of the power stage pole and the ESR zero and Equation 45 is the mean of power stage pole and the switching frequency.Thecrossoverfrequencyischosenas2.5kHzfromEquation45. To determine the compensation resistor, R , use Equation 46. Assume the power stage transconductance, COMP gmps, is 0.65 A/V. The output voltage, V , reference voltage, V , and amplifier transconductance, gmea, are O REF 3.3 V, 0.8 V and 102 µS, respectively. R is calculated to be 32.7 kΩ, use the nearest standard value of 32.4 COMP kΩ. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 139 nF for compensating capacitor C , a 330 nF is used on the board. Use the larger value of Equation 48 or COMP Equation 49 to calculate the C , to set the compensation pole. Equation 49 yields 98 pF so the nearest POLE standardof100pFisused. s 1+ 2 ´ p ´ f Gdcm(s) » Fm ´ Kdcm ´ ZERO s 1+ 2 ´ p ´ f POLE (39) 2 V ´ (V - V ) Kdcm = ´ O S O D1 æ ö ç Rdc÷ V ´ ç2+ ÷ - V S V O ç O ÷ ç I ÷ è O ø (40) gmps Fm = æ V - V ö ç S O ÷+0.277 èL ´ f ø O SW (41) æ V ö ç2 - O ÷ 1 V f (Hz)= ´ ç S ÷ POLE V ç V ÷ IO ´ CO ´ 2 ´ p çè1 - VO ÷ø O S (42) 1 f (Hz)= ZERO R ´ C ´ 2 ´ p C O (43) f (Hz)= (f ´ f )0.5 CO1 ZERO POLE (44) f (Hz)= (f ´ f )0.5 CO2 SW POLE (45) Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) R = fCO x VO COMP Kdcm x Fm x f VREF xgmea POLE (46) 1 C = COMP 2 ´ p ´ R ´ Kdcm ´ Fm COMP (47) R ´ C C = C O POLE1 R COMP (48) 1 C = POLE2 R ´ f ´ p COMP SW (49) 8.2.2.3 ApplicationCurves 100 100 90 VOUT =3.3V 90 80 80 70 70 %) %) y ( 60 y ( 60 nc 50 nc 50 e e Effici 40 Effici 40 30 30 20 VIN = 10V 20 VIN = 10V 10 VIN = 24V 10 VIN = 24V VIN = 40V VOUT = 5V VIN = 40 0 0 0 0.0050.010.0150.020.0250.030.0350.040.0450.05 0 0.0050.010.0150.020.0250.030.0350.040.0450.05 Output Current (A) Output Current (A) G020 G021 Figure37.EfficiencyvsOutputCurrent Figure38.EfficiencyvsOutputCurrent 40 180 0.5 VIN = 24V 0.4 VIN = 24V 30 IOUT = 5ma 135 %) VOUT = 3.3V 20 90 ed ( 0.3 z 0.2 ali Gain (dB) −11000 −04545 Phase (°) oltage Norm −00..011 −20 −90 utput V −−00..32 O −30 Gain −135 −0.4 Phase −0.5 −40 −180 0 0.01 0.02 0.03 0.04 0.05 10 100 1000 10000 100000 Output Current (A) Frequency (Hz) G022 G018 Figure40.OutputVoltagevsOutputCurrent Figure39.GainvsPhase 28 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 Typical Applications (continued) 0.25 0.20 IOUT = 7.5mA %) d ( 0.15 e z 0.10 ali m 0.05 or e N 0.00 g a −0.05 olt V −0.10 ut utp −0.15 O −0.20 −0.25 0 10 20 30 40 50 Input Voltage (V) G023 Figure41.OutputVoltagevsInputVoltage Figure42.LoadTransient Figure43.UnloadTransient Figure44.Start-UpWithENA Figure45.Start-UpWithV Figure46.PrebiasStart-UpWithENA IN Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com Typical Applications (continued) Figure47.PrebiasStart-UpWithVIN Figure48.InputandOutputRippleinDCM Figure49.InputandOutputRippleinCCM 30 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

TPS54062 www.ti.com SLVSAV1D–MAY2011–REVISEDJULY2016 9 Power Supply Recommendations The TPS54062 is designed to operate from an input voltage supply range between 4.7 V and 60 V. This input supply should remain within the input voltage supply range. If the input supply is located more than a few inches fromtheTPS54062converterbulkcapacitancemayberequiredinadditiontotheceramicbypasscapacitors. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See Figure 50 for a PCB layout example. Since the PH connection is the switching node and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has been shown to produce goodresultsandismeantasaguideline. All sensitive analog traces and components such as VSENSE, RT/CLK and COMP should be placed away from high-voltage switching nodes such as PH, BOOT and inductor to avoid coupling. The topside resistor of the feedback voltage divider should be connected to the positive node of the VOUT capacitors or after the VOUT capacitors. 10.2 Layout Example VOUT Output Output Capacitor Route Boot Capacitor Inductor Trace on another layer to GND provide wide path for topside ground Input Capacitor Boot Capacitor BOOT PH Compensation Network VIN VIN GND EN COMP Feedback UVLO Resistors Adjust RT/CLK VSENSE Resistor Signal VIA Frequency Set Resistor Figure50. PCBLayoutExample Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54062

TPS54062 SLVSAV1D–MAY2011–REVISEDJULY2016 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks SwitcherPro,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 32 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54062

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54062DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54062 & no Sb/Br) TPS54062DRBR ACTIVE SON DRB 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 062 & no Sb/Br) TPS54062DRBT ACTIVE SON DRB 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 062 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54062DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54062DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54062DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54062DGKR VSSOP DGK 8 2500 370.0 355.0 55.0 TPS54062DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS54062DRBT SON DRB 8 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DRB0008B VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.08 C 0.00 EXPOSED 1.65 0.05 (0.2) TYP THERMAL PAD 4 5 2X 1.95 2.4 0.05 8 1 6X 0.65 0.35 8X 0.25 PIN 1 ID 0.5 0.1 C A B (OPTIONAL) 8X 0.3 0.05 C 4218876/A 12/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRB0008B VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) 8X (0.6) SYMM 1 8 8X (0.3) (2.4) (0.95) 6X (0.65) 4 5 (R0.05) TYP (0.575) ( 0.2) VIA (2.8) TYP LAND PATTERN EXAMPLE SCALE:20X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218876/A 12/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRB0008B VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM 8X (0.6) METAL TYP 1 8X (0.3) 8 (0.63) SYMM 6X (0.65) (1.06) 5 4 (R0.05) TYP (1.47) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218876/A 12/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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