Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 TPS54060 0.5-A, 60-V Step Down DC-DC Converter with Eco-Mode™ 1 Features 3 Description • 3.5-Vto60-VInputVoltageRange The TPS54060 device is a 60-V, 0.5-A, step-down 1 regulator with an integrated high-side MOSFET. • 200-mΩ High-SideMOSFET Current-mode control provides simple external • HighEfficiencyatLightLoadswithaPulse compensation and flexible component selection. A SkippingEco-Mode™ low ripple pulse skip mode reduces the no load, • 116-μAOperatingQuiescentCurrent regulated output supply current to 116 μA. Using the enable pin, shutdown supply current is reduced to 1.3 • 1.3-μAShutdownCurrent μA,whentheenablepinislow. • 100-kHzto2.5-MHzSwitchingFrequency VINundervoltagelockoutisinternallysetat2.5V,but • SynchronizestoExternalClock can be increased using the enable pin. The output • AdjustableSlowStartandSequencing voltage startup ramp is controlled by the slow start • UVandOVPowerGoodOutput pin that can also be configured for sequencing/tracking. An open-drain power good • AdjustableUVLOVoltageandHysteresis signal indicates the output is within 94% to 107% of • 0.8-VInternalVoltageReference itsnominalvoltage. • 10-PinHVSSOPWithPowerPAD™Packageand A wide switching frequency range allows efficiency 3-mm×3-mm10-PinVSONPackage and external component size to be optimized. • Supportedby WEBENCH™andSwitcherPro™ Frequency fold back and thermal shutdown protects SoftwareTool thepartduringanoverloadcondition. The TPS54060 is available in 10-pin thermally 2 Applications enhanced HVSSOP PowerPAD™ package and 10- • 12-V,24-V,and48-VIndustrialandCommercial pin3-mm× 3-mmVSONpackage. LowPowerSystems DeviceInformation(1) • AftermarketAutoAccessories:Video,GPS, Entertainment PARTNUMBER PACKAGE BODYSIZE(NOM) VSON(10) 3.00mm×3.00mm TPS54060 HVSSOP(10) 3.00mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic EfficiencyvsLoadCurrent 100 VIN PWRGD 90 TPS54060 80 EN BOOT 70 %) 60 PH y ( nc 50 SS/TR e ci RT/CLK Effi 40 COMP VSENSE 30 20 VI= 12 V V = 3.3 V GND 10 ƒO = 500 kHz sw 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Load Current (A) C033 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.2 FunctionalBlockDiagram.......................................12 2 Applications........................................................... 1 7.3 FeatureDescription.................................................12 3 Description............................................................. 1 7.4 DeviceFunctionalModes........................................20 4 RevisionHistory..................................................... 2 8 ApplicationandImplementation........................ 22 8.1 ApplicationInformation............................................22 5 PinConfigurationandFunctions......................... 3 8.2 TypicalApplications ...............................................30 6 Specifications......................................................... 4 9 PowerSupplyRecommendations...................... 40 6.1 AbsoluteMaximumRatings .....................................4 10 Layout................................................................... 41 6.2 ESDRatings..............................................................4 6.3 RecommendedOperatingConditions.......................4 10.1 LayoutGuidelines.................................................41 6.4 ThermalInformation..................................................5 10.2 LayoutExample....................................................41 6.5 ElectricalCharacteristics...........................................5 11 DeviceandDocumentationSupport................. 42 6.6 TimingResistorandExternalClock(RT/CLKPin) 11.1 DeviceSupport......................................................42 TimingRequirements.................................................6 11.2 DocumentationSupport........................................42 6.7 TimingResistorandExternalClock(RT/CLKPIN) 11.3 Trademarks...........................................................42 SwitchingCharacteristics...........................................6 11.4 ElectrostaticDischargeCaution............................42 6.8 TypicalCharacteristics..............................................7 11.5 Glossary................................................................42 7 DetailedDescription............................................ 11 12 Mechanical,Packaging,andOrderable 7.1 Overview.................................................................11 Information........................................................... 42 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(January2014)toRevisionC Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 ChangesfromRevisionA(July2010)toRevisionB Page • DeletedSWIFTfromthedatasheetTitleandFeatures......................................................................................................... 1 ChangesfromOriginal(January2009)toRevisionA Page • AddedtheDRCpackageoptiontotheFeaturesandDescription......................................................................................... 1 • AddedtheDRCPinConfiguration.......................................................................................................................................... 3 • ReplacedthePACKAGEDISSIPATIONRATINGStablewiththeThermalInformationTable............................................. 5 • UpdatedFigure63................................................................................................................................................................ 39 • AddedFigure64................................................................................................................................................................... 40 2 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 5 Pin Configuration and Functions DGQPackage 10-PinVSSOP TopView BOOT 1 10 PH VIN 2 9 GND Thermal EN 3 Pad 8 COMP (11) SS/TR 44 7 VSENSE RT/CLK 5 6 PWRGD DRCPackage 10-PinVSON TopView BOOT 1 10 PH VIN 2 9 GND Thermal EN 3 Pad 8 COMP (11) SS/TR 44 7 VSENSE RT/CLK 5 6 PWRGD PinFunctions PIN I/O DESCRIPTION NAME NO. AbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitorisbelowthe BOOT 1 I minimumrequiredbytheintegratedgatedriverforthehigh-sidepowerMOSFET,theoutputisforcedto switchoffuntilthecapacitorisrefreshed. Erroramplifieroutputandinputtotheoutputswitchcurrentcomparator.Connectfrequencycompensation COMP 8 I componentstothispin. Enablepin,internalpull-upcurrentsource.Pullbelow1.2Vtodisable.Floattoenable.Adjusttheinput EN 3 I undervoltagelockoutwithresistordivider. GND 9 – Ground PH 10 O Thesourceoftheinternalhigh-sidepowerMOSFET. Thermalpad 11 – GNDpinmustbeelectricallyconnectedtotheexposedpadontheprintedcircuitboardforproperoperation. Anopendrainoutput,assertslowifoutputvoltageislowduetothermalshutdown,dropout,over-voltageor PWRGD 6 O ENshutdown. ResistorTimingandExternalClock.Aninternalamplifierholdsthispinatafixedvoltagewhenusingan externalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLLupperthreshold, RT/CLK 5 I amodechangeoccursandthepinbecomesasynchronizationinput.Theinternalamplifierisdisabledand thepinisahighimpedanceclockinputtotheinternalPLL.Ifclockingedgesstop,theinternalamplifierisre- enabledandthemodereturnstoaresistorsetfunction. Slow-startandTracking.Anexternalcapacitorconnectedtothispinsetstheoutputrisetime.Sincethe SS/TR 4 I voltageonthispinoverridestheinternalreference,itcanbeusedfortrackingandsequencing. VIN 2 I Inputsupplyvoltage,3.5Vto60V. VSENSE 7 I Invertingnodeofthetransconductance(gm)erroramplifier. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) Overoperatingtemperaturerange(unlessotherwisenoted). MIN MAX UNIT VIN –0.3 65 EN –0.3 5 VSENSE –0.3 3 COMP –0.3 3 PWRGD –0.3 6 Voltage V SS/TR –0.3 3 RT/CLK –0.3 3.6 BOOT-PH –0.3 8 PH –0.6 65 PH,10-nsTransient –2 65 Voltage ThermalPADtoGND ±200 mV Difference EN 100 μA BOOT 100 mA Sourcecurrent VSENSE 10 μA PH CurrentLimit A RT/CLK 100 μA VIN CurrentLimit A COMP 100 μA Sinkcurrent PWRGD 10 mA SS/TR 200 μA Operatingjunctiontemperature –40 150 °C Storagetemperature –65 150 °C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Supplyinputvoltage,V 3.5 60 V VIN Outputvoltage,V 0.8 57 V O Outputcurrent,I 0 0.5 A O Operatingjunctiontemperature,T -40 150 °C J 4 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 6.4 Thermal Information TPS54060 THERMALMETRIC(1)(2)(2) DGQ(VSSOP) DRC(VSON) UNIT 10PINS 10PINS R Junction-to-ambientthermalresistance(standardboard) 62.5 40 °C/W θJA R Junction-to-ambientthermalresistance(customboard) (3) 57 56.5 °C/W θJA ψ Junction-to-topcharacterizationparameter 1.7 0.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 20.1 7.5 °C/W JB R Junction-to-case(top)thermalresistance 83 65 °C/W θJC(top) R Junction-to-case(bottom)thermalresistance 21 7.8 °C/W θJC(bot) R Junction-to-boardthermalresistance 28 8 °C/W θJB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. (2) PowerratingataspecificambienttemperatureTAshouldbedeterminedwithajunctiontemperatureof150°C.Thisisthepointwhere distortionstartstosubstantiallyincrease.Seepowerdissipationestimateinapplicationsectionofthisdatasheetformoreinformation. (3) Testboardsconditions: (a) 3inchesx3inches,2layers,thickness:0.062inch (b) 2oz.coppertraceslocatedonthetopofthePCB (c)2oz.coppergroundplane,bottomlayer (d)6thermalvias(13mil)locatedunderthedevicepackage 6.5 Electrical Characteristics T =–40°Cto150°C,VIN=3.5to60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage 3.5 60 V Internalundervoltagelockout Novoltagehysteresis,risingandfalling 2.5 V threshold Shutdownsupplycurrent EN=0V,25°C,3.5V≤VIN≤60V 1.3 4 Operating:nonswitchingsupply μA VSENSE=0.83V,VIN=12V,25°C 116 136 current ENABLEANDUVLO(ENPIN) Enablethresholdvoltage Novoltagehysteresis,risingandfalling,25°C 0.9 1.25 1.55 V Enablethreshold+50mV –3.8 Inputcurrent μA Enablethreshold–50mV –0.9 Hysteresiscurrent –2.9 μA VOLTAGEREFERENCE T =25°C 0.792 0.8 0.808 J Voltagereference V 0.784 0.8 0.816 HIGH-SIDEMOSFET VIN=3.5V,BOOT-PH=3V 300 On-resistance mΩ VIN=12V,BOOT-PH=6V 200 410 ERRORAMPLIFIER Inputcurrent 50 nA Erroramplifiertransconductance(g ) –2μA<I <2μA,V =1V 97 μS M COMP COMP Erroramplifiertransconductance(gM) –2μA<ICOMP<2μA,VCOMP=1V, 26 μS duringslowstart V =0.4V VSENSE Erroramplifierdcgain V =0.8V 10,000 V/V VSENSE Erroramplifierbandwidth 2700 kHz Erroramplifiersource/sink V =1V,100mVoverdrive ±7 μA (COMP) COMPtoswitchcurrent 1.9 A/V transconductance CURRENTLIMIT Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Electrical Characteristics (continued) T =–40°Cto150°C,VIN=3.5to60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Currentlimitthreshold VIN=12V,T =25°C 0.6 0.94 A J THERMALSHUTDOWN Thermalshutdown 182 °C SLOWSTARTANDTRACKING(SS/TR) Chargecurrent V =0.4V 2 μA SS/TR SS/TR-to-VSENSEmatching V =0.4V 45 mV SS/TR SS/TR-to-referencecrossover 98%nominal 1.0 V SS/TRdischargecurrent(overload) VSENSE=0V,V(SS/TR)=0.4V 112 μA SS/TRdischargevoltage VSENSE=0V 54 mV POWERGOOD(PWRGDPIN) VSENSEfalling 92% VSENSErising 94% V VSENSEthreshold VSENSE VSENSErising 109% VSENSEfalling 107% Hysteresis VSENSEfalling 2% Outputhighleakage VSENSE=VREF,V(PWRGD)=5.5V,25°C 10 nA Onresistance I(PWRGD)=3mA,VSENSE<0.79V 50 Ω MinimumVINfordefinedoutput V(PWRGD)<0.5V,II(PWRGD)=100μA 0.95 1.5 V 6.6 Timing Resistor and External Clock (RT/CLK Pin) Timing Requirements MIN TYP MAX UNIT MinimumCLKinputpulsewidth 40 ns RT/CLKfallingedgetoPHrisingedgedelay 60 ns 6.7 Timing Resistor and External Clock (RT/CLK PIN) Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f Switchingfrequency R =200kΩ 450 581 720 kHz SW T SwitchingFrequencyRangeusing 100 2500 kHz RTmode Switchingfrequencyrangeusing 300 2200 kHz CLKmode PLLlockintime Measuredat500kHz 100 μs 6 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 6.8 Typical Characteristics W)500 0.816 m e ( c n a sist375 BOOT-PH = 3 V V) 0.808 Re e ( ate enc n-St250 efer 0.800 O BOOT-PH = 6 V R e e c g our olta n-S125 V 0.792 ai Dr c ati St 0 0.784 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C001 C002 Figure1.ONResistancevsJunctionTemperature Figure2.VoltageReferencevsJunctionTemperature 1.1 610 600 1 z) H nt (A) ncy (k590 e e urr 0.9 qu580 C e h Fr Switc ching 570 0.8 wit S 560 0.7 550 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C003 C004 Figure3.SwitchCurrentLimitvsJunctionTemperature Figure4.SwitchingFrequencyvsJunctionTemperature 2500 500 2000 400 Hz) Hz) Frequency (k1500 Frequency (k 300 witching 1000 witching 200 S 500 S 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) RT/CLK Resistance (kW) C005 C006 Figure5.SwitchingFrequencyvsRT/CLKResistanceHigh Figure6.SwitchingFrequencyvsRT/CLKResistanceLow FrequencyRange FrequencyRange Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Typical Characteristics (continued) 40 150 130 30 V) V)110 A/ A/ μ μ m ( m ( g g 90 20 70 10 50 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C007 C008 Figure7.EATransconductanceDuringSlowStartvs Figure8.EATransconductancevsJunctionTemperature JunctionTemperature 1.40 –3.25 –3.5 V) 1.30 d ( ol A) Thresh μI((EN)–3.75 N E 1.20 –4 1.10 –4.25 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C009 C010 Figure9.ENPinVoltagevsJunctionTemperature Figure10.ENPinCurrentvsJunctionTemperature –0.8 –1 –0.85 –1.5 A) A) μI((EN) –0.9 μI((SS/TR) –2 –0.95 –2.5 –1 –3 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C011 C012 Figure11.ENPinCurrentvsJunctionTemperature Figure12.SS/TRChargeCurrentvsJunctionTemperature 8 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Typical Characteristics (continued) 120 100 80 115 A) nal fsw 60 μI(I(SS/TR)110 of Nomi 40 % 105 20 100 0 –50 –25 0 25 50 75 100 125 150 0 0.2 0.4 0.6 0.8 JunctionTemperature (°C) V (V) C013 SENSE C014 Figure13.SS/TRDischargeCurrentvsJunction Figure14.SwitchingFrequencyvsVSENSE Temperature 2 2 1.5 1.5 A) A) μ μ ( 1 ( 1 I(VIN) I(VIN) 0.5 0.5 0 0 –50 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 JunctionTemperature (°C) Input Voltage (V) C015 C016 Figure15.ShutdownSupplyCurrentvsJunction Figure16.ShutdownSupplyCurrentvsInputVoltage(V ) in Temperature 140 140 130 130 120 120 A) A) μ μ ( ( I(VIN)110 I(VIN)110 100 100 90 90 –50 –25 0 25 50 75 100 125 150 0 20 40 60 JunctionTemperature (°C) Input Voltage (V) C017 C018 Figure17.VINSupplyCurrentvsJunctionTemperature Figure18.VINSupplyCurrentvsInputVoltage Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Typical Characteristics (continued) 100 115 VSENSE Rising 80 V)ref110 % of 105 VSENSE Falling W) 60 d ( ON ( shol100 RDS 40 DThre 95 VSENSE Rising G R W 20 P 90 VSENSE Falling 0 85 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C019 C020 Figure19.PWRGDONResistancevsJunctionTemperature Figure20.PWRGDThresholdvsJunctionTemperature 2.5 3 2.25 2.75 V) ( V) VI(BOOT-PH) 2 V(I(VIN) 2.50 1.75 2.25 1.5 2 –50 –25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C021 C022 Figure21.BOOT-PHUVLOvsJunctionTemperature Figure22.InputVoltage(UVLO)vsJunctionTemperature 500 60 55 400 50 V)300 V) m m et ( et (45 s s Off200 Off 40 100 35 0 30 0 100 200 300 400 500 600 700 800 –50 –25 0 25 50 75 100 125 150 VSENSE (mV) JunctionTemperature (°C) C023 C024 Figure23.SS/TRTOVSENSEOffsetvsVSENSE Figure24.SS/TRTOVSENSEOffsetvsTemperature 10 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 7 Detailed Description 7.1 Overview The TPS54060 device is a 60-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switchturnontoafallingedgeofanexternalsystemclock. The TPS54060 has a default VIN start up voltage of approximately 2.5V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will operate. The operating current is 116μA when not switching and under no load. When the device is disabled,thesupplycurrentis1.3μA. The integrated 200mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering 0.5 amperes of continuous current to a load. The TPS54060 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54060 can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V reference. The TPS54060 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pintotransitionhighwhenapull-upresistorisused. The TPS54060 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from turningonuntiltheoutputvoltageislowerthan107%. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor dividercanbecoupledtothepinforcriticalpowersupplysequencingrequirements.TheSS/TRpinisdischarged before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault, UVLOfaultoradisabledcondition. The TPS54060, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startupandovercurrentfaultconditionstohelpcontroltheinductorcurrent. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 7.2 Functional Block Diagram PWRGD EN VIN 6 3 2 Shutdown Thermal Shutdown UVLO Enable UV Logic Comparator Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Minimum Boot Reference Clamp UVLO Current Pulse Sense ERROR Skip AMPLIFIER PWM VSENSE 7 Comparator 1 BOOT SS/TR 4 Logic And PWM Latch Shutdown Slope Compensation COMP 8 10PH 11 POWERPAD Frequency Shift Overload Maximum Recovery Clamp Oscillator TPS54060Block Diagram 9 GND with PLL 5 RT/CLK 7.3 Feature Description 7.3.1 FixedFrequencyPWMControl The TPS54060 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximumlevel.TheEco-Mode™isimplementedwithaminimumclampontheCOMPpin. 7.3.2 SlopeCompensationOutputCurrent The TPS54060 adds a compensating ramp to the switch current signal. This slope compensation prevents sub- harmonicoscillations.Theavailablepeakinductorcurrentremainsconstantoverthefulldutycyclerange. 7.3.3 PulseSkipEco-mode The TPS54060 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing switching and gate drive losses. The TPS54060 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or 500mV. 12 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Feature Description (continued) When in Eco-mode, the COMP pin voltage is clamped at 500mV and the high side MOSFET is inhibited. Further decreasesinloadcurrentorinoutputvoltagecannotdrivetheCOMPpinbelowthisclampvoltagelevel. Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates forthefallingoutputvoltage,theCOMPpinvoltagebeginstorise.Atthistime,thehighsideMOSFETisenabled andaswitchingpulseinitiatesonthenextswitchingcycle.ThepeakcurrentissetbytheCOMPpinvoltage.The output voltage re-charges the regulated value (see Figure 25), then the peak switch current starts to decrease, andeventuallyfallsbelowtheEcomodethresholdatwhichtimethedeviceagainentersEcomode. For Eco mode operation, the TPS54060 senses peak current, not average or load current, so the load current where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in Figure 50 enters Eco mode at about 20 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 116μA input quiescent current. The average input current will be slightly higher than the non-switching input quiescent current because some switching is required to keep the output voltage regulated. The average input current will vary between applications. The internal PLL remains operating when in sleep mode. When operating at light load currents in thepulseskipmode,theswitchingtransitionsoccursynchronouslywiththeexternalclocksignal. VOUT (ac) I L PH Figure25. PulseSkipModeOperation 7.3.4 LowDropoutOperationandBootstrapVoltage(BOOT) The TPS54060 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the low side diode conducts. The value of this ceramic capacitor should be 0.1μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended becauseofthestablecharacteristicsovertemperatureandvoltage. To improve drop out, the TPS54060 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1V. When the voltage from BOOT to PH drops below 2.1V, the high side MOSFET is turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the BOOT capacitor. Since the supply current sourced from the BOOT capacitor is low, the high side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switchingregulatorishigh. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Feature Description (continued) The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low side diode and printed circuit board resistance. During operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the high side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH voltagefallsbelow2.1V. Attention must be taken in maximum duty cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the high sideMOSFETisturnedoff,buttheremaynotbeenoughinductorcurrenttopullthePHpindowntorechargethe BOOT capacitor. The high side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1V. The output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the BOOTUVLOtriggerconditionattheminimumloadoftheapplicationusingtheadjustableVINUVLOfeaturewith resistorsontheENpin. The start and stop voltages for typical 3.3V and 5V output applications are shown in Figure 26 and Figure 27. The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching. During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot capacitorbeinglongerthanthetypicalhighsideofftimewhenswitchingoccurseverycycle. 4 5.6 3.8 5.4 V) V) ge ( 3.6 Start ge ( 5.2 Start a a olt olt V V ut 3.4 Stop ut 5 p p n n I I Stop 3.2 4.8 3 4.6 0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20 Output Current (A) Output Current (A) C025 C026 Figure26.3.3-VStart/StopVoltage Figure27.5.0-VStart/StopVoltage 7.3.5 ErrorAmplifier The TPS54060 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance (gm) of the error amplifier is 97μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8VandthedeviceisregulatingusingtheSS/TRvoltage,thegmis25μA/V. The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin toground. 7.3.6 VoltageReference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output ofatemperaturestablebandgapcircuit. 14 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Feature Description (continued) 7.3.7 SlowStart/TrackingPin(SS/TR) The TPS54060 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54060 has an internal pull-up current source of 2μA that charges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 1. The voltage reference (V ) is 0.8 V and the slow start current (I ) is 2μA. The slow start capacitor should REF SS remainlowerthan0.47μFandgreaterthan0.47nF. Tss(ms) ´ Iss(mA) Css(nF)= Vref(V) ´ 0.8 (1) At power up, the TPS54060 will not start switching until the slow start pin is discharged to less than 40 mV to ensureaproperpowerup,seeFigure28. Also, during normal operation, the TPS54060 will stop switching and the SS/TR must be discharged to 40 mV, whentheVINvoltageisbelowtheVINUVLO,ENpinpulledbelow1.25V,orathermalshutdowneventoccurs. The VSENSE voltage will follow the SS/TR pin voltage with a 45mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure23).TheSS/TRvoltagewillramplinearlyuntilclampedat1.7V. EN SS/TR V SENSE VOUT Figure28. OperationofSS/TRPinwhenStarting 7.3.8 OverloadRecoveryCircuit The TPS54060 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of 100μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed,theoutputwillslowstartfromthefaultvoltagetonominaloutputvoltage. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Feature Description (continued) 7.3.9 ConstantSwitchingFrequencyandTimingResistor(RT/CLKPin) The switching frequency of the TPS54060 is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 2 or the curves in Figure 29 or Figure 30. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltageandminimumcontrollableontimeshouldbeconsidered. Theminimumcontrollableontimeistypically130nsandlimitsthemaximumoperatinginputvoltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of themaximumswitchingfrequencyislocatedbelow. 206033 RT (kW) = ¦sw (kHz)1.0888 (2) 2500 500 2000 400 Hz) Hz) Frequency (k1500 Frequency (k 300 witching 1000 witching 200 S 500 S 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) RT/CLK Resistance (kW) C005 C006 Figure29.SwitchingFrequencyvsRT/CLKResistance Figure30.SwitchingFrequencyvsRT/CLKResistance HighFrequencyRange LowFrequencyRange 7.3.10 OvercurrentProtectionandFrequencyShift The TPS54060 implements current mode control which uses the COMP pin voltage to turn off the high side MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high input voltages the TPS54060 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSEpin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum inputvoltagelimitinwhichthedeviceoperatesandstillhavefrequencyshiftprotection. Duringshort-circuitevents(particularlywithhighinputvoltageapplications),thecontrolloophasafiniteminimum controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp upamount.Thefrequencyshifteffectivelyincreasestheofftimeallowingthecurrenttorampdown. 16 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Feature Description (continued) 7.3.11 PowerGood(PWRGDPin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will achievefullcurrentsinkingcapabilityasVINinputvoltageapproaches3V. ThePWRGDpinispulledlowwhentheVSENSEislowerthan92%orgreaterthan109%ofthenominalinternal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulledlow. 7.3.12 OvervoltageTransientProtection The TPS54060 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high side MOSFET is allowed toturnonatthenextclockcycle. 7.3.13 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence bydischargingtheSS/TRpin. 7.3.14 SmallSignalModelforLoopResponse Figure31showsanequivalentmodelfortheTPS54060controlloopwhichcanbemodeledinacircuitsimulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 97 μA/V. The error amplifier can be modeled using an ideal voltage controlled current EA source. The resistor R and capacitor C model the open loop gain and frequency response of the amplifier. The o o 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing R with a L current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent modelisonlyvalidforcontinuousconductionmodedesigns. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Feature Description (continued) PH V Power Stage O gm 1.9A/V ps a b R1 RESR COMP RL c VSENSE C 0.8 V OUT CO RO R3 gm ea C2 97mA/V R2 C1 Figure31. SmallSignalModelforLoopResponse 7.3.15 SimpleSmallSignalModelforPeakCurrentModeControl Figure 32 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54060 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer functionisshowninEquation3andconsistsofadcgain,onedominantpole,andoneESRzero.Thequotientof the change in switch current and the change in COMP pin voltage (node c in Figure 31) is the power stage transconductance. The gm for the TPS54060 is 1.9A/V. The low-frequency gain of the power stage frequency PS responseistheproductofthetransconductanceandtheloadresistanceasshowninEquation4. Astheloadcurrentincreasesanddecreases,thelow-frequencygaindecreasesandincreases,respectively.This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 5). The combined effect is highlighted by the dashed line in the right half of Figure 32. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases from the ESRzeroatthelowerfrequencies(seeEquation6). VO VC Adc RESR fp RL gmps COUT fz Figure32. SimpleSmallSignalModelandFrequencyResponseforPeakCurrentModeControl 18 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Feature Description (continued) æ s ö ç1+ ÷ VOUT = Adc´è 2p´fZ ø V æ s ö C ç1+ ÷ è 2p´fP ø (3) Adc=gm ´ R ps L (4) 1 f = P C ´R ´2p OUT L (5) 1 f = Z C ´R ´2p OUT ESR (6) 7.3.16 SmallSignalModelforFrequencyCompensation The TPS54060 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 33. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors.. Equation 7 and Equation 8 show how to relate the frequency response of the amplifier to the small signal model in Figure 33. The open-loop gain and bandwidth are modeled using the R O and C shown in Figure 33. See the application section for a design example using a Type 2A network with a O lowESRoutputcapacitor. Equation 7 through Equation 16 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application sectionoruseswitchedinformation. V O R1 VSENSE gm Type 2A Type 2B Type 1 ea COMP Vref R3 C2 R3 R2 RO CO C2 C1 C1 Figure33. TypesofFrequencyCompensation Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Feature Description (continued) Aol P1 A0 Z1 P2 A1 BW Figure34. FrequencyResponseoftheType2AandType2BFrequencyCompensation Aol(V/V) Ro= gm ea (7) gm C = ea O 2p ´ BW (Hz) (8) æ s ö ç1+ ÷ è 2p´fZ1ø EA = A0´ æ s ö æ s ö ç1+ ÷´ç1+ ÷ è 2p´fP1ø è 2p´fP2 ø (9) R2 A0=gm ´ Ro ´ ea R1+R2 (10) R2 A1=gm ´ Ro||R3 ´ ea R1+R2 (11) 1 P1= 2p´Ro´C1 (12) 1 Z1= 2p´R3´C1 (13) 1 P2= type2a 2p ´ R3||R ´ (C2+C ) O O (14) 1 P2= type2b 2p ´ R3||R ´ C O O (15) 1 P2 = type 1 2p ´ R ´ (C2 + C ) O O (16) 7.4 Device Functional Modes The TPS54060 is designed to operate with input voltages above 3.5 V. When the VIN voltage is above the 2.5 V typical UVLO threshold and the EN voltage is above the 1.25 V typical threshold the device is active. If the VIN voltage falls below the typical 2.5-V UVLO threshold the device stops switching. If the EN voltage falls below the 1.25-V threshold the device stops switching and enters a shutdown mode with low supply current of 1.3 µA typical. 20 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Device Functional Modes (continued) The TPS54060 will operate in CCM when the output current is enough to keep the inductor current above 0 A at the end of each switching period. As a non-synchronous converter it will enter DCM at low output currents when the inductor current falls to 0 A before the end of a switching period. At very low output current the COMP voltage will drop to the pulse skipping threshold and the device operates in a pulse-skipping Eco-mode. In this mode the high-side MOSFET does not switch every switching period. This operating mode reduces power loss while keeping the output voltage regulated. For more information on Eco-mode see the Pulse Skip Eco-mode section. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54060 device is a 60-V, 0.5-A, step-down regulator with an integrated high-side MOSFET. This device typically converts a higher dc voltage to a lower dc voltage with a maximum available output current of 0.5 A. Example applications are: 12-V, 24-V, and 48-V industrial, automotive and communication power systems. Use the following design procedure to select component values for the TPS54060 device. The Excel® spreadsheet (SLVC432) located on the product page can help on all calculations. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensivedatabaseofcomponentswhengeneratingadesign. 8.1.1 AdjustingtheOutputVoltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 17 to calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable æVout - 0.8Vö R1=R2 ´ ç ÷ è 0.8V ø (17) 8.1.2 EnableandAdjustingUndervoltageLockout The TPS54060 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 35 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of 0.9μA that provides the default condition of the TPS54060 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25V, an additional 2.9μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 18 to set the external hysteresis for the input voltage. Use Equation 19 to set theinputstartvoltage. TPS54060 VIN Ihys I1 R1 0.9mA 2.9mA + R2 EN 1.25 V - Figure35. AdjustableUndervoltageLockout(UVLO) V -V R1= START STOP I HYS (18) 22 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Application Information (continued) V R2= ENA V -V START ENA +I R1 1 (19) Another technique to add input voltage hysteresis is shown in Figure 36. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sourcesadditionalhysteresiscurrentintotheENpin. TPS54060 VIN Ihys R1 I1 2.9mA 0.9mA + R2 EN 1.25 V - VOUT R3 Figure36. AddingAdditionalHysteresis V -V R1= START STOP V I + OUT HYS R3 (20) V R2= ENA V -V V START ENA +I - ENA R1 1 R3 (21) 8.1.3 Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 37 using two TPS54060 devices. The power good is coupled to the EN pin on the TPS54060 which will enable the second power supply once the primary supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply will provide a 1msstartupdelay.Figure38showstheresultsofFigure37. TPS54060 PWRGD EN EN SS/TR SS/TR PWRGD Figure37. SchematicforSequentialStart-UpSequence Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Application Information (continued) EN1 PWRGD1 VOUT1 VOUT2 Figure38. SequentialStartupUsingENandPWRGD TTPPSS5544106600 3 EN EN1, EN2 4 SS/TR 6 PWRGD VOUT1 TTPPSS5544106600 3 EN VOUT2 4 SS/TR 6 PWRGD Figure39.SchematicforRatiometricStart-UpSequence Figure40.RatiometricStart-UpUsingCoupledSS/TRPins Figure 39 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pullupcurrentsourcemustbedoubledinEquation1.Figure40showstheresultsofFigure39. 24 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Application Information (continued) TPS54060 EN VOUT1 SS/TR PWRGD TPS54060 EN VOUT2 R1 SS/TR R2 PWRGD R3 R4 Figure41. SchematicforRatiometricandSimultaneousStart-UpSequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 41 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 22 and Equation 23, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 24 is the voltage difference between Vout1 andVout2atthe95%ofnominaloutputregulation. The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and trackingresistors,theVssoffsetandIssareincludedasvariablesintheequations. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 22 through Equation 24 for deltaV. Equation 24 will result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Since the SS/TR pin must be pulled below 40mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 22 is greater than the value calculated in Equation 25 to ensure the device canrecoverfromafault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3V for a complete handoff to the internal voltage reference as shown in Figure23. Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Application Information (continued) Vout2+deltaV Vssoffset R1= ´ VREF Iss (22) VREF ´ R1 R2= Vout2+deltaV - VREF (23) deltaV=Vout1 - Vout2 (24) R1>2800 ´ Vout1 - 180 ´ deltaV (25) EN EN VOUT1 VOUT1 VOUT2 VOUT2 Figure42.RatiometricStartupWithTrackingResistors Figure43.RatiometricStartupWithTrackingResistors EN VOUT1 VOUT2 Figure44.SimultaneousStartupWithTrackingResistor 26 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Application Information (continued) 8.1.4 SelectingtheSwitchingFrequency The switching frequency that is selected should be the lower value of the two equations, Equation 26 and Equation27.Equation26isthemaximumswitchingfrequencylimitationsetbytheminimumcontrollableontime. Settingtheswitchingfrequencyabovethisvaluewillcausetheregulatortoskipswitchingpulses. Equation 27 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the fsw(maxshift) frequency. In Equation 27, to calculate the maximum switching frequency one must take into accountthattheoutputvoltagedecreasesfromthenominalvoltageto0volts,thefdivintegerincreasesfrom1to 8correspondingtothefrequencyshift. In Figure 45, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.130Ω, FET on resistance of 0.2Ω and the diode voltage drop is 0.5V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switchingfrequency. fSW(maxskip)=æçt1 ö÷´æçç(I(LV´ -RIdc´+VROhUsT++VVdd))ö÷÷ è ONø è IN L ø (26) æ ö f = fdiv´ç(IL´Rdc+VOUTSC +Vd)÷ SW(shift) tON çè (VIN-IL x Rhs+Vd) ÷ø (27) I inductorcurrent L Rdc inductorresistance V maximuminputvoltage IN V outputvoltage OUT V outputvoltageduringshort OUTSC Vd diodevoltagedrop R switchonresistance DS(on) t controllableontime ON ƒ frequencydivideequals(1,2,4,or8) DIV 2500 2000 z) Shift H k y ( nc1500 e u q Fre Skip g 1000 n hi c wit S 500 0 10 20 30 40 50 60 Input Voltage (V) C027 Figure45. MaximumSwitchingFrequencyvsInputVoltage Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com Application Information (continued) 8.1.5 HowtoInterfacetoRT/CLKPin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 46. The square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended to use a frequency set resistor connected as shown in Figure 46 through a 50Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLKthresholdthedeviceswitchesfromtheRTresistorfrequencytoPLLmode.Theinternal0.5Vvoltagesource is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decreasetheswitchingfrequencyuntilthePLLlocksontotheCLKfrequencywithin100microseconds. When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 47, Figure 48 and Figure 49 show the device synchronized to an external system clockincontinuousconductionmode(ccm)discontinuousconduction(dcm)andpulseskipmode(psm). TPS54060 10 pF 4 kW PLL R fset EXT RT/CLK Clock 50W Source Figure46. SynchronizingtoaSystemClock 28 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 Application Information (continued) PH PH EXT EXT IL IL Figure47.PlotofSynchronizinginCCM Figure48.PlotofSynchronizinginDCM PH EXT IL Figure49.PlotofSynchronizinginPSM Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 8.2 Typical Applications 8.2.1 BuckConverterfor3.3-VOutput Figure50. HighFrequency,3.3VOutputPowerSupplyDesignwithAdjustedUVLO 8.2.1.1 DesignRequirements This example details the design of a high frequency switching regulator design using ceramic output capacitors. Afewparametersmustbeknowninordertostartthedesignprocess.Theseparametersaretypicallydetermined atthesystemlevel.Forthisexample,wewillstartwiththefollowingknownparameters: Table1.DesignParameters DESIGNPARAMETERS EXAMPLEVALUES OutputVoltage 3.3V TransientResponse0to0.5-A ΔVout=4% loadstep MaximumOutputCurrent 0.5A InputVoltage 34Vnom.12Vto48V OutputVoltageRipple 1%ofVout StartInputVoltage(risingVIN) 8.9V StopInputVoltage(fallingVIN) 7.9V 8.2.1.2 DetailedDesignProcedure 8.2.1.2.1 SelectingtheSwitchingFrequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switchesatalowerfrequency.Theswitchingfrequencythatcanbeselectedislimitedbytheminimumon-timeof theinternalpowerswitch,theinputvoltageandtheoutputvoltageandthefrequencyshiftlimitation. Equation 26 and Equation 27 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping orthelackofovercurrentprotectionduringashortcircuit. 30 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 The typical minimum on time, t , is 130 ns for the TPS54060. For this example, the output voltage is 3.3 V onmin and the maximum input voltage is 48 V, which allows for a maximum switch frequency up to 616 kHz when including the inductor resistance, on resistance and diode voltage in Equation 26. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 27 or the solid curve in Figure 45 to determine the maximum switching frequency. With a maximum input voltage of 48 V, assuming a diode voltage of 0.5 V, inductor resistance of 130mΩ, switch resistance of 400mΩ, a current limit value of 0.94 A and a short circuitoutputvoltageof0.1V.Themaximumswitchingfrequencyisapproximately923kHz. Choosing the lower of the two values and adding some margin a switching frequency of 500kHz is used. To determinethetimingresistanceforagivenswitchingfrequency,useEquation2 orthecurveinFigure29. TheswitchingfrequencyissetbyresistorR showninFigure50. 3 8.2.1.2.2 OutputInductorSelection(L ) O Tocalculatetheminimumvalueoftheoutputinductor,useEquation28. K isacoefficientthatrepresentstheamountofinductorripplecurrentrelativetothemaximumoutputcurrent. IND The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion ofthedesigner;however,thefollowingguidelinesmaybeused. For designs using low ESR output capacitors such as ceramics, a value as high as K = 0.3 may be used. IND When using higher ESR output capacitors, K = 0.2 yields better results. Since the inductor ripple current is IND part of the PWM control system, the inductor ripple current should always be greater than 30 mA for dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allowstheinductortostillhaveameasurableripplecurrentwiththeinputvoltageatitsminimum. For this design example, use K = 0.3 and the minimum inductor value is calculated to be 39.7 μH. For this IND design, a nearest standard value was chosen: 47μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation30andEquation31. For this design, the RMS inductor current is 0.501 A and the peak inductor current is 0.563 A. The chosen inductorisaMSS1048-473ML.Ithasasaturationcurrentratingof1.44AandanRMScurrentratingof1.83A. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of theregulatorbutallowforalowerinductancevalue. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitchcurrentlimitratherthanthepeakinductorcurrent. Vinmax - Vout Vout Lomin= ´ Io ´ K Vinmax ´ ƒsw IND (28) IRIPPLE = VOUVTin´ma(xVin´mLaOx ´-fSVWOUT) (29) 2 I = (I )2 + 1 ´æçVOUT ´ (Vinmax - VOUT)ö÷ L(rms) O 12 ç Vinmax ´ L ´ f ÷ è O SW ø (30) Iripple ILpeak = Iout+ 2 (31) Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 8.2.1.2.3 OutputCapacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in loadcurrent.Theoutputcapacitanceneedstobeselectedbasedonthemorestringentofthesethreecriteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance necessarytoaccomplishthis. For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no load) to 0.5 A (full load). For this example, ΔIout = 0.5-0 = 0.5 A and ΔVout = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 15.2μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.AluminumelectrolyticandtantalumcapacitorshavehigherESRthatshouldbetakenintoaccount. The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 51. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. For this example, the worst case load step will be from 0.5 A to 0 A. The output voltage will increase during this load transition and the stated maximum in our specification is 4% of the output voltage. This will make Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation33yieldsaminimumcapacitanceof13.2 μF. Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, V is the maximum allowable output voltage ripple, and I is the oripple ripple inductorripplecurrent.Equation34yields1μF. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.Equation35indicatestheESRshouldbelessthan248mΩ. The most stringent criteria for the output capacitor is 15.2μF of capacitance to keep the output voltage in regulationduringanloadtransient. Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase thisminimumvalue.Forthisexample,a47 μF10VX5Rceramiccapacitorwith5mΩ ofESRwillbeused. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRootMeanSquare(RMS)valueofthemaximumripplecurrent.Equation36 canbeused to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields 37.7mA. 2 ´ DIout Cout> ¦sw ´ DVout where • ΔIoutisthechangeinoutputcurrent. • ƒswistheregulatorsswitchingfrequency. • ΔVoutistheallowablechangeintheoutputvoltage. (32) 32 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 (Ioh2 - Iol2) Cout>Lo ´ (V¦2 -Vi2) where • Listhevalueoftheinductor. • I istheoutputcurrentunderheavyload. OH • I istheoutputunderlightload. OL • VFisthefinalpeakoutputvoltage. • Viistheinitialcapacitorvoltage. (33) 1 1 Cout> ´ 8 ´¦sw VORIPPLE I RIPPLE (34) V R < ORIPPLE ESR I RIPPLE (35) Vout ´ (Vinmax - Vout) Icorms= 12 ´ Vinmax ´ Lo ´ ¦sw (36) 8.2.1.2.4 CatchDiode The TPS54060 requires an external catch diode between the PH pin and GND. The selected diode must have a reversevoltageratingequaltoorgreaterthanVinmax.Thepeakcurrentratingofthediodemustbegreaterthan the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the highertheefficiencyoftheregulator. Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since the design example has an input voltage up to 48V, a diode with a minimum of 60V reverse voltage will be selected. For the example design, the B160A Schottky diode is selected for its lower forward voltage and it comes in a largerpackagesizewhichhasgoodthermalcharacteristicsoversmalldevices.Thetypicalforwardvoltageofthe B160Ais0.50volts. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power dissipation,conductionlossesplusaclosses,ofthediode. The B160A has a junction capacitance of 110pF. Using Equation 37, the selected diode will dissipate 0.297 Watts. This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in thediodewhentheinputvoltageis48Vandtheloadcurrentis0.5A. If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diodewhichhasalowleakagecurrentandslightlyhigherforwardvoltagedrop. 2 (Vinmax - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin+ Vƒd) Pd= + Vinmax 2 (37) Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 8.2.1.2.5 InputCapacitor The TPS54060 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54060. TheinputripplecurrentcanbecalculatedusingEquation38. The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreasesasthedcbiasacrossacapacitorincreases. For this example design, a ceramic capacitor with at least a 60V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4V, 6.3V, 10V, 16V, 25V, 50V or 100V so a 100V capacitor should be selected. For this example, two 2.2μF, 100V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value determinestheinputripplevoltageoftheregulator.TheinputvoltageripplecanbecalculatedusingEquation39. Using the design example values, Ioutmax = 0.5 A, Cin = 4.4μF, ƒsw = 500 kHz, yields an input voltage ripple of 57mVandarmsinputripplecurrentof0.223A. Vout (Vinmin - Vout) Icirms=Iout ´ ´ Vinmin Vinmin (38) Ioutmax ´ 0.25 ΔVin= Cin ´ ¦sw (39) Table2.CapacitorTypes VENDOR VALUE(μF) EIASize VOLTAGE DIALECTRIC COMMENTS 1.0to2.2 100V 1210 GRM32series 1.0to4.7 50V Murata 1.0 100V 1206 GRM31series 1.0to2.2 50V 1.0101.8 50V 2220 1.0to1.2 100V Vishay VJX7Rseries 1.0to3.9 50V 2225 1.0to1.8 100V X7R 1.0to2.2 100V 1812 CseriesC4532 1.5to6.8 50V TDK 1.0.to2.2 100V 1210 CseriesC3225 1.0to3.3 50V 1.0to4.7 50V 1210 1.0 100V AVX X7Rdielectricseries 1.0to4.7 50V 1812 1.0to2.2 100V 8.2.1.2.6 SlowStartCapacitor The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54060 reach the current limit or excessive current draw from the input power supply may cause the input voltagerailtosag.Limitingtheoutputvoltageslewratesolvesbothoftheseproblems. 34 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the 47μF output capacitor up to 3.3V while only allowing theaverageinputcurrenttobe0.125Awouldrequirea1msslowstarttime. Once the slow start time is known, the slow start capacitor value can be calculated using Equation 1. For the example circuit, the slow start time is not too critical since the output capacitor value is 47μF which does not require much current to charge to 3.3V. The example circuit has the slow start time set to an arbitrary value of 3.2mswhichrequiresa0.01μFcapacitor. Cout ´ Vout ´ 0.8 tss> Issavg (40) 8.2.1.2.7 BootstrapCapacitorSelection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V orhighervoltagerating. 8.2.1.2.8 UndervoltageLockout(UVLO)SetPoint TheUVLOcanbeadjustedusinganexternalvoltagedividerontheENpinoftheTPS54060.TheUVLOhastwo thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 8.9V (enabled). After the regulator starts switching, it should continue to do so until the inputvoltagefallsbelow7.9V(UVLOstop). TheprogrammableUVLOandenablevoltagesaresetusingaresistordividerbetweenVinandgroundtotheEN pin.Equation18throughEquation19 canbeusedtocalculatetheresistancevaluesnecessary.Fortheexample application,a332kΩ betweenVinandENanda56.2kΩ betweenENandgroundarerequiredtoproducethe8.9 and7.9voltstartandstopvoltages. 8.2.1.2.9 OutputVoltageandFeedbackResistorsSelection For the example design, 10.0 kΩ was selected for R2. Using Equation 17, R1 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease quiescentcurrentandimproveefficiencyatlowoutputcurrentsbutmayintroducenoiseimmunityproblems. 8.2.1.2.10 Compensation There are several methods used to compensate DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency used in the calculations. This method assume the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more accuratedesign. To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 603 Hz and fzmod is 796 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 21.9 kHz and Equation44gives12.3kHz.UsethelowervalueofEquation43 orEquation44foraninitialcrossoverfrequency. For this example, fco is 12.3kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensatingpole. Ioutmax ¦pmod= 2×p ×Vout×Cout (41) Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 1 ¦zmod= 2 ´ p ´ Resr×Cout (42) f = f mod´ f mod co p z (43) f f = f mod´ sw co p 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 1.9A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3V, 0.8V and 97μS, respectively. R4 is calculated to be 72.6 kΩ, use the nearest standard value of 73.2kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 3600pF for compensatingcapacitorC7,a3300pFisusedontheboard. æ2´p´ f ´C ö æ V ö R4=ç co out ÷´ç out ÷ è gmps ø èVref´gmeaø (45) 1 C7= 2´p´R4´ f mod p (46) Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole. Equation48yields8.7pFsotheneareststandardof10pFisused. C ´Resr C8= o R4 (47) 1 C8= R4´ f ´p sw (48) 8.2.1.2.11 DiscontinuousModeandEcoModeBoundary With an input voltage of 34V, the power supply enters discontinuous mode when the output current is less than 60mA.ThepowersupplyentersEcoModewhentheoutputcurrentislowerthan38mA. Theinputcurrentdrawatnoloadis228μA. 8.2.1.2.12 PowerDissipationEstimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation.Theseequationsshouldnotbeusedifthedeviceisworkingindiscontinuousconductionmode(DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supplycurrent(Pq). Vout Pcon=Io2 ´ R ´ DS(on) Vin (49) Psw=Vin2 ´ ¦sw ´ lo ´ 0.25 ´ 10-9 (50) Pgd=Vin ´ 3 ´ 10-9´¦sw (51) Pq=116 ´ 10-6 ´Vin (52) Where: Ioistheoutputcurrent(A). R istheon-resistanceofthehigh-sideMOSFET(Ω). DS(on) VOUTistheoutputvoltage(V). VINistheinputvoltage(V). fswistheswitchingfrequency(Hz). So Ptot=Pcon+Psw +Pgd+Pq (53) 36 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 ForgivenT , A TJ=TA+Rth ´ Ptot (54) ForgivenT =150°C JMAX TAmax=TJmax - Rth ´ Ptot (55) Where: Ptotisthetotaldevicepowerdissipation(W). T istheambienttemperature(°C). A T isthejunctiontemperature(°C). J RthisthethermalresistancejunctiontoambientforagivenPCBlayout(°C/W). T ismaximumjunctiontemperature(°C). JMAX T ismaximumambienttemperature(°C). AMAX Therewillbeadditionalpowerlossesintheregulatorcircuitduetotheinductoracanddclosses,thecatchdiode andtraceresistancethatwillimpacttheoverallefficiencyoftheregulator. 8.2.1.3 ApplicationCurves V = 20 V/div (AC Coupled) IN V = 1 V/div OUT I = 200 mA/div (0.125 to 0.375AStep) OUT V = 20 V/div IN Time = 5 ms/div Time = 2 ms/div Figure51.LoadTransient Figure52.Start-UpWithVIN V = 10 mV/div (AC Coupled) OUT V = 10 mV/div (AC Coupled) OUT PH = 20 V/div PH = 20 V/div Inductor Current = 100 mA/div Time = 1μs/div Time = 5μs/div Figure53.OutputRippleCCM Figure54.OutputRipple,DCM Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com V = 10 mV/div (AC Coupled) OUT V = 20 mV/div (AC Coupled) IN PH = 20 V/div PH = 20 V/div Time = 50μs/div Time = 1μs/div Figure55.OutputRipple,PSM Figure56.InputRippleCCM 100 V = 20 V/div (AC Coupled) IN 90 80 70 PH = 20 V/div ency (%) 5600 VIN= 34 VVIN= 24 VVIN= 18 VVIN= 12 V Effici 40 VIN= 42 V 30 Inductor Current = 100 mA/div 20 10 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Time = 5μs/div Output Current (A) C028 Figure57.InputRippleDCM Figure58.EfficiencyvsLoadCurrent 100 60 90 150 40 80 100 70 Phase 20 %) 60 50 Efficiency ( 4500 VIN= 34 VVIN= 24 VVIN= 18 VVIN= 12 V Gain (dB) 0 Gain 0–50 oPhase () –20 30 V = 42 V IN –100 20 –40 –150 10 0 –60 0 0.02 0.04 0.06 0.08 0.10 100 1k 10k 100k 1M Output Current (A) Frequency (Hz) C029 C030 Figure59.LightLoadEfficiency Figure60.OverallLoopFrequencyResponse 38 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 0.1 0.1 0.08 0.08 0.06 0.06 0.04 0.04 Regulation (%) –00..00022 Regulation (%) –00..00022 –0.04 –0.04 –0.06 –0.06 –0.08 –0.08 –0.1 –0.1 0.00 0.25 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 10 15 20 25 30 35 40 45 50 55 60 Load Current (A) Input Voltage (V) C031 C032 Figure61.RegulationvsLoadCurrent Figure62.RegulationvsInputVoltage 8.2.2 InvertingPowerSupply VIN + Cin Cboot Lo VIN BOOT PH GND Cd R1 GND + TPS54060 R2 Co VOUT VSENSE EN SS/TR COMP RT/CLK Rcomp Czero Cpole Css RT Figure63. InvertingPowerSupplyfromtheSLVA317 ApplicationNote Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 8.2.3 SplitRailPowerSupply VOPOS + VIN Copos + Cin Cboot GND VIN BOOT PH Lo Cd R1 + GND Coneg TPS54060 R2 VONEG VSENSE EN SS/TR COMP RT/CLK Rcomp Czero Cpole Css RT Figure64. SplitRailPowerSupplyBasedontheSLVA369 ApplicationNote 9 Power Supply Recommendations The design of the device is for operation from an power supply range between 3.5 V and 60 V. It is essential that the power supply voltage remains within this range. If the power supply is more distant than a few inches from the TPS54060 converter, the circuit may require additional bulk capacitance besides the ceramic bypass capacitors.Anelectrolyticcapacitorwithavalueof100 µFisatypicalchoice. 40 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

TPS54060 www.ti.com SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the ICandthepowerpad. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, andtheareaofthePCBconductorminimizedtopreventexcessivecapacitivecoupling.Foroperationatfullrated load,thetopsidegroundareamustprovideadequateheatdissipatingarea.TheRT/CLKpinissensitivetonoise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meantasaguideline. 10.1.1 EstimatedCircuitArea TheestimatedprintedcircuitboardareaforthecomponentsusedinthedesignofFigure50 is0.55in2.Thisarea doesnotincludetestpointsorconnectors. 10.2 Layout Example Vout Output Capacitor Output Topside Inductor Ground Route Boot Capacitor Catch Area Trace on another layer to Diode provide wide path for topside ground Input Bypass Capacitor BOOT PH Vin VIN GND EN COMP UVLO Adjust SS/TR VSENSE Compensation Resistor Resistors Network RT/CLK PWRGD Divider Slow Start Frequency Thermal VIA Capacitor Set Resistor Signal VIA Figure65. PCBLayoutExample Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TPS54060

TPS54060 SLVS919C–JANUARY2009–REVISEDSEPTEMBER2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.1.2 DevelopmentSupport FortheTPS54060andTPS54060AfamilyExceldesigntool,seeSLVC432. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • TPS54060EVM-4570.5-A,SWIFT(TM)RegulatorEVM, SLVU299 • CreateanInvertingPowerSupplyFromaStep-DownRegulator, SLVA317 • LevelShiftingControlforanInvertingBuck-boost, SLVA540 • CreatingaSplit-RailPowerSupplyWithaWideInputVoltageBuckRegulator, SLVA369 • TPS54060EVM-590100mA,SplitRailSWIFT™RegulatorEvaluationModule, SLVU374 • ImprovedLoadCurrentCapabilityforCap-DropOff-LinePowerSupplyforE-Meter, SLVA491 11.3 Trademarks Eco-Mode,PowerPAD,WEBENCH,SwitcherProaretrademarksofTexasInstruments. ExcelisaregisteredtrademarkofMicrosoftCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 42 SubmitDocumentationFeedback Copyright©2009–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54060

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54060DGQ ACTIVE HVSSOP DGQ 10 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 150 54060 & no Sb/Br) TPS54060DGQR ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 150 54060 & no Sb/Br) TPS54060DRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 150 54060 & no Sb/Br) TPS54060DRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 150 54060 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54060 : •Enhanced Product: TPS54060-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54060DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS54060DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS54060DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54060DGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0 TPS54060DRCR VSON DRC 10 3000 346.0 346.0 35.0 TPS54060DRCT VSON DRC 10 250 203.0 203.0 35.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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