(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 (cid:1) (cid:1) Qualified for Automotive Applications Supply Voltage Range...2.7 V to 6 V (cid:1) Dual Supervisory Circuits With Power Fail (cid:1) Defined RESET Output From V ≥ 1.1 V DD for DSP and Processor-Based Systems (cid:1) SO-8 Package (cid:1) Voltage Monitor for Power Fail or (cid:1) Temperature Range...−40°C to 125°C Low-Battery Warning (cid:1) Applications Include: (cid:1) Watchdog Timer With 0.8-s Time-Out Multivoltage DSPs and Processors (cid:1) Power-On Reset Generator With Integrated Portable Battery-Powered Equipment 100-ms Delay Time Embedded Control Systems (cid:1) Open-Drain Reset and Power-Fail Output Intelligent Instruments (cid:1) Supply Current of 15 µA (Typ) Automotive Systems D PACKAGE (TOP VIEW) description The TPS3306 family is a series of supervisory SENSE1 1 8 VDD SENSE2 2 7 WDI circuits designed for circuit initialization, which PFI 3 6 PFO require two supply voltages, primarily in DSP and GND 4 5 RESET processor-based systems. The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of 3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V. TYPICAL OPERATING CIRCUIT 3.3 V 1.5 V AVDD TPS3306−15 CVDD R3 R4 SENSE1 VDD DVDD R1 SENSE2 WDI B_XF 1% TMS320 VC5441 PFI PFO A_XF R2 GND RESET RESET 1% VSS VSSA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:2)(cid:18)(cid:19)(cid:14)(cid:15)(cid:20)(cid:1)(cid:23)(cid:19)(cid:28) (cid:14)(cid:16)(cid:1)(cid:16) (cid:29)(cid:30)(cid:31)!"#$%(cid:29)!(cid:30) (cid:29)& ’("")(cid:30)% $& !(cid:31) *(+,(cid:29)’$%(cid:29)!(cid:30) -$%). Copyright  2008 Texas Instruments Incorporated (cid:2)"!-(’%& ’!(cid:30)(cid:31)!"# %! &*)’(cid:29)(cid:31)(cid:29)’$%(cid:29)!(cid:30)& *)" %/) %)"#& !(cid:31) (cid:1))0$& (cid:23)(cid:30)&%"(#)(cid:30)%& &%$(cid:30)-$"- 1$""$(cid:30)%2. (cid:2)"!-(’%(cid:29)!(cid:30) *"!’)&&(cid:29)(cid:30)3 -!)& (cid:30)!% (cid:30))’)&&$"(cid:29),2 (cid:29)(cid:30)’,(-) %)&%(cid:29)(cid:30)3 !(cid:31) $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 description (continued) The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the following supply-voltage monitoring table. SUPPLY-VOLTAGE MONITORING NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) DDEEVVIICCEE SENSE1 SENSE2 SENSE1 SENSE2 TPS3306-15 3.3 V 1.5 V 2.93 V 1.4 V TPS3306-18 3.3 V 1.8 V 2.93 V 1.68 V TPS3306-20 3.3 V 2 V 2.93 V 1.85 V TPS3306-25 3.3 V 2.5 V 2.93 V 2.25 V TPS3306-33 5 V 3.3 V 4.55 V 2.93 V During power on, RESET is asserted when the supply voltage, V becomes higher than 1.1 V. Thereafter, the DD, supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below the threshold voltage, V . IT An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td(typ) = 100 ms, starts after SENSE1 and SENSE2 inputs have risen above VIT. When the voltage at SENSE1 or SENSE2 input drops below the V , the output becomes active (low) again. IT The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply. The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative transition of the watch-dog timer (WDI). When the supervising system fails to retrigger the watchdog circuit within the time-out interval, tt(out) = 0.50 s, RESET becomes active for the time period td . This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. The TPS3306-xx devices are available in standard 8-pin SO packages. The TPS3306-xxQ family is characterized for operation over a temperature range of −40°C to 125°C. (cid:1) AVAILABLE OPTIONS (cid:2) PACKAGED DEVICES TTOOPP--SSIIDDEE TTAA SMALL OUTLINE (D) MARKING Tape and reel TPS3306-15QDRQ1 615Q1 Tape and reel TPS3306-18QDRQ1 618Q1 −−4400(cid:2)CC ttoo 112255(cid:2)CC Tape and reel TPS3306-20QDRQ1 620Q1 Tape and reel TPS3306-25QDRQ1 625Q1 Tape and reel TPS3306-33QDRQ1 633Q1 †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 FUNCTION/TRUTH TABLES SENSE1 > VIT1 SENSE2 > VIT2 RESET 0 0 L 0 1 L 1 0 L 1 1 H PFI > VIT PFO TYPICAL DELAY 0→1 L→H 0.5 µs 1→0 H→L 0.5 µs functional block diagram TPS3306 SENSE 1 R1 VDD + _ SENSE 2 RESET RESET R2 R3 Logic + Timer + _ R4 GND Reference Oscillator Voltage PFO of 1.25 V _ PFI + Transition Watchdog WDI Detection Logic + Timer 40 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 timing diagram SENSEn V(nom) VIT 1.1 V t WDI 1 tt(out) 0 t RESET 1 Undefined Undefined Behavior Behavior 0 t td td td Reset Due to Power Down Reset Due to WDI Reset Due to Power Drop Below VIT− Reset Due to Power Up Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. GND 4 I Ground PFI 3 I Power-fail comparator input PFO 6 O Power-fail comparator output, open drain RESET 5 O Active-low reset output, open drain SENSE1 1 I Sense voltage 1 SENSE2 2 I Sense voltage 2 WDI 7 I Watchdog timer input VDD 8 I Supply voltage detailed description watchdog In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to typically toggle the watchdog input (WDI) within 0.8 s to avoid a time-out occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected or tied with a high-impedance driver, the watchdog is disabled and is retriggered internally. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 saving current while using the watchdog WDI is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If, instead, WDI is externally driven high for the majority of the time-out period, a current of 5 V/40 kΩ ≈ 125 µA can flow into WDI. VDD VIT t WDI t(tout) t RESET td td t Figure 1. Watchdog Timing power-fail comparator (PFI and PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input (PFI) is compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold (V ) of 1.25 V (typ), the power-fail output (PFO) goes low. If PFO goes above 1.25 V plus about 10−mV hysteresis, PFI the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above 1.25 V. The sum of both resistors should be approximately 1 MΩ, to minimize power consumption and also to ensure that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected. R1 + R2 V(SENSE) VPFI,trip = 1.25 V× R2 R1 1% VCC PFI PFO TPS3306 R2 1% GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (see Note1):V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Maximum low output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA OL Maximum high output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA OH Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260(cid:2)C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h continuously. DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW recommended operating conditions at specified temperature range MIN MAX UNIT Supply voltage, VDD 2.7 6 V Input voltage at WDI and PFI, VI 0 VDD + 0.3 V Input voltage at SENSE1 and SENSE2, VI 0 (VDD + 0.3)VIT/1.25 V V High-level input voltage at WDI, VIH 0.7 × VDD V Low-level input voltage at WDI, VIL 0.3 ×VDD V Operating free-air temperature range, TA −40 125 °C 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 2.7 V to 6 V,IOL = 20 µA 0.2 RESET, VOOLL Low-level output voltage VDD = 3.3 V, IOL = 2 mA 0.4 V PPFFOO VDD = 6 V, IOL = 3 mA 0.4 Power-up reset voltage (see Note 2) VDD ≥1.1 V, IOL = 20 µA 0.4 V 1.35 1.4 1.44 1.62 1.68 1.74 VVSSEENNSSEE11,, 1.79 1.85 1.91 NNeeggaattiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VVDDDD == 22..77 VV ttoo 66 VV,, VVIITT ((sseeee NNoottee 33)) VVSSEENNSSEE22 TTAA == −−4400°°CC ttoo 112255°°CC 2.18 2.25 2.34 VV 2.84 2.93 3.04 4.44 4.55 4.68 PFI 1.2 1.25 1.3 PFI VIT = 1.25 V 10 VIT = 1.4 V 15 VIT = 1.68 V 15 VVhhyyss HHyysstteerreessiiss VIT = 1.86 V 20 mmVV VVSSEENNSSEEnn VIT = 2.25 V 20 VIT = 2.93 V 30 VIT = 4.55 V 40 IH(AV) Average high-level input current WDI WDI = VDD = 6 V, 100 150 µA Time average (dc = 88%) IL(AV) Average low-level input current WDI WDI = 0 V, VDD = 6 V, −15 −20 µA Time average (dc = 12%) WDI WDI = VDD = 6 V 120 170 IIHH HHiigghh--lleevveell iinnppuutt ccuurrrreenntt SENSE1 VSENSE1 = VDD = 6 V 5 10 µµAA SENSE2 VSENSE2 = VDD = 6 V 6 10 IL Low-level input current WDI WDI = 0 V, VDD = 6 V −120 −170 µA II Input current PFI VDD = 6 V, 0 V ≤ VI ≤ VDD −30 30 nA IDD Supply current 15 40 µA Ci Input capacitance VI = 0 V to VDD 10 pF NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥15 µs/V. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals. timing requirements at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN MAX UNIT SENSEn VSENSEnL = VIT − 0.2 V, VSENSEnH = VIT + 0.2 V 6 µs ttww PPuullssee wwiiddtthh WDI VIH = 0.7 × VDD, VIL = 0.3 × VDD 100 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 switching characteristics at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C FROM TO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) VI(SENSEn) ≥VIT + 0.2 V, tt(out) Watchdog time-out 0.5 0.8 1.2 s See timing diagram VI(SENSEn) ≥VIT + 0.2 V, td Delay time 70 100 140 ms See timing diagram tPHL Propagation (delay) time, SENSEn RESET VIH = VIT + 0.2 V, 1 5 µs high- to low-level output VIL = VIT − 0.2 V Propagation (delay) time, tPHL high- to low-level output PPFFII PPFFOO 00..55 11 µss Propagation (delay) time, tPLH low- to high-level output TYPICAL CHARACTERISTICS NORMALIZED SENSE THRESHOLD VOLTAGE SUPPLY CURRENT vs vs (cid:1)C) FREE-AIR TEMPERATURE AT VDD SUPPLY VOLTAGE 5 (2T 1.005 18 VI VDD = 6 V 16 , A) 1.004 14 T VIT( 1.003 12 TPS3306-33 — 1.002 µA 10 e − ag 1.001 nt 8 olt re 6 d V 1 Cur 4 ol y resh 0.999 uppl 2 h S 0 ut T 0.998 − D −2 p D d In 0.997 I −4 SENSEn = VDD ze −6 TA = 25°C ali 0.996 m −8 r 0.995 o −10 N −40 −15 10 35 60 85 −0.50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 TA − Free-Air Temperature − °C VDD − Supply Voltage − V Figure 2 Figure 3 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:12)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:5)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:13)(cid:9)(cid:7)(cid:10)(cid:8)(cid:11) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:4)(cid:4)(cid:7)(cid:10)(cid:8) (cid:14)(cid:15)(cid:16)(cid:17) (cid:2)(cid:18)(cid:19)(cid:20)(cid:21)(cid:3)(cid:3)(cid:19)(cid:18) (cid:3)(cid:15)(cid:2)(cid:21)(cid:18)(cid:22)(cid:23)(cid:3)(cid:19)(cid:18)(cid:24) (cid:20)(cid:23)(cid:18)(cid:20)(cid:15)(cid:23)(cid:1)(cid:3) (cid:25)(cid:23)(cid:1)(cid:26) (cid:2)(cid:19)(cid:25)(cid:21)(cid:18) (cid:27)(cid:16)(cid:23)(cid:17) SGLS241B − MARCH 2004 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT 2.8 6.5 VDD = 2.7 V 6 VDD = 6 V 2.4 Output Voltage − V 1.62 Output Voltage − V 345...55554 w-Level 1.2 85°C w-Level 2.53 85°C − LoVOL 00..48 −40°C − LoVOL 1.521 −40°C 0.5 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 5 10 15 20 25 30 35 40 45 50 55 60 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 4 Figure 5 MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE 10 s VDD = 6 V µ 9 − e s 8 n e s V 7 at n o 6 ati r u 5 D e uls 4 P m 3 u m ni 2 Mi − 1 w t 0 0 100 200 300 400 500 600 700 800 9001000 SENSE − Threshold Overdrive − mV Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS3306-15QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 615Q1 & no Sb/Br) TPS3306-15QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 615Q1 & no Sb/Br) TPS3306-18QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 618Q1 & no Sb/Br) TPS3306-18QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 618Q1 & no Sb/Br) TPS3306-20QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 620Q1 & no Sb/Br) TPS3306-25QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 625Q1 & no Sb/Br) TPS3306-33QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 633Q1 & no Sb/Br) TPS3306-33QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 633Q1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS3306-Q1 : •Catalog: TPS3306 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS3306-15QDRG4Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-15QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-18QDRG4Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-18QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-20QDRG4Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-25QDRG4Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-33QDRG4Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3306-33QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS3306-15QDRG4Q1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-15QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-18QDRG4Q1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-18QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-20QDRG4Q1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-25QDRG4Q1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-33QDRG4Q1 SOIC D 8 2500 350.0 350.0 43.0 TPS3306-33QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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