Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 TPS28226 High-Frequency 4-A Sink Synchronous MOSFET Drivers 1 Features 2 Applications • DrivesTwoN-ChannelMOSFETswith14-ns • Multi-PhaseDC-to-DCConverterswithAnalogor 1 AdaptiveDeadTime DigitalControl • WideGateDriveVoltage:4.5VUpto8.8VWith • DesktopandServerVRMsandEVRDs BestEfficiencyat7Vto8V • PortableandNotebookRegulators • WidePowerSystemTrainInputVoltage:3VUp • SynchronousRectificationforIsolatedPower to27V Supplies • WideInputPWMSignals:2.0Vupto13.2-V Amplitude 3 Description • CapabletoDriveMOSFETswith ≥40-ACurrent The TPS28226 is a high-speed driver for N-channel perPhase complimentary driven power MOSFETs with adaptive dead-time control. This driver is optimized for use in • HighFrequencyOperation:14-nsPropagation variety of high-current one and multi-phase DC-to-DC Delayand10-nsRise/FallTimeAllowF –2 SW converters. The TPS28226 is a solution that provides MHz highefficiency,smallsizeandlowEMIemissions. • CapabletoPropagate <30-nsInputPWMPulses The efficiency is achieved by up to 8.8-V gate drive • Low-SideDriverSinkOn-Resistance(0.4Ω) voltage, 14-ns adaptive dead-time control, 14-ns PreventsdV/dTRelatedShoot-ThroughCurrent propagation delays and high-current 2-A source and • 3-StatePWMInputforPowerStageShutdown 4-A sink drive capability. The 0.4-Ω impedance for the lower gate driver holds the gate of power • SpaceSavingEnable(Input)andPowerGood MOSFET below its threshold and ensures no shoot- (Output)SignalsonSamePin through current at high dV/dt phase node transitions. • ThermalShutdown The bootstrap capacitor charged by an internal diode • UVLOProtection allows use of N-channel MOSFETs in a half-bridge configuration. • InternalBootstrapDiode • EconomicalSOIC-8andThermallyEnhanced3- DeviceInformation(1) mmx3-mmDFN-8Packages PARTNUMBER PACKAGE BODYSIZE(NOM) • HighPerformanceReplacementforPopular3- SOIC(8) 4.90mm×3.91mm StateInputDrivers TPS28226 VSON(8) 3.00mmx3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic TPS28226 Vc (4.5V to 8V) Vin (4.5V to 24V) 6 VDD BOOT 2 UGATE 1 TL500X 3 PWM PHASE 8 VCC 3 Vout OUT3 7 ENBL FB 3 LGATE 5 GND 3 GND 4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................17 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 17 3 Description............................................................. 1 8.1 ApplicationInformation............................................17 4 RevisionHistory..................................................... 2 8.2 TypicalApplication .................................................18 8.3 SystemExamples...................................................25 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 27 6 Specifications......................................................... 4 10 Layout................................................................... 27 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings ............................................................4 10.1 LayoutGuidelines.................................................27 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................28 6.4 ThermalInformation..................................................5 11 DeviceandDocumentationSupport................. 29 6.5 ElectricalCharacteristics..........................................5 11.1 DeviceSupport ....................................................29 6.6 SwitchingCharacteristics..........................................6 11.2 DocumentationSupport .......................................29 6.7 TypicalCharacteristics..............................................7 11.3 CommunityResources..........................................29 7 DetailedDescription............................................ 11 11.4 Trademarks...........................................................29 7.1 Overview.................................................................11 11.5 ElectrostaticDischargeCaution............................29 7.2 FunctionalBlockDiagram.......................................11 11.6 Glossary................................................................29 7.3 FeatureDescription.................................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 29 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(April2010)toRevisionD Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 ChangesfromRevisionB(July2007)toRevisionC Page • ChangedFUNCTIONALBLOCKDIAGRAM.......................................................................................................................... 3 2 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 5 Pin Configuration and Functions DPackage 8-PinSOIC TopView UGATE 1 8 PHASE BOOT 2 7 EN/PG PWM 3 6 VDD GND 4 5 LGATE DRBPackage 8-PinVSON TopView UGATE 1 8 PHASE BOOT 2 Exposed 7 EN/PG Thermal PWM 3 Die Pad 6 VDD GND 4 5 LGATE PinFunctions PIN NO. I/O DESCRIPTION NAME SOIC VSON Floatingbootstrapsupplypinfortheuppergatedrive.Connectthebootstrap BOOT 2 2 I/O capacitorbetweenthispinandthePhasepin.Thebootstrapcapacitor providesthechargetoturnontheupperMOSFET. Enable/powergoodinput/outputpinwith1-MΩimpedance.Connectthispin toHightoenableandLowtodisablethedevice.Whendisabled,thedevice EN/PG 7 7 I/O drawslessthan350-μAbiascurrent.IftheV isbelowUVLOthresholdor DD overtemperatureshutdownoccurs,thispinisinternallypulledlow. GND 4 4 – Groundpin.Allsignalsarereferencedtothisnode. Lowergatedrivesinkandsourceoutput.Connecttothegateofthelow-side LGATE 5 5 O powerN-ChannelMOSFET. ConnectthispintothesourceoftheupperMOSFETandthedrainofthe PHASE 8 8 I lowerMOSFET.Thispinprovidesareturnpathfortheuppergatedriver. ThePWMsignalisthecontrolinputforthedriver.ThePWMsignalcanenter threedistinctstatesduringoperation,seethe3-statePWMInputsection PWM 3 3 I underDETAILEDDESCRIPTIONforfurtherdetails.Connectthispintothe PWMoutputofthecontroller. Exposeddie Thermalpad – ConnectdirectlytotheGNDforbetterthermalperformanceandEMI. pad Uppergatedrivesink/sourceoutput.Connecttogateofhigh-sidepowerN- UGATE 1 1 O ChannelMOSFET. Connectthispintoa5-Vbiassupply.Placeahighqualitybypasscapacitor VDD 6 6 I fromthispintoGND. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT Inputsupplyvoltagerange,V (3) –0.3 8.8 V DD Bootvoltage,V –0.3 33 V BOOT 32orV +0.3– Phasevoltage,V DC –2 BOOT V PHASE V whicheverisless DD 33.1orV +0.3– Pulse<400ns,E=20μJ –7 BOOT V V whicheverisless DD Inputvoltagerange,V ,V –0.3 13.2 V PWM EN/PG V +0.3, BOOT V –0.3 (V –V < V PHASE BOOT PHASE 8.8) Outputvoltagerange,V UGATE V +0.3, BOOT Pulse<100ns,E=2μJ V –2 (V –V < V PHASE BOOT PHASE 8.8) –0.3 V +0.3 V DD Outputvoltagerange,V LGATE Pulse<100ns,E=2μJ –2 V +0.3 V DD Continuoustotalpowerdissipation SeeThermalInformation Operatingvirtualjunctiontemperaturerange,T –40 150 °C J Operatingambienttemperaturerange,T –40 125 °C A Leadtemperature(soldering,10sec.) 300 °C Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Thesedevicesaresensitivetoelectrostaticdischarge;followproperdevicehandlingprocedures. (3) AllvoltagesarewithrespecttoGNDunlessotherwisenoted.Currentsarepositiveinto,negativeoutofthespecifiedterminal.Consult PackagingSectionoftheDatabookforthermallimitationsandconsiderationsofpackages. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- C101(2) ±500 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Inputsupplyvoltage 6.8 7.2 8 V DD V Powerinputvoltage 3 32V–VDD V IN T Operatingjunctiontemperaturerange –40 125 °C J 4 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 6.4 Thermal Information TPS28226 THERMALMETRIC VSON(DRB) SOIC(D) UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 50.2 123.2 °C/W θJA R Junction-to-case(top)thermalresistance 57.5 77.0 °C/W θJC(top) R Junction-to-boardthermalresistance 25.9 63.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 1.5 27.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 26.0 63.0 °C/W JB R Junction-to-case(bottom)thermalresistance 9.5 N/A °C/W θJC(bot) 6.5 Electrical Characteristics(1) V =7.2V,EN/PGpulleduptoV by100-kΩresistor,T =T =–40°Cto125°C(unlessotherwisenoted) DD DD A J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT UNDERVOLTAGELOCKOUT Risingthreshold V =0V 6.35 6.70 V PWM Fallingthreshold V =0V 4.7 5.0 V PWM Hysteresis 1.00 1.35 V BIASCURRENTS I Biassupplycurrent V =low,PWMpinfloating 350 μA DD(off) EN/PG I Biassupplycurrent V =high,PWMpinfloating 500 μA DD EN/PG INPUT(PWM) V =5V 185 μA PWM I Inputcurrent PWM V =0V –200 μA PWM PWM3-staterisingthreshold(2) 1.0 V PWM3-statefallingthreshold V PEAK=5V 3.4 3.8 4.0 V PWM t 3-stateshutdownHold-offtime 250 ns HLD_R PWMminimumpulsetoforceU T GATE C =3nFatU ,V =5V 30 ns MIN pulse L GATE PWM ENABLE/POWERGOOD(EN/PG) Enablehighrisingthreshold PGFETOFF 1.7 2.1 V Enablelowfallingthreshold PGFETOFF 0.8 1.0 V Hysteresis 0.35 0.70 V Powergoodoutput V =2.5V 0.2 V DD UPPERGATEDRIVEROUTPUT(UGATE) Sourceresistance 500mAsourcecurrent 1.0 2.0 Ω Sourcecurrent (2) V =2.5V 2.0 A UGATE-PHASE t Risetime C =3nF 10 ns RU L Sinkresistance 500mAsinkcurrent 1.0 2.0 Ω Sinkcurrent (2) V =2.5V 2.0 A UGATE-PHASE t Falltime C =3nF 10 ns FU L (1) TypicalvaluesforT =25°C A (2) Notproductiontested. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com Electrical Characteristics(1) (continued) V =7.2V,EN/PGpulleduptoV by100-kΩresistor,T =T =–40°Cto125°C(unlessotherwisenoted) DD DD A J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT LOWERGATEDRIVEROUTPUT(LGATE) Sourceresistance 500mAsourcecurrent 1.0 2.0 Ω Sourcecurrent(2) V =2.5V 2.0 A LGATE t Risetime(2) C =3nF 10 ns RL L Sinkresistance 500mAsinkcurrent 0.4 1.0 Ω Sinkcurrent(2) V =2.5V 4.0 A LGATE Falltime(2) C =3nF 5 ns L BOOTSTRAPDIODE V Forwardvoltage Forwardbiascurrent100mA 1.0 V F THERMALSHUTDOWN Risingthreshold(2) 150 160 170 °C Fallingthreshold(2) 130 140 150 °C Hysteresis 20 °C 6.6 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SWITCHINGTIME t UGATEturn-offpropagationDelay C =3nF 14 ns DLU L t LGATEturn-offpropagationDelay C =3nF 14 ns DLL L DeadtimeLGATEturnoffto t C =3nF 14 ns DTU UGATEturnon L DeadtimeUGATEturnoffto t C =3nF 14 ns DTL LGATEturnon L Enterinto3-Stateat Enterinto3-Stateat Normalswitching Exit3-State PWMrise PWMfall 90% PWM 50% 50% 3-State window t 10% t PWM_MIN t HLD_F HLD_R t RU 90% t 90% 90% UGATE DLU 10% 10% 90% tFU tRL t 90% LGATE tDLL DTU tDTL 90% 10% 10% t FL LGATEexits3-StateafterPWM goesHighandthenLow Figure1. TPS28226TimingDiagram 6 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 6.7 Typical Characteristics 500 8.00 480 7.50 460 7.00 A 440 Bias Supply - P 440200 ockout - V 66..0500 TPS28226 Rising tI DD(off) 336800 oltage L 55..0500 TPS28226 Falling V 340 er 4.50 d 320 Un 300 O - 4.00 -40 25 125 VL 3.50 U TJ - Temperature - °C VEN/PG=Low PWMInputFloating VDD=7.2V 3.00 Figure2.BiasSupplyCurrentvsTemperature 2.50 2.00 -40 25 125 T - Temperature - °C J Figure3.UndervoltageLockoutThresholdvsTemperature 2.00 5.0 4.5 1.75 Rising 4.0 Falling V EN/PG - Enable/Power Good - V 01011.....7250555000 Falling PWM - PWM 3-State Threshold - 231221......000555 Rising 0.25 0.5 0.00 0.0 -40 25 125 -40 25 125 TJ - Temperature - °C V =7.2V TJ - Temperature - °C V =7.2V DD DD Figure5.PWM3-StateThresholds,(5-VInputPulses)vs Figure4.Enable/PowerGoodThresholdvsTemperature Temperature Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com Typical Characteristics (continued) 2.00 2.00 1.75 1.75 1.50 1.50 :R- Output Impedance - OUT 0101....72505500 RSOURCE RSINK :R- Output Impedance - OUT 0101....72505500 RSOURCE RSINK 0.25 0.25 0 0 -40 25 125 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C VDD=7.2V VDD=7.2V Figure6.UGATEDCOutputImpedancevsTemperature Figure7.LGATEDCOutputImpedancevsTemperature 15 14 14 13 t and t - Rise and Fall Time - nsRUFU 1111891302 Rise Fall t and t - Rise and Fall Time - nsRLFL 1116798021 Rise Fall 7 5 6 4 -40 25 125 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C V =7.2V C =3nF V =7.2V C =3nF DD LOAD DD LOAD Figure8.UGATERiseandFallTimevsTemperature Figure9.LGATERiseandFallTimevsTemperature 30 20.0 17.5 UGATE 25 UGATE t and t - U and L - nsDLUDLLGATEGATE 211005 LGATE t and t- U and L - nsDTUDTL GATEGATE 11175205.....50500 LGATE 5 2.5 0 0.0 -40 25 125 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C VDD=7.2V CLOAD=3nF VDD=7.2V CLOAD=3nF Figure10.UGATEandLGATE(TurningOFFPropagation Figure11.UGATEandLGATE(DeadTime)vsTemperture Delays)vsTemperture 8 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 Typical Characteristics (continued) 30 1.3 1.2 25 ns 1.1 um Short Pulse - 1250 ward Voltage - V 10..09 m w T - MiniMIN 10 V - ForF 00..87 5 0.6 0 0.5 -40 25 125 -40 25 125 TJ - Temperature - °C TJ - Temperature - °C V =7.2V C =3nF V =7.2V I =100mA DD LOAD DD F Figure12.UGATEMinimumShortPulsevsTemperature Figure13.BootstrapDiodeForwardVoltagevsTemperature 15 1200 UG = 50 nC, LG = 50 nC 1000 I - Bias Supply Current - mADD 150 P - Dissipated Power - mWDISS 468000000 LUGG = = 1 2050 n nCC, ULGG == 2550 nnCC, 200 0 0 100 300 500 700 900 1100130015001700 1900 100 300 500 700 900 1100130015001700 1900 FSW - Switching Frequency - kHz FSW - Switching Frequency - kHz NoLoad VDD=7.2V TJ=25°C DifferentLoad VDD=7.2V TJ=25°C Charge Figure14.BiasSupplyCurrentvsSwitchingFrequency Figure15.DriverDissipatedPowervsSwitchingFrequency VDD = 7.2 V, CL = 3 nF, TJ = 25oC VDD = 7.2 V, CL = 3 nF, TJ = 25oC PWM PWM v v di di V/ V/ 5 5 ±e LGATE ±e LGATE g g a a olt olt V V UGATE UGATE t ± Time ± 10 ns/div t ± Time ± 10 ns/div Figure16.PWMInputRisingSwitchingWaveforms Figure17.PWMInputFallingSwitchingWaveforms Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com Typical Characteristics (continued) V = 7.2 V, C = 3 nF, T = 25oC DD L J PWM 30ns v PWM ± 2 V/div di 5 V/ ge ±e LGATE olta 3-St Trigger, High = 3-St g V a Volt UGATE ± 10 V/div UGATE LGATE ± 10 V/div t ± Time ± 20 ns/div t ± Time ± 5 és/div Figure18.MinimumUGATEPulseSwitchingWaveforms Figure19.Normaland3-StateOperationEnter/Exit Conditions 10 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 7 Detailed Description 7.1 Overview TheTPS28226featuresa3-statePWMinputcompatiblewithallmulti-phasecontrollersemploying3-stateoutput feature. As long as the input stays within 3-state window for the 250-ns hold-off time, the driver switches both outputslow.Thisshutdownmodepreventsaloadfromthereversed-output-voltage. The other features include undervoltage lockout, thermal shutdown and two-way enable/power good signal. Systems without 3-state featured controllers can use enable/power good input/output to hold both outputs low duringshuttingdown. The TPS28226 is offered in an economical SOIC-8 and thermally enhanced low-size Dual Flat No-Lead (DFN-8) packages. The driver is specified in the extended temperature range of –40°C to 125°C with the absolute maximumjunctiontemperature150°C. 7.2 Functional Block Diagram VDD 6 2 BOOT UVLO 1 UGATE EN/PG 7 THERMAL 8 PHASE SD SHOOT- HLD-OFF TIME THROUGH PROTECTION VDD 27K 3-STATE INPUT PWM 3 CIRCUIT 5 LGATE 13K 4 GND FortheTPS28226DRBthethermalPADonthebottomsideofpackagemustbesolderedandconnectedtotheGND pinandtotheGNDplaneofthePCBintheshortestpossibleway. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com 7.3 Feature Description 7.3.1 UndervoltageLockout(UVLO) The TPS28226 incorporates an under voltage lockout circuit that keeps the driver disabled and external power FETs in an OFF state when the input supply voltage V is insufficient to drive external power FETs reliably. DD During power up, both gate drive outputs remain low until voltage V reaches UVLO threshold, typically 6.35 V. DD Once the UVLO threshold is reached, the condition of the gate drive outputs is defined by the input PWM and EN/PG signals. During power down the UVLO threshold is set lower, typically 5.0 V. The 1.35 V for the TPS28226 hysteresis is selected to prevent the driver from turning ON and OFF while the input voltage crosses UVLO thresholds, especially with low slew rate. The TPS28226 has the ability to send a signal back to the system controller that the input supply voltage V is insufficient by internally pulling down the EN/PG pin. The DD TPS28226releasesEN/PGpinimmediatelyaftertheV hasrisenabovetheUVLOthreshold. DD 7.3.2 OutputActiveLow The output active-low circuit effectively keeps the gate outputs low even if the driver is not powered up. This prevents open-gate conditions on the external power FETs and accidental turn on when the main power-stage supply voltage is applied before the driver is powered up. For the simplicity, the output active low circuit is shown in a block diagram as the resistor connected between LGATE and GND pins with another one connected betweenUGATEandPHASEpins. 12 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 Feature Description (continued) 7.3.3 Enable/PowerGood The Enable/Power Good circuit allows the TPS28226 to follow the PWM input signal when the voltage at EN/PG pin is above 2.1 V maximum. This circuit has a unique two-way communication capability. This is illustrated by Figure20. VCC VDD = 4.5 V to 8 V Driver TPS28226 6 8(cid:3)20 k: System 2 V Rise Controller 1 V Fall 1 k: EN/PG 7 R = 1 k: DS(on) UVLO 1 M Thermal SD Figure20. Enable/PowerGoodCircuit The EN/PG pin has approximately 1-kΩ internal series resistor. Pulling EN/PG high by an external ≥ 20-kΩ resistor allows two-way communication between controller and driver. If the input voltage V is below UVLO DD threshold or thermal shut down occurs, the internal MOSFET pulls EN/PG pin to GND through 1-kΩ resistor. The voltage across the EN/PG pin is now defined by the resistor divider comprised by the external pull up resistor, 1- kΩ internal resistor and the internal FET having 1-kΩ R . Even if the system controller allows the driver to DS(on) start by setting its own enable output transistor OFF, the driver keeps the voltage at EN/PG low. Low EN/PG signal indicates that the driver is not ready yet because the supply voltage V is low or that the driver is in DD thermal shutdown mode. The system controller can arrange the delay of PWM input signals coming to the driver until the driver releases EN/PG pin. If the input voltage V is back to normal, or the driver is cooled down below DD its lower thermal shutdown threshold, then the internal MOSFET releases the EN/PG pin and normal operation resumes under the external Enable signal applied to EN/PG input. Another feature includes an internal 1-MΩ resistor that pulls EN/PG pin low and disables the driver in case the system controller accidentally loses connection with the driver. This could happen if, for example, the system controller is located on a separate PCB daughterboard. The EN/PG pin can serve as the second pulse input of the driver additionally to PWM input. The delay between EN/PG and the UGATE going high, provided that PWM input is also high, is only about 30 ns. If the PWM input pulses are synchronized with EN/PG input, then when PWM and EN/PG are high, the UGATE is high and LGATE is low. If both PWM and EN/PG are low, then UGATE and LGATE are both low as well. This means the driver allows operation of a synchronous buck regulator as a conventional buck regulator using the body diode of the low-side power MOSFET as the freewheeling diode. This feature can be useful in some specific applications to allow startup with a pre-biased output or, to improve the efficiency of buck regulator when in power saving modewithlowoutputcurrent. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com Feature Description (continued) 7.3.4 3-StateInput As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below). The dead-time control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the TPS28226 has a self-adjustable PWM 3-state input circuit. The 3-state circuit sets both gate drive outputs low, and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250 ns typical. At this condition, the PWM input voltage level is defined by the internal 27-kΩ to 13-kΩ resistor divider shownintheblockdiagram.Thisresistordividerforcestheinputvoltagetomoveintothe3-statewindow.Initially the 3-state window is set between 1.0-V and 2.0-V thresholds. The lower threshold of the 3-state window is always fixed at about 1.0 V. The higher threshold is adjusted to about 75% of the input signal amplitude. The self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input signal was high, thus keeping the high-side power FET in ON state just slightly longer than 250 ns time constant setbyaninternal3-statetimer.Bothmodesofoperation,PWMinputpulsesequencingandthe3-statecondition, are illustrated in the timing diagrams shown in Figure 19. The self-adjustable upper threshold allows operation in wide range amplitude of input PWM pulse signals. After entering into the 3-state window and staying within the window for the hold-off time, the PWM input signal level is defined by the internal resistor divider and, depending on the input pulse amplitude, can be pulled up above the normal PWM pulse amplitude (Figure 21) or down belowthenormalinputPWMpulse(Figure22). 7.3.4.1 TPS282263-StateExitMode • Toexitthe3-stateoperationmode,thePWMsignalshouldgohighandthenlowatleastonce. This is necessary to restore the voltage across the bootstrap capacitor that could be discharged during the 3- statemodeifthe3-stateconditionlastslongenough. Figure21.6-VAmplitudePWMPulse(TPS28225example) Figure22.2.5-VAmplitudePWMPulse(TPS28225 example) NOTE The driver sets UGATE low and LGATE high when PWM is low. When the PWM goes high,UGATEgoeshighandLGATEgoeslow. 14 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 Feature Description (continued) 7.3.4.2 ExternalResistorInterference AnyexternalresistorbetweenPWMinputandGNDwiththevaluelowerthan40kΩ caninterferewiththe3-state thresholds. If the driver is intended to operate in the 3-state mode, any resistor below 40 kΩ at the PWM and GND should be avoided. A resistor lower than 3.5 kΩ connected between the PWM and GND completely disables the 3-state function. In such case, the 3-state window shrinks to zero and the lower 3-state threshold becomestheboundarybetweentheUGATEstayinglowandLGATEbeinghighandviceversadependingonthe PWM input signal applied. It is not necessary to use a resistor <3.5 kΩ to avoid the 3-state condition while using a controller that is 3-state capable. If the rise and fall time of the input PWM signal is shorter than 250 ns, then thedriverneverentersintothe3-statemode. In the case where the low-side MOSFET of a buck converter stays on during shutdown, the 3-state feature can be fused to avoid negative resonant voltage across the output capacitor. This feature also can be used during start up with a pre-biased output in the case where pulling the output low during the startup is not allowed due to system requirements. If the system controller does not have the 3-state feature and never goes into the high- impedance state, then setting the EN/PG signal low will keep both gate drive outputs low and turn both low- and high-sideMOSFETsOFFduringtheshutdownandstartupwiththepre-biasedoutput. Theself-adjustableinputcircuitacceptswiderangeofinputpulseamplitudes(2Vupto13.2V)allowinguseofa variety of controllers with different outputs including logic level. The wide PWM input voltage allows some flexibility if the driver is used in secondary side synchronous rectifier circuit. The operation of the TPS28226 with a 12-V input PWM pulse amplitude, and with V = 7.2 V and V = 5 V respectively is shown in Figure 23 and DD DD Figure24. Figure23.12-VPWMPulseatVDD=7.2V Figure24.12-VPWMPulseatVDD=5V Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com Feature Description (continued) 7.3.5 BootstrapDiode The bootstrap diode provides the supply voltage for the UGATE driver by charging the bootstrap capacitor connected between BOOT and PHASE pins from the input voltage VDD when the low-side FET is in ON state. At the very initial stage when both power FETs are OFF, the bootstrap capacitor is pre-charged through this path including the PHASE pin, output inductor and large output capacitor down to GND. The forward voltage drop acrossthediodeisonly1.0Vatbiascurrent100mA.Thisallowsquickchargerestoreofthebootstrapcapacitor duringthehigh-frequencyoperation. 7.3.6 UpperandLowerGateDrivers The upper and lower gate drivers charge and discharge the input capacitance of the power MOSFETs to allow operation at switching frequencies up to 2 MHz. The output stage consists of a P-channel MOSFET providing source output current and an N-channel MOSFET providing sink current through the output stage. The ON state resistances of these MOSFETs are optimized for the synchronous buck converter configuration working with low duty cycle at the nominal steady state condition. The UGATE output driver is capable of propagating PWM input puses of less than 30-ns while still maintaining proper dead time to avoid any shoot through current conditions. ThewaveformsrelatedtothenarrowinputPWMpulseoperationareshowninFigure18. 7.3.7 Dead-TimeControl The dead-time control circuit is critical for highest efficiency and no shoot through current operation throughout the whole duty cycle range with the different power MOSFETs. By sensing the output of driver going low, this circuit does not allow the gate drive output of another driver to go high until the first driver output falls below the specified threshold. This approach to control the dead time is called adaptive. The overall dead time also includes the fixed portion to ensure that overlapping never exists. The typical dead time is around 14 ns, although it varies over the driver internal tolerances, layout and external MOSFET parasitic inductances. The proper dead time is maintained whenever the current through the output inductor of the power stage flows in the forward or reverse direction. Reverse current could happen in a buck configuration during the transients or while dynamically changing the output voltage on the fly, as some microprocessors require. Because the dead time doesnotdependoninductorcurrentdirection,thisdrivercanbeusedbothinbuckandboostregulatorsorinany bridge configuration where the power MOSFETs are switching in a complementary manner. Keeping the dead time at short optimal level boosts efficiency by 1% to 2% depending on the switching frequency. Measured switching waveforms in one of the practical designs show 10-ns dead time for the rising edge of PHASE node and22nsforthefallingedge(Figure39andFigure40intheApplicationSectionofthedatasheet). Large non-optimal dead time can cause duty cycle modulation of the DC-to-DC converter during the operation point where the output inductor current changes its direction right before the turn ON of the high-side MOSFET. This modulation can interfere with the controller operation and it impacts the power stage frequency response transfer function. As the result, some output ripple increase can be observed. The TPS28226 driver is designed with the short adaptive dead time having fixed delay portion that eliminates risk of the effective duty cycle modulationatthedescribedboundarycondition. 7.3.8 ThermalShutdown If the junction temperature exceeds 160°C, the thermal shutdown circuit will pull both gate driver outputs low and thus turning both, low-side and high-side power FETs OFF. When the driver cools down below 140°C after a thermal shutdown, then it resumes its normal operation and follows the PWM input and EN/PG signals from the external control circuit. While in thermal shutdown state, the internal MOSFET pulls the EN/PG pin low, thus setting a flag indicating the driver is not ready to continue normal operation. Normally the driver is located close to the MOSFETs, and this is usually the hottest spots on the PCB. Thus, the thermal shutdown feature of the TPS28226canbeusedasanadditionalprotectionforthewholesystemfromoverheating. 16 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 7.4 Device Functional Modes TPS28226devicefunctionalmodetruthtable. Table1.TruthTable V FALLING>3VANDT <150°C DD J V RISING<3.5V EN/PGFALLING>1.0V PIN DODRT >160°C EN/PGRISING J <1.7V PWM<1V TPWM/T>1.5<V2A00NDns PW>4M0SkIΩGNFAOLRS>O2U5R0CnEs(IM3-PSEtaDteA)N(1C)E RISE FALL LGATE Low Low High Low Low UGATE Low Low Low High Low EN/PG Low – – – – (1) Toexitthe3-statecondition,thePWMsignalshouldgolow.OneHighPWMinputsignalfollowedbyoneLowPWMinputsignalis requiredbeforere-enteringthe3-statecondition. 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information To effect fast switching of power devices and reduce associated switching power losses, a powerful MOSFET driver is employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, MOSFET drivers are indispensable when it is impossible for the PWM controller to directly drive the MOSFETs of the switching devices. With the advent of digital power, this situation will be often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power because they lack level-shifting capability. MOSFET drivers effectively combine boththelevel-shiftingandbuffer-drivefunctions. MOSFET drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gatechargepowerlossesfromthecontrollerintothedriver. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com 8.2 Typical Application The DC-DC converter in Figure 25 displays the schematic of the TPS28226 in a multiphase high-current step- down power supply (only one phase is shown). This design uses a single high-side MOSFET Q10 and two low- side MOSFETs Q8 and Q9, the latter connected in parallel. The TPS28226 is controlled by multiphase buck DC- to-DCcontrollerlikeTPS40090.AsTPS28226hasinternalshoot-throughprotectiononlyonePWMcontrolsignal isrequiredforeachchannel. Figure25. OneofFourPhasesDrivenbyTPS28226Driverin4-PhaseVRMReferenceDesign 18 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 Typical Application (continued) 8.2.1 DesignRequirements The VRM Reference Design is capable of driving 35 A per phase. In this example it has a nominal input voltage of 12 V within a tolerance range of ±5%. The switching frequency is 500 kHz. The nominal duty cycle is 10%, therefore the low-side MOSFETs are conducting 90% of the time. By choosing lower R the conduction DS(on) lossesoftheswitchingelementsareminimized. Table2.VRMReferenceDesignRequirements DESIGNPARAMETER VALUE Supplyvoltage 12V±5% Outputvoltage 0.83Vto1.6V Frequency 500kHz Peak-to-peakoutputvoltagevariationonloadcurrenttransient(0Ato100A) <160mV within1µs Dynamicoutputvoltagechangeslewrate 12.25mVper5µs 8.2.2 DetailedDesignProcedure The bootstrap current can be limited by changing R32 to prevent overcharging of the bootstrap capacitor and to slow the turn-on transition of the high-side MOSFET. This reduces the peak amplitude and ringing of the switching node. Furthermore it minimizes the possibility of Cdv/dt-induced shoot-through of the low-side MOSFETs.ThesnubberscomposedofC50withR51andC51withR52helptoreduceswitchingnoise. The output component selection considers the requirement of a fast transient response. For output capacitors small capacitance values are chosen because of rapid changes of the output voltage. These changes also require an inductor with low inductance. Due to the small duty cycle the low-side MOSFETs conduct a long time. Twolow-sideMOSFETsareselectedtoincreaseboththermalperformanceandefficiency. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com 8.2.2.1 FourPhasesDrivenbyTPS28226Driver WhenusingthesamepowerstageFigure25,thedriverwiththeoptimaldrivevoltageandoptimaldeadtimecan boost efficiency up to 5%. The optimal 8-V drive voltage versus 5-V drive contributes 2% to 3% efficiency increase and the remaining 1% to 2% can be attributed to the reduced dead time. The 7-V to 8-V drive voltage is optimal for operation at switching frequency range above 400 kHz and can be illustrated by observing typical R curvesofmodernFETsasafunctionoftheirgate-drivevoltage.ThisisshowninFigure26. DS(on) Figure 26 and Figure 27 show that the R at 5-V drive is substantially larger than at 7 V and above that the DS(on) R curve is almost flat. This means that moving from 5-V drive to an 8-V drive boosts the efficiency because DS(on) of lower R of the MOSFETs at 8 V. Further increase of drive voltage from 8 V to 12 V only slightly DS(on) decreases the conduction losses but the power dissipated inside the driver increases dramatically (by 125%). The power dissipated by the driver with 5-V, 8-V and 12-V drive as a function of switching frequency from 400 kHz to 800 kHz. It should be noted that the 12-V driver exceeds the maximum dissipated power allowed for an SOIC-8packageevenat400-kHzswitchingfrequency. 2.0 12-V Estimation 1.5 W SOIC-8 Package oss - Limit at 45CO e L 1.0 v Dri RRVVddggss oo==nn 55@@VV RRVVddggss oo==nn 77VV@@ D - L 8-V TPS28225 0.5 5-V Ind. Stand. 0.0 400 500 600 700 800 fS - Switching Frequency - kHz Figure27.DrivePowerasFunctionofV andF GS SW Figure26.R ofMOSFETasFunctionofV DS(on) GS 20 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 8.2.2.2 SwitchingTheMOSFETs Driving the MOSFETs efficiently at high switching frequencies requires special attention to layout and the reduction of parasitic inductances. Efforts need to be done both at the driver’s die and package level and at the PCB layout level to keep the parasitic inductances as low as possible. Figure 28 shows the main parasitic inductancesandcurrentflowduringturningONandOFFoftheMOSFETbychargingitsC gatecapacitance. GS Lbond wire Ltrace Lpin 6 VDD I source Cvdd Rsource Ltrace Driver Lbond wire Lpin Rg Output 5 Stage LGATE Rsink I sink Cgs Lbond wire Lpin Ltrace Ltrace 4 GND Figure28. MOSFETDrivePathsandMainCircuitParasitics Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com The I current charges the gate capacitor and the I current discharges it. The rise and fall time of SOURCE SINK voltage across the gate defines how quickly the MOSFET can be switched. The timing parameters specified in datasheet for both upper and lower driver are shown in Figure 16 and Figure 17 where 3-nF load capacitor has been used for the characterization data. Based on these actual measurements, the analytical curves in Figure 29 and Figure 30 show the output voltage and current of upper and low side drivers during the discharging of load capacitor.Theleftwaveformsshowthevoltageandcurrentasafunctionoftime,whiletherightwaveformsshow the relation between the voltage and current during fast switching. These waveforms show the actual switching process and its limitations because of parasitic inductances. The static V / I curves shown in many OUT OUT datasheets and specifications for the MOSFET drivers do not replicate actual switching condition and provide limitedinformationfortheuser. Turning Off of the MOSFET needs to be done as fast as possible to reduce switching losses. For this reason the TPS28226 driver has very low output impedance specified as 0.4 Ω typical for lower driver and 1 Ω typical for upper driver at DC current. Assuming 8-V drive voltage and no parasitic inductances, one can expect an initial sink current amplitude of 20 A and 8 A respectively for the lower and upper drivers. With pure R-C discharge circuit for the gate capacitor, the voltage and current waveforms are expected to be exponential. However, because of parasitic inductances, the actual waveforms have some ringing and the peak current for the lower driver is about 4 A and about 2.5 A for the upper driver (Figure 29 and Figure 30). The overall parasitic inductance for the lower drive path is estimated as 4 nH and for the upper drive path as 6 nH. The internal parasitic inductance of the driver, which includes inductances of bonded wires and package leads, can be estimated for SOIC-8 package as 2 nH for lower gate and 4 nH for the upper gate. Use of DFN-8 package reducestheinternalparasiticinductancesbyapproximately50%. Figure29. LGATETurningOffVoltageandSinkCurrentvsTime(RelatedSwitchingDiagram(right)) Figure30. UGATETurningOffVoltageandSinkCurrentvsTime(RelatedSwitchingDiagram(right)) 22 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 8.2.2.3 ListofMaterials For this specific example see Table 3. The component vendors are not limited to those shown in the table below. It should be noted that in this example, the power MOSFET packages were chosen with drains on top. The decoupling capacitors C47, C48, C65, and C66 were chosen to have low profiles. This allows the designer to meet good layout rules and place a heatsink on top of the FETs using an electrically isolated and thermally conductivepad. Table3.ListofMaterials REFDES COUNT DESCRIPTION MANUFACTURE PARTNUMBER C47,C48, 4 Capacitor,ceramic,4.7μF,16V,X5R10%,lowprofile0.95mm,1206 TDK C3216X5R1C475K C65,C66 C41,C42 2 Capacitor,ceramic,10μF,16V,X7R10%,1206 TDK C3216X7R1C106K C50,C51 2 Capacitor,ceramic,1000pF,50V,X7R,10%,0603 Std Std C23 1 Capacitor,ceramic,0.22μF,16V,X7R,10%,0603 Std Std C25,C49, 3 Capacitor,ceramic,1μF,16V,X7R,10%,'0603 Std Std C71 L3 1 Inductor,SMT,0.12μH,31A,0.36mΩ,0.400x0.276 Pulse PA0511-101 Q8,Q9 2 Mosfet,N-channel,VDS30V,RDS2.4mΩ,ID45A,LFPAK-i Renesas RJK0301DPB-I Q10 1 Mosfet,N-channel,VDS30V,RDS6.2mΩ,ID30A,LFPAK-i Renesas RJK0305DPB-I R32 1 Resistor,chip,0Ω,1/10W,1%,'0805 Std Std R51,R52 2 Resistor,chip,2.2Ω,1/10W,1%,'0805 Std Std Device,HighFrequency4-ASinkSynchronousBuckMOSFETDriver, U7 1 TexasInstruments TPS28226DRB DFN-8 Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com 8.2.3 ApplicationCurves Efficiency achieved using TPS28226 driver with 8-V drive at different switching frequencies a similar industry 5-V driverusingthepowerstageinFigure25isshowninFigure31,Figure32,Figure33,Figure34andFigure35. 90 90 % 85 % 85 y - y - c c n n e e ci ci Effi Effi 80 80 TI: 400kHz TI: 500kHz Ind: 400kHz Ind: 500kHz 75 75 5 10 15 20 25 30 35 5 10 15 20 25 30 35 CL ± Load Current - A CL ± Load Current - A Figure31.EfficiencyvsLoadCurrent Figure32.EfficiencyvsLoadCurrent 90 90 TI: 600kHz TI: 700kHz Ind: 600kHz Ind: 700kHz % 85 % 85 y - y - c c n n e e ci ci Effi Effi 80 80 75 75 5 10 15 20 25 30 35 5 10 15 20 25 30 35 CL ± Load Current - A CL ± Load Current - A Figure33.EfficiencyvsLoadCurrent Figure34.EfficiencyvsLoadCurrent 90 TI: 800kHz Ind: 800kHz % 85 y - c n e ci Effi 80 75 5 10 15 20 25 30 35 CL ± Load Current - A Figure35.EfficiencyvsLoadCurrent 24 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 8.3 System Examples Figure 36, Figure 37 and Figure 38below illustrate typical implementations of the TPS28226 in step-down power supplies. TPS28226 Vc (4.5V to 8V) Vin (4.5V to 24V) 6 VDD BOOT 2 UGATE 1 TL500X 3 PWM PHASE 8 VCC 3 Vout OUT3 7 ENBL FB 3 LGATE 5 GND 3 GND 4 Figure36. One-PhasePOLRegulator +12V +35V to 75V Vout: 3.3V Primary High Side VDD High Voltage Driver HB HI L DRIVE HO O HI PWM R T HS LINEAR CONTROLLER ON REG. LI C DRIVE LO LO TPS28226 BOOT2 VSS Vc (4.5V to 8V) 6 VDD ISOLATION UGATE1 AND FEEDBACK 7EN/PG PHASE8 3PWM LGATE5 GND4 Figure37. DriverforSynchronousRectificationwithComplementaryDrivenMOSFETs Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com System Examples (continued) Vc (4.5V to 8V) Vin (3V to 15V) 6 VDD BOOT 2 TPS28226 UGATE 1 3 PWM PHASE 8 7 EN/PG LGATE 5 PWM1 2 GND 4 CS1 To Driver To Controller oger PWM2 1 TPS4009xor any other analor digital controll PWVMIN3 88 To Driver 6 VDD BOOT 2 TPS28226 To Controller PWM4 5 CS4 CSCN UGATE 1 GND 4 GNDS VOUT 3 PWM PHASE 8 7 3 Vout 7 EN/PG Enable LGATE 5 GND 4 Figure38. Multi-PhaseSynchronousBuckConverter 26 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 9 Power Supply Recommendations The supply voltage range for operation is 4.5 to 8 V. The lower end of this range is governed by the under- voltage lockout thresholds. The UVLO disables the driver and keeps the power FETs OFF when V is too low. DD A lows ESR ceramic decoupling capacitor in the range of 0.22 µF to 4.7 µF between V and GND is DD recommended. 10 Layout 10.1 Layout Guidelines Toimprovetheswitchingcharacteristicsandefficiencyofadesign,thefollowinglayoutrulesneedtobefollowed. • LocatethedriverascloseaspossibletotheMOSFETs. • LocatetheV andbootstrapcapacitorsascloseaspossibletothedriver. DD • Pay special attention to the GND trace. Use the thermal pad of the DFN-8 package as the GND by connecting it to the GND pin. The GND trace or pad from the driver goes directly to the source of the MOSFET but should not include the high current path of the main current flowing through the drain and sourceoftheMOSFET. • UseasimilarruleforthePHASEnodeasfortheGND. • Use wide traces for UGATE and LGATE closely following the related PHASE and GND traces. Eighty to 100 milswidthispreferablewherepossible. • Useatleast2ormoreviasiftheMOSFETdrivingtraceneedstoberoutedfromonelayertoanother.Forthe GND the number of vias are determined not only by the parasitic inductance but also by the requirements for thethermalpad. • AvoidPWMandenabletracesgoingclosetothePHASEnodeandpadwherehighdV/dTvoltagecaninduce significantnoiseintotherelativelyhighimpedanceleads. It should be taken into account that poor layout can cause 3% to 5% less efficiency versus a good layout design andcanevendecreasethereliabilityofthewholesystem. The schematic of one of the phases in a multi-phase synchronous buck regulator and the related layout are shown in Figure 25 and Figure 41. These help to illustrate good design practices. The power stage includes one high-side MOSFET Q10 and two low-side MOSFETS (Q8 and Q9). The driver (U7) is located on bottom side of PCB close to the power MOSFETs. The related switching waveforms during turning ON and OFF of upper FET are shown in Figure 39 and Figure 40. The dead time during turning ON is only 10 ns (Figure 39) and 22 ns duringturningOFF(Figure40). Figure39.PhaseRising-EdgeSwitchingWaveforms(20 Figure40.PhaseFalling-EdgeSwitchingWaveforms(10 ns/div)ofthePowerStageinFigure25 ns/div)ofthePowerStateinFigure25 Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS28226

TPS28226 SLUS791A–JULY2007–REVISEDSEPTEMBER2015 www.ti.com 10.2 Layout Example Figure41. ComponentPlacementBasedonSchematicinFigure25 28 SubmitDocumentationFeedback Copyright©2007–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS28226

TPS28226 www.ti.com SLUS791A–JULY2007–REVISEDSEPTEMBER2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Documentation Support 11.2.1 RelatedDocumentation • TPS40090,TPS400912/3/4-PhaseMulti-PhaseController,(SLUS578) 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2007–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS28226

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS28226D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 28226 & no Sb/Br) TPS28226DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 28226 & no Sb/Br) TPS28226DRBR ACTIVE SON DRB 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 8226 & no Sb/Br) TPS28226DRBT ACTIVE SON DRB 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 8226 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS28226DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS28226DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS28226DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS28226DR SOIC D 8 2500 340.5 338.1 20.6 TPS28226DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS28226DRBT SON DRB 8 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DRB0008A VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.08 C DIM A 0.00 OPT 1 OPT 2 1.5 0.1 (0.1) (0.2) 4X (0.23) EXPOSED (DIM A) TYP THERMAL PAD 4 5 2X 1.95 1.75 0.1 8 1 6X 0.65 0.37 8X 0.25 PIN 1 ID 0.1 C A B (OPTIONAL) (0.65) 0.05 C 0.5 8X 0.3 4218875/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.5) (0.65) SYMM 8X (0.6) (0.825) 8X (0.31) 1 8 SYMM (1.75) (0.625) 6X (0.65) 4 5 (R0.05) TYP ( 0.2) VIA TYP (0.23) (0.5) (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218875/A 01/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.65) 4X (0.23) SYMM METAL TYP 8X (0.6) 4X (0.725) 8X (0.31) 1 8 (2.674) SYMM (1.55) 6X (0.65) 4 5 (R0.05) TYP (1.34) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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