(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 (cid:1) Industry-Standard Driver Replacement TPS2811, TPS2812, TPS2813...D, P, AND PW (cid:1) PACKAGES 25-ns Max Rise/Fall Times and 40-ns Max (TOP VIEW) Propagation Delay − 1-nF Load, V = 14 V CC (cid:1) 2-A Peak Output Current, V = 14 V REG_IN 1 8 REG_OUT CC (cid:1) 5-µA Supply Current — Input High or Low 1IN 2 7 1OUT (cid:1) GND 3 6 VCC 4-V to 14-V Supply-Voltage Range; Internal 2IN 4 5 2OUT Regulator Extends Range to 40 V (TPS2811, TPS2812, TPS2813) (cid:1) −40°C to 125°C Ambient-Temperature TPS2814...D, P, AND PW PACKAGES (TOP VIEW) Operating Range 1IN1 1 8 GND description 1IN2 2 7 1OUT The TPS28xx series of dual high-speed MOSFET 2IN1 3 6 VCC drivers are capable of delivering peak currents of 2 A 2IN2 4 5 2OUT into highly capacitive loads. This performance is achieved with a design that inherently minimizes TPS2815...D, P, AND PW PACKAGES shoot-through current and consumes an order of (TOP VIEW) magnitude less supply current than competitive products. 1IN1 1 8 GND 1IN2 2 7 1OUT The TPS2811, TPS2812, and TPS2813 drivers include 2IN1 3 6 VCC a regulator to allow operation with supply inputs 2IN2 4 5 2OUT between 14 V and 40 V. The regulator output can power other circuitry, provided power dissipation does not exceed package limitations. When the regulator is not required, REG_IN and REG_OUT can be left disconnected or both can be connected to V or GND. CC The TPS2814 and the TPS2815 have 2-input gates that give the user greater flexibility in controlling the MOSFET. The TPS2814 has AND input gates with one inverting input. The TPS2815 has dual-input NAND gates. TPS281x series drivers, available in 8-pin PDIP, SOIC, and TSSOP packages operate over a ambient temperature range of −40°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICES INTERNAL SMALL PLASTIC TA LOGIC FUNCTION REGULATOR OUTLINE DIP TSSOP (PW) (D) (P) Dual inverting drivers TPS2811D TPS2811P TPS2811PW Yes Dual noninverting drivers TPS2812D TPS2812P TPS2812PW −40°C One inverting and one noninverting driver TPS2813D TPS2813P TPS2813PW ttoo 125°C Dual 2-input AND drivers, one inverting input on each driver TPS2814D TPS2814P TPS2814PW No Dual 2-input NAND drivers TPS2815D TPS2815P TPS2815PW The D package is available taped and reeled. Add R suffix to device type (e.g., TPS2811DR). The PW package is only available left-end taped and reeled and is indicated by the R suffix on the device type (e.g., TPS2811PWR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:2)(cid:23)(cid:21)(cid:11)(cid:12)(cid:25)(cid:1)(cid:16)(cid:21)(cid:26) (cid:11)(cid:13)(cid:1)(cid:13) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’, Copyright  2002, Texas Instruments Incorporated (cid:2)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #-’ #’(cid:31)!$ (cid:30)(cid:29) (cid:1)’."$ (cid:16)(cid:28)$#(cid:31)&!’(cid:28)#$ $#"(cid:28)+"(cid:31)+ /"(cid:31)(cid:31)"(cid:28)#0, (cid:2)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, www.ti.com 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 functional block diagram regulator diagram (TPS2811, TPS2812, TPS2813 only) REG_IN TPS2811 1 8 REG_IN Regulator REG_OUT 6 VCC 2 1IN 7 1OUT 4 2IN 5 3 2OUT GND 7.5 Ω REG_OUT TPS2812 1 8 REG_IN Regulator REG_OUT 6 2 VCC 1IN 7 1OUT 4 2IN 5 3 2OUT GND input stage diagram VCC TPS2813 1 8 REG_IN Regulator REG_OUT 6 VCC 2 1IN 7 1OUT 4 2IN 5 To Drive 3 2OUT IN GND Stage TPS2814 6 1 VCC 1IN1 2 7 1IN2 1OUT 3 2IN1 4 5 output stage diagram 2IN2 2OUT VCC 8 GND Predrive TPS2815 6 VCC 1 1IN1 7 2 1OUT 1IN2 3 OUT 2IN1 5 4 2OUT 2IN2 8 GND 2 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 TPS28xxY chip information This chip, when properly assembled, displays characteristics similar to those of the TPS28xx. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (8) (1) REG_OUT REG_IN (7) TPS2811Y 1OUT (2) (1) (8) 1IN TPS2812Y (6) (4) TPS2813Y VCC 2IN (5) 2OUT (3) (7) GND (1) (2) 1IN1 (7) (2) 1OUT 1IN2 (6) (3) TPS2814Y VCC 2IN1 (5) (4) 2OUT 2IN2 (8) 57 (6) GND (1) 1IN1 (7) (2) 1OUT (3) 1IN2 (6) (3) TPS2815Y VCC 2IN1 (5) (4) 2OUT 2IN2 (5) (8) GND (4) CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM 47 TJmax OPERATING TEMPERATURE = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. www.ti.com 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 Terminal Functions TPS2811, TPS2812, TPS2813 TERMINAL NUMBERS TERMINAL TPS2811 TPS2812 TPS2813 DESCRIPTION NAME Dual Inverting Dual Noninverting Complimentary Drivers Drivers Drivers REG_IN 1 1 1 Regulator input 1IN 2 2 2 Input 1 GND 3 3 3 Ground 2IN 4 4 4 Input 2 2OUT 5 = 2IN 5 = 2IN 5 = 2IN Output 2 VCC 6 6 6 Supply voltage 1OUT 7 = 1IN 7 = 1IN 7 = 1IN Output 1 REG_OUT 8 8 8 Regulator output TPS2814, TPS2815 TERMINAL NUMBERS TERMINAL TPS2814 TPS2815 DESCRIPTION NAME Dual AND Drivers with Single Dual NAND Drivers Inverting Input 1IN1 1 1 Noninverting input 1 of driver 1 1IN2 2 - Inverting input 2 of driver 1 1IN2 - 2 Noninverting input 2 of driver 1 2IN1 3 3 Noninverting input 1 of driver 2 2IN2 4 - Inverting input 2 of driver 2 2IN2 - 4 Noninverting input 2 of driver 2 2OUT 5 = 2IN1 •2IN2 5 = 2IN1 •2IN2 Output 2 VCC 6 6 Supply voltage 1OUT 7 = 1IN1 •1IN2 7 = 1IN1 •1IN2 Output 1 GND 8 8 Ground DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING P 1090 mW 8.74 mW/°C 697 mW 566 mW D 730 mW 5.84 mW/°C 467 mW 380 mW PW 520 mW 4.17 mW/°C 332 mW 270 mW 4 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V CC Regulator input voltage range, REG_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V −0.3 V to 42 V CC Input voltage range, 1IN, 2IN, 1IN1, 1IN2, 1IN2, 2IN1, 2IN2, 2IN2 . . . . . . . . . . . . . . . . . −0.3 V to V +0.5 V CC Output voltage range, 1OUT, 2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 < V < V +0.5 V CC Continuous regulator output current, REG_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous output current, 1OUT, 2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to device GND pin. recommended operating conditions MIN MAX UNIT Regulator input voltage range 8 40 V Supply voltage, VCC 4 14 V Input voltage, 1IN1, 1IN2, 1IN2, 2IN1, 2IN2, 2IN2, 1IN, 2IN −0.3 VCC V Continuous regulator output current, REG_OUT 0 20 mA Ambient temperature operating range −40 125 °C TPS28xx electrical characteristics over recommended operating ambient temperature range, VCC = 10 V, REG_IN open for TPS2811/12/13, CL = 1 nF (unless otherwise noted) inputs PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VCC = 5 V 3.3 4 V PPoossiittiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VCC = 10 V 5.8 9 V VCC = 14 V 8.3 13 V VCC = 5 V 1 1.6 V NNeeggaattiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VCC = 10 V 1 4.2 V VCC = 14 V 1 6.2 V Input hysteresis VCC = 5 V 1.6 V Input current Inputs = 0 V or VCC −1 0.2 1 µA Input capacitance 5 10 pF †Typicals are for TA = 25°C unless otherwise noted. outputs PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT IO = −1 mA 9.75 9.9 HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VV IO = −100 mA 8 9.1 IO = 1 mA 0.18 0.25 LLooww--lleevveell oouuttppuutt vvoollttaaggee VV IO = 100 mA 1 2 Peak output current VCC = 10 V 2 A †Typicals are for TA = 25°C unless otherwise noted. www.ti.com 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 regulator (TPS2811/2812/2813 only) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Output voltage 14 ≤REG_IN ≤40 V, 0 ≤IO ≤20 mA 10 11.5 13 V Output voltage in dropout IO = 10 mA, REG_IN = 10 V 9 9.6 V †Typicals are for TA = 25°C unless otherwise noted. supply current PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Supply current into VCC Inputs high or low 0.2 5 µA Supply current into REG_IN REG_IN = 20 V, REG_OUT open 40 100 µA †Typicals are for TA = 25°C unless otherwise noted. TPS28xxY electrical characteristics at TA = 25°C, VCC = 10 V, REG_IN open for TPS2811/12/13, CL = 1 nF (unless otherwise noted) inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 5 V 3.3 V PPoossiittiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VCC = 10 V 5.8 V VCC = 14 V 8.2 V VCC = 5 V 1.6 V NNeeggaattiivvee--ggooiinngg iinnppuutt tthhrreesshhoolldd vvoollttaaggee VCC = 10 V 3.3 V VCC = 14 V 4.2 V Input hysteresis VCC = 5 V 1.2 V Input current Inputs = 0 V or VCC 0.2 µA Input capacitance 5 pF outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO = −1 mA 9.9 HHiigghh--lleevveell oouuttppuutt vvoollttaaggee VV IO = −100 mA 9.1 IO = 1 mA 0.18 LLooww--lleevveell oouuttppuutt vvoollttaaggee VV IO = 100 mA 1 Peak output current VCC = 10.5 V 2 A regulator (TPS2811, 2812, 2813) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage 14 ≤REG_IN ≤40 V, 0 ≤IO ≤20 mA 11.5 V Output voltage in dropout IO = 10 mA, REG_IN = 10 V 9.6 V power supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply current into VCC Inputs high or low 0.2 µA Supply current into REG_IN REG_IN = 20 V, REG_OUT open 40 µA 6 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 switching characteristics for all devices over recommended operating ambient temperature range, REG_IN open for TPS2811/12/13, CL = 1 nF (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 14 V 14 25 ttrr RRiissee ttiimmee VCC = 10 V 15 30 nnss VCC = 5 V 20 35 VCC = 14 V 15 25 ttff FFaallll ttiimmee VCC = 10 V 15 30 nnss VCC = 5 V 18 35 VCC = 14 V 25 40 ttPPHHLL PPrroopp ddeellaayy ttiimmee hhiigghh--ttoo--llooww--lleevveell oouuttppuutt VCC = 10 V 25 45 nnss VCC = 5 V 34 50 VCC = 14 V 24 40 ttPPLLHH PPrroopp ddeellaayy ttiimmee llooww--ttoo--hhiigghh--lleevveell oouuttppuutt VCC = 10 V 26 45 nnss VCC = 5 V 36 50 PARAMETER MEASUREMENT INFORMATION TPS2811 VCC + 1 8 Regulator 0.1 µF 4.7 µF 2 7 Input Output 50 Ω 1 nF 3 6 4 5 NOTE A: Input rise and fall times should be ≤10 ns for accurate measurement of ac parameters. Figure 1. Test Circuit For Measurement of Switching Characteristics www.ti.com 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION TPS2811 1 8 Regulator 2 7 0−10 V dc xOUT Current Loop 3 6 VCC 10 V + 0.1 µF 4.7 µF 4 5 Figure 2. Shoot-through Current Test Setup 1IN 50% 50% 0 V tf tr 90% 90% 1OUT 50% 50% 10% 10% 0 V tPHL tPLH Figure 3. Typical Timing Diagram (TPS2811) TYPICAL CHARACTERISTICS Tables of Characteristics Graphs and Application Information typical characteristics PARAMETER vs PARAMETER 2 FIGURE PAGE Rise time Supply voltage 4 10 Fall time Supply voltage 5 10 Propagation delay time Supply voltage 6, 7 10 Supply voltage 8 11 SSuuppppllyy ccuurrrreenntt Load capacitance 9 11 Ambient temperature 10 11 Input threshold voltage Supply voltage 11 11 Regulator output voltage Regulator input voltage 12, 13 12 Regulator quiescent current Regulator input voltage 14 12 Peak source current Supply voltage 15 12 Peak sink current Supply voltage 16 13 Input voltage, high-to-low 17 13 SShhoooott--tthhrroouugghh ccuurrrreenntt Input voltage, low-to-high 18 13 8 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS Tables of Characteristics Graphs and Application Information (Continued) general applications PARAMETER vs PARAMETER 2 FIGURE PAGE Switching test circuits and application information 19, 20 15 Low-to-high 21, 23, 25 16, 17 VVoollttaaggee ooff 11OOUUTT vvss 22OOUUTT TTiimmee High-to-low 22, 24, 26 16, 17 circuit for measuring paralleled switching characteristics PARAMETER vs PARAMETER 2 FIGURE PAGE Switching test circuits and application information 27 17 Low-to-high 28, 30 18 IInnppuutt vvoollttaaggee vvss oouuttppuutt vvoollttaaggee TTiimmee High-to-low 29, 31 18 Hex-1 to Hex-4 application information PARAMETER vs PARAMETER 2 FIGURE PAGE Driving test circuit and application information 32 19 Hex-1 size 33 20 Hex-2 size 36 20 DDrraaiinn--ssoouurrccee vvoollttaaggee vvss ddrraaiinn ccuurrrreenntt TTiimmee Hex-3 size 39 21 Hex-4 size 41 22 Hex-4 size parallel drive 45 23 Hex-1 size 34 20 Hex-2 size 37 21 DDrraaiinn--ssoouurrccee vvoollttaaggee vvss ggaattee--ssoouurrccee vvoollttaaggee aatt ttuurrnn--oonn TTiimmee Hex-3 size 40 21 Hex-4 size 43 22 Hex-4 size parallel drive 46 23 Hex-1 size 35 20 Hex-2 size 38 21 DDrraaiinn--ssoouurrccee vvoollttaaggee vvss ggaattee--ssoouurrccee vvoollttaaggee aatt ttuurrnn--ooffff TTiimmee Hex-3 size 42 22 Hex-4 size 44 22 Hex-4 size parallel drive 47 23 synchronous buck regulator application PARAMETER vs PARAMETER 2 FIGURE PAGE 3.3-V 3-A Synchronous-Rectified Buck Regulator Circuit 48 24 Q1 drain voltage vs gate voltage at turn-on 49 26 Q1 drain voltage vs gate voltage at turn-off 50 26 Q1 drain voltage vs Q2 gate-source voltage TTiimmee 51, 52, 53 26, 27 3 A 54 27 OOuuttppuutt rriippppllee vvoollttaaggee vvss iinndduuccttoorr ccuurrrreenntt 5 A 55 27 www.ti.com 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS RISE TIME FALL TIME vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 22 22 CL = 1 nF CL = 1 nF 20 20 me − ns 18 TA = 125°C me − ns 18 TA = 125°C − Rise Ti 16 TTAA == 7255°°CC − Fall Ti 16 TTAA == 7255°°CC tr 14 tf 14 TA = −25°C TA = −50°C TA = −25°C TA = −50°C 12 12 10 10 5 6 7 8 9 10 11 12 13 14 5 6 7 8 9 10 11 12 13 14 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 4 Figure 5 PROPAGATION DELAY TIME, PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT LOW-TO-HIGH-LEVEL OUTPUT vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 45 45 CL = 1 nF CL = 1 nF 40 40 Propagation Delay Time,t −PHLHigh-To-Low-Level Output − ns 32230505 TA T=A 7 5=T° A−C 5=0 T1°AC25 =° C25°C Propagation Delay Time, t −PLHLow-To-High-Level Output − ns 32230505 TA = 25TT°AAC == −7255°C°CTA=125°C TA = −25°C TA = −50°C 15 15 5 6 7 8 9 10 11 12 13 14 5 6 7 8 9 10 11 12 13 14 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 6 Figure 7 10 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE LOAD CAPACITANCE 16 2.5 VCC = 10 V Duty Cycle = 50% f = 100 kHz 14 CL = 1 nF TA = 25°C Supply Current − mA 11028 1 MHz Supply Current − mA 1.512 I −CC 64 500 kHz 100 kHz I −CC 0.5 75 kHz 40 kHz 2 0 0 4 6 8 10 12 14 0 0.5 1 1.5 2 VCC − Supply Voltage − V CL − Load Capacitance − nF Figure 8 Figure 9 SUPPLY CURRENT INPUT THRESHOLD VOLTAGE vs vs AMBIENT TEMPERATURE SUPPLY VOLTAGE 1.2 9 CL = 1 nF TA = 25°C 1.19 VCC = 10 V 8 Duty Cycle = 50% 1.18 V f = 100 kHz − 7 A e urrent − m 11..1167 old Voltag 65 + Threshold y C 1.15 esh − Threshold pl hr 4 p 1.14 T Su ut p 3 I −CC 11..1132 InV −IT 2 1.11 1 1.1 0 −50 −25 0 25 50 75 100 125 4 6 8 10 12 14 TA − Temperature − °C VCC − Supply Voltage − V Figure 10 Figure 11 www.ti.com 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS REGULATOR OUTPUT VOLTAGE REGULATOR OUTPUT VOLTAGE vs vs REGULATOR INPUT VOLTAGE REGULATOR INPUT VOLTAGE 14 13 RL = 10 kΩ RL = 10 kΩ TA = −55°C 13 12 TA = 25°C TA = −55°C 12 V V 11 e − 11 e − TA = 125°C oltag 10 TA = 25°C TA = 125°C oltag 10 ut V ut V 9 p 9 p ut ut O O 8 or 8 or at at 7 ul 7 ul g g e e R R 6 6 5 5 4 4 4 8 12 16 20 24 28 32 36 40 4 6 8 10 12 14 Regulator Input Voltage − V Regulator Input Voltage − V Figure 12 Figure 13 REGULATOR QUIESCENT CURRENT PEAK SOURCE CURRENT vs vs REGULATOR INPUT VOLTAGE SUPPLY VOLTAGE 50 2.5 45 TA = −55°C fR =L 1=0 00. 5k HΩz Duty Cycle = 5% A µ 40 2 TA = 25°C − TA = 25°C ent 35 − A Curr 30 rent 1.5 cent 25 TA = 125°C e Cur s c e r Qui 20 Sou 1 ator 15 eak ul P g e 10 .5 R RL = 10 kΩ 5 0 0 4 8 12 16 20 24 28 32 36 40 4 6 8 10 12 14 Regulator Input Voltage − V VCC − Supply Voltage − V Figure 14 Figure 15 12 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS PEAK SINK CURRENT vs SUPPLY VOLTAGE 2.5 RL = 0.5 Ω f = 100 kHz Duty Cycle = 5% 2 TA = 25°C A − nt 1.5 e r r u C k n Si 1 k a e P .5 0 4 6 8 10 12 14 VCC − Supply Voltage − V Figure 16 SHOOT-THROUGH CURRENT SHOOT-THROUGH CURRENT vs vs INPUT VOLTAGE, HIGH-TO-LOW INPUT VOLTAGE, LOW-TO-HIGH 6 6 VCC = 10 V VCC = 10 V CL = 0 CL = 0 5 TA = 25°C 5 TA = 25°C A A m m nt − 4 nt − 4 urre urre C C h 3 h 3 g g u u o o hr hr ot-T 2 ot-T 2 o o h h S S 1 1 0 0 10 8 6 4 2 0 0 2 4 6 8 10 VI − Input Voltage, High-to-Low − V VI − Input Voltage, Low-to-High − V Figure 17 Figure 18 www.ti.com 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION The TPS2811, TPS2812 and TPS2813 circuits each contain one regulator and two MOSFET drivers. The regulator can be used to limit VCC to between 10 V and 13 V for a range of input voltages from 14 V to 40 V, while providing up to 20 mA of dc drive. The TPS2814 and TPS2815 both contain two drivers, each of which has two inputs. The TPS2811 has inverting drivers, the TPS2812 has noninverting drivers, and the TPS2813 has one inverting and one noninverting driver. The TPS2814 is a dual 2-input AND driver with one inverting input on each driver, and the TPS2815 is a dual 2-input NAND driver. These MOSFET drivers are capable of supplying up to 2.1 A or sinking up to 1.9 A (see Figures 15 and 16) of instantaneous current to n-channel or p-channel MOSFETs. The TPS2811 family of MOSFET drivers have very fast switching times combined with very short propagation delays. These features enhance the operation of today’s high-frequency circuits. The CMOS input circuit has a positive threshold of approximately 2/3 of V , with a negative threshold of 1/3of V , CC CC and a very high input impedance in the range of 109 Ω. Noise immunity is also very high because of the Schmidt trigger switching. In addition, the design is such that the normal shoot-through current in CMOS (when the input is biased halfway between VCC and ground) is limited to less than 6 mA. The limited shoot-through is evident in the graphs in Figures 17 and 18. The input stage shown in the functional block diagram better illustrates the way the front end works. The circuitry of the device is such that regardless of the rise and/or fall time of the input signal, the output signal will always have a fast transition speed; this basically isolates the waveforms at the input from the output. Therefore, the specified switching times are not affected by the slopes of the input waveforms. The basic driver portion of the circuits operate over a supply voltage range of 4 V to 14 V with a maximum bias current of 5 µA. Each driver consists of a CMOS input and a buffered output with a 2-A instantaneous drive capability. They have propagation delays of less than 30 ns and rise and fall times of less than 20 ns each. Placing a 0.1-µF ceramic capacitor between VCC and ground is recommended; this will supply the instantaneous current needed by the fast switching and high current surges of the driver when it is driving a MOSFET. The output circuit is also shown in the functional block diagram. This driver uses a unique combination of a bipolar transistor in parallel with a MOSFET for the ability to swing from VCC to ground while providing 2 A of instantaneous driver current. This unique parallel combination of bipolar and MOSFET output transistors provides the drive required at VCC and ground to guarantee turn-off of even low-threshold MOSFETs. Typical bipolar-only output devices don’t easily approach VCC or ground. The regulator, included in the TPS2811, TPS2812 and TPS2813, has an input voltage range of 14 V to 40 V. It produces an output voltage of 10 V to 13 V and is capable of supplying from 0 to 20 mA of output current. In grounded source applications, this extends the overall circuit operation to 40 V by clamping the driver supply voltage (V ) to CC a safe level for both the driver and the MOSFET gate. The bias current for full operation is a maximum of 150 µA. A 0.1-µF capacitor connected between the regulator output and ground is required to ensure stability. For transient response, an additional 4.7-µF electrolytic capacitor on the output and a 0.1-µF ceramic capacitor on the input will optimize the performance of this circuit. When the regulator is not in use, it can be left open at both the input and the output, or the input can be shorted to the output and tied to either the VCC or the ground pin of the chip. 14 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION matching and paralleling connections Figures 21 and 22 show the delays for the rise and fall time of each channel. As can be seen on a 5-ns scale, there is very little difference between the two channels at no load. Figures 23 and 24 show the difference between the two channels for a 1-nF load on each output. There is a slight delay on the rising edge, but little or no delay on the falling edge. As an example of extreme overload, Figures 25 and 26 show the difference between the two channels, or two drivers in the package, each driving a 10-nF load. As would be expected, the rise and fall times are significantly slowed down. Figures 28 and 29 show the effect of paralleling the two channels and driving a 1-nF load. A noticeable improvement is evident in the rise and fall times of the output waveforms. Finally, Figures 30 and 31 show the two drivers being paralleled to drive the 10-nF load and as could be expected the waveforms are improved. In summary, the paralleling of the two drivers in a package enhances the capability of the drivers to handle a larger load. Because of manufacturing tolerances, it is not recommended to parallel drivers that are not in the same package. VCC TPS2811 + 0.1 µF 4.7 µF 1 8 Regulator 2 7 Output 50 Ω 3 6 1 nF 4 5 Figure 19. Test Circuit for Measuring Switching Characteristics VCC TPS2811 + 0.1 µF 4.7 µF 1 8 Regulator 2 7 Output 1 50 Ω 3 6 CL(1) 4 5 Output 2 CL(2) NOTE A: Input rise and fall times should be ≤10 ns for accurate measurement of ac parameters. Figure 20. Test Circuit for Measuring Switching Characteristics with the Inputs Connected in Parallel www.ti.com 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION TA = 25°C VO at 1OUT (5 V/div, 5 ns/div) VI = 14 V CL = 0 Paralleled Input VO at 2OUT (5 V/div, 5 ns/div) VO at 1OUT (5 V/div, 5 ns/div) VO at 2OUT (5 V/div, 5 ns/div) TA = 25°C VI = 14 V CL = 0 Paralleled Inputs t − Time t − Time Figure 21. Voltage of 1OUT vs Voltage at Figure 22. Voltage at 1OUT vs Voltage 2OUT, Low-to-High Output Delay at 2OUT, High-to-Low Output Delay VO at 1OUT (5 V/div, 10 ns/div) TA = 25°C VI = 14 V CL = 1 nF on Each Output Paralleled Input VO at 2OUT (5 V/div, 10 ns/div) VO at 1OUT (5 V/div, 10 ns/div) VO at 2OUT (5 V/div, 10 ns/div) TA = 25°C VI = 14 V CL = 1 nF Each Output Paralleled Input t − Time t − Time Figure 23. Voltage at 1OUT vs Voltage at Figure 24. Voltage at 1OUT vs Voltage at 2OUT, Low-to-High Output Delay 2OUT, High-to-Low Output Delay 16 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION VO at 1OUT (5 V/div, 20 ns/div) VO at 2OUT (5 V/div, 20 ns/div) VO at (5 V/div, 20 ns/div) VO at 2OUT (5 V/div, 20 ns/div) TA = 25°C TA = 25°C VCC = 14 V VCC = 14 V CL = 10 nF on Each Output CL = 10 nF on Each Output Paralleled Input Paralleled Input t − Time t − Time Figure 25. Voltage at 1OUT vs Voltage at Figure 26. Voltage at 1OUT vs Voltage at 2OUT, Low-to-High Output Delay 2OUT, High-to-Low Output Delay VCC TPS2811 + 0.1 µF 4.7 µF 1 8 Regulator 2 7 Output 50 Ω 3 6 CL 4 5 NOTE A: Input rise and fall times should be ≤10 ns for accurate measurement of ac parameters. Figure 27. Test Circuit for Measuring Paralleled Switching Characteristics www.ti.com 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION TA = 25°C VCC = 14 V VI (5 V/div, 20 ns/div) CL = 1 nF VI (5 V/div, 20 ns/div) Paralleled Input TA = 25°C and Output VCC = 14 V CL = 1 nF Paralleled Input and Output VO (5 V/div, 20 ns/div) VO (5 V/div, 20 ns/div) t − Time t − Time Figure 28. Input Voltage vs Output Voltage, Figure 29. Input Voltage vs Output Voltage, Low-to-High Propagation Delay of Paralleled High-to-Low Propagation Delay of Paralleled Drivers Drivers TA = 25°C VCC = 14 V CL = 10 nF Paralleled Input VI (5 V/div, 20 ns/div) and Output VI (5 V/div, 20 ns/div) TA = 25°C VCC = 14 V VO (5 V/div, 20 ns/div) CL = 10 nF Paralleled Input and Output VO (5 V/div, 20 ns/div) t − Time t − Time Figure 30. Input Voltage vs Output Voltage, Figure 31. Input Voltage vs Output Voltage, Low-to-High Propagation Delay of Paralleled High-to-Low Propagation Delay of Paralleled Drivers Drivers 18 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION Figures 33 through 47 illustrate the performance of the TPS2811 driving MOSFETs with clamped inductive loads, similar to what is encountered in discontinuous-mode flyback converters. The MOSFETs that were tested range in size from Hex-1 to Hex-4, although the TPS28xx family is only recommended for Hex-3 or below. The test circuit is shown in Figure 32. The layout rules observed in building the test circuit also apply to real applications. Decoupling capacitor C1 is a 0.1-µF ceramic device, connected between VCC and GND of the TPS2811, with short lead lengths. The connection between the driver output and the MOSFET gate, and between GND and the MOSFET source, are as short as possible to minimize inductance. Ideally, GND of the driver is connected directly to the MOSFET source. The tests were conducted with the pulse generator frequency set very low to eliminate the need for heat sinking, and the duty cycle was set to turn off the MOSFET when the drain current reached 50% of its rated value. The input voltage was adjusted to clamp the drain voltage at 80% of its rating. As shown, the driver is capable of driving each of the Hex-1 through Hex-3 MOSFETs to switch in 20 ns or less. Even the Hex-4 is turned on in less than 20 ns. Figures 45, 46 and 47 show that paralleling the two drivers in a package enhances the gate waveforms and improves the switching speed of the MOSFET. Generally, one driver is capable of driving up to a Hex-4 size. The TPS2811 family is even capable of driving large MOSFETs that have a low gate charge. VI CR1 L1 Current Loop 1 8 Regulator Q1 + VDS 2 7 VDS − 3 6 VGS R1 50 Ω 4 5 VCC + C1 C2 0.1 µF 4.7 µF Figure 32. TPS2811 Driving Hex-1 through Hex-4 Devices www.ti.com 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION TA = 25°C VDS (20 V/div, 0.5 µs/div) TA = 25°C VCC = 14 V VCC = 14 V VI = 48 V VI = 48 V VDS (20 V/div, 50 ns/div) VGS (5 V/div, 50 ns/div) ID (0.5 A/div, 0.5 µs/div) t − Time t − Time Figure 33. Drain-Source Voltage vs Drain Figure 34. Drain-Source Voltage vs Current, TPS2811 Driving an IRFD014 Gate-Source Voltage, at Turn-on, (Hex-1 Size) TPS2811 Driving an IRFD014 (Hex-1 Size) TA = 25°C VCC = 14 V VDS (20 V/div, 50 ns/div) VI = 48 V VDS (50 V/div, 0.2 µs/div) TA = 25°C VCC = 14 V VI = 80 V VGS (5 V/div, 50 ns/div) VGS (0.5 A/div, 0.2 µs/div) t − Time t − Time Figure 35. Drain-Source Voltage vs Figure 36. Drain-Source Voltage vs Drain Gate-Source Voltage, at Turn-off, Current, TPS2811 Driving an IRFD120 TPS2811 Driving an IRFD014 (Hex-1 Size) (Hex-2 Size) 20 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION TA = 25°C TA = 25°C VCC = 14 V VCC = 14 V VDS (50 V/div, 50 ns/div) VI = 80 V VI = 80 V VDS (50 V/div, 50 ns/div) VGS (5 V/div, 50 ns/div) VGS (5 V/div, 50 ns/div) t − Time t − Time Figure 37. Drain-Source Voltage vs Figure 38. Drain-Source Voltage vs Gate-Source Voltage, Gate-Source Voltage, at Turn-on, TPS2811 Driving an IRFD120 at Turn-off, TPS2811 Driving an IRFD120 (Hex-2 Size) (Hex-2 Size) TA = 25°C VCC = 14 V VI = 80 V VDS (50 V/div, 50 ns/div) VDS (50 V/div, 2 µs/div) TA = 25°C VCC = 14 V VI = 80 V VGS (5 A/div, 50 ns/div) ID (5 A/div, 2 µs/div) t − Time t − Time Figure 39. Drain-Source Voltage vs Drain Figure 40. Drain-Source Voltage vs Current, TPS2811 Driving an IRF530 Gate-Source Voltage, at Turn-on, TPS2811 (Hex-3 Size) Driving an IRF530 (Hex-3 Size) www.ti.com 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION VDS (50 V/div, 0.2 µs/div) VDS (50 V/div, 50 ns/div) TA = 25°C VCC = 14 V VI = 350 V TA = 25°C VCC = 14 V VI = 80 V ID (2 A/div, 0.2 µs/div) VGS (5 V/div, 50 ns/div) t − Time t − Time Figure 41. Drain-Source Voltage vs Drain Figure 42. Drain-Source Voltage vs Current, Gate-Source Voltage, One Driver, TPS2811 Driving an IRF840 at Turn-off, TPS2811 Driving an IRF530 (Hex-4 Size) (Hex-3 Size) VDS (50 V/div, 50 ns/div) VDS (50 V/div, 50 ns/div) VGS (5 V/div, 50 ns/div) VGS (5 V/div, 50 ns/div) TA = 25°C TA = 25°C VCC = 14 V VCC = 14 V VI = 350 V VI = 350 V t − Time t − Time Figure 43. Drain-Source Voltage vs Figure 44. Drain-Source Voltage vs Gate-Source Gate-Source Voltage, at Turn-on, Voltage, at Turn-off, One Driver, One Driver, TPS2811 Driving an IRF840 TPS2811 Driving an IRF840 (Hex-4 Size) (Hex-4 Size) 22 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION VDS (50 V/div, 0.2 µs/div) VDS (50 V/div, 50 ns/div) TA = 25°C VCC = 14 V VI = 350 V ID (2 A/div, VGS (5 V/div, 0.2 µs/div) 50 ns/div) TA = 25°C VCC = 14 V VI = 350 V t − Time t − Time Figure 45. Drain-Source Voltage vs Drain Figure 46. Drain-Source Voltage vs Gate-Source Current, Parallel Drivers, Voltage, at Turn-on, Parallel Drivers, TPS2811 Driving an IRF840 (Hex-4 Size) TPS2811 Driving an IRF840 (Hex-4 Size) VDS (50 V/div, 50 ns/div) VGS (5 V/div, 50 ns/div) TA = 25°C VCC = 14 V VI = 350 V t − Time Figure 47. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off, Parallel Drivers, TPS2811 Driving an IRF840 (Hex-4 Size) www.ti.com 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION synchronous buck regulator Figure 48 is the schematic for a 100-kHz synchronous-rectified buck converter implemented with a TL5001 pulse-width-modulation (PWM) controller and a TPS2812 driver. The bill of materials is provided in Table 1. The converter operates over an input range from 5.5 V to 12 V and has a 3.3-V output capable of supplying 3 A continuously and 5 A during load surges. The converter achieves an efficiency of 90.6% at 3 A and 87.6% at 5 A. Figures 49 and 50 show the power switch switching performance. The output ripple voltage waveforms are documented in Figures 54 and 55. The TPS2812 drives both the power switch, Q2, and the synchronous rectifier, Q1. Large shoot-through currents, caused by power switch and synchronous rectifier remaining on simultaneously during the transitions, are prevented by small delays built into the drive signals, using CR2, CR3, R11, R12, and the input capacitance of the TPS2812. These delays allow the power switch to turn off before the synchronous rectifier turns on and vice versa. Figure 51 shows the delay between the drain of Q2 and the gate of Q1; expanded views are provided in Figures 52 and 53. Q1 IRF7406 L1 27 µF 3 1 J1 J2 VVII 12 10C1016 µ0 VF0 +10106 Cµ VF5 +0.47C µ1F1 10 RkΩ5 2 1 CR1 + C110610 2V µF + C110670 V µF C11001 3µVF 12 33..33 VV GND 3 30BQ015 3 GND GND 4 4 GND 2 R7 1 8 3.3 Ω REG_IN REG_OUT 2 7 1 IN U2 1 OUT 34 GND TPS2812D VCC 65 3IRFQ72201 1000 CpF6 2.32 RkΩ4 180R Ω3 2 IN 2 OUT R13 1% 0.1C µ1F4 10 k1ΩR5 6Ω 0.00Cµ2F32 1.R6 2kΩ C0.4022 µF C2 0.033 µF R10 1 2 3 4 CR2 1 kΩ OUT VCC COMP FB BAS16ZX R1 C15 U1 1.00 kΩ R11 1 µF GND RT TL5001CDDTC SCP 1% CR3 30 kΩ 8 7 6 5 BAS16ZX R9 R8 + 90.9 kΩ 121 kΩ C1 R12 1% 1% C9 1 µF 10 kΩ 0.22 µF Figure 48. 3.3-V 3-A Synchronous-Rectified Buck Regulator Circuit NOTE: If the parasitics of the external circuit cause the voltage to violate the Absolute Maximum Rating for the Output pins, Schottky diodes should be added from ground to output and from output to Vcc. 24 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION Table 1. Bill of Materials, 3.3-V, 3-A Synchronous-Rectified Buck Converter REFERENCE DESCRIPTION VENDOR U1 TL5001CD, PWM Texas Instruments, 972-644-5580 U2 TPS2812D, N.I. MOSFET Driver Texas Instruments, 972-644-5580 CR1 3 A, 15 V, Schottky, 30BQ015 International Rectifier, 310-322-3331 CR2,CR3 Signal Diode, BAS16ZX Zetex, 516-543-7100 C1 1 µF, 16 V, Tantalum C2 0.033 µF, 50 V C3 0.0022 µF, 50 V C4 0.022 µF, 50 V C5,C7,C10,C12 100 µF, 16 V, Tantalum, TPSE107M016R0100 AVX, 800-448-9411 C6 1000 pF, 50 V C9 0.22 µF, 50 V C11 0.47 µF, 50 V, Z5U C13 10 µF, 10 V, Ceramic, CC1210CY5V106Z TDK, 708-803-6100 C14 0.1 µF, 50 V C15 1.0 µF, 50 V J1,J2 4-Pin Header L1 27 µH, 3 A/5 A, SML5040 Nova Magnetics, Inc., 972-272-8287 Q1 IRF7406, P-FET International Rectifier, 310-322-3331 Q2 IRF7201, N-FET International Rectifier, 310-322-3331 R1 1.00 kΩ, 1% R2 1.6 kΩ R3 180 Ω R4 2.32 kΩ, 1 % R5,R12,R13 10 kΩ R6 15 Ω R7 3.3 Ω R8 121 kΩ, 1% R9 90.9 kΩ, 1% R10 1 kΩ R11 30 kΩ NOTES: 2. Unless otherwise specified, capacitors are X7R ceramics. 3. Unless otherwise specified, resistors are 5%, 1/10 W. www.ti.com 25

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION VD (5 V/div, 20 ns/div) VG (2 V/div, 20 ns/div) VD (5 V/div, 20 ns/div) TVAI = = 1 225 V°C VG (2 V/div, 20 ns/div) TA = 25°C VO = 3.3 V at 5A VI = 12 V VO = 3.3 V at 5A t − Time t − Time Figure 49. Q1 Drain Voltage vs Gate Voltage, Figure 50. Q1 Drain Voltage vs Gate Voltage, at Switch Turn-on at Switch Turn-off TA = 25°C VI = 12 V VD (5 V/div, 0.5 µs/div) VO = 3.3 V at 5A TA = 25°C VI = 12 V VO = 3.3 V at 5A VD (5 V/div, 20 ns/div) VGS (2 V/div, 0.5 µs/div) VGS (2 V/div, 20 ns/div) t − Time t − Time Figure 51. Q1 Drain Voltage vs Q2 Figure 52. Q1 Drain Voltage vs Q2 Gate-Source Voltage Gate-Source Voltage 26 www.ti.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:6)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:9)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:15)(cid:18)(cid:3)(cid:2)(cid:19)(cid:19)(cid:11) (cid:20)(cid:21)(cid:3)(cid:22)(cid:19)(cid:1) (cid:11)(cid:23)(cid:16)(cid:24)(cid:19)(cid:23)(cid:3) SLVS132F − NOVEMBER 1995 − REVISED OCTOBER 2004 APPLICATION INFORMATION TA = 25°C VD (5 V/div, 20 ns/div) VI = 12 V VO = 3.3 V at 5A VGS (2 V/div, 20 ns/div) t − Time Figure 53. Q1 Drain Voltage vs Q2 Gate-Source Voltage TA = 25°C Inductor Current (2 A/div, 2 µs/div) VI = 12 V VO = 3.3 V at 3A Inductor Current (1 A/div, 2 µs/div) TA = 25°C VI = 12 V VO = 3.3 V at 5 A 1 1 Output Ripple Voltage (20 mV/div, 2 µs/div) 2 2 Output Ripple Voltage (20 mV/div, 2 µs/div) t − Time t − Time Figure 54. Output Ripple Voltage vs Figure 55. Output Ripple Voltage vs Inductor Current, at 3 A Inductor Current, at 5 A www.ti.com 27

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS2811D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2811 & no Sb/Br) TPS2811DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2811 & no Sb/Br) TPS2811P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TPS2811P & no Sb/Br) TPS2811PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM PS2811 & no Sb/Br) TPS2811PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM PS2811 & no Sb/Br) TPS2812D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2812 & no Sb/Br) TPS2812DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 2812 & no Sb/Br) TPS2812DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 2812 & no Sb/Br) TPS2812P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TPS2812P & no Sb/Br) TPS2812PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM PS2812 & no Sb/Br) TPS2813D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2813 & no Sb/Br) TPS2813DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2813 & no Sb/Br) TPS2813P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 125 TPS2813P & no Sb/Br) TPS2813PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 PS2813 & no Sb/Br) TPS2814D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2814 & no Sb/Br) TPS2814DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2814 & no Sb/Br) TPS2814DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2814 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS2814P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TPS2814P & no Sb/Br) TPS2814PE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TPS2814P & no Sb/Br) TPS2814PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM PS2814 & no Sb/Br) TPS2814PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 PS2814 & no Sb/Br) TPS2815D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2815 & no Sb/Br) TPS2815DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2815 & no Sb/Br) TPS2815DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 2815 & no Sb/Br) TPS2815P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TPS2815P & no Sb/Br) TPS2815PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM PS2815 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS2811 : •Automotive: TPS2811-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS2811DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2811PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TPS2812DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2812DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2812PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TPS2813DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2813PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TPS2814DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2814DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2814PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TPS2815DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2815PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS2811DR SOIC D 8 2500 340.5 338.1 20.6 TPS2811PWR TSSOP PW 8 2000 367.0 367.0 35.0 TPS2812DR SOIC D 8 2500 340.5 338.1 20.6 TPS2812DR SOIC D 8 2500 367.0 367.0 35.0 TPS2812PWR TSSOP PW 8 2000 367.0 367.0 35.0 TPS2813DR SOIC D 8 2500 340.5 338.1 20.6 TPS2813PWR TSSOP PW 8 2000 367.0 367.0 35.0 TPS2814DR SOIC D 8 2500 340.5 338.1 20.6 TPS2814DR SOIC D 8 2500 367.0 367.0 35.0 TPS2814PWR TSSOP PW 8 2000 367.0 367.0 35.0 TPS2815DR SOIC D 8 2500 340.5 338.1 20.6 TPS2815PWR TSSOP PW 8 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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