TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Positive Voltage Intelligent Protection Device 2 Hotswap Controller and I C Current Monitor CheckforSamples:TPS2480,TPS2481 FEATURES DESCRIPTION 1 • ProgrammableFETPowerLimit TheTPS2480/81aredesignedtominimizeinrushinto • ExternalN-ChannelFETGateDrive applications and protect both the load and the FET from over-current or short circuit events. They control • ProgrammableFaultTimer an external N-channel MOSFET switch and provide • OpenDrainPowerGoodOutput accuratevoltage,current,andpowermonitoringusing • I2CmonitoringofCurrent,VoltageandPower a configurable 12 bit A/D converter via an I2C interface. The independently adjustable power limit • HighAccuracyCurrentMonitoring and current limit ensure that the external MOSFET (1%overtemperature) operates within the FET's Safe Operating Area • DynamicCalibration (SOA). • 9-Vto26-VInputRange The flexible design includes a Power Good output which can be used for sequencing as well as load APPLICATIONS fault indication. An external timer capacitor can set • Servers the fault time to help immunize the system from • HardDrives nuisanceshutdownsduringbrieftransientevents. • StorageNetworks The monitoring circuitry incorporates a high accuracy • BaseStations A/D converter which can be configured from a 9 to 13 bit converter. The internal gain of the A/D can be configured to scale the current, voltage and power readingstotheneedsoftheapplication.Anadditional multiplying register calculates power in Watts. The I2C interface uses multi-level addressing to allow up to16programmableaddresses. SimplifiedApplicationDiagram 9Vto26V 2mW 0.01mF 3.3Vto5V 0.01mF 10kW 10kW 4 17 15 14 18 13 12 10kW VS VINP VCCSENSEVINM GATEVOUT 2 SCL PG 11 1 SDA TPS2480/1 6 EN 7 VREF PROG GND GND A0 A1 TIMER 190kW 8 10 16 20 19 9 0.01mF 33kW 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com DESCRIPTION (CONT.) The TPS2480 and TPS2481 monitors shunts on buses that can vary from 9 V to 26 V and with a few external componentsitispossibletomonitorbusesashighas80V. Themonitoringcircuitryusesasingle3-Vto5.5-Vsupply,drawingamaximumof1mAofsupplycurrent. DEVICEINFORMATION (1) JUNCTION DEVICE PACKAGE FUNCTION MARKING TEMPERATURE TPS2480 -40°Cto125°C PW20 LatchOff TPS2480 TPS2481 -40°Cto125°C PW20 AutoRetry TPS2481 (1) ForpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocumentorseetheTIWebsiteat www.ti.com. DISSIPATION RATINGS(1) (2) (3) PACKAGE q HIGHK,°C/W q (AirFlow)HIGH-k (4),°C/W JA JA TPS2480 88.3 74.5 TPS2481 88.3 74.5 (1) TestedperJEDECJESD51,naturalconvection.Thedefinitionsofhigh-kandlow-kareperJESD51-7andJESD51-3. (2) Low-k(2signal-noplane,3in.by3in.board,0.062in.thick,1oz.copper)testboardwiththepadsoldered,andanadditional0.12 in.2oftop-sidecopperaddedtothepad. (3) High-kisa(2signal–2plane)testboardwiththepadsoldered. (4) ThebestcasethermalresistanceisobtainedusingtherecommendationsperSLMA002A(2signal-2planewiththepadconnectedto theplane). RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT VCC Inputvoltagerange 9 80 V PROG Inputvoltagerange 0.4 4 V Sourcingcurrent 0 1 mA REF V Inputvoltagerange 3 5.5 S V V ,V Inputvoltagerange (1) 0 24 INP INM T Operatingfreeairtemperature -40 85 stg °C T Operatingjunctiontemperature -40 125 J (1) Hotswapcircuitsmayexperiencevoltagesurgesduringeventssuchashotplugandoutputshorts.ThemaximumRecommended OperatingVoltageisderatedbelowtheAbsoluteMaximumtoallowfortoleranceofprotectiondevices(clamps).Iftheapplicationdoes nothaveinputsurges,theTPS2480maybeuseduptoitsAbsoluteMaximumRatingwithnodegradationofperformanceorreliability. 2 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 ABSOLUTE MAXIMUM RATINGS(1) (2) (3) overoperatingfree-airtemperaturerange(unlessotherwisenoted) UNIT Inputvoltagerange,VCC,Sense,Enable,OUT -0.3to100 Supplyvoltage,V GND-0.3to6 S Inputvoltage,commonmode,VINP,VINM GND-0.3to+26 Inputvoltage,differential,VINP,VINM -26to+26 V Inputvoltagerange,PROG -0.3to6 Outputvoltagerange,GATE,PG -0.3to100 Outputvoltagerange,TIMER,VREF -0.3to6 Sinkcurrent,PG 10 Sourcecurrent,VREF 0to2 mA Sinkcurrent,PROG 2 SDA GND-0.3to+6.0 V SCL GND-0.3toVS+0.3 CurrentintoSDA,SCL,VS,VINP,VINM,A0,A1,GNDB 5 mA Opendraindigitaloutputcurrent 10 ESDrating,HBM 2k V ESDrating,CDM 500 Operatingjunctiontemperaturerange,T -40to+125 J °C Storagetemperaturerange,T -40to150 stg (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperating conditions”isnotimplied.Exposuretoabsolute–maximum–ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttoGNDunlessotherwisestated. (3) Donotapplyvoltagetothesepins. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SupplyCurrent(VCC) Enabled V =HiV =V =V 450 1000 EN SENSE OUT VCC I mA VCC Disabled V =LoV =V =V =0 90 250 EN SENSE VCC OUT Quiescentcurrent operating 0.7 1.0 mA I VS Quiescentcurrent Powerdownmode 6 15 mA V PowerOnresetthreshold 2 V POR CurrentSenseInput(SENSE) I Inputbiascurrent V =V V =V 7.5 20 mA SENSE SENSE VCC OUT VCC ReferenceVoltageOutput(VREF) V Referencevoltage 0<I <1mA 3.9 4 4.1 V REF VREF PowerLimitingInput(PROG) Inputbiascurrent;device I 0<V <4VV =48V 5 mA PROG enabled;sourcingorsinking PROG EN Pulldownresistance;device R I =200mA;V =0V 375 600 Ω PROG disabled PROG EN PowerLimitingandCurrentLimiting(SENSE) Currentsensethreshold V =2.4V;V =0VorV =0.9V;V V V(VCC-SENSE)withpower PROG OUT PROG OUT 17 25 33 CL =30V;V =48V limitingtrip VCC mV Currentsensethreshold V V(VCC-sense)withoutpower V =4V;V =V 45 50 55 SENSE PROG SENSE OUT limitingtrip V =4V;V =V ;V :0 Largeoverloadresponsetime PROG OUT SENSE (VCC-SENSE) t risingto200mV;C =2nF;V = 1.2 ms F_TRIP toGATElow (GATE-OUT) (GATE-OUT) 1V TimerOperation(TIMER) V =0V 15.0 25.0 34.0 TIMER I Chargecurrent(sourcing) SOURCE V =0V;T =25°C 20.0 25.0 30.0 TIMER J mA V =5V 1.50 2.5 3.70 TIMER I Dischargecurrent(sinking) SINK V =5V;T =25°C 2.10 2.5 3.10 TIMER J TIMERupperthreshold 3.9 4.0 4.1 voltage V TIMERlowerresetthreshold TPS2481only 0.96 1.0 1.04 voltage D Faultretrydutycycle TPS2481only 0.5% 0.75% 1.0% RETRY GateDriveOutput(GATE) I GATEsourcingcurrent V =VVCC;V(GATE-OUT)=7V;VEN=Hi 15 22 35 mA GATE SENSE V =Lo;V =V 1.8 2.4 2.8 EN GATE VCC GATEsinkingcurrent mA V =Hi;V =V ;V ³200mV 75 125 250 EN GATE VCC (VCC-SENSE) V GATEoutputvoltage 12 16 V GATE-OUT Propagationdelay:ENgoing V =0→2.5V,50%ofV to50%ofV , t EN EN GATE 25 40 D_ON truetoGATEoutputhigh V =V ,R =1MOhm OUT VCC (GATE-OUT) Propagationdelay:ENgoing V =2.5V→0V,50%ofV to50%ofV , t false(0V)toGATEoutput EN EN GATE 0.5 1 ms D_OFF V =V ,R =1MΩ,t <0.1ms low OUT VCC (GATE-OUT) FALL Propagationdelay:TIMER V :0→5V,t <0.1ms.50%ofV to TIMER RISE TIMER 0.8 1 expirestoGATEoutputlow 50%ofV ,V =V ,R =1MΩ, GATE OUT CC (GATE-OUT) 4 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT PowerGoodOutput(PG) I =2mA 0.1 0.25 PG V Lowvoltage(sinking) PG_L I =4mA 0.25 0.5 PG PGthresholdvoltage;VOUT V V =V ;measureV 0.8 1.25 1.7 PGTL rising;PGgoesopendrain SENSE VCC (VCC-OUT) V PGthresholdvoltage;VOUT V V =V ;measureV 2.2 2.7 3.2 PGTH falling;PGgoeslow SENSE VCC (VCC-OUT) PGthresholdhysteresis V V =V 1.4 HYST_PG voltage;V(SENSE-OUT) SENSE VCC PGdeglitchdelay;detection t tooutput;risingandfalling V =V 5 9 15 ms DPG SENSE VCC edges Leakagecurrent;PGfalse; opendrain 10 mA OutputVoltageFeedbackInput(OUT) V =V ,V =Hi;sinking 8 20 OUT VCC EN I Biascurrent mA OUT V =GND;V =Lo;sourcing 18 40 OUT EN EnableInput(EN) V ThresholdVENgoinghigh 1.32 1.35 1.38 EN_H V V ThresholdVENgoinglow 1.20 1.25 1.30 EN_L VENhysteresis 100 mV Leakagecurrent V =30V 1 mA EN InputSupplyUVLO(VCC) V turnon Rising 8.4 8.8 VCC V V turnoff Falling 7.2 8.3 VCC Hysteresis 75 mV DigitalInputs(SDAininputmode,SCL,A0,A1) C Inputcapacitance 3 pF IN I Inputleakagecurrent 0<V <V 0.1 1 mA LEAKAGE IN S V LogicHiinputlevel 0.7(V ) 6 INHI S V Logiclowinputlevel -0.3 0.3(V ) V INLO S V Hysteresis 0.5 HYS OpenDrainDigitalOutput(SDA) V SDALowOutput Sinking5mA 0.15 0.4 V LO I Highlevelleakagecurrent V =V 0.1 1.0 mA LEAKAGE OUT S Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Input PGA=x1 0 ±40 Full-scalecurrentsense PGA=x2 0 ±80 mV (input)voltagerange PGA=x4 0 ±160 PGA=x8 0 ±320 Busvoltage(inputvoltage) BRNG=1 0 32 V range BRNG=0 0 16 Common-moderejection VIN+=0Vto26V 100 120 dB CMRR PGA=x1 ±10 ±100 PGA=x2 ±20 ±125 Inputoffset mV PGA=x4 ±30 ±150 V OS PGA=x8 ±40 ±200 Tempstability 0.1 mV/°C PSRR VS=3Vto5.5V 10 mV/V CSAgainerror ±0.04% Gain CSA Tempstability 10 ppm I 20 mA VNP Inputbiascurrent Activemode I 20||320 mA||kΩ VINM I I ,I Powerdownmode,leakageinputcurrent 0.1 ±0.5 mA LEAKAGE VNP VINM A/DConverter Shuntvoltage 10 mV StepSize 1LSB Busvoltage 4 mV Current Currentmeasurement Error ±0.2% ±0.5% Accuracy Tempdrift Overfullrange ±1.0% Voltage Busvoltagemeasurement Error ±0.2% ±0.5% Accuracy Tempdrift(-25°Cto85°C) Overfullrange ±1.0% 12Bit 532 586 11Bit 276 304 T Conversiontime CONV 10Bit 148 163 ms 9Bit 84 92 T Conversiontime MinimumA/Dconversiontime 4 LOWCONV 6 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 DEVICE INFORMATION FunctionalBlockDiagram VINM VS 18 4 1 SDA X PowerRegister 2 SCL I2C CurrentRegister VINP 17 Interface 20 A0 PGA ADC VoltageRegister GND 16 19 A1 4V 15 7 VREF VCC Reference Constant Charge Enable Power Engine Pump 22m A PROG 8 A GateControl V(DS)Detector 2AB 50mVmax + Amplifier 13 GATE S B 14V 12 OUT I(D)Detector S Inrushcomplete 11 PG SENSE 14 + 9-ms 2mA 2.7V/ Deglitch 1.25V + 8.4V/ 8.3V UVLO 25m A Enable 6 + EN 1.35V/ Fault Logic 1.25V Enable + 4V/1V GND 10 POR 2.5m A Forautoretryoption withdutycycleof75% 9 TIMER Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com RegisterBlockDiagram (1) Power (1) Bus Voltage ´ (1) Current Shunt Voltage Channel ADC Bus Voltage Channel (2) Full-Scale Calibration ´ (1) Shunt Voltage PGA (In Configuration Register) NOTES: (1) Read-only Data Registers (2) Read/write 8 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 20-PinTSSOP SDA 1 20 A0 SDL 2 19 A1 NC 3 18 VINM VS 4 TPS2480/81 17 VINP NC 5 16 GND EN 6 15 VCC VREF 7 14 SENSE PROG 8 13 GATE TIMER 9 12 OUT GND 10 11 PG Table1. TERMINALFUNCTIONS FUNCTION TPS2480/81 DESCRIPTION SDA 1 I2CDataLine SCL 2 I2CClock NC 3 TietoGNDorfloat VS 4 PowerinputtotheI2Cblock,3.3Vto5V NC 5 Noconnection,tietoGNDorfloat EN 6 Deviceenable VREF 7 Referencevoltageoutput,usedtosetpowerthresholdonPROGpin PROG 8 Power-limitsettinginput TIMER 9 Faulttimingcapacitor GND 10 GND PG 11 Powergoodreportingoutput,open-drain OUT 12 Outputvoltagefeedback GATE 13 Gateoutput SENSE 14 Current-limitsenseinput VCC 15 MainpowersupplyinputtodeviceandFET GND 16 GND VINP 17 Positivedifferentialshuntvoltage.Connecttopositivesideofshuntresistor Negativedifferentialshuntvoltage.Connecttonegativesideofshuntresistor.Busvoltageis VINM 18 measuredfromthispintoGND A1 19 Addresspin.Table2showspinsettingsandcorrespondingaddresses. A0 20 Addresspin.Table2showspinsettingsandcorrespondingaddresses. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Pin Description A0, A1: Address pins for setting the TPS2480 I2C address. These bits can be tied to one of four pins ( GND, SDA,SCL,VS)whichgivesatotalof16differentaddressasshowninTable2. EN:TheGATEdriverisenabledifthepositivethresholdisexceededandtheinternalPORandUVLOthresholds have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by R1/R2 in the Functional Block Diagram, or it can be tied to VCC to always enable the TPS2480/81. The hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition and shutting the downstream circuits off. A TPS2480 that has latched off can be reset by cycling EN below its negativethresholdandbackhigh. GATE: Provides the high side (above VCC) gate drive for the external FET. It is controlled by the internal gate drive amplifier, which provides a pull-up of 22 mA from an internal charge pump and a strong pull-down to ground of75mA(min).Thepull-downcurrentisanon-linearfunctionoftheamplifieroverdrive;itprovidessmalldrivefor small overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut the external FET off when EN or UVLO causes this to happen. An internal clamp protects the gate of the external FET (to OUT) and generally eliminates the need for an external clamp in almost all cases for devices with 20-V V ratings; an external Zener may be required to protect the gate of devices with V < 16 V. GS(max) GS(max) A small series resistance of 10 Ω should be inserted in the gate lead if the C of the external FET > 200 pF, ISS otherwise use 33 Ω for small MOSFETs. A capacitor can be connected from GATE to ground to create a slower inrushwithaconstantcurrentprofilewithoutaffectingtheamplifierstability.Addaseriesresistorofabout1kΩ to thegatecapacitortomaintainthegateclampingandcurrentlimitresponsetime. GND:Thispinisconnectedtosystemground. OUT:ThisinputpinisusedbytheconstantpowerengineandthePGcomparatortomeasureV oftheexternal DS FET as V . Internal protection circuits leak a small current from this pin when it is low. If the load circuit (SENSE-OUT) candriveOUTbelowground,connectaclamp(orfreewheel)diodefromOUT(cathode)toGND(anode). PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG goes open-drain (high voltage with a pull-up) after V of the external FET has fallen to about 1.25 V and a 9-ms DS deglitch time period has elapsed. PG is false (low or low resistance to ground) whenever EN is false, V of the DS external FET is above 2.7 V, or UVLO is active. PG can also be viewed as having an input and output voltage monitor function. The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a momentary overload or input voltage step. V voltage can be greater than V because its ESD PG VCC protectionisonlywithrespecttoground. PROG: The voltage applied to this pin (0.4 V to 4.0 V) programs the power limit used by the constant power engine. Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to thefollowingequation: P V = LIM PROG (10´I ) LIM (1) where P is the desired power limit of the external FET and I is the current limit setpoint (see SENSE). P LIM LIM LIM isdeterminedbythedesiredthermalstressontheexternalFET: T -T P < J(max) S(max) LIM R qJC(max) (2) where T is the maximum desired transient junction temperature of the external FET and T is the J(max) S(max) maximumcasetemperaturepriortoastartorrestart. V is used in conjunction with V to compute the (scaled) current, I , by the constant power engine. PROG DS D_ALLOWED I is compared by the gate amplifier to the actual I , and used to generate a gate drive. If I < D_ALLOWED D D I , the amplifier turns the gate of the external FET full on because there is no overload condition; D_ALLOWED otherwise GATE is regulated to maintain the I = I relationship. A capacitor may be tied from PROG to D D_ALLOWED 10 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp. PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2480 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROGshouldbetiedtoVREFthrougha47-kΩ resistor. SCL:ThispinistheclockinputfortheI2Cinterface. SDA:ThispinisthedatainputfortheI2Cinterface. SENSE: Monitors the voltage at the drain of the external FET, and the downstream side of R providing the S constant power limit engine with feedback of both the external FET current (I ) and voltage (V ). Voltage is D DS determined by the difference between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses V to compute the allowed I and is clamped to 50 mV, acting DS D likeatraditionalcurrentlimitatlowV .Themaximumcurrentlimitissetbythefollowingequation: DS 50mV I = LIM R S (3) Design the connections to SENSE to minimize R voltage sensing errors. Don't drive SENSE to a large voltage S difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by connectingSENSEtoVCC. TIMER: An integrating capacitor, C , connected to the TIMER pin provides a timing function that controls the T fault-time for both versions and the restart interval for the TPS2481. The timer charges at 25 mA whenever the TPS2480/81isinpowerlimitorcurrentlimitanddischargesat2.5mAotherwise.Thecharge-to-dischargecurrent ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the TPS2480 pulls GATE to ground, latches off, and discharges C . The TPS2491 pulls GATE to T ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging C down to 1 V T followed by 15 more charge and discharge cycles. The TPS2480 can be reset by either cycling the EN pin or the UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin shouldbetiedtogroundifthisfeatureisnotused.ThegeneralequationforfaultretrytimeasafunctionofC is: T T =C ´1347´106 F T (4) VCC:Thispinisassociatedwiththreefunctions: 1. biasingpowertotheintegratedcircuit, 2. inputtopoweronreset(POR)andundervoltagelockout(UVLO)functions,and 3. voltagesenseatoneterminalofR fortheexternalFETcurrentmeasurement. S The voltage must exceed the POR (about 6 V for roughly 400 ms) and the internal UVLO (about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize R voltage S sensing errors and to maximize the effect of C1 and D1; place C1 at R rather than at the device pin to eliminate S transientsensingerrors.GATE,PROG,PG,andTIMERareheldlowwheneitherUVLOorPORareactive. VINM: This pin is Kelvin connected to the negative (load) side of the current sensing resistor. It will appear to externalcircuitryasa20-mAsinkinparallelwitha320-kΩ resistortoGND. VINP:ThispinisKelvinconnectedtothepositive(source)sideofthecurrentsensingresistor.Itwilltypicallysink ~20mA. VS:PowersourceforthelogicandI2Cinterface.Typicallybetween3Vand5V. VREF: Provides a 4.0-V reference voltage for use in conjunction with the resistor divider of a typical application circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholdshavebeenmet.Itisnotdesignedasasupplyvoltageforothercircuitry,thereforeensurethatnomore than1mAisdrawn.Althoughnottypicallyrequired,upto1000pFcanbeplacedonthispin. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com TYPICAL CHARACTERISTICS A/DFREQUENCYRESPONSE ADCSHUNTOFFSETvsTEMPERATURE 2.0 100 V = 5V S+ 80 1.5 320mV Range 60 160mV Range mA) 1.0 40 ut Currents ( 0.50 VVSS++== 33VV mOffset (V) -22000 80mV Range 40mV Range p n -0.5 -40 I -60 -1.0 V =5V -80 S+ -1.5 -100 0 5 10 15 20 25 30 -40 -25 0 25 50 75 100 125 V Voltage (V) Temperature (°C) IN- Figure1. Figure2. ADCSHUNTGAINERRORvsTEMPERATURE ADCBUSVOLTAGEOFFSETvsTEMPERATURE 100 50 80 45 60 40 %) 40 35 Error (m 200 320mV Range 160mV Range set (mV) 3205 Gain -20 Off 20 32V Range 16V Range -40 15 80mV Range 40mV Range -60 10 -80 5 -100 0 -40 -25 0 25 50 75 100 125 -40 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure3. Figure4. ADCBUSGAINERRORvsTEMPERATURE INTEGRALNONLINEARITYvsINPUTVOLTAGE 100 20 80 15 60 10 %) 40 16V Gain Error (m -22000 32V mINL (V) -505 -40 -10 -60 -15 -80 -100 -20 -40 -25 0 25 50 75 100 125 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 Temperature (°C) Input Voltage (V) Figure5. Figure6. 12 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 TYPICAL CHARACTERISTICS (continued) INPUTCURRENTSWITHLARGEDIFFERENTIAL VOLTAGES (V at12V,SweepofV ) ACTIVEI vsTEMPERATURE IN+ IN– Q 0 1.2 -10 1.0 -20 V = 5V -30 S 0.8 dB) -40 A) ain ( -50 (mQ 0.6 G -60 I V = 3V S 0.4 -70 -80 0.2 -90 -100 0 10 100 1k 10k 100k 1M -40 -25 0 25 50 75 100 125 Input Frequency (Hz) Temperature (°C) Figure7. Figure8. SHUTDOWNI vsTEMPERATURE ACTIVEI vsI2CCLOCKFREQUENCY Q Q 16 1.0 0.9 14 V = 5V 0.8 S 12 0.7 10 0.6 mI(A)Q 8 VS= 5V I(mA)Q 00..54 VS=3V 6 VS= 3V 0.3 4 0.2 2 0.1 0 0 -40 -25 0 25 50 75 100 125 1k 10k 100k 1M 10M Temperature (°C) SCL Frequency (Hz) Figure9. Figure10. SHUTDOWNI vsI2CCLOCKFREQUENCY Q 300 250 V = 5V S 200 A) m 150 ( Q I 100 50 V = 3V S 0 1k 10k 100k 1M 10M SCL Frequency (Hz) Figure11. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com APPLICATION INFORMATION Basic Operation TheTPS2480/81providesallthefeaturesneededforapositivehotswapcontroller. Thesefeaturesinclude: 1. Under-voltagelockout; 2. Adjustable(system-level)enable; 3. Turn-oninrushlimit; 4. High-sidegatedriveforanexternalN-channelMOSFET; 5. MOSFETprotection(powerlimitandcurrentlimit); 6. Adjustableoverloadtimeout(alsocalledanelectroniccircuitbreaker); 7. Charge-completeindicatorfordownstreamconvertersequencing;and 8. Optionalautomaticrestartmode. The TPS2480/81 features superior power-limiting, MOSFET protection that allows independent control of current limit (to set maximum full-load current), power limit and overload time (to keep FET in its SOA), and overload time (to control case temperature rise). The typical application circuit, and oscilloscope plots of Figure 12 and Figure16demonstratemanyofthefunctionsdescribedabove. BoardPlug-In(Figure12) Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS2480/81 is held inactive, and GATE, PROG, TIMER, and PG are held low for less than 1 ms while internalvoltagesstabilize,thenGATE,PROG,TIMER,andPGarereleasedandthepartbeginssourcingcurrent to the GATE pin and the external FET begins to turn on while the voltage across it, V , and current (SENSE-OUT) through it, V , are monitored. Current initially rises to the value which satisfies the power limit engine (VCC-SENSE) (P ÷V )sincetheoutputcapacitorwasdischarged. LIM VCC 14 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 TIMERandPGOperation(Figure12) The TIMER pin charges C as long as limiting action continues, and discharges at a 1/10 charge rate when T limiting stops. If the voltage on C reaches 4 V before the output is charged, the external FET is turned off and T either a latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a deglitched end-of-charge indication which is based on the voltage across the external FET. PG is useful for preventing a downstream DC-to-DC converter from starting while C is still charging. PG goes active (open O drain) about 9 ms after C is charged. This delay allows the external FET to fully turn on and any transients in O the power circuits to end before the converter starts up. The resistor pull-up shown on pin PG in the typical application diagram only demonstrates operation; the actual connection to the converter depends on the application. Timing can appear to terminate early in some designs if operation transitions out of the power limit modeintoagatechargelimitedmodeatlowV values. DS Figure12. BasicBoardInsertion Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com ActionoftheConstantPowerEngine(Figure13) The calculated power dissipated in the external FET, V x I , is computed under the same startup conditions as DS D Figure 12. The current of the external FET, labeled I , initially rises to the value that satisfies the constant power IN engine; in this case it is 54 W / 48 V = 1.1 A. The 54-W value is programmed into the engine by setting the PROG voltage using Equation 1. V of the external FET, which is calculated as V , falls as C DS (SENSE-OUT) O charges, thus allowing the the external FET drain current to increase. This is the result of the internal constant power engine adjusting the current limit reference to the GATE amplifier as C charges and V falls. The O DS calculated device power in Figure 13, labeled MOSFET POWER, is seen to be flat-topped and constant within the limitations of circuit tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine output to 50 mV when V is low. This protection technique can be viewed as a DS specialized form of foldback limiting; the benefit over linear foldback is that it yields the maximum output current fromadeviceoverthefullrangeofV andstillprotectsthedevice. DS Figure13. ComputationoftheExternalFETStressDuringStartup 16 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 ResponsetoaHardOutputShort(Figure14andFigure15) Figure 14 shows the short circuit response over the full time-out period. This begins when the output voltage falls and ends when the external FET is turned off. The external FET current is actively controlled by the power limiting engine and gate amplifier circuit while the TIMER pin charges C to the 4-V threshold. Once this T threshold is reached, the TPS2480/81 disable and latch off the external FET. The TPS2480 remains latched off until either the input voltage drops below the UVLO threshold or EN cycles through the false (low) state. The TPS2481willattemptarestartaftergoingthroughatimingcycle. Figure14. CurrentLimitOverview Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com The TPS2480/81 responds rapidly to the short circuit as seen in Figure 15. The falling OUT voltage is the result of the external FET and C currents through the short circuit impedance. The internal GATE clamp causes the O GATE voltage to follow the output voltage down and subsequently limits the negative V to 1.2 V. The rapidly DS rising fault current overdrives the GATE amplifier causing it to overshoot and rapidly turn the external FET off by sinking current to ground. The external FET slowly turns back on as the GATE amplifier recovers; the external FETthensettlestoanequilibriumoperatingpointdeterminedbythepowerlimitingcircuit. Figure15. CurrentLimitOnset Minimal input voltage overshoot appears in Figure 15 because a local 100-mF bypass capacitor and very short input leads were used. The input voltage would overshoot as the input current abruptly drops in a typical application due to the stored energy in the input distribution inductance. The exact waveforms seen in an application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the short itself. 18 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 AutomaticRestart(Figure16) The TPS2481 automatically initiates a restart after a fault has caused it to turn off the external FET. Internal control circuits use C to count 16 cycles before re-enabling the external FET. This sequence repeats if the fault T persists.TheTIMERhasa1:10charge-to-dischargecurrentratio,andusesa1-Vlowerthreshold.Thefault-retry duty cycle specification quantifies this behavior. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and reduces the need for additional protection devices. Figure16. TPS2480/81RestartCycleTiming Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Low Voltage Application Design Example The following example illustrates the design and component selection process for a 12-V, 40-A hotswap application.Figure17showstheapplicationcircuitforthisdesignexample. VCC VOUT R S D1 C R O G A1 R I2C A0 PG 1kW Addresses 20 19 18 17 16 15 14 13 12 11 C1 CG Optional: 0.1mF UsewithdV/dtcontrol 0 1 M P D C E E T G 0/1 A A VIN VIN GN VC ENS GAT OU P 48 S 2 TPS DA CL C S C N REF ROG MER ND S S N V N E V P TI G VCC 1 2 3 4 5 6 7 8 9 10 SDA R EN1 SCL C T R PROG1 C 0.1EmNF REN2 1R0SkDWA 1R0SkDWA R PROG2 C 3P3V_USB VS 0.1mF Figure17. TPS2480/81LowVoltageDesignExampleSchematic 20 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 1. Choose R S The following equation includes a factor of 1.2 (20%) for V and R tolerance along with some additional SENSE S margin. V 50mV R = SENSE = =1.042mΩ S 1.2´I 1.2´40A LIMIT (5) • ChooseR =1mΩ S V 55mV I = SENSE(MAX) = =55A LIMIT(MAX) R 1mΩ S (6) R Power =I2 ´R =55A2´1mW =3.025W S LIMIT(MAX) S (7) Multiplesenseresistorsinparallelshouldbeconsidered. 2. Choose M1 Select the M1 V rating allowing for maximum input voltage and transients. Then select an operating R , DS DSON package, and cooling to control the operating temperature. Most manufacturers list R at 25°C and DSON(MAX) provideaderatingcurvefromwhichvaluesatothertemperaturescanbederived.Thenextequationcanbeused toestimatedesiredR atthemaximumoperatingjunctiontemperatureofT .(usually125°C).T DSON(MAX) J(MAX) A(MAX) isthemaximumexpectedambienttemperature. C T =125C,T =50C,R =10 ,I =50A J(MAX) A(MAX) qJA W LIMIT(NOM) (8) T -T 125C - 50C R = J(MAX) A(MAX) = =3mΩ DSON(MAX) R ´I2 C qJA LIMIT(NOM) 10 ´(50A)2 W (9) The junction-to-ambient thermal resistance R , depends upon the package style chosen and the details of qJA heat-sinking and cooling including the PCB. Actual “in-system” temperature measurements will be required to validateheat-sinkingandcoolingperformance. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com 3. Choose the Power Limit P and the PROG Resistors, R and R LIM PROG1 PROG2 M1 dissipates large amounts of power during power-up or output short circuit. Power limit, P should be set to LIM prevent M1 die temperature from exceeding a short term maximum temperature, T . Short term T J(MAX2) J(MAX2) may be set as high as 150°C while still leaving ample margin for the typical manufacturer's rating of 175°C. P LIM canbeestimatedasfollows: C C T =150C,T =50C,R =9.8 ,R =0.2 ,R =1.18mW J(MAX2) A(MAX) qCA W qJC W DS(on) (10) 0.7*(T -R ´I2 ´R -T ) P = J(MAX2) qCA LIMIT(NOM) DSON A(MAX) =249W LIM R qJC (11) Where R is M1+PCB case-to-ambient thermal resistance, R is M1 junction-to-case thermal resistance, qCA qJC R is M1 channel resistance at the maximum operating temperature, and the factor of 0.7 accounts for the DS(on) tolerance of the constant power engine. The maximum power limit for the constant power engine, P and LIM(MAX) nominalpowerP settingsforthiscircuitarecalculatedwiththenextequation: OUT(nom) V = 4V,R =1mW,V =12V,I =50A REF S OUT(NOM) LIMIT(NOM) (12) 1V´V P = REF =2kW LIM(MAX) 2´R S (13) P = V ´I =12V ´50A =600W OUT(NOM) OUT(NOM) LIMIT(NOM) (14) The PROG resistors should be chosen using the smallest of P , P , or P values. Choose R LIM LIM(MAX) LIM(MAX) PROG2 =20kΩ .ChooseR asshownbelow. PROG1 2´P ´R 2´249W´1mΩ V = LIM(ACT) S = =0.498V PROG 1V 1V (15) V R =R ´( REF -1)=140.6kΩ PROG1 PROG2 V PROG (16) • ChooseR =140kΩ PROG1 ThepowerandcurrentlimitcurveforthisconfigurationisshowninFigure18. CurrentLimitvs.Vout(Vvcc=12V) 60 s) 50 p m A ( 40 nt e urr 30 C ut utp 20 O 10 0 10 8 6 4 2 00 OutputVoltage(V) Figure18. TPS2480/81PowerandCurrentLimitCurve 22 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 4. Choose the Timer Capacitor, C and Turn On Time T The turn on time t , represents the time it takes the circuit to charge up the output capacitance C and load. C ON O T programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of start up. The turn on time is a function of the type of control; current limit, power limit, or dV/dt control. The next equation calculates t for both the power limit and current limit cases and assumes that only C draws current ON O duringstartup. C ´P C ´V2 For P < V ´I : t = O LIM(ACT) + O VCC(MAX) LIM(ACT) VCC(MAX) LIMIT(NOM) ON 2´I2 2´P LIMIT(NOM) LIM(ACT) (17) C ´V For P ³ V ´I : t = O VCC(MAX) LIM(ACT) VCC(MAX) LIMIT(NOM) ON I LIMIT(NOM) (18) C ´P C ´V2 1000mF´249W 1000mF´13.5V2 t = O LIM(ACT) + O VCC(MAX) = + = 416ms ON 2´I2 2´P 2´502A 2´249W LIMIT(NOM) LIM(ACT) (19) The next equation allows C to be selected assuming that only C draws current during startup. TPS2480/81 T O timercurrentsourceandcapacitortolerancesareaccountedfor. I C = SOURCE(MAX) ´t ´(1+C +C ) T V ON O-TOL T-TOL TMR-TH(MAX) (20) 34mA C = ´416ms´(1+0.2+0.1)= 4.48nF T 4.1V (21) • ChooseC =0.01µF T 5. Choose the Turn On Voltage, V and the EN Resistors, R and R ON EN1 EN2 When the EN pin is used as an analog control, the desired turn on voltage, V can be used to select the EN ON resistors.SelectR andR takingintoaccountdeviceleakagecurrents.ChooseR =10kΩ. EN1 EN2 EN2 V R =R ´( ON -1)=55.22kW EN1 EN2 V EN_H(MAX) (22) • ChooseR =54.9kΩ EN2 Theactualturnonandturnoffvoltages,VON(ACT)andVOFF(ACT)canbecalculatedasfollows: R +R R +R V = V ´ EN1 EN2 ,V = V ´ EN1 EN2 ON EN_H(MAX) R OFF EN_L(MIN) R EN2 EN2 (23) 54.9kW+10kW V =1.38V ´ =8.96V ON 10kW (24) 54.9kW+10kW V =1.22V ´ =7.92V OFF 10kW (25) Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Alternative Inrush Designs GateCapacitor(dV/dt)Control The TPS2480/81 can be configured to provide a linear dV/dt turn on characteristic. The load capacitor charging current I , is controlled by a single capacitor from the GATE terminal to ground. M1 operates as a source CHARGE follower (following the gate voltage) in this implementation. Choose a charge time, t , based on the load ON capacitor, C input voltage V, and desired charge current. When power limiting is used (V < V ) choose O I PROG REF I to be less than P /V to prevent the fault timer from starting. The fault timer starts only if power or CHARGE LIM VCC currentlimitisinvoked. C ´V t = O VCC ON I CHARGE (26) Use the following equation to select the gate capacitance, C . C is the gate capacitance of M1, and I is G ISS GATE the TPS2480/81 nominal gate charge current. As shown in Figure 17, a series resistor of about 1 kΩ should be usedinserieswithC . G I ´t C = GATE ON -C G V ISS VCC (27) If neither power nor current limit faults are invoked during turn on, C can be chosen for fast transient turn off T response using the M1 SOA curve. Choose the single pulse time conservatively from the M1 SOA curve using maximumoperatingvoltageandmaximumtripcurrent. PROGInrushControl A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 12. This method maintains a relatively fast turn-on time without the drawbacks of a gate-to-ground capacitor that includeincreasedshortcircuitresponsetimeandlesspredictablegateclamping. 24 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 HighVoltageApplicationExample The TPS2480/81 can be used to monitor current from a voltage source greater than 26 V by using the OPAMP circuitshowninFigure19. M1 VIN VCC 9Vto57V VOUT R S R IN R MA C2 D1 0.1mF R CO G + D2 5.1V R MB RB C RPG 1kW VIN C G Optional: A1 UsewithdV/dtcontrol I2C A0 Addresses 20 19 18 17 16 15 14 13 12 11 C1 0.1mF 0 1 M P D C E E T G 480/1 A A VIN VIN GN VC SENS GAT OU P 2 TPS SDA SCL NC VS NC EN VREF PROG TIMER GND VCC 1 2 3 4 5 6 7 8 9 10 SDA R EN1 SCL C T R PROG1 0C.1EmNF REN2 1R0SkDWA 1R0SkDWA R PROG2 C 3P3V_USB VS 0.1mF Figure19. TPS2480/81HighVoltageApplication The basic operating principle of U2, Q1, R , and R is to mirror the voltage seen across R from a VCC MA MB S referenced voltage to a GND referenced voltage. As load current flows through R , the voltage input to U2-3 S decreases and the output of U2/Q1 as seen at Q1-S follows this sense voltage. Ideally, the voltage drop across R mirrors the voltage drop across R . Current flow through R will mirror current flow through R , and if MA S MB MA R =R thenthesensevoltageacrossR ismirroredatVINP. MA MB S Since only a small voltage will be across R and R , their nominal value should be fairly low to offset input MA MB bias current effects (I ). TPS2480/1 input bias current sums with the current that flows through R increasing VINP MA the voltage drop across R . To block the bias current from R , an additional buffer may be inserted between MB MB Q1-D and VINP. Using a network type resistor for R and R designed with temperature coefficient tracking MA MB willprovidegoodvoltagemirroring. U2 should be a high quality, low drift operational amplifier. The OPA333AID provides low input voltage offset and very low drift over time and temperature. U2 is referenced to VCC through D2 and R and can operate from rail B torail. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Additional Design Considerations UseofPG Use the PG pin to control and sequence a downstream DC/DC converter. If this is not done a long time delay maybeneededtoallowC tofullychargebeforetheconverterstarts. O OutputClampDiode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during current limit. The OUT pin ratings can be maintained with a small diode such as an S1B, between the TPS2480/81 OUT toGNDpins. GateClampDiode The TPS2480/81 has a relatively well-regulated gate voltage of 12 V to 16 V, even at low supply voltages. A small clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if V of M1 is rated GS belowthis. HighGateCapacitanceApplications Gatevoltageoverstressandlargefaultcurrentspikescanbecausedbylargegatecapacitance.Anexternalgate clamp Zener diode is recommended if the total gate capacitance of M1 exceeds 4000 pF. When gate capacitor dV/dTcontrolisused,a1-kΩ resistorinserieswithC isrecommended,asshowninFigure17.IftheseriesR-C G combinationisusedforMOSFETswithCISSlessthan3000pF,thenaZenerisnotrequired. InputTransientProtection The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on VINP and VINM solely to provide margin for transients on the bus. The TPS2480 will operate properly up to the absolute maximumvoltageratingsonVINPandVINM. Hotswap systems experience positive transients on their input during hotplug or rapid turnoff with high current due to inductance in the input circuit. These same systems experience negative transients on the output during rapid turnoff with high current due to inductance in the output circuit. The TPS2480 may not require operational voltage margin below the absolute maximum if it is operated from a non-inductive input. An example is an application where the TPS2480 is used as an output protector with a large input capacitance located directly at theinputterminals. Transient protection, e.g. a TVS diode (transient voltage suppressor, a type of Zener diode), may be required on the input in addition to a bypass capacitor if the system design does not inherently limit transient voltages below the absolute maximum ratings. An example of this is a system with significant input inductance. If a TVS is required,itmustprotecttotheabsolutemaximumratingsattheworstcaseclampingcurrent. An output voltage clamp diode may be required on the output to limit negative transients if the local output capacitance does not adequately control it. An example of this is a system with significant output bus inductance and little local capacitance. Select a schottky diode with low forward voltage at the anticipated current during an outputshort. 26 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 OutputShortCircuitMeasurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to varying results. The actual short itself exhibits a certain degree of randomness as it microscopicallybouncesandarcs.Careinconfigurationandmethodsmustbeusedtoobtainrealisticresults.Do notexpecttoseewaveformsexactlylikethoseinthedatasheetsinceeverysetupdiffers. Applicationsusingtheretryfeature(TPS2481) Applications using the retry feature may want to estimate fault retry time. The TPS2481 will retry (enable M1 to attempt turn on) once for every 16 timer charge/discharge cycles (15 cycles between 1 V and 4 V, 1 cycle between0Vand4V). ( ) é 1 1 ù T =C ´éV +15´ V -V ù´ê + ú RETRY T ë TMRHI(NOM) TMRHI(NOM) TMRLO(NOM) û êëI I úû SOURCE(NOM) SINK(NOM) (28) T =C ´21.56´106 RETRY T (29) NOTE Equation29simplified-assumesnoerror. LayoutConsiderations Good layout practice places the power devices D1, R , M1, and C so power flows in a sequential, linear S O fashion. A ground plane under the power and the TPS2480/81 is desirable. The TPS2480/81 should be placed close to the sense resistor and MOSFET using a Kelvin type connection to achieve accurate current sensing across R . A low-impedance GND connection is required because the TPS2480/81 can momentarily sink S upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the GATE trace length short. The PROG, TIMER, and EN pins have high input impedances, therefore keep their input leads short. Oversize power traces and power device connections to assure low voltage drop and good thermalperformance. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Power, Current, and Voltage Monitoring (PIV) The TPS2480/81 digital current-shunt monitor has an I2C / SMBus-compatible interface. It provides digital current, voltage, and power readings for accurate decision-making in precisely-controlled systems. Programmable registers allow flexible configuration for measurement resolution, and continuous versus-triggered operation. Detailed register information appears in the Register Information Section. See the Register Block DiagramforablockdiagramoftheTPS2480/81PIVmonitoringcircuits. PIV Monitoring - Typical Application Circuit Considerations Figure 17 shows a typical application circuit for the TPS2480/81. 0.1-mF ceramic capacitors must be placed as closeaspossibletothesupplyandgroundpinsforsupplybypassing. The pull-up resistors shown on the SDA and SCL lines are not needed if there are pull-up resistors on these same lines elsewhere in the system. Resistor values shown are typical: consult the I2C or SMBus specification to determineacceptablevalues. I2C Bus Overview The I2C and SMBus protocols are essentially compatible with each other and the TPS2480/81 are compatible with both. This allows use of the I2C interface throughout this data sheet as the primary example, with SMBus protocolspecifiedonlywhenthereisadifference. Two bidirectional lines, SCL and SDA, connect the TPS2480 / 81 to the bus. Both SCL and SDA are open-drain connections. The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls, the busaccess,andgeneratesSTARTandSTOPconditions. Toaddressaspecificdevice,themasterinitiatesaSTARTconditionbypullingSDAfromaHIGHtoaLOWlogic level while SCL is HIGH. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressedrespondstothemasterbygeneratinganAcknowledgeandpullingSDALOW. Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH is interpreted as a STARTorSTOPcondition. Once all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The TPS2480/81 includes a 28-ms timeout on its interface to prevent locking upanSMBus. 28 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Serial Bus Address TocommunicatewiththeTPS2480/81,themastermustfirstaddressslavedevicesviaaslaveaddressbyte.The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or writeoperation. The TPS2480/81 have two address pins, A0 and A1. Table 2 describes the pin logic levels for each of the 16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set beforeanyactivityontheinterfaceoccurs.Theaddresspinsarereadatthestartofeachcommunicationevent. Table2.TPS2480/81AddressPinsand SlaveAddresses A1 A0 SLAVEADDRESS GND GND 1000000 GND V 1000001 S+ GND SDA 1000010 GND SCL 1000011 V GND 1000100 S+ V V 1000101 S+ S+ V SDA 1000110 S+ V SCL 1000111 S+ SDA GND 1001000 SDA V 1001001 S+ SDA SDA 1001010 SDA SCL 1001011 SCL GND 1001100 SCL V 1001101 S+ SCL SDA 1001110 SCL SCL 1001111 Serial Interface The TPS2480/81 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TPS2480/81 support the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes are transmittedmostsignificantbytefirst. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Writing To/Reading From The TPS2480/81 Accessing a particular register on the TPS2480/81 is accomplished by writing the appropriate value to the register pointer. Refer to Table 4 for a complete list of registers and corresponding addresses. The value for the register pointer as shown in Figure 20 is the first byte transferred after the slave address byte with the R/W bit LOW.EverywriteoperationtotheTPS2480/81requiresavaluefortheregisterpointer. Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/W bit LOW. The TPS2480/81 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register to which data will be written. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The TPS2480/81 acknowledges receipt of each data byte. The master may terminate data transfer by generatingaSTARTorSTOPcondition. When reading from the TPS2480/81, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a START condition and sends the slave address byte with the R/W bit HIGH to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte.Themasteracknowledgesreceiptofthedatabyte.Themaster may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the TPS2480/81retainstheregisterpointervalueuntilitischangedbythenextwriteoperation. Figure 20 and Figure 21 show write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte. Figure 22 shows the timing diagram for theSMBusAlertresponseoperation.Figure23illustratesatypicalregisterpointerconfiguration. 30 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Stop ByMaster Stop 9 D0 ACK ByTPS2480/81 9 0 (3)NoACK ByMaster D5D4D3D2D1 Frame 4 Data LSByte DDDD321 FromPS2480/81 (2)me 3 Data LSByte 4 T a D6 D Fr 1 D7 D5 19919 D15D14D13D12D11D10D9D80A3A2A1A0R/WP7P6P5P4P3P2P1P0 ACK ByACK ACK ByByTPS2480/81TPS2480/8TPS2480/811(1)me 1 TwFrameo-Wire Slave 2 Register Address ByPointer ByteteFrame 3 Data MSByte e value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. 9119 DD7600AR/WD1D1D1D1D1D1D9D83543210A2A1A0 FromACK ByACK ByTPS2480/81TPS2480/81Master((1)2)Frame 1 TFrawo-Wire Slme 2 Datave Addra MSByteess Byte NOTES: (1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins.Refer to Table 1.(2) Read data is from the last register pointer location. If a new register is desired, the registerpointer must be updated. See Figure 19.(3) ACK by Master can also be sent. 0 Fra Th 1 1 1 1 Start ByMaster NOTE (1): L A Start ByMaster SCL SDA SC SD Figure20.TimingDiagramforWriteWordFormat Figure21.TimingDiagramforReadWordFormat Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com ALERT 1 9 1 9 SCL SDA 0 0 0 1 1 0 0 R/W 1 0 0 A3 A2 A1 A0 0 Start By ACK By From NACK By Stop By Master TPS2480/81 TPS2480/81 Master Master (1) Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure22. TimingDiagramforSMBusALERT 1 9 1 9 ¼ SCL SDA 1 0 0 A3 A2 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0 Stop Start By ACK By ACK By Master TPS2480/81 TPS2480/81 Frame 1 Two-Wire Slave Address Byte(1) Frame 2 Register Pointer Byte NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1. Figure23. TypicalRegisterPointerSet 32 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 High-SpeedI2CMode When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The TPS2480/81 does not acknowledge the HS master code, but does recognize it and switches its internal filters to support3.4-Mbpsoperation. Themasterthengeneratesarepeatedstartcondition(arepeatedstartconditionhasthesametimingasthestart condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the TPS2480/81tosupporttheF/Smode. t (LOW) tR tF t(HDSTA) SCL t t t t (HDSTA) (HIGH) (SUSTA) (SUSTO) t t (HDDAT) (SUDAT) SDA t (BUF) P S S P Figure24. Table3. FASTMODE HIGH-SPEEDMODE UNITS PARAMETER MIN MAX MIN MAX f SCLoperatingfrequency 0.001 0.4 0.001 3.4 MHz (SCL) T BusfreetimebetweenSTOPandSTARTcondition 600 160 ns (BUF) T HoldtimeafterrepeatedSTARTcondition.Afterthisperiod, (HDSTA) 100 100 ns thefirstclockisgenerated. T RepeatedSTARTconditionsetuptime 100 100 ns (SUSTA) T STOPconditionsetuptime 100 100 ns (SUSTO) T Dataholdtime 0 0 ns (HDDAT) T Datasetuptime 100 10 ns (SUDAT) T SCLclockLOWperiod 1300 160 ns (LOW) T SCLclockHIGHperiod 600 60 ns (HIGH) t Clock/datafalltime 300 160 ns F t /t Clock/datarisetimeclock/datarisetimeforSCLK≤100kHz 300/1000 160 ns/ns R R Power-UpConditions Power-up conditions are caused by a software reset via the R bit (bit 15) in the Configuration Register, or the ST I2CbusGeneralCallReset. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com ADC Operation ThetwoanaloginputstotheTPS2480/81,VINPandVINM,connecttoashuntresistorinthebusofinterest.The TPS2480/81 is typically powered by a separate supply from 3 V to 5 .5V. The bus being sensed can vary from 0 V to 26 V. There are no special considerations for power-supply sequencing (for example, a bus voltage can be present with the supply voltage off, and vice-versa). The TPS2480/81 senses the small drop across the shunt for shunt voltage, and senses the voltage with respect to ground from VIN– for the bus voltage. Figure 25 illustrates thisoperation. VSHUNT= VIN+-VIN- Typically < 50mV + - Current Shunt Supply Load 3V to 5.5V 3.3V Supply VIN+ VIN- VS ´ Power Register Data (SDA) VBUS= VIN--GND Current Register InteI2rCface A0 Clock (SCL) Range of 0V to 26V PGA ADC Typical Application 12V Voltage Register A1 GND Figure25. TPS2480/81ConfiguredForCurrentandVoltageMeasurement When the TPS2480/81 is in the normal operating mode (that is, MODE bits of the Configuration Register are set to '111'), it continuously converts the shunt voltage up to the number set in the shunt voltage averaging function (Configuration Register, SADC bits). The device then converts the bus voltage up to the number set in the bus voltage averaging (Configuration Register, BADC bits). The Mode control in the Configuration Register also permits selecting modes to convert only voltage or current, either continuously or in response to an event (triggered). 34 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 All current and power calculations are performed in the background and do not contribute to conversion time; conversion times shown in the Electrical Characteristics table can be used to determine the actual conversion time. Power-Down mode reduces the quiescent current and turns off current into the TPS2480/81 inputs, avoiding any supply drain. Full recovery from Power-Down requires 40 ms. ADC Off mode (set by the Configuration Register, MODEbits)stopsallconversions. In triggered mode, the external Convert line becomes active. Convert commands are initiated by taking the Convert line low for a minimum of 4 ms. The Convert line may be connected high when unused. Any re-trigger of the Convert line during a conversion is ignored, and the Convert line state is disregarded until the conversion ends. There are several available triggered modes; however, all conversions are performed repeatedly up to the numbersetintheAveragingfunction(ConfigurationRegister,BADCandSADCbits). If the Convert line is held low, writing any of the triggered convert modes into the Configuration Register (even if thedesiredmodeisalreadyprogrammedintotheregister)triggersasingle-shotconversion. Although the TPS2480/81 can be read at any time, and the data from the last conversion remain available, the Conversion Ready bit (Status Register, CNVR bit) is provided to help co-ordinate one-shot or triggered conversions. The Conversion Ready bit is set after all conversions, averaging, and multiplication operations are complete. TheConversionReadybitclearsundertheseconditions: 1. Writing to the Configuration Register, except when configuring the MODE bits for Power Down or ADC off (Disable)modes; 2. ReadingtheStatusRegister;or 3. Triggeringasingle-shotconversionwiththeConvertpin. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com PowerMeasurement Current and bus voltage are converted at different points in time, depending on the resolution and averaging mode settings. For instance, when configured for 12-bit and 128 sample averaging, up to 68 ms in time between samplingthesetwovaluesispossible.Again,thesecalculationsareperformedinthebackgroundanddonotadd totheoverallconversiontime. PGAFunction If larger full-scale shunt voltages are desired, the TPS2480/81 provides a PGA function that increases the full-scale range up to 2, 4, or 8 times (320 mV). Additionally, the bus voltage measurement has two full-scale ranges:16Vor32V. FilteringandInputConsiderations Measuringcurrentcanbenoisy,andsuchnoisecanbedifficulttodefine. The internal ADC has a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This architecture has good inherent noise rejection. However, transients that occur at or very close to the sampling rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be dealt with by incorporating filtering at the input of the TPS2480/81. The high frequency enables the use of low-value series resistors on the filter for reducing effects on measurement accuracy. In general, filtering the TPS2480/81 input is only necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate (>1 MHz). Filter usingthelowestpossibleseriesresistanceandceramiccapacitor.Recommendedvaluesare0.1mFto1.0mF. Overload conditions are another consideration for the TPS2480/81 inputs. The TPS2480/81 inputs are specified to tolerate 26 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long the power supply or energy storage capacitors support it). It must be remembered that removing a short to ground can result in inductive kickbacks that could exceed the 26-V differential and common-mode rating of the TPS2480/81. Inductive kickback voltages are best dealt with by zener-type transient-absorbing devices (commonly called transzorbs)combinedwithsufficientenergystoragecapacitance. In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem occurs because an excessive dV/dt can activate the ESD protection in the TPS2480/81 in systems where large currentsareavailable. SimpleCurrentShuntMonitorUsage(NoProgrammingNecessary) The TPS2480/81 can be used without any programming if it is only necessary to read a shunt voltage drop and bus voltage with the default 12-bit resolution, 320-mV shunt full-scale range (PGA = ÷ 8), 32-V bus full-scale range,andcontinuousconversionofshuntandbusvoltage. Without programming, current is measured by reading the shunt voltage. The Current Register and Power RegisterareonlyavailableiftheCalibrationRegistercontainsaprogrammedvalue. ProgrammingtheTPS2480/81 The default power-up states of the registers are shown in the register information section. These registers are volatile, and if programmed to other than default values, must be re-programmed at every device power-up. Detailed information on programming the Calibration Register specifically is given in the Programming the TPS2480/81PowerMeasurementEnginesection. 36 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Programming The TPS2480/81 Power Measurement Engine CalibrationRegisterandScaling The Calibration Register makes it possible to set the scaling of the Current and Power Registers to whatever values are most useful for a given application. One strategy may be to set the Calibration Register such that the largest possible number is generated in the Current Register or Power Register at the expected full-scale point; thisapproachyieldsthehighestresolution.TheCalibrationRegistercanalsobeselectedtoprovidevaluesinthe Current and Power Registers that either provide direct decimal equivalents of the values being measured, or yield a round LSB number. After these choices have been made, the Calibration Register also offers possibilities forendusersystem-levelcalibration,wherethevalueisadjustedslightlytocanceltotalsystemerror. Below are two examples for configuring the TPS2480/81 calibration. Both examples are written so the informationdirectlyrelatestothecalibrationsetupfoundintheTPS2480/81EVMsoftware. CalibrationExample1:CalibratingtheTPS2480/81WithNoPossibilityforOverflow NOTE The numbers used in this example are the same used with the TPS2480/81EVM software asshowninFigure26.Thisdoesnotmeantheinputcangoover26V! 1. Establishthefollowingparameters: V =32,Thisdoesnotmeantheinputcangoover26V! BUS_MAX V =0.32 SHUNT_MAX R =0.5 SHUNT 2. UsingEquation30,determinethemaximumpossiblecurrent. V MaxPossible_I = SHUNT_MAX R SHUNT MaxPossible_I = 0.64 (30) 3. Choosethedesiredmaximumcurrentvalue.Thisvalueisselectedbasedonsystemexpectations. Max_Expected_I=0.6 4. Calculate the possible range of current LSBs. To calculate this range, first compute a range of LSBs that is appropriate for the design. Next, select an LSB within this range. Note that the results will have the most resolution when the minimum LSB is selected. Typically, an LSB is selected to be the nearest round number totheminimumLSBvalue. Max_Expected_I Minimum_LSB = 32767 Minimum_LSB = 18.311´10-6 (31) Max_Expected_I Maximum_LSB = 4096 Maximum_LSB = 146.520´10-6 (32) ChooseanLSBintherange:Minimum_LSB<Selected_LSB <Maximum_LSB Current_LSB=20× 10–6 NOTE This value was selected to be a round number near the Minimum_LSB. This selection allowsforgoodresolutionwitharoundedLSB. Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com 5. ComputetheCalibrationRegistervalueusingEquation33: 0.04096 Cal = trunc Current_LSB´R SHUNT Cal = 4096 (33) 6. CalculatethePowerLSB,usingEquation34.Equation34showsageneralformula;becausethebusvoltage measurementLSBisalways4mV,thepowerformulareducestothecalculatedresult. Power_LSB = 20´Current_LSB Power_LSB = 400´10-6 (34) 7. Compute the maximum current and shunt voltage values (before overflow), as shown by Equation 35 and Equation36.NotethatbothEquation35andEquation36involveanIf-thencondition: Max_Current = Current_LSB´32767 Max_Current = 0.65534 (35) IfMax_Current≥ MaxPossible_Ithen Max_Current_Before_Overflow=MaxPossible_I Else Max_Current_Before_Overflow=Max_Current EndIf NOTE (Max_CurrentisgreaterthanMaxPossible_Iinthisexample.) 38 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Max_Current_Before_Overflow=0.64(Note:ThisresultisdisplayedbysoftwareasseeninFigure26.) Max_ShuntVoltage = Max_Current_Before_Overflow´R SHUNT Max_ShuntVoltage = 0.32 (36) IfMax_ShuntVoltage≥ V SHUNT_MAX Max_ShuntVoltage_Before_Overflow=V SHUNT_MAX Else Max_ShuntVoltage_Before_Overflow=Max_ShuntVoltage EndIf Max_ShuntVoltage_Before_Overflow=0.32 NOTE ThisresultisdisplayedbysoftwareasseeninFigure26. (Max_ShuntVoltageisgreaterthanV inthisexample.) SHUNT_MAX 8. ComputethemaximumpowerwithEquation37. MaximumPower = Max_Current_Before_Overflow´V BUS_MAX MaximumPower = 20.48 (37) 9. (Optional second Calibration step.) Compute corrected full-scale calibration value based on measured current. TPS2480/81_Current=0.0504 MeaShuntCurrent=0.05006 Cal´MeasShuntCurrent Corrected_Full_Scale_Cal = trunc TPS2480/81_Current Corrected_Full_Scale_Cal = 4068 (38) Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Figure 26 illustrates how to perform the same procedure discussed in this example using the automated TPS2480/81EVMsoftware. NOTE The same numbers used in the nine-step example are used in the software example in Figure 26. Also note that Figure 26 illustrates which results correspond to which step (for example, the information entered in Step 1 is enclosed in a box in Figure 26 and labeled). Thisdoesnotmeantheinputcangoover26V! Step 1 Optional Step 2 Step 9 Step 3 Step 4 Step 5 Step 7 Step 6 Step 8 Figure26. TPS2480/81CalibrationSofwareAutomaticallyComputesCalibrationSteps1-9 40 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Calibration Example 2 (Overflow Possible) This design example uses the nine-step procedure for calibrating the TPS2480/81 where overflow is possible. Figure27illustrateshowthesameprocedureisperformedusingtheautomatedTPS2480/81EVMsoftware. NOTE (The same numbers used in the nine-step example are used in the software example in Figure 27. Also note that Figure 27 illustrates which results correspond to which step (for example,theinformationenteredinStep1iscircledinFigure27andlabeled). 1. Establishthefollowingparameters: V =32,Thisdoesnotmeantheinputcangoover26V! BUS_MAX V =0.32 SHUNT_MAX R =0.001 SHUNT 2. DeterminethemaximumpossiblecurrentusingEquation39: V MaxPossible_I = SHUNT_MAX R SHUNT MaxPossible_I = 320 (39) 3. Choose the desired maximum current value: Max_Expected_I, ≤ MaxPossible_I. This value is selected basedonsystemexpectations. Max_Expected_I=60 4. Calculate the possible range of current LSBs. This calculation is done by first computing a range of LSB's that is appropriate for the design. Next, select an LSB withing this range. Note that the results will have the most resolution when the minimum LSB is selected. Typically, an LSB is selected to be the nearest round numbertotheminimumLSB. Max_Expected_I Minimum_LSB = 32767 Minimum_LSB = 1.831´10-3 (40) Max_Expected_I Maximum_LSB = 4096 Maximum_LSB = 14.652´10-3 (41) ChooseanLSBintherange:Minimum_LSB<Selected_LSB<Maximum_LSB Current_LSB=1.9×10–3 NOTE This value was selected to be a round number near the Minimum_LSB. This section allowsforgoodresolutionwitharoundedLSB. 5. ComputethecalibrationregisterusingEquation42: 0.04096 Cal = trunc Cal = 21557 Current_LSB´R SHUNT (42) 6. Calculate the Power LSB using Equation 43. Equation 43 shows a general formula; because the bus voltage measurementLSBisalways4mV,thepowerformulareducestocalculatetheresult. Power_LSB = 20´Current_LSB Power_LSB = 38´10-3 (43) Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com 7. Compute the maximum current and shunt voltage values (before overflow), as shown by Equation 44 and Equation45.NotethatbothEquation44andEquation45involveanIf-thencondition. Max_Current = Current_LSB´32767 Max_Current = 62.2573 (44) IfMax_Current≥ MaxPossible_Ithen Max_Current_Before_Overflow=MaxPossible_I Else Max_Current_Before_Overflow=Max_Current EndIf (NotethatMax_CurrentislessthanMaxPossible_Iinthisexample.) Max_Current_Before_Overflow=62.2573(Note:ThisresultisdisplayedbysoftwareasseeninFigure27.) Max_ShuntVoltage = Max_Current_Before_Overflow´R SHUNT Max_ShuntVoltage = 0.0622573 (45) IfMax_ShuntVoltage≥ V SHUNT_MAX Max_ShuntVoltage_Before_Overflow=V SHUNT_MAX Else Max_ShuntVoltage_Before_Overflow=Max_ShuntVoltage EndIf (NotethatMax_ShuntVoltageislessthanV inthisexample.) SHUNT_MAX Max_ShuntVoltage_Before_Overflow = 0.0622573 (Note: This result is displayed by software as seen in Figure27.) 8. Computethemaximumpowerwithequation8. MaximumPower = Max_Current_Before_Overflow´V BUS_MAX MaximumPower = 1992 (46) 9. (Optional second calibration step.) Compute the corrected full-scale calibration value based on measured current. TPS2480/81_Current=25.2472 MeaShuntCurrent=25.09 Cal´MeasShuntCurrent Corrected_Full_Scale_Cal = trunc TPS2480/81_Current Corrected_Full_Scale_Cal = 21422 (47) 42 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Figure 27 illustrates how to perform the same procedure discussed in this example using the automated TPS2480/81EVMsoftware. NOTE (The same numbers used in the nine-step example are used in the software example in Figure 27. Also note that Figure 27 illustrates which results correspond to which step (for example,theinformationenteredinStep1isenclosedinaboxinFigure27andlabeled). Step 1 Optional Step 2 Step 9 Step 3 Step 4 Step 5 Step 7 Step 6 Step 8 Figure27. CalibrationSoftwareAutomaticallyComputesCalibrationSteps1-9 Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com REGISTER INFORMATION The TPS2480/81 uses a bank of registers for holding configuration settings, measurement results, maximum/minimum limits, and status information. Table 4 summarizes the TPS2480/81 registers; illustrates registers. Register contents are updated 4 ms after completion of the write command. Therefore, a 4-ms delay is required between completion of a write to a given register and a subsequent read of that register (without changing the pointer)whenusingSCLfrequenciesinexcessof1MHz. Table4.SummaryofRegisterSet POINTER POWER-ONRESET ADDRESS REGISTERNAME FUNCTION TYPE(1) HEX BINARY HEX All-registerreset,settingsforbus 00 ConfigurationRegister voltagerange,PGAGain,ADC 0011100110011111 399F R/W resolution/averaging. 01 ShuntVoltage Shuntvoltagemeasurementdata. Shuntvoltage — R 02 BusVoltage Busvoltagemeasurementdata. Busvoltage — R 03 Power(2) Powermeasurementdata. 0000000000000000 0000 R 04 Current(2) Containsthevalueofthecurrentflowing 0000000000000000 0000 R throughtheshuntresistor. Setsfull-scalerangeandLSBofcurrent 05 Calibration andpowermeasurements.Overall 0000000000000000 0000 R/W systemcalibration. (1) Type:R=Read-Only,R/W=Read/Write. (2) ThePowerRegisterandCurrentRegisterdefaultto'0'becausetheCalibrationRegisterdefaultsto'0',yieldingazerocurrentvalueuntil theCalibrationRegisterisprogrammed. 44 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Register Details AllTPS2480/8116-bitregistersareactuallytwo8-bitregisters. ConfigurationRegister00h(Read/Write) BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT RST — BRNG PG1 PG0 BADC4 BADC3 BADC2 BADC1 SADC4 SADC3 SADC2 SADC1 MODE3 MODE2 MODE1 NAME POR 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 VALUE BitDescriptions RST: ResetBit Bit15 Settingthisbitto'1'generatesasystemresetthatisthesameaspower-onreset.Resetsallregisterstodefault values;thisbitself-clears. BRNG: BusVoltageRange Bit13 0=16-VFSR 1=32-VFSR(defaultvalue) PG: PGA(ShuntVoltageOnly) Bits11,12 SetsPGAgainandrange.NotethatthePGAdefaultsto÷8(320-mVrange).Table5showsthegainandrangefor thevariousproductgainsettings. Table5.PGBitSettings(1) PG1 PG0 GAIN RANGE 0 0 1 ±40mV 0 1 ÷2 ±80mV 1 0 ÷4 ±160mV 1 1 ÷8 ±320mV (1) Shadedvaluesaredefault. BADC: BADCBusADCResolution/Averaging Bits7–10 ThesebitsadjusttheBusADCresolution(9-,10-,11-,or12-bit)orsetthenumberofsamplesusedwhen averagingresultsfortheBusVoltageRegister(02h). Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com SADC: SADCShuntADCResolution/Averaging Bits3–6 ThesebitsadjusttheShuntADCresolution(9-,10-,11-,or12-bit)orsetthenumberofsamplesusedwhen averagingresultsfortheShuntVoltageRegister(01h). BADC(Bus)andSADC(Shunt)ADCresolution/averagingandconversiontimesettingsareshowninTable6. Table6.ADCSettings(1) ADC4 ADC3 ADC2 ADC1 MODE/SAMPLES CONVERSIONTIME 0 X(2) 0 0 9-bit 84ms 0 X(2) 0 1 10-bit 148ms 0 X(2) 1 0 11-bit 276ms 0 X(2) 1 1 12-bit 532ms 1 0 0 0 12-bit 532ms 1 0 0 1 2 1.06ms 1 0 1 0 4 2.13ms 1 0 1 1 8 4.26ms 1 1 0 0 16 8.51ms 1 1 0 1 32 17.02ms 1 1 1 0 64 34.05ms 1 1 1 1 128 68.10ms (1) Shadedvaluesaredefault. (2) X=Don'tcare. MODE: OperatingMode Bits0–2 Selectscontinuous,triggered,orpower-downmodeofoperation.Thesebitsdefaulttocontinuousshuntandbus measurementmode.ThemodesettingsareshowninTable7. Table7.ModeSettings(1) MODE3 MODE2 MODE1 MODE 0 0 0 Power-down 0 0 1 Shuntvoltage,triggered 0 1 0 Busvoltage,triggered 0 1 1 Shuntandbus,triggered 1 0 0 ADCoff(disabled) 1 0 1 Shuntvoltage,continuous 1 1 0 Busvoltage,continuous 1 1 1 Shuntandbus,continuous (1) Shadedvaluesaredefault. 46 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 Data Output Registers ShuntVoltageRegister01h(Read-Only) The Shunt Voltage Register stores the current shunt voltage reading, V . Shunt Voltage Register bits are SHUNT shifted according to the PGA setting selected in the Configuration Register (00h). When multiple sign bits are present, they will all be the same value. Negative numbers are represented in two's complement format. Generate the two's complement of a negative number by complementing the absolute value binary number and adding 1. Extend the sign, denoting a negative number by setting the MSB = '1'. Extend the sign to any additionalsignbitstoformthe16-bitword. Example:ForavalueofV =–320mV: SHUNT 1. Taketheabsolutevalue(includeaccuracyto0.01mV)==> 320.00 2. Translatethisnumbertoawholedecimalnumber==> 32000 3. Convertittobinary==> 111110100000000 4. Complementthebinaryresult:000001011111111 5. Add1totheComplementtocreatetheTwo’sComplementformattedresult==> 000001100000000 6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h (Remember to extend the sign to allsign-bits,asnecessarybasedonthePGAsetting.) At PGA = ÷8, full-scale range = ±320 mV (decimal = 32000, positive value hex = 7D00, negative value hex = 8300),andLSB=10mV. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT SIGN SD14_8 SD13_8 SD12_8 SD11_8 SD10_8 SD9_8 SD8_8 SD7_8 SD6_8 SD5_8 SD4_8 SD3_8 SD2_8 SD1_8 SD0_8 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE At PGA = ÷4, full-scale range = ±160 mV (decimal = 16000, positive value hex = 3E80, negative value hex = C180),andLSB=10mV. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT SIGN SIGN SD13_4 SD12_4 SD11_4 SD10_4 SD9_4 SD8_4 SD7_4 SD6_4 SD5_4 SD4_4 SD3_4 SD2_4 SD1_4 SD0_4 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE At PGA = ÷2, full-scale range = ±80 mV (decimal = 8000, positive value hex = 1F40, negative value hex = E0C0),andLSB=10mV. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT SIGN SIGN SIGN SD12_2 SD11_2 SD10_2 SD9_2 SD8_2 SD7_2 SD6_2 SD5_2 SD4_2 SD3_2 SD2_2 SD1_2 SD0_2 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE AtPGA=÷1,full-scalerange=±40mV(decimal=4000,positivevaluehex=0FA0,negativevaluehex=F060), andLSB=10mV. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT SIGN SIGN SIGN SIGN SD11_1 SD10_1 SD9_1 SD8_1 SD7_1 SD6_1 SD5_1 SD4_1 SD3_1 SD2_1 SD1_1 SD0_1 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com Table8.ShuntVoltageRegisterFormat(1) VSHUNT Decimal PGA=÷8 PGA=÷4 PGA=÷2 PGA=÷1 Reading(mV) Value (D15…..................D0) (D15…..................D0) (D15…..................D0) (D15…..................D0) 320.02 32002 0111110100000000 0011111010000000 0001111101000000 0000111110100000 320.01 32001 0111110100000000 0011111010000000 0001111101000000 0000111110100000 320.00 32000 0111110100000000 0011111010000000 0001111101000000 0000111110100000 319.99 31999 0111110011111111 0011111010000000 0001111101000000 0000111110100000 319.98 31998 0111110011111110 0011111010000000 0001111101000000 0000111110100000 - - - - - - 160.02 16002 0011111010000010 0011111010000000 0001111101000000 0000111110100000 160.01 16001 0011111010000001 0011111010000000 0001111101000000 0000111110100000 160.00 16000 0011111010000000 0011111010000000 0001111101000000 0000111110100000 159.99 15999 0011111001111111 0011111001111111 0001111101000000 0000111110100000 159.98 15998 0011111001111110 0011111001111110 0001111101000000 0000111110100000 - - - - - - 80.02 8002 0001111101000010 0001111101000010 0001111101000000 0000111110100000 80.01 8001 0001111101000001 0001111101000001 0001111101000000 0000111110100000 80.00 8000 0001111101000000 0001111101000000 0001111101000000 0000111110100000 79.99 7999 0001111100111111 0001111100111111 0001111100111111 0000111110100000 79.98 7998 0001111100111110 0001111100111110 0001111100111110 0000111110100000 - - - - - - 40.02 4002 0000111110100010 0000111110100010 0000111110100010 0000111110100000 40.01 4001 0000111110100001 0000111110100001 0000111110100001 0000111110100000 40.00 4000 0000111110100000 0000111110100000 0000111110100000 0000111110100000 39.99 3999 0000111110011111 0000111110011111 0000111110011111 0000111110011111 39.98 3998 0000111110011110 0000111110011110 0000111110011110 0000111110011110 - - - - - - 0.02 2 0000000000000010 0000000000000010 0000000000000010 0000000000000010 0.01 1 0000000000000001 0000000000000001 0000000000000001 0000000000000001 0 0 0000000000000000 0000000000000000 0000000000000000 0000000000000000 –0.01 –1 1111111111111111 1111111111111111 1111111111111111 1111111111111111 –0.02 –2 1111111111111110 1111111111111110 1111111111111110 1111111111111110 - - - - - - –39.98 –3998 1111000001100010 1111000001100010 1111000001100010 1111000001100010 –39.99 –3999 1111000001100001 1111000001100001 1111000001100001 1111000001100001 –40.00 –4000 1111000001100000 1111000001100000 1111000001100000 1111000001100000 –40.01 –4001 1111000001011111 1111000001011111 1111000001011111 1111000001100000 –40.02 –4002 1111000001011110 1111000001011110 1111000001011110 1111000001100000 - - - - - - –79.98 –7998 1110000011000010 1110000011000010 1110000011000010 1111000001100000 –79.99 –7999 1110000011000001 1110000011000001 1110000011000001 1111000001100000 –80.00 –8000 1110000011000000 1110000011000000 1110000011000000 1111000001100000 –80.01 –8001 1110000010111111 1110000010111111 1110000011000000 1111000001100000 –80.02 –8002 1110000010111110 1110000010111110 1110000011000000 1111000001100000 - - - - - - –159.98 –15998 1100000110000010 1100000110000010 1110000011000000 1111000001100000 –159.99 –15999 1100000110000001 1100000110000001 1110000011000000 1111000001100000 –160.00 –16000 1100000110000000 1100000110000000 1110000011000000 1111000001100000 –160.01 –16001 1100000101111111 1100000110000000 1110000011000000 1111000001100000 –160.02 –16002 1100000101111110 1100000110000000 1110000011000000 1111000001100000 - - - - - - –319.98 –31998 1000001100000010 1100000110000000 1110000011000000 1111000001100000 –319.99 –31999 1000001100000001 1100000110000000 1110000011000000 1111000001100000 –320.00 –32000 1000001100000000 1100000110000000 1110000011000000 1111000001100000 –320.01 –32001 1000001100000000 1100000110000000 1110000011000000 1111000001100000 –320.02 –32002 1000001100000000 1100000110000000 1110000011000000 1111000001100000 (1) Out-of-rangevaluesareshowningreyshading. 48 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 BusVoltageRegister02h(Read-Only) TheBusVoltageRegisterstoresthemostrecentbusvoltagereading,V . BUS Atfull-scalerange=32V(decimal=8000,hex=1F40),andLSB=4mV. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE Atfull-scalerange=16V(decimal=4000,hex=0FA0),andLSB=4mV. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT 0 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE CNVR: ConversionReady Bit1 Althoughthedatafromthelastconversioncanbereadatanytime,theTPS2480/81ConversionReadybit(CNVR) indicateswhendatafromaconversionisavailableinthedataoutputregisters.TheCNVRbitissetafterall conversions,averaging,andmultiplicationsarecomplete.CNVRwillclearunderthefollowingconditions: 1)WritinganewmodeintotheOperatingModebitsintheConfigurationRegister(exceptforPower-Downor Disable) 2.)ReadingthePowerRegister OVF: MathOverflowFlag Bit0 TheMathOverflowFlag(OVF)issetwhenthePowerorCurrentcalculationsareoutofrange.Itindicatesthat currentandpowerdatamaybemeaningless. PowerRegister03h(Read-Only) Full-scale range and LSB are set by the Calibration Register. See the TPS2480/81 Power Measurement Engine section. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE The Power Register records power in watts by multiplying the values of the current with the value of the bus voltageaccordingtotheequation: Current´BusVoltage Power = 5000 Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 SLUS939B –APRIL2010–REVISEDDECEMBER2010 www.ti.com CurrentRegister04h(Read-Only) Full-scale range and LSB depend on the value entered in the Calibration Register. See the TPS2480/81 Power MeasurementEnginesection.Negativevaluesarestoredintwo'scomplementformat. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE The value of the Current Register is calculated by multiplying the value in the Shunt Voltage Register with the valueintheCalibrationRegisteraccordingtotheequation: ShuntVoltage´Calibration Register Current = 4096 Calibration Register CalibrationRegister05h(Read/Write) CurrentandpowercalibrationaresetbybitsD15toD1oftheCalibrationRegister.NotethatbitD0isnotusedin the calculation. This register sets the current that corresponds to a full-scale drop across the shunt. Full-scale range and the LSB of the current and power measurement depend on the value entered in this register. See the TPS2480/81 Power Measurement Engine section. This register is suitable for use in overall system calibration. Notethatthe'0'PORvaluesarealldefault. BIT# D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0(1) BIT FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 NAME POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE (1) D0isavoidbitandwillalwaysbe'0'.Itisnotpossibletowritea'1'toD0.CALIBRATIONisthevaluestoredinD15:D1. 50 SubmitDocumentationFeedback Copyright©2010,TexasInstrumentsIncorporated ProductFolderLink(s):TPS2480TPS2481

TPS2480 TPS2481 www.ti.com SLUS939B –APRIL2010–REVISEDDECEMBER2010 REVISION HISTORY ChangesfromRevisionA(April,2010)toRevisionB Page • ChangedIncreasedtheinputrangefrom20-Vto26-V........................................................................................................ 1 • ChangedSimplifiedApplicationDiagramdrawingonthefirstpage..................................................................................... 1 • AddedFunctioncolumntotheDEVICEINFORMATIONTable. .......................................................................................... 2 • ChangedRECOMMENDEDOPERATINGCONDITIONSInputVoltagerangeincreaseto24.5V..................................... 2 • AddedsplitInputbiascurrentrowandupdatedvalues........................................................................................................ 6 • ChangedDesignExampleSchematicdrawing................................................................................................................... 20 • ChangedFigure17TPS2480/81LowVoltageDesignExampleSchematicdrawing ........................................................ 20 • ChangedHighVoltageApplicationdrawing. ...................................................................................................................... 25 • ChangedFigure19TPS2480/81HighVoltageApplicationdrawing .................................................................................. 25 • AddedInputTransientProtectionsection. ........................................................................................................................... 26 Copyright©2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLink(s):TPS2480TPS2481

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS2480PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2480 & no Sb/Br) TPS2480PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2480 & no Sb/Br) TPS2481PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2481 & no Sb/Br) TPS2481PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2481 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS2480PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS2481PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS2480PWR TSSOP PW 20 2000 367.0 367.0 38.0 TPS2481PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated