Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 TPIC6C596 Power Logic 8-Bit Shift Register 1 Features 3 Description • LowR ,7Ω (Typical) The TPIC6C596 device is a monolithic, medium- 1 DS(on) voltage, low-current, 8-bit shift register designed for • AvalancheEnergy,30mJ use in systems that require relatively moderate load • EightPowerDMOSTransistorOutputsof100-mA power such as LEDs. The device contains a built-in ContinuousCurrent voltage clamp on the outputs for inductive transient • 250-mACurrentLimitCapability protection. Power driver applications include relays, solenoids, and other low-current or medium-voltage • ESDProtection,2500V loads. • OutputClampVoltage,33V This device contains an 8-bit serial-in, parallel-out • EnhancedCascadingforMultipleStages shift register that feeds an 8-bit D-type storage • AllRegistersClearedWithSingleInput register. Data transfers through both the shift and • LowPowerConsumption storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), 2 Applications respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is • InstrumentationClusters high. When CLR is low, all registers in the device are • Tell-TaleLamps cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs • LEDIlluminationandControls are off. When G is held low, data from the storage • AutomotiveRelayorSolenoidsDrivers register is transparent to the output buffers. When data in the output buffers is low, the DMOS transistor LogicSymbol outputs are off. When data is high, the DMOS 8 transistoroutputshavesink-currentcapability. G EN3 RCK 10 C2 The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide 7 SRG8 CLR R additional hold time for cascaded applications. This 15 SRCK C1 will provide improved performance for applications where clock signals may be skewed, devices are not SER IN 2 1D 2 3 DRAIN0 located near one another, or the system must tolerate 4 electromagneticinterference. DRAIN1 5 DRAIN2 Outputs are low-side, open-drain DMOS transistors 6 with output ratings of 33 V and 100 mA continuous DRAIN3 11 sink-current capability. Each output provides a 250- DRAIN4 mA maximum current limit at T = 25°C. The current 12 C DRAIN5 limit decreases as the junction temperature increases 13 for additional device protection. The device also DRAIN6 14 provides up to 2500 V of ESD protection when tested 2 DRAIN7 using the human body model and the 200-V machine 9 SER OUT model. The TPIC6C596 device is characterized for operation Thissymbolisinaccordancewith over the operating case temperature range of −40°C ANSI/IEEEStd91-1984andIEC Publication617-12. to125°C. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(16) 9.90mm×3.91mm TPIC6C596 PDIP(16) 19.30mm×6.35mm TSSOP(16) 5.00mm×4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.......................................12 2 Applications........................................................... 1 8.3 FeatureDescription.................................................13 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................13 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 14 9.1 ApplicationInformation............................................14 5 PinConfigurationandFunctions......................... 3 9.2 TypicalApplication .................................................14 6 Specifications......................................................... 4 10 PowerSupplyRecommendations..................... 17 6.1 AbsoluteMaximumRatings......................................4 11 Layout................................................................... 17 6.2 ESDRatings ............................................................4 6.3 RecommendedOperatingConditions.......................4 11.1 LayoutGuidelines.................................................17 6.4 ThermalInformation..................................................5 11.2 LayoutExample....................................................18 6.5 ElectricalCharacteristics...........................................5 11.3 ThermalConsiderations........................................19 6.6 SwitchingCharacteristics..........................................6 12 DeviceandDocumentationSupport................. 20 6.7 TypicalCharacteristics..............................................7 12.1 Trademarks...........................................................20 7 ParameterMeasurementInformation..................9 12.2 ElectrostaticDischargeCaution............................20 12.3 Glossary................................................................20 8 DetailedDescription............................................ 12 13 Mechanical,Packaging,andOrderable 8.1 Overview.................................................................12 Information........................................................... 20 4 Revision History ChangesfromRevisionC(April2005)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 5 Pin Configuration and Functions D,N,orPWPackages 16-PinSOIC,PDIP,andTSSOP TopView VCC 1 16 GND SERIN 2 15 SRCK DRAIN0 3 14 DRAIN7 DRAIN1 4 13 DRAIN6 DRAIN2 5 12 DRAIN5 DRAIN3 6 11 DRAIN4 CLR 7 10 RCK G 8 9 SEROUT PinFunctions PIN I/O DESCRIPTION NAME NO. CLR 7 I Shiftregisterclear,active-low DRAIN0 3 O Open-drainoutput DRAIN1 4 O Open-drainoutput DRAIN2 5 O Open-drainoutput DRAIN3 6 O Open-drainoutput DRAIN4 11 O Open-drainoutput DRAIN5 12 O Open-drainoutput DRAIN6 13 O Open-drainoutput DRAIN7 14 O Open-drainoutput G 8 I Outputenable,active-low GND 16 — Powerground RCK 10 I Registerclock SERIN 2 I Serialdatainput SEROUT 9 O Serialdataoutput SRCK 15 I Shiftregisterclock VCC 1 I Powersupply Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT V Logicsupplyvoltage(2) –0.3 7 V CC V Logicinputvoltage –0.3 7 V I V PowerDMOSdrain-to-sourcevoltage(3) –0.3 33 V DS Continuoussource-to-draindiodeanodecurrent 250 mA Pulsedsource-to-draindiodeanodecurrent(4) 500 mA I Pulseddraincurrent,eachoutput,alloutputson,T =25°C(4) 250 mA D C I Continuousdraincurrent,eachoutput,alloutputson,T =25°C(4) 100 mA D C I Peakdraincurrentsingleoutput,T =25°C(4) 250 mA DM C E Single-pulseavalancheenergy(seeFigure11) 30 mJ AS I Avalanchecurrent(5) 200 mA AS Continuoustotaldissipation SeeThermalInformation T Operatingcasetemperature –40 125 °C C T Operatingvirtualjunctiontemperature –40 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttoGND. (3) EachpowerDMOSsourceisinternallyconnectedtoGND. (4) Pulseduration≤100μsanddutycycle≤2%. (5) DRAINsupplyvoltage=15V,startingjunctiontemperature(T )=25°C,L=1.5H,I =200mA(seeFigure11). JS AS 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±2500 V (ESD) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Logicsupplyvoltage 4.5 5.5 V CC V High-levelinputvoltage 0.85V V IH CC V Low-levelinputvoltage 0.15V V IL CC Pulseddrainoutputcurrent,T =25°C,V =5V,alloutputson(1) (2)(seeFigure7) 250 mA C CC t Setuptime,SERINhighbeforeSRCKM↑(seeFigure9) 15 ns su t Holdtime,SERINhighafterSRCKM↑,(seeFigure9) 15 ns h t Pulseduration(seeFigure9) 40 ns w T Operatingcasetemperature –40 125 °C C (1) Pulseduration≤100μsanddutycycle≤2%. (2) TechniqueshouldlimitT −T to10°Cmaximum. J C 4 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 6.4 Thermal Information TPIC6C596 THERMALMETRIC(1) PW(TSSOP) D(SOIC) N(PDIP) UNIT 16PINS 16PINS 16PINS R Junction-to-ambientthermalresistance 109.7 83.7 51.5 θJA R θJC( Junction-to-case(top)thermalresistance 44.6 45.1 38.3 top) °C/W R Junction-to-boardthermalresistance 54.8 41.2 31.4 θJB ψ Junction-to-topcharacterizationparameter 5 12.1 23.6 JT ψ Junction-to-boardcharacterizationparameter 54.2 40.9 31.3 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Drain-to-sourcebreakdown V I =1mA 33 37 V (BR)DSX voltage D Source-to-draindiodeforward V I =100mA 0.85 1.2 V SD voltage F High-leveloutputvoltage,SER IOH=−20µA, VCC=4.5V 4.4 4.49 V V OH OUT I =−4mA, V =4.5V 4 4.2 OH CC Low-leveloutputvoltage,SER IOL=20µA, VCC=4.5V 0.005 0.1 V V OL OUT I =4mA, V =4.5V 0.3 0.5 OL CC I High-levelinputcurrent V =5.5V, V =V 1 µA IH CC I CC I Low-levelinputcurrent V =5.5V, V =0 –1 µA IL CC I Alloutputsoff 20 200 I Logicsupplycurrent V =5.5V µA CC CC Alloutputson 150 500 I Logicsupplycurrentat fSRCK=5MHz, CL=30pF, 1.2 5 mA CC(FRQ) frequency Alloutputsoff, SeeFigure9andFigure2 V =0.5V, I =I , I Nominalcurrent DS(on) N D 90 mA N T =85°C See (1)(2)(3) C V =30V, V =5.5V 0.1 0.2 DS CC IDSX OFF-statedraincurrent VDS=30V V =5.5V 0.15 0.3 µA T =125°C CC C I =50mA, D 6.5 9 V =4.5V CC I =50mA, Staticdrain-sourceON-state D See (1)and(2)andFigure3 r T =125°C, 9.9 12 Ω DS(on) resistance C andFigure4 V =4.5V CC I =100mA, D 9.9 10 V =4.5V CC (1) TechniqueshouldlimitT −T to10°Cmaximum. J C (2) Theseparametersaremeasuredwithvoltage-sensingcontactsseparatefromthecurrent-carryingcontacts. (3) Nominalcurrentisdefinedforaconsistentcomparisonbetweendevicesfromdifferentsources.Itisthecurrentthatproducesavoltage dropof0.5VatT =85°C. C Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com 6.6 Switching Characteristics V =5V,T =25°C CC C PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Propagationdelaytime,low-to-high-leveloutput t 80 ns PLH fromG tPHL PfrorompaGgationdelaytime,high-to-low-leveloutput CFiLgu=re308paFn,dIDFi=gu7r5em9A,SeeFigure5, 50 ns t Risetime,drainoutput 100 ns r t Falltime,drainoutput 80 ns f t Propagationdelaytime,SRCK↓toSEROUT C =30pF,I =75mA,SeeFigure9 15 ns pd L D f Serialclockfrequency C =30pF,I =75mA(1) 10 MHz (SRCK) L D ta Reverse-recovery-currentrisetime IF=100mA,di/dt=10A/µs(2) (3), 100 ns t Reverse-recoverytime SeeFigure10 120 rr (1) Thisisthemaximumserialclockfrequencyassumingcascadedoperationwhereserialdataispassedfromonestagetoasecond stage.TheclockperiodallowsforSRCK→SEROUTpropagationdelayandsetuptimeplussometimingmargin. (2) TechniqueshouldlimitT −T to10°Cmaximum. J C (3) Theseparametersaremeasuredwithvoltage-sensingcontactsseparatefromthecurrent-carryingcontacts. 6 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 6.7 Typical Characteristics 1 6 TC=25°C VCC= 5 V TC=−40C°to125°C A 5 − ent mA Curr nt− 4 nche 0.1 Curre 3 Avala upply eak −S 2 P C − C S I IA 1 0.01 0 0.1 1 10 0.1 1 10 100 tav−TimeDurationofAvalanche−ms f−Frequency−MHz Figure1.PeakAvalancheCurrent Figure2.SupplyCurrentvsFrequency vsTimeDurationofAvalanche Ω 30 Ω n-State Resistance− 2205 VSeCeC N=o 5te VA TC= 125°C On-State Resistance− 11802 TC= 125°C ISDee= N50o tmeAA Source O 15 o-Source 6 TC= 25°C ain-to- 10 TC= 25°C Drain-t 4 TC=−40°C −Dron) 5 TC=−40°C −Static 2 rDS( 0 S(on) 0 50 70 90 110 130 150 170 190 221500 rD 4.0 4.5 5.0 5.5 6.0 6.5 7.0 ID−Drain Current−mA VCC−Logic Supply Voltage−V TechniqueshouldlimitT −T to10°Cmaximum. J C Figure3.Drain-to-SourceON-StateResistance Figure4.StaticDrain-to-SourceON-StateResistance vsDrainCurrent vsLogicSupplyVoltage 140 A ISDee= N75o tmeAA tr put− 0.25 120 Out VCC= 5 V h 100 tf Eac 0.20 −Tnsime 80 tPLH Currentof 0.15 TC= 25°C witching 60 tPHL ousDrain 0.10 TC= 100°C S 40 nu nti Co 0.05 TC= 125°C 20 m u m 0 Maxi 0.00 −50 −25 0 25 50 75 100 125 − 1 2 3 4 5 6 7 8 D TC−CaseTemperature−°C I N−NumberofOutputsConductingSimultaneously TechniqueshouldlimitT −T to10°Cmaximum J C Figure5.SwitchingTimevsCaseTemperature Figure6. MaximumContinuousDrainCurrentof EachOutputvsNumberofOutputsConducting Simultaneously Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com Typical Characteristics (continued) A 0.30 − ut utp d=10% O 0.25 h c Ea d = 20% of 0.20 nt e d = 50% urr C 0.15 n ai d = 80% Dr ak 0.10 e P mum 0.05 VTCCC= =2 55° CV axi d = tw/tperiod M = 1 ms/tperiod −D 0.00 I 1 2 3 4 5 6 7 8 N−Number of Outputs Conducting Simultaneously Figure7.MaximumPeakDrainCurrentof EachOutputvsNumberofOutputsConductingSimultaneously 8 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 7 Parameter Measurement Information 5 V 15 V 7 6 5 4 3 2 1 0 5 V SRCK 1 7 VCC ID 0 V CLR 5 V G 15 RL= 200Ω 0 V SRCK DUT 3−6, Output 5 V Word 2 SER IN DRAIN 11−14 SER IN 0 V Generator 5 V (see NoteA) 10 RCK CL= 30 pF RCK 0 V (see Note B) 8 5 V G CLR 0 V GND 15 V 16 DRAIN1 0.5V TESTCIRCUIT VOLTAGEWAVEFORMS NOTES: A. Thewordgeneratorhasthefollowingcharacteristics:tr≤10ns,tf≤10ns,tw=300ns,pulsedrepetitionrate(PRR)=5kHz, ZO= 50Ω. B. CLincludes probe and jig capacitance. Figure8. Resistive-LoadTestCircuitandVoltageWaveforms Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com Parameter Measurement Information (continued) 5 V G 50% 50% 0 V 5V 15V tPLH tPHL 1 24 V 90% 90% 7 CLR VCC ID Output 10% 10%0.5 V 15 RL= 200Ω SRCK 3−6, tr tf Word DUT Output 2 11−14 SWITCHING TIMES Generator SER IN DRAIN (see NoteA) 5 V 10 RCK CL= 30 pF SRCK 50% 8 (see Note B) 0 V G GND tsu th 16 5 V SER IN 50% 50% TESTCIRCUIT 0 V tw INPUTSETUPANDHOLDWAVEFORMS SRCK 50% 50% tpd tpd SER OUT 50% 50% SEROUTPROPAGATIONDELAYWAVEFORM NOTES: A. Thewordgeneratorhasthefollowingcharacteristics:tr≤10ns,tf≤10ns,tw=300ns,pulsedrepetitionrate(PRR)=5kHz, ZO= 50Ω. B. CLincludes probe and jig capacitance. Figure9. TestCircuit,SwitchingTimes,andVoltageWaveforms 10 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 Parameter Measurement Information (continued) TPK DRAIN 0.1A Circuit 2500µF Under 250 V di/dt = 10A/µs Test + IF L= 0.85 mH 15 V IF − (see NoteA) 0 TPA 25% of IRM t2 t1 t3 Driver IRM RG VGG 50Ω ta (see Note B) trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. TheDRAIN terminal under test is connected to theTPK test point.All other terminals are connected together and connected to the TPAtestpoint. B. TheVGGamplitude and RGare adjusted for di/dt = 10A/µs.AVGGdouble-pulse train is used to set IF=0.1A,wheret1= 10µs, t2= 7µs, and t3= 3µs. Figure10. Reverse-Recovery-CurrentTestCircuitandWaveformsofSource-to-DrainDiode 5 V 15V tw 1 tav 7 VCC 30Ω 5 V CLR Input 15 SRCK ID See Note B 0 V DUT Word 2 1.5 H IAS= 200 mA SER IN Generator 3−6, ID (see NoteA) 10 11−14 RCK DRAIN VDS 8 G GND V(BR)DSX= 33 V VDS MIN 16 SINGLE-PULSEAVALANCHEENERGYTESTCIRCUIT VOLTAGEAND CURRENT WAVEFORMS NOTES: A. Thewordgeneratorhasthefollowingcharacteristics:tr≤10 ns, tf≤10 ns, ZO= 50Ω. B. Inputpulseduration,tw, is increased until peak current IAS= 200 mA. Energy test level is defined as EAS= IAS×V(BR)DSX×tav/2 = 30 mJ. Figure11. Single-PulseAvalancheEnergyTestCircuitandWaveforms Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com 8 Detailed Description 8.1 Overview The TPIC6C596 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection, so it can also drive relays, solenoids, and other low-current or medium-voltage loads. 8.2 Functional Block Diagram 8 G 10 RCK 3 7 DRAIN0 CLR D D 15 SRCK C1 C2 CLR CLR 4 2 DRAIN1 SERIN D D C1 C2 CLR CLR 5 DRAIN2 D D C1 C2 CLR CLR 6 DRAIN3 D D C1 C2 CLR CLR 11 DRAIN4 D D C1 C2 CLR CLR 12 DRAIN5 D D C1 C2 CLR CLR 13 DRAIN6 D D C1 C2 CLR CLR 14 DRAIN7 D D C1 C2 CLR CLR 16 GND D C1 9 CLR SER OUT Figure12. LogicDiagram(PositiveLogic) 12 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 8.3 Feature Description 8.3.1 Serial-InInterface The TPIC6C596 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregisterclear(CLR)ishigh. 8.3.2 ClearRegister A logical low on CLR clears all registers in the device. TI suggests clearing the device during power up or initialization. 8.3.3 OutputControl Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sink- current.ThispincanalsobeusedforglobalPWMdimming. 8.4 Device Functional Modes 8.4.1 OperationWithV(VIN)< 4.5V(MinimumV ) (VIN) This device works normally during 4.5 V ≤ V(VIN) ≤ 5.5 V, when operation voltage is lower than 4.5 V. The behaviorofdevicecan'tbeensured,includingcommunicationinterfaceandcurrentcapability. 8.4.2 OperatingWith5.5V < V(VIN) <6V This device works normally during this voltage range, but reliability issues may occurs while the device works for alongtimeinthisvoltagerange. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The TPIC6C596 device is a serial-in parallel-out, Power+LogicE 8-bit shift register with low-side switch DMOS outputs rating of a 100 mA per channel. The device is designed to drive resistive and inductive loads and is particularly well-suited as an interface between a microcontroller and LEDs or lamps. The TPIC6C596 device is an enhancement of the TPIC6C595 device, where the shift register serial output (SER OUT) is clocked on the falling edge of the serial clock to provide additional hold-time in applications where several devices are cascaded. 9.1.1 CascadedApplication The serial output (SEROUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. Connect the device (SEROUT) pin to the next device (SERIN) for daisy Chain. This provides improved performance for applications where clock signals may be skewed, devices are not located nearoneanother,orthesystemmusttolerateelectromagneticinterference. EQUIVALENT OF EACH INPUT TYPICALOFALLDRAIN OUTPUTS VCC DRAIN 33 V Input 25 V 20 V 12 V GND GND Figure13. SchematicofInputsandOutputs 9.2 Typical Application The typical application of TPIC6C596 device is an automotive cluster driver. In this example, two TPIC6C596 power shift registers are cascaded and used to turn on LEDs in the cluster panel. In this case, the LED must be updated after all 16 bits of data have been loaded into the serial shift registers. The MCU outputs the data to the serial input (SER IN) while clocking the shift register clock (SRCK). After the 16th clock, a pulse to the register clock (RCK) transfers the data to the storage registers. If output enable (G) is low, then the LEDs are turned on corresponding to the status word with ones being on and zeros off. With this simple scheme, MCU can use the SPIinterfacetoturnon16LEDsusingonlytwoICsasillustratedinFigure14. 14 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 Typical Application (continued) Vbattery Vbattery 5V 5V R1 R2 R3 R4 R5 R6 R7 R8 R9 R9 R9 R9 R9 R9 R9 R9 0.1uF 0.1uF 10kŸ 10kŸ VCC VCC TPIC6C596 TPIC6C596 DRAIN0 D1 D2 D3 D4 D5 D6 D7 D8 DRAIN0 D9 D10 D11 D12 D13 D14 D15 D16 SRCK DRAIN1 SRCK DRAIN1 RCK DRQIN2 RCK DRQIN2 MCU SER IN DRAIN3 SER IN DRAIN3 CLR DRAIN4 CLR DRAIN4 G DRAIN5 G DRAIN5 DRAIN6 DRAIN6 DRAIN7 DRAIN7 TO SERIAL INPUT OF THE NEXT SER OUT SER OUT STAGE GND GND Figure14. TypicalApplicationSchematic 9.2.1 DesignRequirements Table1liststhedesignparametersforFigure14. Table1.DesignParameters DESIGNPARAMTER EXAMPLEVALUE Vsupply 9to16V V(D1),V(D2),V(D3),V(D4),V(D5),V(D6),V(D7),V(D8) 2V V(D9),V(D10),V(D11),V(D12),V(D13),V(D14),V(D15),V 3.3V (D16) I(D1),I(D2),I(D3),I(D4),I(D5),I(D6),I(D7),I(D8) 20mAwhenVbatteryis12V I(D9),I(D10),I(D11),I(D12),I(D13),I(D14),I(D15),I(D16) 30mAwhenVbatteryis12V 9.2.2 DetailedDesignProcedure To begin the design process, the designer must decide on a few parameters. The designer must know the following: • Vsupply: LED supply is connected directly to the car battery, which has a voltage range from 9 V to 16 V, or fixedvoltage.Thisapplicationconnectstothebatterydirectly. • V(Dx):LEDforwardvoltage • I(Dx):LEDsettingcurrentwhenbatteryis12V. 9.2.2.1 R1,R2,R3,R4,R5,R6,R7,R8R1=R2=R3=R4=R5=R6=R7=R8= (Vsupply –V(Dx))/I(Dx)=(12V – 2V)/0.02A=500Ω WhenVsupplyis9V,I(D1)=I(D2)=I(D3)=I(D4)=I(D5)=I(D6)=I(D7)=I(D8)=(Vsupply –V(Dx))/Rx =14mA. When Vsupply is 16 V, I (D9) = I (D10) = I (D11) = I (D12) = I (D13) = I (D14) = I (D15) = I (D16) =(Vsupply – V(Dx))/Rx=43.8mA. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com NOTE If designers can accept the current variation when battery voltage is changing, they can connect the device directly to the battery. If a designer need the less variation of current, they need to use the voltage regulator as supply voltage of LED, or change to constant currentLEDdriverdirectly 9.2.3 ApplicationCurve Figure15.CH1isSRCK,CH2isRCK,CH3isSERINand CH4isD1Current 16 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 10 Power Supply Recommendations The TPIC6C596 device is designed to operate from an input voltage supply range from 4.5 V and 5.5 V. This inputsupplyshouldbewellregulated.TIrecommendsplacingtheceramicbypasscapacitorsneartheVCCpin. 11 Layout 11.1 Layout Guidelines There is no special layout requirement for the digital signal pin; the only requirement is placing the ceramic bypass capacitors near the corresponding pin. Because the TPIC6C596 device does not have a thermal shutdown protection function, to prevent thermal damage, T must be less than 150°C. If the total sink current is J high, the power dissipation might be large. The devices are currently not available in the thermal pad package, so good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the device. Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the major heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely importantwhenthedesigndoesnotincludeheatsinksattachedtothePCBontheothersideofthepackage. • Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivityoftheboard. • All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent soldervoids.Toensurereliabilityandperformance,thesoldercoverageshouldbeatleast85%. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com 11.2 Layout Example Power Ground both in TOP and Bottom Vcc GND TPIC6C596 VIA to Ground SER IN SRCK DRAIN0 DRAIN7 DRAIN1 DRAIN6 DRAIN2 DRAIN5 DRAIN3 DRAIN4 CLR RCK SER OUT G Figure16. RecommendedLayoutExample 18 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

TPIC6C596 www.ti.com SLIS093D–MARCH2000–REVISEDMARCH2015 11.3 Thermal Considerations 10 W C/ °− DC Conditions e 1 nc d = 0.5 a st esi d = 0.2 R mal d = 0.1 Ther 0.1 d = 0.05 nt e mbi d = 0.02 A n-to- d = 0.01 ctio 0.01 n u d J Single Pulse e aliz m or N 0.001 −A tc θJ tw R ID 0 0.0001 0.0001 0.001 0.01 0.1 1 10 tw−Pulse Duration−s †Device mounted on FR4 printed-circuit board with no heat sink NOTES: ZθA(t) = r(t) RθJA tw= pulse duration tc= cycle time d = duty cycle = tw/tc Figure17. DPackage†,NormalizedJunction-to-AmbientThermalResistancevsPulseDuration Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPIC6C596

TPIC6C596 SLIS093D–MARCH2000–REVISEDMARCH2015 www.ti.com 12 Device and Documentation Support 12.1 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 12.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPIC6C596

PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPIC6C596D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6C596 & no Sb/Br) TPIC6C596DG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 6C596 & no Sb/Br) TPIC6C596DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6C596 & no Sb/Br) TPIC6C596DRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 6C596 & no Sb/Br) TPIC6C596DRQ1 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 6C596Q & no Sb/Br) TPIC6C596N ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 125 TPIC6C596 (RoHS) TPIC6C596PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 6C596PW & no Sb/Br) TPIC6C596PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 6C596PW & no Sb/Br) TPIC6C596PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 6C596PW & no Sb/Br) TPIC6C596PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 6C596PW & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPIC6C596DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPIC6C596DRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPIC6C596PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPIC6C596PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPIC6C596DR SOIC D 16 2500 367.0 367.0 38.0 TPIC6C596DRQ1 SOIC D 16 2500 367.0 367.0 38.0 TPIC6C596PWR TSSOP PW 16 2000 350.0 350.0 43.0 TPIC6C596PWRG4 TSSOP PW 16 2000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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