TNY274-280 TinySwitch®-III Family Energy-Effi cient, Off-Line Switcher With Enhanced Flexibility and Extended Power Range Product Highlights + + Lowest System Cost with Enhanced Flexibility DC • Simple ON/OFF control, no loop compensation needed Output • Selectable current limit through BP/M capacitor value - • Higher current limit extends peak power or, in open Wide-Range D frame applications, maximum continuous power HV DC Input EN/UV • Lower current limit improves effi ciency in enclosed TinySwitch-III BP/M adapters/chargers S • Allows optimum TinySwitch-III choice by swapping - devices with no other circuit redesign PI-4095-082205 • Tight I2f parameter tolerance reduces system cost • Maximizes MOSFET and magnetics power delivery Figure 1. Typical Standby Application. • Minimizes max overload power, reducing cost of transformer, primary clamp & secondary components • ON-time extension – extends low line regulation range/hold-up Output Power Table time to reduce input bulk capacitance 230 VAC ± 15% 85-265 VAC • Self-biased: no bias winding or bias components • Frequency jittering reduces EMI fi lter costs Product3 Adapter1 POeapke nor Adapter1 POeapke nor • Pin-out simplifi es heatsinking to the PCB Frame2 Frame2 • SOURCE pins are electrically quiet for low EMI TNY274P/G 6 W 11 W 5 W 8.5 W Enhanced Safety and Reliability Features TNY275P/G 8.5 W 15 W 6 W 11.5 W • Accurate hysteretic thermal shutdown protection with TNY276P/G 10 W 19 W 7 W 15 W automatic recovery eliminates need for manual reset TNY277P/G 13 W 23.5 W 8 W 18 W • Improved auto-restart delivers <3% of maximum power in short TNY278P/G 16 W 28 W 10 W 21.5 W circuit and open loop fault conditions • Output overvoltage shutdown with optional Zener TNY279P/G 18 W 32 W 12 W 25 W • Line undervoltage detect threshold set using a single optional TNY280P/G 20 W 36.5 W 14 W 28.5 W resistor Table 1. Output Power Table. • Very low component count enhances reliability and enables Notes: single-sided printed circuit board layout 1. Minimum continuous power in a typical non-ventilated enclosed adapter • High bandwidth provides fast turn on with no overshoot and measured at +50 °C ambient. Use of an external heatsink will increase power excellent transient load response capability. 2. Minimum peak power capability in any design or minimum continuous power in • Extended creepage between DRAIN and all other pins improves an open frame design (see Key Applications Considerations). fi eld reliability 3. Packages: P: DIP-8C, G: SMD-8C. See Part Ordering Information. EcoSmart®– Extremely Energy Effi cient • Easily meets all global energy effi ciency regulations Description • No-load <150 mW at 265 VAC without bias winding, <50 mW TinySwitch-III incorporates a 700 V power MOSFET, oscillator, with bias winding high voltage switched current source, current limit (user • ON/OFF control provides constant effi ciency down to very light selectable) and thermal shutdown circuitry. The IC family uses an loads – ideal for mandatory CEC regulations and 1 W PC ON/OFF control scheme and offers a design fl exible solution with standby requirements a low system cost and extended power capability. Applications • Chargers/adapters for cell/cordless phones, PDAs, digital cameras, MP3/portable audio, shavers, etc. • PC Standby and other auxiliary supplies • DVD/PVR and other low power set top decoders • Supplies for appliances, industrial systems, metering, etc. www.powerint.com January 2009

TNY274-280 BYPASS/ MULTI-FUNCTION DRAIN (BP/M) (D) REGULATOR 5.85 V LINE UNDER-VOLTAGE 115 μA 25 μA FAULT BYPASS PIN PRESENT + UNDER-VOLTAGE AUTO- BYPASS RESTART CAPACITOR - COUNTER SELECT AND 5.85 V V CURRENT 4.9 V ILIMIT 6.4 V RESET LIMIT STATE MACHINE CURRENT LIMIT COMPARATOR ENABLE - + JITTER CLOCK 1.0 V + V T DCMAX THERMAL SHUTDOWN OSCILLATOR ENABLE/ S Q 1.0 V UNDER- VOLTAGE (EN/UV) R Q LEADING OVP EDGE LATCH BLANKING SOURCE (S) PI-4077-062306 Figure 2. Functional Block Diagram. Pin Functional Description P Package (DIP-8C) DRAIN (D) Pin: G Package (SMD-8C) This pin is the power MOSFET drain connection. It provides internal operating current for both startup and steady-state operation. EN/UV 1 8 S BYPASS/MULTI-FUNCTION (BP/M) Pin: BP/M 2 7 S This pin has multiple functions: 6 S 1. It is the connection point for an external bypass capacitor for D 4 5 S the internally generated 5.85 V supply. 2. It is a mode selector for the current limit value, depending on the value of the capacitance added. Use of a 0.1 μF capacitor results in the standard current limit value. Use of a 1 μF capacitor results in the current limit being reduced to PI-4078-080905 that of the next smaller device size. Use of a 10 μF capacitor Figure 3. Pin Confi guration. results in the current limit being increased to that of the next larger device size for TNY275-280. ENABLE/UNDERVOLTAGE (EN/UV) Pin: 3. It provides a shutdown function. When the current into the This pin has dual functions: enable input and line undervoltage bypass pin exceeds I , the device latches off until the sense. During normal operation, switching of the power SD BP/M voltage drops below 4.9 V, during a power down. This MOSFET is controlled by this pin. MOSFET switching is can be used to provide an output overvoltage function with a terminated when a current greater than a threshold current is Zener connected from the BP/M pin to a bias winding supply. drawn from this pin. Switching resumes when the current being 2 Rev. I 01/09 www.powerint.com

TNY274-280 pulled from the pin drops to less than a threshold current. A measured with the oscilloscope triggered at the falling edge of modulation of the threshold current reduces group pulsing. The the DRAIN waveform. The waveform in Figure 4 illustrates the threshold current is between 75 μA and 115 μA. frequency jitter. The EN/UV pin also senses line undervoltage conditions through Enable Input and Current Limit State Machine an external resistor connected to the DC line voltage. If there is The enable input circuit at the EN/UV pin consists of a low no external resistor connected to this pin, TinySwitch-III detects impedance source follower output set at 1.2 V. The current its absence and disables the line undervoltage function. through the source follower is limited to 115 μA. When the current out of this pin exceeds the threshold current, a low logic SOURCE (S) Pin: level (disable) is generated at the output of the enable circuit, This pin is internally connected to the output MOSFET source for until the current out of this pin is reduced to less than the high voltage power return and control circuit common. threshold current. This enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. If TinySwitch-III Functional Description high, the power MOSFET is turned on for that cycle (enabled). If low, the power MOSFET remains off (disabled). Since the TinySwitch-III combines a high voltage power MOSFET switch sampling is done only at the beginning of each cycle, with a power supply controller in one device. Unlike conventional subsequent changes in the EN/UV pin voltage or current during PWM (pulse width modulator) controllers, it uses a simple the remainder of the cycle are ignored. ON/OFF control to regulate the output voltage. The current limit state machine reduces the current limit by The controller consists of an oscillator, enable circuit (sense and discrete amounts at light loads when TinySwitch-III is likely to logic), current limit state machine, 5.85 V regulator, BYPASS/ switch in the audible frequency range. The lower current limit MULTI-FUNCTION pin undervoltage, overvoltage circuit, and raises the effective switching frequency above the audio range current limit selection circuitry, over-temperature protection, and reduces the transformer fl ux density, including the current limit circuit, leading edge blanking, and a 700 V power associated audible noise. The state machine monitors the MOSFET. TinySwitch-III incorporates additional circuitry for line sequence of enable events to determine the load condition and undervoltage sense, auto-restart, adaptive switching cycle on- adjusts the current limit level accordingly in discrete amounts. time extension, and frequency jitter. Figure 2 shows the functional block diagram with the most important features. Under most operating conditions (except when close to no- load), the low impedance of the source follower keeps the Oscillator voltage on the EN/UV pin from going much below 1.2 V in the The typical oscillator frequency is internally set to an average of disabled state. This improves the response time of the 132 kHz. Two signals are generated from the oscillator: the optocoupler that is usually connected to this pin. maximum duty cycle signal (DC ) and the clock signal that MAX indicates the beginning of each cycle. 5.85 V Regulator and 6.4 V Shunt Voltage Clamp The 5.85 V regulator charges the bypass capacitor connected The oscillator incorporates circuitry that introduces a small to the BYPASS pin to 5.85 V by drawing a current from the amount of frequency jitter, typically 8 kHz peak-to-peak, to voltage on the DRAIN pin whenever the MOSFET is off. The minimize EMI emission. The modulation rate of the frequency BYPASS/MULTI-FUNCTION pin is the internal supply voltage jitter is set to 1 kHz to optimize EMI reduction for both average node. When the MOSFET is on, the device operates from the and quasi-peak emissions. The frequency jitter should be energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows TinySwitch-III to 600 1 0 operate continuously from current it takes from the DRAIN pin. 9 1 500 1-04 A bypass capacitor value of 0.1 μF is suffi cient for both high 4 frequency decoupling and energy storage. V 7 400 DRAIN PI-2 In addition, there is a 6.4 V shunt regulator clamping the 300 BYPASS/MULTI-FUNCTION pin at 6.4 V when current is provided to the BYPASS/MULTI-FUNCTION pin through an 200 external resistor. This facilitates powering of TinySwitch-III externally through a bias winding to decrease the no-load 100 consumption to well below 50 mW. 0 BYPASS/MULTI-FUNCTION Pin Undervoltage 136 kHz The BYPASS/MULTI-FUNCTION pin undervoltage circuitry 128 kHz disables the power MOSFET when the BYPASS/MULTI- FUNCTION pin voltage drops below 4.9 V in steady state operation. Once the BYPASS/MULTI-FUNCTION pin voltage 0 5 10 drops below 4.9 V in steady state operation, it must rise back to Time (μs) 5.85 V to enable (turn-on) the power MOSFET. Figure 4. Frequency Jitter. 3 www.powerint.com Rev. I 01/09

TNY274-280 Over Temperature Protection Adaptive Switching Cycle On-Time Extension The thermal shutdown circuitry senses the die temperature. Adaptive switching cycle on-time extension keeps the cycle on The threshold is typically set at 142 °C with 75 °C hysteresis. until current limit is reached, instead of prematurely terminating When the die temperature rises above this threshold the power after the DC signal goes low. This feature reduces the MAX MOSFET is disabled and remains disabled until the die minimum input voltage required to maintain regulation, temperature falls by 75 °C, at which point it is re-enabled. A extending hold-up time and minimizing the size of bulk large hysteresis of 75 °C (typical) is provided to prevent over- capacitor required. The on-time extension is disabled during the heating of the PC board due to a continuous fault condition. startup of the power supply, until the power supply output reaches regulation. Current Limit The current limit circuit senses the current in the power Line Undervoltage Sense Circuit MOSFET. When this current exceeds the internal threshold The DC line voltage can be monitored by connecting an (I ), the power MOSFET is turned off for the remainder of that external resistor from the DC line to the EN/UV pin. During LIMIT cycle. The current limit state machine reduces the current limit power up or when the switching of the power MOSFET is threshold by discrete amounts under medium and light loads. disabled in auto-restart, the current into the EN/UV pin must exceed 25 μA to initiate switching of the power MOSFET. During The leading edge blanking circuit inhibits the current limit power up, this is accomplished by holding the BYPASS/MULTI- comparator for a short time (t ) after the power MOSFET is FUNCTION pin to 4.9 V while the line undervoltage condition LEB turned on. This leading edge blanking time has been set so that exists. The BYPASS/MULTI-FUNCTION pin then rises from current spikes caused by capacitance and secondary-side 4.9 V to 5.85 V when the line undervoltage condition goes rectifi er reverse recovery time will not cause premature away. When the switching of the power MOSFET is disabled in termination of the switching pulse. auto-restart mode and a line undervoltage condition exists, the auto-restart counter is stopped. This stretches the disable time Auto-Restart beyond its normal 2.5 seconds until the line undervoltage In the event of a fault condition such as output overload, output condition ends. short circuit, or an open loop condition, TinySwitch-III enters into auto-restart operation. An internal counter clocked by the The line undervoltage circuit also detects when there is no oscillator is reset every time the EN/UV pin is pulled low. If the external resistor connected to the EN/UV pin (less than ~2 μA EN/UV pin is not pulled low for 64 ms, the power MOSFET into the pin). In this case the line undervoltage function is switching is normally disabled for 2.5 seconds (except in the disabled. case of line undervoltage condition, in which case it is disabled until the condition is removed). The auto-restart alternately TinySwitch-III Operation enables and disables the switching of the power MOSFET until the fault condition is removed. Figure 5 illustrates auto-restart TinySwitch-III devices operate in the current limit mode. When circuit operation in the presence of an output short circuit. enabled, the oscillator turns the power MOSFET on at the beginning of each cycle. The MOSFET is turned off when the In the event of a line undervoltage condition, the switching of current ramps up to the current limit or when the DC limit is MAX the power MOSFET is disabled beyond its normal 2.5 seconds reached. Since the highest current limit level and frequency of a until the line undervoltage condition ends. TinySwitch-III design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. Hence, designing the supply 320000 VDRAIN PI-4098-082305 ifacnopavrlp octrhluvoeleap stmre iacdata xeilniclmydu cuulahmctoitn asogneu ctnthep fe uow tpr i plrtl hiomreawa mperoypr w riuneepdqr uu tloecir vtecaedunl.,r c rItfeeh t neoht ef c l itumThriernite ytnbrSate wnifnosit rfcteohh ret-mh IIeIe irs DC limit is reached. MAX 100 Enable Function TinySwitch-III senses the EN/UV pin to determine whether or 0 not to proceed with the next switching cycle. The sequence of 10 cycles is used to determine the current limit. Once a cycle is V started, it always completes the cycle (even when the EN/UV 5 DC-OUTPUT pin changes state half way through the cycle). This operation results in a power supply in which the output voltage ripple is 0 determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback. 0 2500 5000 The EN/UV pin signal is generated on the secondary by Time (ms) comparing the power supply output voltage with a reference voltage. The EN/UV pin signal is high when the power supply Figure 5. Auto-Restart Operation. output voltage is less than the reference voltage. 4 Rev. I 01/09 www.powerint.com

TNY274-280 In a typical implementation, the EN/UV pin is driven by an ON/OFF Operation with Current Limit State Machine optocoupler. The collector of the optocoupler transistor is The internal clock of the TinySwitch-III runs all the time. At the connected to the EN/UV pin and the emitter is connected to the beginning of each clock cycle, it samples the EN/UV pin to SOURCE pin. The optocoupler LED is connected in series with decide whether or not to implement a switch cycle, and based a Zener diode across the DC output voltage to be regulated. on the sequence of samples over multiple cycles, it determines When the output voltage exceeds the target regulation voltage the appropriate current limit. At high loads, the state machine level (optocoupler LED voltage drop plus Zener voltage), the sets the current limit to its highest value. At lighter loads, the optocoupler LED will start to conduct, pulling the EN/UV pin state machine sets the current limit to reduced values. low. The Zener diode can be replaced by a TL431 reference circuit for improved accuracy. V V EN EN CLOCK CLOCK DC DC MAX MAX IDRAIN IDRAIN VDRAIN VDRAIN PI-2749-082305 PI-2667-082305 Figure 6. Operation at Near Maximum Loading. Figure 7. Operation at Moderately Heavy Loading. V V EN EN CLOCK CLOCK DCMAX DCMAX IDRAIN IDRAIN VDRAIN VDRAIN PI-2377-082305 PI-2661-082305 Figure 8. Operation at Medium Loading. Figure 9. Operation at Very Light Load. 5 www.powerint.com Rev. I 01/09

TNY274-280 At near maximum load, TinySwitch-III will conduct during nearly (Figure 9). Only a small percentage of cycles will occur to satisfy all of its clock cycles (Figure 6). At slightly lower load, it will the power consumption of the power supply. “skip” additional cycles in order to maintain voltage regulation at the power supply output (Figure 7). At medium loads, cycles The response time of the ON/OFF control scheme is very fast will be skipped and the current limit will be reduced (Figure 8). compared to PWM control. This provides tight regulation and At very light loads, the current limit will be reduced even further excellent transient response. 1200000 VDC-INPUT PI-2383-030801 1200000 VDC-INPUT PI-2381-1030801 10 10 5 VBYPASS 5 VBYPASS 0 0 400 400 200 V 200 V DRAIN DRAIN 0 0 0 1 2 0 1 2 Time (ms) Time (ms) Figure 11. Power Up Without Optional External UV Resistor Figure 10. Power Up with Optional External UV Resistor (4 MΩ) Connected to EN/UV Pin. Connected to EN/UV Pin. 200 V PI-2348-030801 200 V PI-2395-030801 100 DC-INPUT 100 DC-INPUT 0 0 400 400 300 300 200 VDRAIN 200 VDRAIN 100 100 0 0 0 .5 1 0 2.5 5 Time (s) Time (s) Figure 12. Normal Power Down Timing (without UV). Figure 13. Slow Power Down Timing with Optional External (4 MΩ) UV Resistor Connected to EN/UV Pin. 6 Rev. I 01/09 www.powerint.com

TNY274-280 Power Up/Down Functional Description). This has two main benefi ts. First, for a The TinySwitch-III requires only a 0.1 μF capacitor on the nominal application, this eliminates the cost of a bias winding BYPASS/MULTI-FUNCTION pin to operate with standard and associated components. Secondly, for battery charger current limit. Because of its small size, the time to charge this applications, the current-voltage characteristic often allows the capacitor is kept to an absolute minimum, typically 0.6 ms. The output voltage to fall close to zero volts while still delivering time to charge will vary in proportion to the BYPASS/MULTI- power. TinySwitch-III accomplishes this without a forward bias FUNCTION pin capacitor value when selecting different current winding and its many associated components. For applications limits. Due to the high bandwidth of the ON/OFF feedback, that require very low no-load power consumption (50 mW), a there is no overshoot at the power supply output. When an resistor from a bias winding to the BYPASS/MULTI-FUNCTION external resistor (4 MΩ) is connected from the positive DC input pin can provide the power to the chip. The minimum to the EN/UV pin, the power MOSFET switching will be delayed recommended current supplied is 1 mA. The BYPASS/MULTI- during power up until the DC line voltage exceeds the threshold FUNCTION pin in this case will be clamped at 6.4 V. This (100 V). Figures 10 and 11 show the power up timing waveform method will eliminate the power draw from the DRAIN pin, in applications with and without an external resistor (4 MΩ) thereby reducing the no-load power consumption and connected to the EN/UV pin. improving full-load effi ciency. Under startup and overload conditions, when the conduction Current Limit Operation time is less than 400 ns, the device reduces the switching Each switching cycle is terminated when the DRAIN current frequency to maintain control of the peak drain current. reaches the current limit of the device. Current limit operation provides good line ripple rejection and relatively constant power During power down, when an external resistor is used, the delivery independent of input voltage. power MOSFET will switch for 64 ms after the output loses BYPASS/MULTI-FUNCTION Pin Capacitor regulation. The power MOSFET will then remain off without any The BYPASS/MULTI-FUNCTION pin can use a ceramic glitches since the undervoltage function prohibits restart when the line voltage is low. capacitor as small as 0.1 μF for decoupling the internal power supply of the device. A larger capacitor size can be used to Figure 12 illustrates a typical power down timing waveform. adjust the current limit. For TNY275-280, a 1 μF BP/M pin capacitor will select a lower current limit equal to the standard Figure 13 illustrates a very slow power down timing waveform as in standby applications. The external resistor (4 MΩ) is current limit of the next smaller device and a 10 μF BP/M pin capacitor will select a higher current limit equal to the standard connected to the EN/UV pin in this case to prevent unwanted current limit of the next larger device. The higher current limit restarts. level of the TNY280 is set to 850 mA typical. The TNY274 MOSFET does not have the capability for increased current limit No bias winding is needed to provide power to the chip so this feature is not available in this device. because it draws the power directly from the DRAIN pin (see 7 www.powerint.com Rev. I 01/09

TNY274-280 C5 2.2 nF 250 VAC L2 P6KVER 115 0A NC T1 8 BYVD2 87- 200 3F.e5r ×rit e7 .B6 emamd 12 V, 1 A C10 C11 D1 D2 R2 1000 μF 100 μF 1N4007 1N4007 100 Ω 1 6 25 V 25 V F1 3.15 A C1 C2 R1 C4 RTN 85V -A 2C65 27R5 VV1A C 64.080 μ VF 42020 μ VF 1 k Ω 110 k nVF 3 4 2R0 7Ω 1N40D057 GP 2 D6 3.R6 5M* Ω UF4 003 D3 D4 5 1N4007 1N4007 1 Lm1 H 1N2V58R2 5V25 B 61C0 μ6 VF BZX1V71R9 V3-C 11 R3 47 Ω *R5 and R8 are optional 1/8 W R6 components 390 Ω R8* 1/8 W 21 kΩ † C7 is used to adjust U1 1% U2 current limit. See circuit D EN/UV PC817A description S BP/M S R4 TinySwitch-III C7 † 2 kΩ U1 100 nF 1/8 W TNY278PN 50 V PI-4244-111708 Figure 14. TNY278P, 12 V, 1 A Universal Input Power Supply. Applications Example voltage falls below the feedback threshold, a conduction cycle is allowed to occur and, by adjusting the number of enabled The circuit shown in Figure 14 is a low cost, high effi ciency, cycles, output regulation is maintained. As the load reduces, fl yback power supply designed for 12 V, 1 A output from the number of enabled cycles decreases, lowering the effective universal input using the TNY278. switching frequency and scaling switching losses with load. This provides almost constant effi ciency down to very light The supply features undervoltage lockout, primary sensed loads, ideal for meeting energy effi ciency requirements. output overvoltage latching shutdown protection, high effi ciency (>80%), and very low no-load consumption (<50 mW As the TinySwitch-III devices are completely self-powered, there at 265 VAC). Output regulation is accomplished using a simple is no requirement for an auxiliary or bias winding on the zener reference and optocoupler feedback. transformer. However by adding a bias winding, the output overvoltage protection feature can be confi gured, protecting the The rectifi ed and fi ltered input voltage is applied to the primary load against open feedback loop faults. winding of T1. The other side of the transformer primary is driven by the integrated MOSFET in U1. Diode D5, C2, R1, R2, When an overvoltage condition occurs, such that bias voltage and VR1 comprise the clamp circuit, limiting the leakage exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION inductance turn-off voltage spike on the DRAIN pin to a safe (BP/M) pin voltage (28 V+5.85 V), current begins to fl ow into the value. The use of a combination a Zener clamp and parallel RC BP/M pin. When this current exceeds I the internal latching SD optimizes both EMI and energy effi ciency. Resistor R2 allows shutdown circuit in TinySwitch-III is activated. This condition is the use of a slow recovery, low cost, rectifi er diode by limiting reset when the BP/M pin voltage drops below 2.6 V after the reverse current through D5. The selection of a slow diode removal of the AC input. In the example shown, on opening the also improves effi ciency and conducted EMI but should be a loop, the OVP trips at an output of 17 V. glass passivated type, with a specifi ed recovery time of ≤2 μs. For lower no-load input power consumption, the bias winding The output voltage is regulated by the Zener diode VR3. When may also be used to supply the TinySwitch-III device. Resistor the output voltage exceeds the sum of the Zener and opto- R8 feeds current into the BP/M pin, inhibiting the internal high coupler LED forward drop, current will fl ow in the optocoupler voltage current source that normally maintains the BP/M pin LED. This will cause the transistor of the optocoupler to sink capacitor voltage (C7) during the internal MOSFET off time. current.When this current exceeds the ENABLE pin threshold This reduces the no-load consumption of this design from current the next switching cycle is inhibited. When the output 140 mW to 40 mW at 265 VAC. 8 Rev. I 01/09 www.powerint.com

TNY274-280 Undervoltage lockout is confi gured by R5 connected between 8. Increased current limit is selected for peak and open frame the DC bus and EN/UV pin of U1. When present, switching is power columns and standard current limit for adapter inhibited until the current in the EN/UV pin exceeds 25 μA. This columns. allows the startup voltage to be programmed within the normal 9. The part is board mounted with SOURCE pins soldered to a operating input voltage range, preventing glitching of the output suffi cient area of copper and/or a heatsink is used to keep under abnormal low voltage conditions and also on removal of the SOURCE pin temperature at or below 110 °C. the AC input. 10.Ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters. In addition to the simple input pi fi lter (C1, L1, C2) for differential mode EMI, this design makes use of E-Shield™ shielding *Below a value of 1, K is the ratio of ripple to peak primary P techniques in the transformer to reduce common mode EMI current. To prevent reduced power capability due to premature displacement currents, and R2 and C4 as a damping network termination of switching cycles a transient K limit of ≥0.25 is P to reduce high frequency transformer ringing. These recommended. This prevents the initial current limit (I ) from INIT techniques, combined with the frequency jitter of TNY278, give being exceeded at MOSFET turn on. excellent conducted and radiated EMI performance with this design achieving >12 dBμV of margin to EN55022 Class B For reference, Table 2 provides the minimum practical power conducted EMI limits. delivered from each family member at the three selectable current limit values. This assumes open frame operation (not For design fl exibility the value of C7 can be selected to pick one thermally limited) and otherwise the same conditions as listed of the 3 current limits options in U1. This allows the designer to above. These numbers are useful to identify the correct current select the current limit appropriate for the application. limit to select for a given device and output power requirement. • Standard current limit (I ) is selected with a 0.1 μF BP/M pin Overvoltage Protection capacitor and is the norLmIMIaTl choice for typical enclosed The output overvoltage protection provided by TinySwitch-III adapter applications. uses an internal latch that is triggered by a threshold current of • When a 1 μF BP/M pin capacitor is used, the current limit is approximately 5.5 mA into the BP/M pin. In addition to an reduced (I or I -1) offering reduced RMS device internal fi lter, the BP/M pin capacitor forms an external fi lter currents aLnIMdIT rtehderefLoIMreIT improved effi ciency, but at the expense providing noise immunity from inadvertent triggering. For the of maximum power capability. This is ideal for thermally bypass capacitor to be effective as a high frequency fi lter, the challenging designs where dissipation must be minimized. capacitor should be located as close as possible to the • When a 10 μF BP/M pin capacitor is used, the current limit is SOURCE and BP/M pins of the device. increased (I or I +1), extending the power capability for applicationsL IMreITqincuiringLIM hITigher peak power or continuous power Peak Output Power Table where the thermal conditions allow. 230 VAC ± 15% 85-265 VAC Product Further fl exibility comes from the current limits between I -1 I I +1 I -1 I I +1 LIMIT LIMIT LIMIT LIMIT LIMIT LIMIT adjacent TinySwitch-III family members being compatible. The reduced current limit of a given device is equal to the standard TNY274P/G 8 W 10.9 W 9.1 W 7.1 W 8.5 W 7.1 W current limit of the next smaller device and the increased TNY275P/G 10.8 W 12 W 15.1 W 8.4 W 9.3 W 11.8 W current limit is equal to the standard current limit of the next TNY276P/G 11.8 W 15.3 W 19.4 W 9.2 W 11.9 W 15.1 W larger device. TNY277P/G 15.1 W 19.6 W 23.7 W 11.8 W 15.3 W 18.5 W Key Application Considerations TNY278P/G 19.4 W 24 W 28 W 15.1 W 18.6 W 21.8 W TNY279P/G 23.7 W 28.4 W 32.2 W 18.5 W 22 W 25.2 W TinySwitch-lll Design Considerations TNY280P/G 28 W 32.7 W 36.6 W 21.8 W 25.4 W 28.5 W Output Power Table Table 2. Minimum Practical Power at Three Selectable Current Limit Levels. The data sheet output power table (Table 1) represents the minimum practical continuous output power level that can be For best performance of the OVP function, it is recommended obtained under the following assumed conditions: that a relatively high bias winding voltage is used, in the range 1. The minimum DC input voltage is 100 V or higher for 85 VAC of 15 V-30 V. This minimizes the error voltage on the bias input, or 220 V or higher for 230 VAC input or 115 VAC with winding due to leakage inductance and also ensures adequate a voltage doubler. The value of the input capacitance should voltage during no-load operation from which to supply the be sized to meet these criteria for AC input designs. BP/M pin for reduced no-load consumption. 2. Effi ciency of 75%. 3. Minimum data sheet value of I2f. Selecting the Zener diode voltage to be approximately 6 V 4. Transformer primary inductance tolerance of ±10%. above the bias winding voltage (28 V for 22 V bias winding) 5. Refl ected output voltage (V ) of 135 V. OR gives good OVP performance for most designs, but can be 6. Voltage only output of 12 V with a fast PN rectifi er diode. adjusted to compensate for variations in leakage inductance. 7. Continuous conduction mode operation with transient K * P Adding additional fi ltering can be achieved by inserting a low value of 0.25. 9 www.powerint.com Rev. I 01/09

TNY274-280 value (10 Ω to 47 Ω) resistor in series with the bias winding capacitor, transformer primary and TinySwitch-III together diode and/or the OVP Zener as shown by R7 and R3 in should be kept as small as possible. Figure 14. The resistor in series with the OVP Zener also limits the maximum current into the BP/M pin. Primary Clamp Circuit A clamp is used to limit peak voltage on the DRAIN pin at turn Reducing No-load Consumption off. This can be achieved by using an RCD clamp or a Zener As TinySwitch-III is self-powered from the BP/M pin capacitor, (~200 V) and diode clamp across the primary winding. In all there is no need for an auxillary or bias winding to be provided cases, to minimize EMI, care should be taken to minimize the on the transformer for this purpose. Typical no-load circuit path from the clamp components to the transformer and consumption when self-powered is <150 mW at 265 VAC input. TinySwitch-III. The addition of a bias winding can reduce this down to <50 mW by supplying the TinySwitch-III from the lower bias voltage and Thermal Considerations inhibiting the internal high voltage current source. To achieve The four SOURCE pins are internally connected to the IC lead this, select the value of the resistor (R8 in Figure 14) to provide frame and provide the main path to remove heat from the the data sheet DRAIN supply current. In practice, due to the device. Therefore all the SOURCE pins should be connected to reduction of the bias voltage at low load, start with a value a copper area underneath the TinySwitch-III to act not only as a equal to 40% greater than the data sheet maximum current, single point ground, but also as a heatsink. As this area is and then increase the value of the resistor to give the lowest no- connected to the quiet source node, this area should be load consumption. maximized for good heatsinking. Similarly for axial output diodes, maximize the PCB area connected to the cathode. Audible Noise The cycle skipping mode of operation used in TinySwitch-III can Y-Capacitor generate audio frequency components in the transformer. To The placement of the Y-capacitor should be directly from the limit this audible noise generation the transformer should be primary input fi lter capacitor positive terminal to the common/ designed such that the peak core fl ux density is below return terminal of the transformer secondary. Such a placement 3000 Gauss (300 mT). Following this guideline and using the will route high magnitude common mode surge currents away standard transformer production technique of dip varnishing from the TinySwitch-III device. Note – if an input π (C, L, C) EMI practically eliminates audible noise. Vacuum impregnation of fi lter is used then the inductor in the fi lter should be placed the transformer should not be used due to the high primary between the negative terminals of the input fi lter capacitors. capacitance and increased losses that result. Higher fl ux Optocoupler densities are possible, however careful evaluation of the audible Place the optocoupler physically close to the TinySwitch-III to noise performance should be made using production minimizing the primary-side trace lengths. Keep the high transformer samples before approving the design. current, high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. Ceramic capacitors that use dielectrics such as Z5U, when used in clamp circuits, may also generate audio noise. If this is Output Diode the case, try replacing them with a capacitor having a different For best performance, the area of the loop connecting the dielectric or construction, for example a fi lm type. secondary winding, the output diode and the output fi lter capacitor, should be minimized. In addition, suffi cient copper TinySwitch-lll Layout Considerations area should be provided at the anode and cathode terminals of Layout the diode for heatsinking. A larger area is preferred at the quiet See Figure 15 for a recommended circuit board layout for cathode terminal. A large anode area can increase high TinySwitch-III. frequency radiated EMI. Single Point Grounding PC Board Leakage Currents Use a single point ground connection from the input fi lter TinySwitch-III is designed to optimize energy effi ciency across capacitor to the area of copper connected to the SOURCE pins. the power range and particularly in standby/no-load conditions. Current consumption has therefore been minimized to achieve Bypass Capacitor (C ) this performance. The EN/UV pin undervoltage feature for BP The BP/M pin capacitor should be located as near as possible example has a low threshold (~1 μA) to detect whether an to the BP/M and SOURCE pins. undervoltage resistor is present. EN/UV Pin Parasitic leakage currents into the EN/UV pin are normally well Keep traces connected to the EN/UV pin short and, as far as is below this 1 μA threshold when PC board assembly is in a well practical, away from all other traces and nodes above source controlled production facility. However, high humidity potential including, but not limited to, the BYPASS and DRAIN conditions together with board and/or package contamination, pins. either from no-clean fl ux or other contaminants, can reduce the surface resistivity enough to allow parasitic currents >1 μA to Primary Loop Area fl ow into the EN/UV pin. These currents can fl ow from higher The area of the primary loop that connects the input fi lter voltage exposed solder pads close to the EN/UV pin such as 10 Rev. I 01/09 www.powerint.com

TNY274-280 Maximize hatched copper Safety Spacing areas ( ) for optimum heatsinking Y1- Capacitor + Output Output Filter Rectifier Capacitor HV Input Filter Capacitor - PRI T r BIAS SEC a n s PRI D f S o h-III mr S c t e wi BP/M BIAS r S S y n Ti TOP VIEW S EN/UV C BP Opto- coupler - DC + OUT PI-4368-042506 Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Undervoltage Lock Out Resistor. the BP/M pin solder pad preventing the design from starting up. 2. Maximum drain current – At maximum ambient temperature, Designs that make use of the undervoltage lockout feature by maximum input voltage and peak output (overload) power, connecting a resistor from the high voltage rail to the EN/UV pin verify drain current waveforms for any signs of transformer are not affected. saturation and excessive leading edge current spikes at startup. Repeat under steady state conditions and verify that If the contamination levels in the PC board assembly facility are the leading edge current spike event is below I at the LIMIT(Min) unknown, the application is open frame or operates in a high end of the t . Under all conditions, the maximum drain LEB(Min) pollution degree environment and the design does not make current should be below the specifi ed absolute maximum use of the undervoltage lockout feature, then an optional ratings. 390 kΩ resistor should be added from EN/UV pin to SOURCE 3. Thermal Check – At specifi ed maximum output power, pin to ensure that the parasitic leakage current into the EN/UV minimum input voltage and maximum ambient temperature, pin is well below 1 μA. verify that the temperature specifi cations are not exceeded for TinySwitch-III, transformer, output diode, and output Note that typical values for surface insulation resistance (SIR) capacitors. Enough thermal margin should be allowed for where no-clean fl ux has been applied according to the part-to-part variation of the R of TinySwitch-III as DS(ON) suppliers’ guidelines are >>10 MΩ and do not cause this issue. specifi ed in the data sheet. Under low line, maximum power, a maximum TinySwitch-III SOURCE pin temperature of Quick Design Checklist 110 °C is recommended to allow for these variations. As with any power supply design, all TinySwitch-III designs Design Tools should be verifi ed on the bench to make sure that component specifi cations are not exceeded under worst case conditions. Up-to-date information on design tools is available at the Power The following minimum set of tests is strongly recommended: Integrations website: www.powerint.com. 1. Maximum drain voltage – Verify that V does not exceed DS 650 V at highest input voltage and peak (overload) output power. The 50 V margin to the 700 V BV specifi cation DSS gives margin for design variation. 11 www.powerint.com Rev. I 01/09

TNY274-280 Absolute Maximum Ratings(1,4) DRAIN Voltage .............................................................................. -0.3 V to 700 V Lead Temperature(4) .....................................................................................260 °C DRAIN Peak Current: TNY274 .......................................400 (750) mA(2) TNY275 .....................................560 (1050) mA(2) Notes: TNY276 .....................................720 (1350) mA(2) 1. All voltages referenced to SOURCE, T = 25 °C. A TNY277 .....................................880 (1650) mA(2) 2. The higher peak DRAIN current is allowed while the DRAIN TNY278 ..................................1040 (1950) mA(2) voltage is simultaneously less than 400 V. TNY279 .................................1200 (2250) mA(2) 3. Normally limited by internal circuitry. TNY280 ................................1360 (2550) mA(2) 4. 1/16 in. from case for 5 seconds. EN/UV Voltage ................................................................................... -0.3 V to 9 V 5. Maximum ratings specifi ed may be applied one at a time, EN/UV Current ........................................................... ..................................100 mA without causing permanent damage to the product. Exposure BP/M Voltage .................................................. ....................................-0.3 V to 9 V to Absolute Rating conditions for extended periods of time may Storage Temperature .............................................................-65 °C to 150 °C affect product reliability. Operating Junction Temperature(3) ............................... -40 °C to 150 °C Thermal Impedance Thermal Impedance: P or G Package: Notes: (θ ) ............................ ....................70 °C/W(2); 60 °C/W(3) 1. Measured on the SOURCE pin close to plastic interface. JA (θ )(1) ............................................... ............................11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad. JC 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad. Conditions SOURCE = 0 V; T = -40 to 125 °C Parameter Symbol J Min Typ Max Units See Figure 16 (Unless Otherwise Specifi ed) Control Functions Average 124 132 140 Output Frequency T = 25 °C f J kHz in Standard Mode OSC See Figure 4 Peak-to-peak Jitter 8 Maximum Duty Cycle DC S1 Open 62 65 % MAX EN/UV Pin Upper Turnoff Threshold I -150 -115 -90 μA DIS Current EN/UV Pin V IEN/UV = 25 μA 1.8 2.2 2.6 V Voltage EN I = -25 μA 0.8 1.2 1.6 EN/UV EN/UV Current > I (MOSFET Not I DIS 290 μA S1 Switching) See Note A TNY274 275 360 TNY275 295 400 DRAIN Supply Current EN/UV Open TNY276 310 430 (MOSFET I TNY277 365 460 μA S2 Switching at f ) OSC See Note B TNY278 445 540 TNY279 510 640 TNY280 630 760 12 Rev. I 01/09 www.powerint.com

TNY274-280 Conditions SOURCE = 0 V; T = -40 to 125 °C Parameter Symbol J Min Typ Max Units See Figure 16 (Unless Otherwise Specifi ed) Control Functions (cont.) TNY274 -6 -3.8 -1.8 V = 0 V, BP/M I T = 25 °C TNY275-278 -8.3 -5.4 -2.5 CH1 J See Note C, D TNY279-280 -9.7 -6.8 -3.9 BP/M Pin Charge mA Current TNY274 -4.1 -2.3 -1 V = 4 V, BP/M I T = 25 °C TNY275-278 -5 -3.5 -1.5 CH2 J See Note C, D TNY279-280 -6.6 -4.6 -2.1 BP/M Pin Voltage V See Note C 5.6 5.85 6.15 V BP/M BP/M Pin Voltage V 0.80 0.95 1.20 V Hysteresis BP/MH BP/M Pin Shunt V I = 2 mA 6.0 6.4 6.7 V Voltage SHUNT BP EN/UV Pin Line Under- I T = 25 °C 22.5 25 27.5 μA voltage Threshold LUV J Circuit Protection di/dt = 50 mA/μs TNY274P 233 250 267 T = 25 °C J See Note E TNY274G 233 250 273 di/dt = 55 mA/μs TNY275P 256 275 294 T = 25 °C J See Note E TNY275G 256 275 300 di/dt = 70 mA/μs TNY276P 326 350 374 T = 25 °C J See Note E TNY276G 326 350 382 Standard Current Limit di/dt = 90 mA/μs TNY277P 419 450 481 (BP/M Capacitor = I T = 25 °C mA LIMIT J 0.1 μF) See Note D See Note E TNY277G 419 450 491 di/dt = 110 mA/μs TNY278P 512 550 588 T = 25 °C J See Note E TNY278G 512 550 600 di/dt = 130 mA/μs TNY279P 605 650 695 T = 25 °C J See Note E TNY279G 605 650 709 di/dt = 150 mA/μs TNY280P 698 750 802 T = 25 °C J See Note E TNY280G 698 750 818 13 www.powerint.com Rev. I 01/09

TNY274-280 Conditions SOURCE = 0 V; T = -40 to 125 °C Parameter Symbol J Min Typ Max Units See Figure 16 (Unless Otherwise Specifi ed) Circuit Protection (cont.) di/dt = 50 mA/μs TNY274P 196 210 233 T = 25 °C J See Note E TNY274G 196 210 237 di/dt = 55 mA/μs TNY275P 233 250 277 T = 25 °C J See Note E TNY275G 233 250 283 di/dt = 70 mA/μs TNY276P 256 275 305 T = 25 °C J See Notes E TNY276G 256 275 311 Reduced Current Limit di/dt = 90 mA/μs TNY277P 326 350 388 (BP/M Capacitor = I T = 25 °C mA LIMITred J 1 μF) See Note D See Notes E TNY277G 326 350 396 di/dt = 110 mA/μs TNY278P 419 450 499 T = 25 °C J See Notes E TNY278G 419 450 509 di/dt = 130 mA/μs TNY279P 512 550 610 T = 25 °C J See Notes E TNY279G 512 550 622 di/dt = 150 mA/μs TNY280P 605 650 721 T = 25 °C J See Notes E TNY280G 605 650 735 di/dt = 50 mA/μs TNY274P 196 210 233 T = 25 °C J See Notes E, F TNY274G 196 210 237 di/dt = 55 mA/μs TNY275P 326 350 388 T = 25 °C J See Notes E TNY275G 326 350 396 di/dt = 70 mA/μs TNY276P 419 450 499 T = 25 °C J See Notes E TNY276G 419 450 509 Increased Current Limit di/dt = 90 mA/μs TNY277P 512 550 610 (BP/M Capacitor = I T = 25 °C mA LIMITinc J 10 μF) See Note D See Notes E TNY277G 512 550 622 di/dt = 110 mA/μs TNY278P 605 650 721 T = 25 °C J See Notes E TNY278G 605 650 735 di/dt = 130 mA/μs TNY279P 698 750 833 T = 25 °C J See Notes E TNY279G 698 750 848 di/dt = 150 mA/μs TNY280P 791 850 943 T = 25 °C J See Notes E TNY280G 791 850 961 14 Rev. I 01/09 www.powerint.com

TNY274-280 Conditions SOURCE = 0 V; T = -40 to 125 °C Parameter Symbol J Min Typ Max Units See Figure 16 (Unless Otherwise Specifi ed) Circuit Protection (cont.) Standard Current 0.9 × 1.12 × TNY274-280P I2f Limit, I2f = I 2 I2f I2f LIMIT(TYP) × f OSC(TYP) TNY274-280G 0.9 × I2f 1.16 × T = 25 °C I2f I2f J Reduced Current 0.9 × 1.16 × TNY274-280P I2f Limit, I2f = I 2 I2f I2f Power Coeffi cient I2f LIMITred(TYP) A2Hz × f OSC(TYP) TNY274-280G 0.9 × I2f 1.20 × T = 25 °C I2f I2f J Increased Current 0.9 × 1.16 × TNY274-280P I2f Limit, I2f = I 2 I2f I2f LIMITinc(TYP) × f OSC(TYP) TNY274-280G 0.9 × I2f 1.20 × T = 25 °C I2f I2f J See Figure 19 0.75 × Initial Current Limit I mA INIT T = 25 °C, See Note G I J LIMIT(MIN) Leading Edge T = 25 °C t J 170 215 ns Blanking Time LEB See Note G Current Limit T = 25 °C t J 150 ns Delay ILD See Note G, H Thermal Shutdown T 135 142 150 °C Temperature SD Thermal Shutdown T 75 °C Hysteresis SDH BP/M Pin Shutdown I 4 6.5 9 mA Threshold Current SD BP/M Pin Power up Reset Threshold V 1.6 2.6 3.6 V BP/M(RESET) Voltage Output T = 25 °C 28 32 TNY274 J I = 25 mA D T = 100 °C 42 48 J T = 25 °C 19 22 ON-State R TNY275 J Ω Resistance DS(ON) ID = 28 mA T = 100 °C 29 33 J T = 25 °C 14 16 TNY276 J I = 35 mA D T = 100 °C 21 24 J 15 www.powerint.com Rev. I 01/09

TNY274-280 Conditions SOURCE = 0 V; T = -40 to 125 °C Parameter Symbol J Min Typ Max Units See Figure 16 (Unless Otherwise Specifi ed) Output (cont.) T = 25 °C 7.8 9.0 TNY277 J I = 45 mA D T = 100 °C 11.7 13.5 J T = 25 °C 5.2 6.0 TNY278 J I = 55 mA ON-State R D TJ = 100 °C 7.8 9.0 Ω Resistance DS(ON) T = 25 °C 3.9 4.5 TNY279 J I = 65 mA D T = 100 °C 5.8 6.7 J T = 25 °C 2.6 3.0 TNY280 J I = 75 mA D T = 100 °C 3.9 4.5 J V = 6.2 V TNY274-276 50 BP/M V = 0 V EN/UV I V = 560 V TNY277-278 100 μA DSS1 DS T = 125 °C OFF-State Drain J See Note I TNY279-280 200 Leakage Current V = 375 V, V = 6.2 V DS I BP/M T = 50 °C 15 DSS2 V = 0 V J EN/UV See Note G, I Breakdown V = 6.2 V, V = 0 V, BV BP EN/UV 700 V Voltage DSS See Note J, T = 25 °C J DRAIN Supply 50 V Voltage Auto-Restart T = 25 °C t J 64 ms ON-Time at f AR See Note K OSC Auto-Restart DC T = 25 °C 3 % Duty Cycle AR J 16 Rev. I 01/09 www.powerint.com

TNY274-280 NOTES: A. I is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these S1 conditions. Total device consumption at no-load is the sum of I and I . S1 DSS2 B. Since the output MOSFET is switching, it is diffi cult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BP/M pin current at 6.1 V. C. BP/M pin is not intended for sourcing supply current to external circuitry. D. To ensure correct current limit it is recommended that nominal 0.1 μF / 1 μF / 10 μF capacitors are used. In addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Tolerance Relative to Nominal Nominal BP/M Capacitor Value Pin Cap Value Min Max 0.1 μF -60% +100% 1 μF -50% +100% 10 μF -50% NA E. For current limit at other di/dt values, refer to Figure 23. F. TNY274 does not set an increased current limit value, but with a 10 μF BP/M pin capacitor the current limit is the same as with a 1 μF BP/M pin capacitor (reduced current limit value). G. This parameter is derived from characterization. H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the I specifi cation. LIMIT I. I is the worst case OFF state leakage specifi cation at 80% of BV and maximum operating junction temperature. I is a DSS1 DSS DSS2 typical specifi cation under worst case application conditions (rectifi ed 265 VAC) for no-load consumption calculations. J. Breakdown voltage may be checked against minimum BV specifi cation by ramping the DRAIN pin voltage up to but not DSS exceeding minimum BV . DSS K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). 17 www.powerint.com Rev. I 01/09

TNY274-280 470 Ω 5 W S2 470 Ω S D S1 S 2 MΩ S BP/M 50 V EN/UV 10 V S 150 V 0.1 μF NOTE: This test circuit is not applicable for current limit or output characteristic measurements. PI-4079-080905 Figure 16. General Test Circuit. DC MAX (internal signal) tP EN/UV V tEN/UV DRAIN 1 t = P f OSC PI-2364-012699 Figure 17. Duty Cycle Measurement. Figure 18. Output Enable Timing. PI-4279-013006 0.8 Figure 19. Current Limit Envelope. 18 Rev. I 01/09 www.powerint.com

TNY274-280 Breakdown Voltage°Normalized to 25 C)11..10 PI-2213-012301 Output Frequency°Normalized to 25 C)11000.....20864 PI-4280-012306 ( (0.2 0.9 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) Figure 20. Breakdown vs. Temperature. Figure 21. Frequency vs. Temperature. 1.2 1.4 andard Current Limit°Normalized to 25 C)0001...864 PI-4102-010906 malized Current Limit 11000.....20846 TTTTNNNNYYYY222277774567 N 5579od0500ri/ mdmmmmta AAAA=li////z μμμμ1essssd Nnlimooritmte v:a aFlilzouere d,t h ucesu err ethnet PI-4081-082305 St(0.2 Nor 0.2 TTNNYY227789 111300 mmAA//μμss tsaypppepiccroaifpli ecrdiua rftroeer Bn tthP le/imMit TNY280 150 mA/μs capacitor. 0 0 -50 0 50 100 150 1 2 3 4 Temperature (°C) Normalized di/dt Figure 22. Standard Current Limit vs. Temperature. Figure 23. Current Limit vs. di/dt. A) 320500 STTTNNNcaYYYli222n777g456 F ac112to...050rs: PI-4082-082305 pF) 1000 PI-4083-082305 ( m 200 TNY277 3.5 e 100 t ( TNY278 5.5 nc Scaling Factors: en TNY279 7.3 ta TNY274 1.0 rr 150 TNY280 11 ci TNY275 1.5 u a C p TNY276 2.0 n Ca TNY277 3.5 ai 100 n 10 TNY278 5.5 Dr ai TNY279 7.3 50 TCASE=25 °C Dr TNY280 11 TCASE=100 °C 0 1 0 2 4 6 8 10 0 100 200 300 400 500 600 DRAIN Voltage (V) Drain Voltage (V) Figure 24. Output Characteristic. Figure 25. C vs. Drain Voltage. OSS 19 www.powerint.com Rev. I 01/09

TNY274-280 5400 STTTNNNcaYYYli222n777g456 F ac112to...050rs: PI-4084-082305 eshold°5 C)11..20 PI-4281-012306 r20.8 (mW) 30 TTTNNNYYY222777789 357...553 ge Thed to 0.6 r TNY280 11 az owe 20 Voltmali0.4 P er-or dN 10 Un(0.2 0 0 -50 -25 0 25 50 75 100 125 0 200 400 600 Junction Temperature (°C) DRAIN Voltage (V) Figure 27. Undervoltage Threshold vs. Temperature. Figure 26. Drain Capacitance Power. DIP-8C ⊕ D S .004 (.10) Notes: -E- 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. .240 (6.10) 3. Dimensions shown do not include mold flash or other .260 (6.60) protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clock- wise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. Pin 1 5. Minimum metal to metal spacing at the package body for .367 (9.32) the omitted lead location is .137 inch (3.48 mm). -D- .387 (9.83) 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be .057 (1.45) perpendicular to plane T. .068 (1.73) (NOTE 6) .125 (3.18) .015 (.38) .145 (3.68) MINIMUM -T- SEATING .008 (.20) PLANE .120 (3.05) .015 (.38) .140 (3.56) .300 (7.62) BSC .100 (2.54) BSC .048 (1.22) .137 (3.48) (NOTE 7) .053 (1.35) MINIMUM P08C .014 (.36) ⊕ .300 (7.62) .022 (.56) T E D S .010 (.25) M .390 (9.91) PI-3933-100504 20 Rev. I 01/09 www.powerint.com

TNY274-280 SMD-8C ⊕ Notes: D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are inches. Millimeter sizes are -E- shown in parentheses. .080 2. Dimensions shown do not include mold flash or other .086 protrusions. Mold flash or protrusions shall not exceed .372 (9.45) .186 .240 (6.10) .006 (.15) on any side. .260 (6.60) ⊕ E.3 S8 8.0 (190.8 (6.2) 5) .286 .420 3 . Panind lcoocnattiinounes csotaurnt tweirt-hc lPoicnk -1 , wise to Pin 8 when viewed from the top. Pin 3 is omitted. 4. Minimum metal to metal spacing at the package body Pin 1 Pin 1 for the omitted lead location .137 (3.48) is .137 inch (3.48 mm). MINIMUM Solder Pad Dimensions 5. Lead width measured at .100 (2.54) (BSC) package body. 6. D and E are referenced -D- .367 (9.32) datums on the package .387 (9.83) body. .057 (1.45) .125 (3.18) .068 (1.73) .145 (3.68) (NOTE 5) .004 (.10) .032 (.81) .048 (1.22) ° ° .037 (.94) .053 (1.35) .009 (.23) .004 (.10) .036 (0.91) 0 - 8 G08C .012 (.30) .044 (1.12) PI-4015-013106 Part Ordering Information • TinySwitch Product Family • Series Number • Package Identifi er G Plastic Surface Mount SMD-8C P Plastic DIP-8C • Lead Finish N Pure Matte Tin (Pb-Free) G RoHS compliant and Halogen Free (P package only) • Tape & Reel and Other Options Blank Standard Confi guration TNY 278 G N - TL TL Tape & Reel, 1000 pcs min./mult., G package only 21 www.powerint.com Rev. I 01/09

TNY274-280 22 Rev. I 01/09 www.powerint.com

TNY274-280 Revision Notes Date D Release fi nal data sheet. 1/06 E Corrected fi gure numbers and references. 2/06 Separated current limit and power coeffi cient values for G package and updated Figure 15. Added F 4/06 EN/UV and PC board leakage currents in Key Applications Considerations section. G Updated line undervoltage current threshold to 2 mA. 6/06 H Updated BP/M Pin Charge current and Power Coeffi cient sections of Parameter Tables. 9/08 I Updated Part Ordering Information section with Halogen Free. 1/09 23 www.powerint.com Rev. I 01/09

For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifi cant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2006, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters Germany Japan Taiwan .. 5245 Hellyer Avenue Rueckertstrasse 3 Kosei Dai-3 Bldg. 5F, No. 318, Nei Hu Rd., Sec. 1 San Jose, CA 95138, USA. D-80336, Munich 2-12-11, Shin-Yokomana, Nei Hu Dist. Main: +1-408-414-9200 Germany Kohoku-ku Taipei, Taiwan 114, R.O.C. Customer Service: Phone: +49-89-5527-3910 Yokohama-shi Kanagwan Phone: +886-2-2659-4570 Phone: +1-408-414-9665 Fax: +49-89-5527-3920 222-0033 Japan Fax: +886-2-2659-4550 Fax: +1-408-414-9765 e-mail: eurosales@powerint.com Phone: +81-45-471-1021 e-mail: taiwansales@powerint.com e-mail: usasales@powerint.com Fax: +81-45-471-3717 India e-mail: japansales@powerint.com Europe HQ China (Shanghai) #1, 14th Main Road 1st Floor, St. James’s House Room 1601/1610, Tower 1 Vasanthanagar Korea East Street, Farnham Kerry Everbright City Bangalore-560052 India RM 602, 6FL Surrey GU9 7TJ No. 218 Tianmu Road West Phone: +91-80-4113-8020 Korea City Air Terminal B/D, 159-6 United Kingdom Shanghai, P.R.C. 200070 Fax: +91-80-4113-8023 Samsung-Dong, Kangnam-Gu, Phone: +44 (0) 1252-730-141 Phone: +86-21-6354-6323 e-mail: indiasales@powerint.com Seoul, 135-728, Korea Fax: +44 (0) 1252-727-689 Fax: +86-21-6354-6325 Phone: +82-2-2016-6610 e-mail: eurosales@powerint.com e-mail: chinasales@powerint.com Italy Fax: +82-2-2016-6630 Via De Amicis 2 e-mail: koreasales@powerint.com Applications Hotline China (Shenzhen) 20091 Bresso MI World Wide +1-408-414-9660 Rm A, B & C 4th Floor, Block C, Italy Singapore Electronics Science and Phone: +39-028-928-6000 51 Newton Road Applications Fax Technology Bldg., 2070 Fax: +39-028-928-6009 #15-08/10 Goldhill Plaza World Wide +1-408-414-9760 Shennan Zhong Rd, e-mail: eurosales@powerint.com Singapore, 308900 Shenzhen, Guangdong, Phone: +65-6358-2160 China, 518031 Fax: +65-6358-2015 Phone: +86-755-8379-3243 e-mail: singaporesales@powerint.com Fax: +86-755-8379-5828 e-mail: chinasales@powerint.com

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