(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 (cid:1) Highest Performance Floating-Point Digital GJC (352-PIN BGA) PACKAGE Signal Processor (DSP) TMS320C6701 (BOTTOM VIEW) − 8.3-, 6.7-, 6-ns Instruction Cycle Time 26 1 − 120-, 150-, 167-MHz Clock Rate − Eight 32-Bit Instructions/Cycle A B − 1 GFLOPS C − TMS320C6201 Fixed-Point DSP D E Pin-Compatible F G (cid:1) VelociTI Advanced Very Long Instruction H J Word (VLIW) C67x CPU Core K − Eight Highly Independent Functional L M Units: N P − Four ALUs (Floating- and Fixed-Point) R − Two ALUs (Fixed-Point) T U − Two Multipliers (Floating- and V W Fixed-Point) Y − Load-Store Architecture With 32 32-Bit AA AB General-Purpose Registers AC AD − Instruction Packing Reduces Code Size AE − All Instructions Conditional AF (cid:1) Instruction Set Features − Hardware Support for IEEE Single-Precision Instructions (cid:1) 16-Bit Host-Port Interface (HPI) − Hardware Support for IEEE − Access to Entire Memory Map Double-Precision Instructions (cid:1) − Byte-Addressable (8-, 16-, 32-Bit Data) Two Multichannel Buffered Serial Ports − 8-Bit Overflow Protection (McBSPs) − Saturation − Direct Interface to T1/E1, MVIP, SCSA − Bit-Field Extract, Set, Clear Framers − Bit-Counting − ST-Bus-Switching Compatible − Normalization − Up to 256 Channels Each (cid:1) − AC97-Compatible 1M-Bit On-Chip SRAM − Serial-Peripheral-Interface (SPI) − 512K-Bit Internal Program/Cache Compatible (Motorola) (16K 32-Bit Instructions) (cid:1) − 512K-Bit Dual-Access Internal Data Two 32-Bit General-Purpose Timers (cid:1) (64K Bytes) Flexible Phase-Locked-Loop (PLL) Clock (cid:1) 32-Bit External Memory Interface (EMIF) Generator − Glueless Interface to Synchronous (cid:1) IEEE-1149.1 (JTAG†) Memories: SDRAM and SBSRAM Boundary-Scan-Compatible − Glueless Interface to Asynchronous (cid:1) 352-Pin Ball Grid Array (BGA) Package Memories: SRAM and EPROM (GJC Suffix) − 52M-Byte Addressable External Memory (cid:1) 0.18-µm/5-Level Metal Process Space − CMOS Technology (cid:1) Four-Channel Bootloading (cid:1) 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz) Direct-Memory-Access (DMA) Controller (cid:1) With an Auxiliary Channel 3.3-V I/Os, 1.9-V Internal (167-MHz Only) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. †IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. (cid:19)(cid:21)(cid:13)(cid:20)(cid:23)(cid:7)(cid:1)(cid:15)(cid:13)(cid:16) (cid:20)(cid:14)(cid:1)(cid:14) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2004, Texas Instruments Incorporated (cid:19)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:1)$+(cid:30)! (cid:15)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:19)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Table of Contents GJC BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 1 parameter measurement information . . . . . . . . . . . . . . . 31 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 signal-transition levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 input and output clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 functional block and CPU diagram . . . . . . . . . . . . . . . . . . . . . 4 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 35 CPU description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 37 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 synchronous DRAM timing. . . . . . . . . . . . . . . . . . . . . . . . 41 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 development support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 48 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 49 power-down logic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 multichannel buffered serial port timing . . . . . . . . . . . . . 52 absolute maximum ratings over operating case DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 63 temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 recommended operating conditions . . . . . . . . . . . . . . . . . . . 29 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 electrical characteristics over recommended ranges of revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 supply voltage and operating case temperature . . . . 30 description The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000 DSP platform. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 device characteristics Table 1 provides an overview of the C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the C6701 Processors HARDWARE FEATURES C6701 EMIF 1 DMA 4-Channel PPeerriipphheerraallss Host-Port Interface (HPI) 1 McBSPs 2 32-Bit Timers 2 Size (Bytes) 64K IInntteerrnnaall PPrrooggrraamm MMeemmoorryy Organization 64K Bytes Cache/Mapped Program Size (Bytes) 64K IInntteerrnnaall DDaattaa MMeemmoorryy Organization 2 Blocks: Eight 16-Bit Banks per Block 50/50 Split Frequency MHz 120, 150, 167 Cycle Time ns 6 ns (6701-167); 6.7 ns (6701-150); 8.3 ns (6701-120) 1.8 (6701-120, -150) CCoorree ((VV)) VVoollttaaggee 1.9 (6701-167 only) I/O (V) 3.3 PLL Options CLKIN frequency multiplier Bypass (x1), x4 BGA Package 35 × 35 mm 352-pin GJC Process Technology µm 0.18 µm Product Preview (PP) Product Status Advance Information (AI) PD Production Data (PD) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 functional block and CPU diagram SDRAM C6701 Digital Signal Processor m SBSSRRAAMM 32 PrograBus AccPerossg/rCaamche In1t eBrlnoaclk P Proroggraramm M/Ceamchoery External Memory Controller (64K Bytes) ROM/FLASH Interface (EMIF) I/O Devices C67x CPU Timer 0 Instruction Fetch Control Registers Timer 1 Instruction Dispatch Control Multichannel Instruction Decode Logic Framing Chips: Buffered Serial Data Path A Data Path B H.100, MVIP, Port 0 Test SCSA, T1, E1 Multichannel A Register File B Register File In-Circuit AC97 Devices, Buffered Serial Emulation SPI Devices, Codecs Port 1 A Buses a Bus .L1† .S1†.M1† .D1 .D2 .M2† .S2† .L2† ICntoenrrtruoplt M at D D Direct Memory Internal Data HOST CONNECTION Access Controller Data Memory MC68360 Glueless (DMA) Power- Access (64K Bytes) MPC860 Glueless Host Port (4 Channels) Down Controller 2 Blocks of 8 Banks PCI9050 Bridge + Inverter 16 Interface PLL Logic Each MC68302 + PAL (HPI) (x1, x4) MPC750 + PAL MPC960 (Jx/Rx) + PAL †These functional units execute floating-point instructions. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the Functional and CPU Block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all TMS320C62x DSP fixed-point instructions. In addition to the C62x DSP fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. TMS320C62x is a trademark of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 CPU description (continued) ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ src1 ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ .L1† src2 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ dst 8 ÁÁÁlongÁ dstÁÁ ÁÁÁÁÁ 8 long src ÁÁÁÁÁÁ 32 ÁÁÁÁÁÁ LD1 32 MSB ST1 ÁÁÁÁÁÁ ÁÁÁÁÁ 32 Register ÁÁÁlongÁ srcÁÁ8 ÁÁFiÁle AÁÁ long dst Data Path A ÁÁÁÁdstÁ 8 ÁÁÁ(A0−ÁA15Á) Á .S1† ÁÁÁsÁrc1ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁsÁÁrc2ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁdstÁÁ ÁÁÁÁÁÁ ÁÁ.M1Á† sÁrc1ÁÁÁÁÁ ÁÁÁÁÁ src2 ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ LD1 32 LSB ÁÁÁÁÁ ÁÁÁÁÁÁÁ dst ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ .D1 src1 DA1 ÁÁ ÁÁÁsÁrc2ÁÁ Á2XÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ 1X ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ src2 DA2 ÁÁ ÁÁ.D2ÁsÁrc1ÁÁ ÁÁÁÁÁÁ dst ÁÁÁÁÁ ÁÁÁÁÁÁÁ LD2 32 LSB ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ src2 ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ .M2† src1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ dst ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ src2 ÁÁÁÁÁÁÁÁ ÁÁRegÁisterÁ Á src1 File B Data Path B ÁÁ.S2Á† ÁdstÁ ÁÁÁ(B0−ÁB15Á) Á 8 ÁÁÁlongÁ dstÁÁ ÁÁÁÁÁ 8 long src ÁÁ ÁÁÁÁÁÁ 32 ÁÁÁÁÁÁ LD2 32 MSB ST2 ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 32 long src ÁÁÁÁÁ 8 ÁÁÁÁÁ long dst 8 ÁÁÁÁdstÁÁÁ ÁÁÁÁÁÁ .L2† ÁÁÁsÁrc2ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁsÁrc1ÁÁÁÁ ÁÁÁÁÁ Control Á Register File †These functional units execute floating-point instructions. Figure 1. TMS320C67x CPU Data Paths 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 signal groups description CLKIN BOOTMODE4 CLKOUT2 BOOTMODE3 CLKOUT1 Boot Mode BOOTMODE2 CLKMODE1 BOOTMODE1 CLKMODE0 BOOTMODE0 CLOCK/PLL PLLFREQ3 PLLFREQ2 RESET PLLFREQ1 NMI PLLV EXT_INT7 PLLG EXT_INT6 PLLF EXT_INT5 Reset and EXT_INT4 Interrupts IACK INUM3 TMS INUM2 TDO INUM1 IEEE Standard TDI 1149.1 INUM0 TCK (JTAG) TRST Emulation EMU1 Little ENDIAN EMU0 LENDIAN Big ENDIAN RSV9 DMAC3 RSV8 DMAC2 RSV7 DMA Status DMAC1 RSV6 DMAC0 RSV5 Reserved RSV4 RSV3 RSV2 Power-Down PD Status RSV1 RSV0 Control/Status HPI 16 HD[15:0] Data (Host-Port Interface) HAS HCNTL0 Register Select HR/W HCNTL1 HCS Control HDS1 HHWIL HDS2 Half-Word/Byte HBE1 HRDY Select HBE0 HINT Figure 2. CPU and Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 signal groups description (continued) 32 ED[31:0] Data ARE Asynchronous AOE Memory AWE CE3 Control ARDY CE2 Memory Map CE1 Space Select CE0 SSADS SBSRAM SSOE 20 EA[21:2] Word Address Control SSWE SSCLK BE3 BE2 Byte Enables SDA10 BE1 BE0 SDRAM SDRAS Control SDCAS SDWE SDCLK HOLD HOLD/ HOLDA HOLDA EMIF (External Memory Interface) TOUT1 TOUT0 Timer 1 Timer 0 TINP1 TINP0 Timers McBSP1 McBSP0 CLKX1 CLKX0 FSX1 Receive Receive FSX0 DX1 DX0 CLKR1 CLKR0 FSR1 Transmit Transmit FSR0 DR1 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 3. Peripheral Signals 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. CLOCK/PLL CLKIN C10 I Clock Input CLKOUT1 AF22 O Clock output at full device speed CLKOUT2 AF20 O Clock output at half of device speed CLKMODE1 C6 Clock mode select II CLKMODE0 C5 (cid:2) Selects whether the output clock frequency = input clock frequency x4 or x1 PLLFREQ3 A9 PPLLLL ffrreeqquueennccyy rraannggee ((33,, 22,, aanndd 11)) PLLFREQ2 D11 II (cid:2)(cid:2) TThhee ttaarrggeett rraannggee ffoorr CCLLKKOOUUTT11 ffrreeqquueennccyy iiss ddeetteerrmmiinneedd bbyy tthhee 33--bbiitt vvaalluuee ooff tthhee PPLLLLFFRREEQQ ppiinnss.. PLLFREQ1 B10 PLLV‡ D12 A§ PLL analog VCC connection for the low-pass filter PLLG‡ C12 A§ PLL analog GND connection for the low-pass filter PLLF A11 A§ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS L3 I JTAG test-port mode select (features an internal pullup) TDO W2 O/Z JTAG test-port data out TDI R4 I JTAG test-port data in (features an internal pullup) TCK R3 I JTAG test-port clock TRST T1 I JTAG test-port reset (features an internal pulldown) EMU1 Y1 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ EMU0 W3 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ CONTROL RESET K2 I Device reset Nonmaskable interrupt NMI L2 I (cid:2) Edge-driven (rising edge) EXT_INT7 U3 EXT_INT6 V2 EExxtteerrnnaall iinntteerrrruuppttss II EXT_INT5 W1 (cid:2)(cid:2) EEddggee--ddrriivveenn ((rriissiinngg eeddggee)) EXT_INT4 U4 IACK Y2 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 AA1 AAccttiivvee iinntteerrrruupptt iiddeennttiiffiiccaattiioonn nnuummbbeerr INUM2 W4 OO (cid:2) VVaalliidd dduurriinngg IIAACCKK ffoorr aallll aaccttiivvee iinntteerrrruuppttss ((nnoott jjuusstt eexxtteerrnnaall)) INUM1 AA2 (cid:2)(cid:2) EEnnccooddiinngg oorrddeerr ffoolllloowwss tthhee iinntteerrrruupptt--sseerrvviiccee ffeettcchh--ppaacckkeett oorrddeerriinngg INUM0 AB1 If high, LENDIAN selects little-endian byte/half-word addressing order within a word LENDIAN H3 I If low, LENDIAN selects big-endian addressing PD D3 O Power-down mode 3 (active if high) †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. §A = Analog Signal (PLL Filter) ¶For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. HOST-PORT INTERFACE (HPI) HINT H26 O Host interrupt (from DSP to host) HCNTL1 F23 I Host control − selects between control, address, or data registers HCNTL0 D25 I Host control − selects between control, address, or data registers HHWIL C26 I Host half-word select − first or second half-word (not necessarily high or low order) HBE1 E23 I Host byte select within word or half-word HBE0 D24 I Host byte select within word or half-word HR/W C23 I Host read or write select HD15 B13 HD14 B14 HD13 C14 HD12 B15 HD11 D15 HD10 B16 HD9 A17 HD8 B17 II//OO//ZZ HHoosstt--ppoorrtt ddaattaa ((uusseedd ffoorr ttrraannssffeerr ooff ddaattaa,, aaddddrreessss,, aanndd ccoonnttrrooll)) HD7 D16 HD6 B18 HD5 A19 HD4 C18 HD3 B19 HD2 C19 HD1 B20 HD0 B21 HAS C22 I Host address strobe HCS B23 I Host chip select HDS1 D22 I Host data strobe 1 HDS2 A24 I Host data strobe 2 HRDY J24 O Host ready (from DSP to host) BOOT MODE BOOTMODE4 D8 BOOTMODE3 B4 BOOTMODE2 A3 II BBoooott mmooddee BOOTMODE1 D5 BOOTMODE0 C4 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AE22 O/Z CE2 AD26 O/Z Memory space enables CE1 AB24 O/Z (cid:2) Enabled by bits 24 and 25 of the word address CE0 AC26 O/Z (cid:2) Only one asserted during any external data access BE3 AB25 O/Z Byte-enable control BE2 AA24 O/Z (cid:2) Decoded from the two lowest bits of the internal address BE1 Y23 O/Z (cid:2) Byte-write enables for most types of memory BE0 AA26 O/Z (cid:2) Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF − ADDRESS EA21 J26 EA20 K25 EA19 L24 EA18 K26 EA17 M26 EA16 M25 EA15 P25 EA14 P24 EA13 R25 EA12 T26 OO//ZZ EExxtteerrnnaall aaddddrreessss ((wwoorrdd aaddddrreessss)) EA11 R23 EA10 U26 EA9 U25 EA8 T23 EA7 V26 EA6 V25 EA5 W26 EA4 V24 EA3 W25 EA2 Y26 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. EMIF − DATA ED31 AB2 ED30 AC1 ED29 AA4 ED28 AD1 ED27 AC3 ED26 AD4 ED25 AF3 ED24 AE4 ED23 AD5 ED22 AF4 ED21 AE5 ED20 AD6 ED19 AE6 ED18 AD7 ED17 AC8 ED16 AF7 II//OO//ZZ EExxtteerrnnaall ddaattaa ED15 AD9 ED14 AD10 ED13 AF9 ED12 AC11 ED11 AE10 ED10 AE11 ED9 AF11 ED8 AE14 ED7 AF15 ED6 AE15 ED5 AF16 ED4 AC15 ED3 AE17 ED2 AF18 ED1 AF19 ED0 AC17 EMIF − ASYNCHRONOUS MEMORY CONTROL ARE Y24 O/Z Asynchronous memory read enable AOE AC24 O/Z Asynchronous memory output enable AWE AD23 O/Z Asynchronous memory write enable ARDY W23 I Asynchronous memory ready input †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. EMIF − SYNCHRONOUS BURST SRAM CONTROL SSADS AC20 O/Z SBSRAM address strobe SSOE AF21 O/Z SBSRAM output enable SSWE AD19 O/Z SBSRAM write enable SSCLK AD17 O SBSRAM clock EMIF − SYNCHRONOUS DRAM CONTROL SDA10 AD21 O/Z SDRAM address 10 (separate for deactivate command) SDRAS AF24 O/Z SDRAM row-address strobe SDCAS AD22 O/Z SDRAM column-address strobe SDWE AF23 O/Z SDRAM write enable SDCLK AE20 O SDRAM clock EMIF − BUS ARBITRATION HOLD AA25 I Hold request from the host HOLDA A7 O Hold-request-acknowledge to the host TIMERS TOUT1 H24 O Timer 1 or general-purpose output TINP1 K24 I Timer 1 or general-purpose input TOUT0 M4 O Timer 0 or general-purpose output TINP0 K4 I Timer 0 or general-purpose input DMA ACTION COMPLETE DMAC3 D2 DMAC2 F4 OO DDMMAA aaccttiioonn ccoommpplleettee DMAC1 D1 DMAC0 E2 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 E25 I External clock source (as opposed to internal) CLKR1 H23 I/O/Z Receive clock CLKX1 F26 I/O/Z Transmit clock DR1 D26 I Receive data DX1 G23 O/Z Transmit data FSR1 E26 I/O/Z Receive frame sync FSX1 F25 I/O/Z Transmit frame sync †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 L4 I External clock source (as opposed to internal) CLKR0 M2 I/O/Z Receive clock CLKX0 L1 I/O/Z Transmit clock DR0 J1 I Receive data DX0 R1 O/Z Transmit data FSR0 P4 I/O/Z Receive frame sync FSX0 P3 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 T2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 G2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 C11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 B9 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV4 A6 I Reserved for testing, pulldown with a dedicated 20-kΩ resistor RSV5 C8 O Reserved (leave unconnected, do not connect to power or ground) RSV6 C21 I Reserved for testing, pullup with a dedicated 20-k(cid:1) resistor RSV7 B22 I Reserved for testing, pullup with a dedicated 20-k(cid:1) resistor RSV8 A23 I Reserved for testing, pullup with a dedicated 20-k(cid:1) resistor RSV9 E4 O Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS A10 A15 A18 A21 A22 B7 C1 D17 F3 G24 DDVVDDDD G25 SS 33..33--VV ssuuppppllyy vvoollttaaggee H25 J25 L25 M3 N3 N23 R26 T24 U24 W24 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. SUPPLY VOLTAGE PINS (CONTINUED) Y4 AB3 AB4 AB26 AC6 AC10 AC19 AC21 AC22 DDVVDDDD AC25 SS 33..33--VV ssuuppppllyy vvoollttaaggee AD11 AD13 AD15 AD18 AE18 AE21 AF5 AF6 AF17 A5 A12 A16 A20 B2 B6 B11 B12 B25 C3 11..88--VV ssuuppppllyy vvoollttaaggee ((ffoorr 66770011--112200,, --115500)) CCVVDDDD C15 SS 11..99--VV ssuuppppllyy vvoollttaaggee ((ffoorr 66770011--116677 oonnllyy)) C20 C24 D4 D6 D7 D9 D14 D18 D20 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. SUPPLY VOLTAGE PINS (CONTINUED) D23 E1 F1 H4 J4 J23 K1 K23 M1 M24 N4 N25 P2 P23 T3 T4 U1 11..88--VV ssuuppppllyy vvoollttaaggee ((ffoorr 66770011--112200,, --115500)) CCVVDDDD V4 SS 11..99--VV ssuuppppllyy vvoollttaaggee ((ffoorr 66770011--116677 oonnllyy)) V23 AC4 AC9 AC12 AC13 AC18 AC23 AD3 AD8 AD14 AD24 AE2 AE8 AE12 AE25 AF12 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. GROUND PINS A1 A2 A4 A13 A14 A25 A26 B1 B3 B5 B24 B26 C2 C7 C13 C16 C17 C25 D13 VVSSSS D19 GGNNDD GGrroouunndd ppiinnss E3 E24 F2 F24 G3 G4 G26 J3 L23 L26 M23 N1 N2 N24 N26 P1 P26 R24 T25 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. GROUND PINS (CONTINUED) U2 U23 V1 V3 Y3 Y25 AA3 AA23 AB23 AC2 AC5 AC7 AC14 AC16 AD2 AD12 AD16 AD20 VVSSSS AD25 GGNNDD GGrroouunndd ppiinnss AE1 AE3 AE7 AE9 AE13 AE16 AE19 AE23 AE24 AE26 AF1 AF2 AF8 AF10 AF13 AF14 AF25 AF26 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL TTYYPPEE†† DDEESSCCRRIIPPTTIIOONN NAME NO. REMAINING UNCONNECTED PINS A8 B8 C9 D10 D21 NNCC G1 UUnnccoonnnneecctteedd ppiinnss H1 H2 J2 K3 R2 †I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000(cid:3) DSP-based applications: Software Development Tools: Code Composer Studio(cid:3) Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000(cid:3) DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320(cid:3) DSP family member devices, including documentation. See this document for further information on TMS320(cid:3) DSP documentation or any TMS320(cid:3) DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320(cid:3) DSP-related products from other companies in the industry. To receive TMS320(cid:3) DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under “Development Tools”, select “Digital Signal Processors”. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 device and development-support tool nomenclature To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GJC), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -167 is 167 MHz). Table 2 identifies the available TMS320C6701 devices by their associated orderable part numbers (P/Ns) and gives device-specific ordering information (for example, device speeds, core and I/O supply voltage values, and device operating temperature ranges). Figure 4 provides a legend for reading the complete device name for any TMS320 DSP family member. Table 2. TMS320C6701 Device P/Ns and Ordering Information OPERATING CASE CVDD DVDD DEVICE ORDERABLE P/N DEVICE SPEED TEMPERATURE (CORE VOLTAGE) (I/O VOLTAGE) RANGE TMSC6701GJC16719V 167 MHz/1 GFLOPS 1.9 V 3.3 V 0(cid:4)C to 90(cid:4)C TMS320C6701GJC150 150 MHz/900 MFLOPS 1.8 V 3.3 V 0(cid:4)C to 90(cid:4)C TMS320C6701GJCA120 120 MHz/720 MFLOPS 1.8 V 3.3 V −40(cid:4)C to 105(cid:4)C POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 device and development-support tool nomenclature (continued) TMS 320 C 6701 GJC (A) 167 PREFIX DEVICE SPEED RANGE TMX= Experimental device 100 MHz 200 MHz TMP= Prototype device 120 MHz 233 MHz TMS= Qualified device 150 MHz 250 MHz SMJ= MIL-PRF-38535 (QML) 167 MHz 300 MHz SM = Commercial processing DEVICE FAMILY 320 = TMS320 DSP family TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperature A = −40°C to 105°C, extended temperature PACKAGE TYPE† N = Plastic DIP TECHNOLOGY J = Ceramic DIP JD = Ceramic DIP side-brazed C = CMOS GB = Ceramic PGA E = CMOS EPROM FZ = Ceramic CC F = CMOS Flash EEPROM FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU= 144-pin plastic BGA GGP= 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW= 340-pin plastic BGA GHK= 288-pin plastic MicroStar BGA(cid:3) DEVICE ’1x DSP: 10 16 14 17 15 ’2x DSP: 25 26 ’2xx DSP: 203 206 240 204 209 ’3x DSP: 30 31 32 ’4x DSP: 40 44 ’5x DSP: 50 53 51 56 52 57 †DIP = Dual-In-Line Package ’54x DSP: PGA = Pin Grid Array 541 545 542 546 CC = Chip Carrier 543 548 QFP = Quad Flat Package 6x DSP: TQFP= Thin Quad Flat Package 6201 6205 BGA = Ball Grid Array 6202 6211 6202B 6701 6203 6711 6204 Figure 4. TMS320 DSP Device Nomenclature (Including TMS320C6701) MicroStar BGA is a trademark of Texas Instruments. 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) briefly describes the functionality of the peripherals available on C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 clock PLL All of the internal C67x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3, Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the C67x device and the external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Table 3. CLKOUT1 Frequency Ranges† PLLFREQ3 PLLFREQ2 PLLFREQ1 CLKOUT1 FREQUENCY RANGE (A9) (D11) (B10) (MHZ) 0 0 0 50−140 0 0 1 65−167 0 1 0 130−167 †Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved. Table 4. C6701 PLL Component Selection Table CPU CLOCK CLKIN CLKOUT2 TYPICAL FREQUENCY R1 C1 C2 CLKMODE RANGE RANGE LOCK TIME (MHz) (CLKOUT1) (MHz) (Ω) (nF) (pF) (µs)‡ RANGE (MHz) x4 12.5−41.7 50−167 25−83.5 60.4 27 560 75 ‡Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 clock PLL (continued) PLLFREQ3 PLLFREQ2 (see Table 3) 3.3V PLLFREQ1 PLLV er CLKMODE0 PLL Internal to C6701 Filt CLKMODE1 PLLMULT MI C3 C4 PLLCLK E 10 (cid:1)F 0.1 (cid:1)F CLKIN CLKIN 1 LOOP FILTER CPU 0 CLOCK F G AVAILABLE MULTIPLY FACTORS LL C2 LL P P PLL CPU CLOCK CLKMODE1 CLKMODE0 MULTIPLY FREQUENCY C1 FACTORS F(CPUCLOCK) R1 0 0 x1(BYPASS) 1 x f(CLKIN) 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 x4 4 x f(CLKIN) NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode PLLFREQ3 PLLFREQ2 (see Table 3) 3.3V PLLFREQ1 PLLV CLKMODE0 Internal to C6701 CLKMODE1 PLL PLLMULT PLLCLK CLKIN CLKIN 1 LOOP FILTER CPU 0 CLOCK F G L L L L P P NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 25

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 power-down mode logic Figure 7 shows the power-down mode logic on the C6701. CLKOUT1 TMS320C6701 Internal Clock Tree PD1 PD2 IFR Power- Clock Internal Internal Down IER PD PLL Peripheral Peripheral Logic (pin) PWRD CSR CPU PD3 CLKIN RESET Figure 7. Power-Down Mode Logic† triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 5. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when “writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 31 16 15 14 13 12 11 10 9 8 Enable or Enabled Reserved Non-Enabled PD3 PD2 PD1 Interrupt Wake Interrupt Wake R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 0 Legend: R/W−x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 8. PWRD Field of the CSR Register Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the CSR. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 5 summarizes all the power-down modes. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 27

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 Table 5. Characteristics of the Power-Down Modes PRWD FIELD POWER-DOWN WAKE-UP METHOD EFFECT ON CHIP’S OPERATION (BITS 15−10) MODE 000000 No power-down — — CPU halted (except for the interrupt logic) 001001 PD1 Wake by an enabled interrupt PPoowweerr--ddoowwnn mmooddee bblloocckkss tthhee iinntteerrnnaall cclloocckk iinnppuuttss aatt tthhee boundary of the CPU, preventing most of the CPU’s logic from Wake by an enabled or 010001 PD1 switching. During PD1, DMA transactions can proceed between non-enabled interrupt peripherals and internal memory. Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being 011010 PD2† Wake by a device reset halted. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Following reset, the 011100 PD3† Wake by a device reset PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked. All others Reserved — — †When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications. 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.3 V DD Supply voltage range, DV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V DD Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Operating case temperature range, T (Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0(cid:4)C to 90(cid:4)C C (A Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40(cid:4)C to 105(cid:4)C Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55(cid:4)C to 150(cid:4)C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT 6701-120, -150 1.71 1.8 1.89 V CCVVDDDD SSuuppppllyy vvoollttaaggee,, CCoorree‡‡ 6701-167 only 1.81 1.9 1.99 V DVDD Supply voltage, I/O‡ 3.14 3.30 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IOH High-level output current −12 mA IOL Low-level output current 12 mA Default 0 90 (cid:4)C TTCC CCaassee tteemmppeerraattuurree A Version −40 105 (cid:4)C ‡TI DSP’s do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. For additional power supply sequencing information, see the Power Supply Sequencing Solutions For Dual Supply Voltage DSPs application report (literature number SLVA073). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 29

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage DVDD = MIN, IOH = MAX 2.4 V VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.6 V II Input current† VI = VSS to DVDD ±10 uA IOZ Off-state output current VO = DVDD or 0 V ±10 uA CVDD = NOM, CPU clock = 150 MHz 470 IIDDDD22VV SSuuppppllyy ccuurrrreenntt,, CCPPUU ++ CCPPUU mmeemmoorryy aacccceessss‡‡ mmAA CVDD = NOM, CPU clock = 120 MHz 380 CVDD = NOM, CPU clock = 150 MHz 250 IIDDDD22VV SSuuppppllyy ccuurrrreenntt,, ppeerriipphheerraallss‡‡ mmAA CVDD = NOM, CPU clock = 120 MHz 200 DVDD = NOM, CPU clock = 150 MHz 85 IIDDDD33VV SSuuppppllyy ccuurrrreenntt,, II//OO ppiinnss‡‡ mmAA DVDD = NOM, CPU clock = 120 MHz 70 Ci Input capacitance 10 pF Co Output capacitance 10 pF †TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡Measured with average activity (50% high / 50% low power). For more detailed information on CPU/peripheral/I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Output Vref Under Test CT = 30 pF† IOH †Typical distributed load circuit capacitance. signal-transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 9. Input and Output Voltage Reference Levels for ac Timing Measurements POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (C6701-150, -167 devices only)†‡ (see Figure 10) C6701-150 C6701-167 NNOO.. CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 UUNNIITT MIN MAX MIN MAX MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 26.7 6.7 24 6 ns Pulse duration, 2 tw(CLKINH) CLKIN high 0.4C 0.45C 0.4C 0.45C ns Pulse duration, 3 tw(CLKINL) CLKIN low 0.4C 0.45C 0.4C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 0.6 5 0.6 ns †The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. timing requirements for CLKIN (C6701-120 device only)†‡ (see Figure 10) C6701-120 NNOO.. CLKMODE = x4 CLKMODE = x1 UUNNIITT MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 33.3 8.3 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 0.6 ns †The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. 1 4 2 CLKIN 3 4 Figure 10. CLKIN Timings 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1†‡ (see Figure 11) C6701-120 C6701-150 C6701-167 NNOO.. PPAARRAAMMEETTEERR UUNNIITT CLKMODE = X4 CLKMODE = X1 MIN MAX MIN MAX 1 tc(CKO1) Cycle time, CLKOUT1 P − 0.7 P + 0.7 P − 0.7 P + 0.7 ns 2 tw(CKO1H) Pulse duration, CLKOUT1 high (P/2) − 0.5 (P/2) + 0.5 PH − 0.5 PH + 0.5 ns 3 tw(CKO1L) Pulse duration, CLKOUT1 low (P/2) − 0.5 (P/2) + 0.5 PL − 0.5 PL + 0.5 ns 4 tt(CKO1) Transition time, CLKOUT1 0.6 0.6 ns †P = 1/CPU clock frequency in nanoseconds (ns). ‡PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. 1 4 2 CLKOUT1 3 4 Figure 11. CLKOUT1 Timings switching characteristics for CLKOUT2§ (see Figure 12) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 1 tc(CKO2) Cycle time, CLKOUT2 2P − 0.7 2P + 0.7 ns 2 tw(CKO2H) Pulse duration, CLKOUT2 high P − 0.7 P + 0.7 ns 3 tw(CKO2L) Pulse duration, CLKOUT2 low P − 0.7 P + 0.7 ns 4 tt(CKO2) Transition time, CLKOUT2 0.6 ns §P = 1/CPU clock frequency in ns. 1 4 2 CLKOUT2 3 4 Figure 12. CLKOUT2 Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 33

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) SDCLK, SSCLK timing parameters SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 13) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 1 td(CKO1-SSCLK) Delay time, CLKOUT1 edge to SSCLK edge −0.8 3.4 ns 2 td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) −1.0 3.0 ns 3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge −1.5 2.5 ns 4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge −1.5 1.9 ns CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Figure 13. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 14 and Figure 15) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 6 tsu(EDV-CKO1H) Setup time, read EDx valid before CLKOUT1 high 4.5 ns 7 th(CKO1H-EDV) Hold time, read EDx valid after CLKOUT1 high 1.5 ns 10 tsu(ARDY-CKO1H) Setup time, ARDY valid before CLKOUT1 high 3.5 ns 11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 1.5 ns †To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 14 and Figure 15) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 1 td(CKO1H-CEV) Delay time, CLKOUT1 high to CEx valid −1.0 4.5 ns 2 td(CKO1H-BEV) Delay time, CLKOUT1 high to BEx valid 4.5 ns 3 td(CKO1H-BEIV) Delay time, CLKOUT1 high to BEx invalid −1.0 ns 4 td(CKO1H-EAV) Delay time, CLKOUT1 high to EAx valid 4.5 ns 5 td(CKO1H-EAIV) Delay time, CLKOUT1 high to EAx invalid −1.0 ns 8 td(CKO1H-AOEV) Delay time, CLKOUT1 high to AOE valid −1.0 4.5 ns 9 td(CKO1H-AREV) Delay time, CLKOUT1 high to ARE valid −0.5 4.5 ns 12 td(CKO1H-EDV) Delay time, CLKOUT1 high to EDx valid 4.5 ns 13 td(CKO1H-EDIV) Delay time, CLKOUT1 high to EDx invalid −1.0 ns 14 td(CKO1H-AWEV) Delay time, CLKOUT1 high to AWE valid −1.0 4.5 ns ‡The minimum delay is also the minimum output hold after CLKOUT1 high. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 5 Not ready = 2 HOLD = 1 CLKOUT1 1 1 CEx 2 3 BE[3:0] 4 5 EA[21:2] 7 6 ED[31:0] 8 8 AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 14. Asynchronous Memory Read Timing Setup = 2 Strobe = 5 Not ready = 2 HOLD = 1 CLKOUT1 1 1 CEx 2 3 BE[3:0] 4 5 EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 11 10 10 ARDY Figure 15. Asynchronous Memory Write Timing 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 16) C6701-150 ’C6701-120 NNOO.. C6701-167 UUNNIITT MIN MAX MIN MAX 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 2.0 2.0 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 2.9 2.1 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 16 and Figure 17) C6701-150 ’C6701-120 NNOO.. PPAARRAAMMEETTEERR C6701-167 UUNNIITT MIN MAX MIN MAX 1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 0.5P − 1.3 0.5P − 1.6 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high 0.5P − 1.3 0.5P − 1.7 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns †When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 BE4 5 6 EA[21:2] A1 A2 A3 A4 8 7 ED[31:0] Q1 Q2 Q3 Q4 9 10 SSADS 11 12 SSOE SSWE Figure 16. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 BE4 5 6 EA[21:2] A1 A2 A3 A4 13 14 ED[31:0] D1 D2 D3 D4 9 10 SSADS SSOE 15 16 SSWE Figure 17. SBSRAM Write Timing (Full-Rate SSCLK) 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 18) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 3.6 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 18 and Figure 19) C6701-150 C6701-120 NNOO.. PPAARRAAMMEETTEERR C6701-167 UUNNIITT MIN MAX MIN MAX 1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns †When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 39

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 BE4 5 6 EA[21:2] A1 A2 A3 A4 7 8 ED[31:0] Q1 Q2 Q3 Q4 9 10 SSADS 11 12 SSOE SSWE Figure 18. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 BE4 5 6 EA[21:2] A1 A2 A3 A4 13 14 ED[31:0] Q1 Q2 Q3 Q4 9 10 SSADS SSOE 15 16 SSWE Figure 19. SBSRAM Write Timing (1/2 Rate SSCLK) 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 20) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 7 tsu(EDV-SDCLKH) Setup time, read EDx valid before SDCLK high 1.8 ns 8 th(SDCLKH-EDV) Hold time, read EDx valid after SDCLK high 3 ns switching characteristics for synchronous DRAM cycles† (see Figure 20−Figure 25) C6701-150 C6701-120 NNOO.. PPAARRAAMMEETTEERR C6701-167 UUNNIITT MIN MAX MIN MAX 1 tosu(CEV-SDCLKH) Output setup time, CEx valid before SDCLK high 1.5P − 4 1.5P − 4 ns 2 toh(SDCLKH-CEV) Output hold time, CEx valid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 3 tosu(BEV-SDCLKH) Output setup time, BEx valid before SDCLK high 1.5P − 4 1.5P − 4 ns 4 toh(SDCLKH-BEIV) Output hold time, BEx invalid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 5 tosu(EAV-SDCLKH) Output setup time, EAx valid before SDCLK high 1.5P − 4 1.5P − 4 ns 6 toh(SDCLKH-EAIV) Output hold time, EAx invalid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 9 tosu(SDCAS-SDCLKH) Output setup time, SDCAS valid before SDCLK high 1.5P − 4 1.5P − 4 ns 10 toh(SDCLKH-SDCAS) Output hold time, SDCAS valid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 11 tosu(EDV-SDCLKH) Output setup time, EDx valid before SDCLK high 1.5P − 4 1.5P − 4 ns 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 13 tosu(SDWE-SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P − 4 1.5P − 4 ns 14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P − 4 1.5P − 4 ns 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns 17 tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P − 4 1.5P − 4 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns †When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 41

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ SDCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 5 6 EA[15:2] CA1 CA2 CA3 7 8 ED[31:0] D1 D2 D3 15 16 SDA10 SDRAS 9 10 SDCAS SDWE Figure 20. Three SDRAM Read Commands WRITE WRITE WRITE SDCLK 1 2 CEx 3 4 BE[3:0] BE1 BE2 BE3 5 6 EA[15:2] CA1 CA2 CA3 11 12 ED[31:0] D1 D2 D3 15 16 SDA10 SDRAS 9 10 SDCAS 13 14 SDWE Figure 21. Three SDRAM Write Commands 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK 1 2 CEx BE[3:0] 5 EA[15:2] Bank Activate/Row Address ED[31:0] 15 SDA10 Row Address 17 18 SDRAS SDCAS SDWE Figure 22. SDRAM ACTV Command DCAB SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] 15 16 SDA10 17 18 SDRAS SDCAS 13 14 SDWE Figure 23. SDRAM DCAB Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 43

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS 9 10 SDCAS SDWE Figure 24. SDRAM REFR Command MRS SDCLK 1 2 CEx BE[3:0] 5 6 EA[15:2] MRS Value ED[31:0] SDA10 17 18 SDRAS 9 10 SDCAS 13 14 SDWE Figure 25. SDRAM MRS Command 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 HOLD/HOLDA TIMING timing requirements for the hold/hold acknowledge cycles† (see Figure 26) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 1 tsu(HOLDH-CKO1H) Setup time, HOLD high before CLKOUT1 high 5 ns 2 th(CKO1H-HOLDL) Hold time, HOLD low after CLKOUT1 high 2 ns †HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. switching characteristics for the hold/hold acknowledge cycles‡ (see Figure 26) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 3 tR(HOLDL-EMHZ) Response time, HOLD low to EMIF high impedance 4P § ns 4 tR(EMHZ-HOLDAL) Response time, EMIF high impedance to HOLDA low 2P ns 5 tR(HOLDH-HOLDAH) Response time, HOLD high to HOLDA high 4P 7P ns 6 td(CKO1H-HOLDAL) Delay time, CLKOUT1 high to HOLDA valid 1 8 ns 7 td(CKO1H-BHZ) Delay time, CLKOUT1 high to EMIF Bus high impedance¶ 1 8 ns 8 td(CKO1H-BLZ) Delay time, CLKOUT1 high to EMIF Bus low impedance¶ 1 12 ns 9 tR(HOLDH-BLZ) Response time, HOLD high to EMIF Bus low impedance¶ 3P 6P ns ‡P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. §All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. ¶EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. DSP Owns Bus External Requester DSP Owns Bus 5 4 9 3 CLKOUT1 2 2 1 1 HOLD 6 6 HOLDA 7 8 EMIF Bus† ’C6701 Ext Req ’C6701 †EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 26. HOLD/HOLDA Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 45

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 RESET TIMING timing requirements for reset (see Figure 27) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX CLKOUT1 Width of the RESET pulse (PLL stable)† 10 11 ttww((RREESSEETT)) cycles Width of the RESET pulse (PLL needs to sync up)‡ 250 µs †This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. ‡This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. switching characteristics during reset§¶ (see Figure 27) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX CLKOUT1 2 tR(RESET) Response time to change of value in RESET signal 1 cycles 3 td(CKO1H-CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid −1 ns 4 td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid 10 ns 5 td(CKO1H-SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid −1 ns 6 td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK valid 10 ns 7 td(CKO1H-SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid −1 ns 8 td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK valid 10 ns 9 td(CKO1H-LOWIV) Delay time, CLKOUT1 high to low group invalid −1 ns 10 td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group valid 10 ns 11 td(CKO1H-HIGHIV) Delay time, CLKOUT1 high to high group invalid −1 ns 12 td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group valid 10 ns 13 td(CKO1H-ZHZ) Delay time, CLKOUT1 high to Z group high impedance −1 ns 14 td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group valid 10 ns §Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HINT. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ¶HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 CLKOUT2 5 6 SDCLK 7 8 SSCLK 9 10 LOW GROUP†‡ 11 12 HIGH GROUP†‡ 13 14 Z GROUP†‡ †Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HINT. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ‡HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. Figure 27. Reset Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 47

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles†‡ (see Figure 28) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 2 tw(ILOW) Width of the interrupt pulse low 2P ns 3 tw(IHIGH) Width of the interrupt pulse high 2P ns †Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. ‡P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. switching characteristics during interrupt response cycles§ (see Figure 28) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 1 tR(EINTH-IACKH) Response time, EXT_INTx high to IACK high 9P ns 4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid −0.5P 13 − 0.5P ns 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 10 − 0.5P ns 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid −0.5P ns §P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. 1 CLKOUT2 3 2 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 INUMx Interrupt Number Figure 28. Interrupt Timing 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 29, Figure 30, Figure 31, and Figure 32) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 1 tsu(SEL-HSTBL) Setup time, select signals§ valid before HSTROBE low 4 ns 2 th(HSTBL-SEL) Hold time, select signals§ valid after HSTROBE low 2 ns 3 tw(HSTBL) Pulse duration, HSTROBE low 2P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 2P ns 10 tsu(SEL-HASL) Setup time, select signals§ valid before HAS low 4 ns 11 th(HASL-SEL) Hold time, select signals§ valid after HAS low 2 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 3 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated 14 th(HRDYL-HSTBL) until HRDY is active (low); otherwise, HPI writes will not complete properly. 1 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns †HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. §Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics during host-port interface cycles†‡ (see Figure 29, Figure 30, Figure 31, and Figure 32) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 5 td(HCS-HRDY) Delay time, HCS to HRDY¶ 1 12 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 1 12 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 4 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low P − 3 P + 3 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 1 12 ns 20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 12 ns †HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. #This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. ||This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 49

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† HCS 15 15 7 9 16 9 HD[15:0] (output) 5 1st half-word 8 2nd half-word 17 5 HRDY (case 1) 5 6 8 17 HRDY (case 2) †HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Read Timing (HAS Not Used, Tied High) HAS 19 19 10 11 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE† 18 18 HCS 15 15 7 9 16 9 HD[15:0] (output) 1st half-word 2nd half-word 5 8 17 5 HRDY (case 1) 20 8 17 5 HRDY (case 2) †HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Read Timing (HAS Used) 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 12 12 13 13 HBE[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 4 HSTROBE† 14 HCS 12 12 13 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 5 HRDY †HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 31. HPI Write Timing (HAS Not Used, Tied High) HAS 12 19 13 12 19 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 4 14 HSTROBE† 18 18 HCS 12 12 13 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 5 HRDY †HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 32. HPI Write Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 51

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 33) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P − 1¶ ns CLKR int 13 55 ttssuu((FFRRHH--CCKKRRLL)) SSeettuupp ttiimmee,, eexxtteerrnnaall FFSSRR hhiigghh bbeeffoorree CCLLKKRR llooww nnss CLKR ext 4 CLKR int 7 66 tthh((CCKKRRLL--FFRRHH)) HHoolldd ttiimmee,, eexxtteerrnnaall FFSSRR hhiigghh aafftteerr CCLLKKRR llooww nnss CLKR ext 4 CLKR int 10 77 ttssuu((DDRRVV--CCKKRRLL)) SSeettuupp ttiimmee,, DDRR vvaalliidd bbeeffoorree CCLLKKRR llooww nnss CLKR ext 1 CLKR int 4 88 tthh((CCKKRRLL--DDRRVV)) HHoolldd ttiimmee,, DDRR vvaalliidd aafftteerr CCLLKKRR llooww nnss CLKR ext 4 CLKX int 13 1100 ttssuu((FFXXHH--CCKKXXLL)) SSeettuupp ttiimmee,, eexxtteerrnnaall FFSSXX hhiigghh bbeeffoorree CCLLKKXX llooww nnss CLKX ext 4 CLKX int 7 1111 tthh((CCKKXXLL--FFXXHH)) HHoolldd ttiimmee,, eexxtteerrnnaall FFSSXX hhiigghh aafftteerr CCLLKKXX llooww nnss CLKX ext 3 †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. §The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. ¶The minimum CLKR/X pulse duration is either (P−1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use 9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P−1) = 11.5 ns as the minimum CLKR/X pulse duration. 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡ (see Figure 33) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from 1 td(CKSH-CKRXH) CLKS input 3 15 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1# C + 1# ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −4 4 ns CLKX int −4 5 99 ttdd((CCKKXXHH--FFXXVV)) DDeellaayy ttiimmee,, CCLLKKXX hhiigghh ttoo iinntteerrnnaall FFSSXX vvaalliidd nnss CLKX ext 3 16 DDiissaabbllee ttiimmee,, DDXX hhiigghh iimmppeeddaannccee ffoolllloowwiinngg llaasstt ddaattaa bbiitt ffrroomm CLKX int −3 2 1122 ttddiiss((CCKKXXHH--DDXXHHZZ)) CLKX high CLKX ext 2 9 nnss CLKX int −2 4 1133 ttdd((CCKKXXHH--DDXXVV)) DDeellaayy ttiimmee,, CCLLKKXX hhiigghh ttoo DDXX vvaalliidd.. nnss CLKX ext 3 16 DDeellaayy ttiimmee,, FFSSXX hhiigghh ttoo DDXX vvaalliidd.. OONNLLYY aapppplliieess wwhheenn iinn ddaattaa FSX int −2 4 1144 ttdd((FFXXHH--DDXXVV)) delay 0 (XDATDLY = 00b) mode. FSX ext 2 10 nnss †CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡Minimum delay times also represent minimum output hold times. §P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. #C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 53

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 8 DR Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 14 13 12 13 DX Bit 0 Bit(n-1) (n-2) (n-3) Figure 33. McBSP Timings 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 34) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X(needs resync) Figure 34. FSR Timing When GSYNC = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 55

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35) C6701-120 C6701-150 C6701-167 NNOO.. UUNNIITT MASTER SLAVE MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 3P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35) C6701-120 C6701-150 C6701-167 NNOO.. PPAARRAAMMEETTEERR UUNNIITT MASTER§ SLAVE MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T − 4 T + 4 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L − 4 L + 4 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −4 4 3P + 1 5P + 17 ns Disable time, DX high impedance following last data bit from 6 tdis(CKXL-DXHZ) CLKX low L − 2 L + 3 ns Disable time, DX high impedance following last data bit from 7 tdis(FXH-DXHZ) FSX high P + 4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. §S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP #FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 8 6 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 57

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36) C6701-120 C6701-150 C6701-167 NNOO.. UUNNIITT MASTER SLAVE MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 3P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 6P ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36) C6701-120 C6701-150 C6701-167 NNOO.. PPAARRAAMMEETTEERR UUNNIITT MASTER§ SLAVE MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ L − 4 L + 4 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# T − 4 T + 4 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid −4 4 3P + 1 5P + 17 ns Disable time, DX high impedance following last data bit from 6 tdis(CKXL-DXHZ) CLKX low −2 4 3P + 4 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 3 2P + 1 4P + 13 ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. §S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP #FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 FSX 6 7 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37) C6701-120 C6701-150 C6701-167 NNOO.. UUNNIITT MASTER SLAVE MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 3P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 6P ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37) C6701-120 C6701-150 C6701-167 NNOO.. PPAARRAAMMEETTEERR UUNNIITT MASTER§ SLAVE MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ T − 4 T + 4 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# H − 4 H + 4 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid −4 4 3P + 1 5P + 17 ns Disable time, DX high impedance following last data bit from 6 tdis(CKXH-DXHZ) CLKX high H − 2 H + 3 ns Disable time, DX high impedance following last data bit from 7 tdis(FXH-DXHZ) FSX high P + 4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. §S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP #FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 59

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 8 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38) C6701-120 C6701-150 C6701-167 NNOO.. UUNNIITT MASTER SLAVE MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 3P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38) C6701-120 C6701-150 C6701-167 NNOO.. PPAARRAAMMEETTEERR UUNNIITT MASTER§ SLAVE MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H − 4 H + 4 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T − 4 T + 4 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −4 4 3P + 1 5P + 17 ns Disable time, DX high impedance following last data bit from 6 tdis(CKXH-DXHZ) CLKX high −2 4 3P + 4 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 3 2P + 1 4P + 13 ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. §S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP #FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 61

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 6 7 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 39) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 1 td(CKO1H-DMACV) Delay time, CLKOUT1 high to DMAC valid 2 11 ns CLKOUT1 1 1 DMAC[0:3] Figure 39. DMAC Timing timing requirements for timer inputs (see Figure 40)† C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 1 tw(TINPH) Pulse duration, TINP high 2P ns †P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. switching characteristics for timer outputs (see Figure 40) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 2 td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid 1 10 ns CLKOUT1 1 TINP 2 2 TOUT Figure 40. Timer Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 63

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs (see Figure 41) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 1 td(CKO1H-PDV) Delay time, CLKOUT1 high to PD valid 1 9 ns CLKOUT1 1 1 PD Figure 41. Power-Down Timing 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 42) C6701-120 C6701-150 NO. C6701-167 UNIT MIN MAX 1 tc(TCK) Cycle time, TCK 35 ns 3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics for JTAG test port (see Figure 42) C6701-120 C6701-150 NO. PARAMETER C6701-167 UNIT MIN MAX 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid –3 12 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 42. JTAG Test-Port Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 65

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 MECHANICAL DATA GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY 35,20 SQ 34,80 33,20 SQ 31,75 TYP 32,80 1,27 21,00 NOM 0,635 AF AE AD AC AB AA Y W 7 V 2 U 1, M T O R N P 0 N 0 1, M 2 L K 35 J 6 H 0, G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Heat Slug See Note E 3,50 MAX 1,00 NOM Seating Plane 0,90 ∅ 0,10 M 0,15 0,60 0,50 MIN 4173506-2/D 07/99 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Thermally enhanced plastic package with heat slug (HSL). D. Flip chip application only E. Possible protrusion in this area, but within 3,50 max package height specification F. Falls within JEDEC MO-151/BAR-2 thermal resistance characteristics (S-PBGA package) NO °C/W Air Flow LFPM† 1 RΘJC Junction-to-case 0.74 N/A 2 RΘJA Junction-to-free air 11.31 0 3 RΘJA Junction-to-free air 9.60 100 4 RΘJA Junction-to-free air 8.34 250 5 RΘJA Junction-to-free air 7.30 500 †LFPM = Linear Feet Per Minute 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:1)(cid:15)(cid:16)(cid:17)(cid:18)(cid:19)(cid:13)(cid:15)(cid:16)(cid:1) (cid:20)(cid:15)(cid:17)(cid:15)(cid:1)(cid:14)(cid:12) (cid:3)(cid:15)(cid:17)(cid:16)(cid:14)(cid:12) (cid:19)(cid:21)(cid:13)(cid:7)(cid:22)(cid:3)(cid:3)(cid:13)(cid:21) SPRS067F − MAY 1998 − REVISED MARCH 2004 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPR067E device-specific data sheet to make it an SPRS067F revision. Scope: Applicable updates to the C67x device family, specifically relating to the C6701 device, have been incor- porated. PAGE(S) ADDITIONS/CHANGES/DELETIONS NO. All Updated the title for literature number SPRU190 to: TMS320C6000 DSP Peripherals Overview Reference Guide 26 Added the power-down mode logic section and accompanying information. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 67

PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320C6701GJC150 ACTIVE FCBGA GJC 352 24 TBD SNPB Level-4-220C-72 HR 0 to 90 TMS320C6701 @ 1998 TI 320C6701 GJC150 TMS320C6701GJCA120 ACTIVE FCBGA GJC 352 24 TBD SNPB Level-4-220C-72 HR -40 to 105 TMS320C6701GJC @ 1998 TI A120 320C6701 TMSC6701GJC16719V ACTIVE FCBGA GJC 352 24 TBD SNPB Level-4-220C-72 HR 0 to 90 TMS320C6701GJC @ 1998 TI 320C6701 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2019 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS320C6701 : •Catalog: SM320C6701 •Enhanced Product: SM320C6701-EP •Military: SMJ320C6701 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 2

MECHANICAL DATA MPBG067B – SEPTEMBER 1998 – REVISED JANUARY 2002 GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY 35,20 SQ 34,80 33,20 SQ 31,75 TYP 32,80 1,27 21,00 NOM 0,635 AF AE AD AC AB AA Y W 7 V 2 U 1, M T O R N P 0 N 0 1, M 2 L K 35 J 6 H 0, G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 A1 Corner 2 4 6 8 10 12 14 16 18 20 22 24 26 Heat Slug See Note E Bottom View 3,50 MAX 1,00 NOM Seating Plane 0,90 ∅ 0,10 M 0,15 0,60 0,50 MIN 4173506-2/E 11/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Thermally enhanced plastic package with heat slug (HSL). D. Flip chip application only E. Possible protrusion in this area, but within 3,50 max package height specification F. Falls within JEDEC MO-151/BAR-2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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