Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-PerformanceAutomotive-Grade • MultipleCommunicationInterfaces MicrocontrollerforSafety-CriticalApplications – 10/100MbpsEthernetMAC(EMAC) – DualCPUsRunninginLockstep • IEEE802.3Compliant(3.3-VI/OOnly) – ECConFlashandRAMInterfaces • SupportsMII,RMII,andMDIO – Built-InSelf-Test(BIST)forCPUandOn-chip – FlexRayControllerWithTwoChannels RAMs • 8KBofMessageRAMWithParityProtection – ErrorSignalingModuleWithErrorPin • DedicatedTransferUnit(FTU) – VoltageandClockMonitoring – ThreeCANControllers(DCANs) • ARM®Cortex®-R4F32-BitRISCCPU • 64Mailboxes,EachWithParityProtection – Efficient1.66DMIPS/MHzWith8-StagePipeline • ComplianttoCANProtocolVersion2.0B – FPUWithSingle-andDouble-Precision – StandardSerialCommunicationInterface(SCI) – 12-RegionMemoryProtectionUnit(MPU) – LocalInterconnectNetwork(LIN)Interface – OpenArchitectureWithThird-PartySupport Controller • OperatingConditions • ComplianttoLINProtocolVersion2.1 – SystemClockupto 180MHz • CanbeConfiguredasaSecondSCI – CoreSupplyVoltage(VCC):1.2VNominal – Inter-IntegratedCircuit(I2C) – I/OSupplyVoltage(VCCIO):3.3VNominal – ThreeMultibufferedSerialPeripheralInterfaces – ADCSupplyVoltage(V ):3.0to5.25V (MibSPIs) CCAD • IntegratedMemory • 128WordsWithParityProtectionEach – 3MBofProgramFlashWithECC – TwoStandardSerialPeripheralInterfaces – 256KBofRAMWithECC (SPIs) – 64KBofFlashWithECCforEmulated • TwoNextGenerationHigh-EndTimer(N2HET) EEPROM Modules • 16-BitExternalMemoryInterface – N2HET1: 32ProgrammableChannels • CommonPlatformArchitecture – N2HET2:18ProgrammableChannels – ConsistentMemoryMapAcrossFamily – 160-WordInstructionRAMEachWithParity – Real-TimeInterrupt(RTI)TimerOSTimer Protection – 96-ChannelVectoredInterruptModule(VIM) – EachN2HETIncludesHardwareAngle Generator – 2-ChannelCyclicRedundancyChecker(CRC) – DedicatedHigh-EndTransferUnit(HTU)With • DirectMemoryAccess(DMA)Controller MPUforEachN2HET – 16Channelsand32ControlPackets • Two12-BitMultibufferedADCModules – ParityProtectionforControlPacketRAM – ADC1:24Channels – DMAAccessesProtectedbyDedicatedMPU – ADC2:16ChannelsSharedWithADC1 • Frequency-ModulatedPhase-LockedLoop – 64ResultBuffersWithParityProtectionEach (FMPLL)WithBuilt-InSlipDetector • General-PurposeInput/Output(GPIO)Pins • SeparateNonmodulatingPLL forFlexRay™ CapableofGeneratingInterrupts • TraceandCalibrationCapabilities – SixteenPinsontheZWTPackage – EmbeddedTraceMacrocell(ETM-R4) – FourPinsonthePGEPackage – DataModificationModule(DMM) • IEEE1149.1JTAG,BoundaryScanandARM – RAMTracePort(RTP) CoreSight™Components – ParameterOverlayModule(POM) • JTAGSecurityModule • Packages – 144-PinQuadFlatpack(PGE)[Green] – 337-BallGridArray(ZWT)[Green] 1 AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 1.2 Applications • BrakingSystems(AntilockBrakeSystemsand • ActiveDriverAssistanceSystems ElectronicStabilityControl) • AerospaceandAvionics • ElectricPowerSteering • RailwayCommunications • HEVandEVInverterSystems • Off-roadVehicles • BatteryManagementSystems 2 DeviceOverview Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 1.3 Description The TMS570LS3137 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os. The TMS570LS3137 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS.Thedevicesupportstheword-invariantbig-endian[BE32]format. TheTMS570LS3137devicehas3MBofintegratedflashand256KBofdataRAM. BoththeflashandRAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes. The TMS570LS3137 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters(ADCs)supportingupto24inputs. The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. AMemoryProtectionUnit(MPU)isbuiltintotheHTU. The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devicesorfasterconversiontimeisdesired. The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, one I2C module, one Ethernet, and one FlexRay controller. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero(NRZ)format. The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication ormultiplexedwiring. The FlexRay controller uses a dual-channel serial, fixed time base multimaster communication protocol with communication rates of 10 Mbps per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from the CPU main memory. Transfers are protected by a dedicated, built-inMPU.TheEthernetmodulesupportsMII,RMII,andMDIOinterfaces. The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and400Kbps. Copyright©2012–2015,TexasInstrumentsIncorporated DeviceOverview 3 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clockdomains. The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicatorofthedeviceoperatingfrequency. The DMA controller has 16 channels, 32 control packets, and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory systemfromanymalfunctionoftheDMA. The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitoredexternallyasanindicatorofafaultconditioninthemicrocontroller. The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronousDRAM(SDRAM)devices,asynchronousmemories,peripheralsorFPGAdevices. Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables withoutrebuildingthecodetoexplicitlyaccessRAMorhaltingtheprocessortoreprogramthedataflash. With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS3137 device is an ideal solution for high-performance real-time control applications with safety- criticalrequirements. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE TMS570LS3137ZWT NFBGA(337) 16.0mm×16.0mm TMS570LS3137PGE LQFP(144) 20.0mm×20.0mm (1) Formoreinformation,seeSection9,MechanicalPackagingandOrderableInformation. 4 DeviceOverview Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 1.4 Functional Block Diagram 3MB 64K 256KB TPCLK TPnENA TPSYNC TPDATA[15:0] MMCLKMMnENA MMSYNC MMDATA[15:0] RACECLKIN RACECLK RACECTL TMDATA[31:0] CCooalrlowea/rRys A LoMneg#e1ndCo freor Pow## 23eRr ADMoma##in12s Flash 64K RAM R R R R DD D D T T T E # 4 #3 with 64K with ECC ECC RTP ETM-R4 #5 64K DMA POM DMM HTU1 FTU HTU2 EMAC Dual Cortex-R4F CPUs in Lockstep Switched Central Resource Switched Central Resource Switched Central Resource Main Cross Bar:Arbitration and Prioritization Control 64KB Flash CRC Switched Central Resource Peripheral Central Resource Bridge for EEPROM Emulation nPORRST with ECC SYS nRST IOMM ECLK EMAC Slaves ESM nERROR MDCLK EMIF_nWAIT PMM MDIO MDIO EMIF_CLK DCAN1 CAN1_RX CAN1_TX MII_RXD[3:0] EMIF_CKE CAN2_RX MII_RXER EMIF_nCS[4:2] DCAN2 VIM CAN2_TX MII_TXD[3:0] EMIF_nCS[0] CAN3_RX MII_TXEN MII EMIF_ADDR[21:0] DCAN3 CAN3_TX MII_TXCLK EMIF_BA[1:0] EMIF MIBSPI1_CLK MII_RXCLK EMIF_DATA[15:0] MIBSPI1_SIMO[1:0] MII_CRS EMIF_nDQM[1:0] RTI MibSPI1 MIBSPI1_SOMI[1:0] MII_RXDV EMIF_nOE MIBSPI1_nCS[5:0] MII_COL EMIF_nWE MIBSPI1_nENA EMIF_nRAS SPI2_CLK EMIF_nCAS SPI2_SIMO EMIF_nRW DCC1 SPI2 SPI2_SOMI SPI2_nCS[1:0] SPI2_nENA MIBSPI3_CLK MIBSPI3_SIMO DCC2 MibSPI3 MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4 SPI4_SOMI SPI4_nCS0 SPI4_nENA MibADC1 MibADC2 N2HET1 N2HET2 GIO FlexRay I2C MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MibSPI5 MIBSPI5_nCS[3:0] VCCADVSSADADREFHI ADREFLOAD1EVTAD1IN[7:0]AD1IN[23:8] AD2IN[15:0] AD2EVTVCCADVSSADADREFHI ADREFLO N2HET1[31:0] ET1_PIN_nDIS N2HET2[15:0] N2HET2[18,16] ET2_PIN_nDIS GIOA[7:0] GIOB[7:0] FRAY_RX1FRAY_TX1FRAY_TXEN1 FRAY_RX2FRAY_TX2 FRAY_TXEN2 I2C_SDA I2C_SCL SLICNI MLLSIICINNBI___SRTRPXXXI5_nENA H H SCI_TX 2 2 N N Figure1-1.FunctionalBlockDiagram Copyright©2012–2015,TexasInstrumentsIncorporated DeviceOverview 5 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table of Contents 1 DeviceOverview......................................... 1 6.11 TightlyCoupledRAM(TCRAM)InterfaceModule.. 80 .............................................. .............. 1.1 Features 1 6.12 ParityProtectionforPeripheralRAMs 80 ........................................... ........... 1.2 Applications 2 6.13 On-ChipSRAMInitializationandTesting 82 ............................................ .................. 1.3 Description 3 6.14 ExternalMemoryInterface(EMIF) 84 ............................ ......................... 1.4 FunctionalBlockDiagram 5 6.15 VectoredInterruptManager 91 2 Revision History......................................... 7 6.16 DMAController...................................... 94 3 Device Comparison..................................... 9 6.17 RealTimeInterruptModule......................... 96 4 TerminalConfigurationandFunctions ........... 10 6.18 ErrorSignalingModule.............................. 98 ............... ...................... 4.1 PGEQFPPackagePinout(144-Pin) 10 6.19 Reset/Abort/ErrorSources 102 ....................... 4.2 ZWTBGAPackageBall-Map(337-BallGridArray) 11 6.20 DigitalWindowedWatchdog 104 ................................. ................................. 4.3 TerminalFunctions 12 6.21 DebugSubsystem 105 5 Specifications .......................................... 41 7 PeripheralInformationandElectrical ........................ Specifications ......................................... 116 5.1 AbsoluteMaximumRatings 41 5.2 ESDRatings........................................ 41 7.1 Peripheral Legend................................. 116 5.3 Power-OnHours(POH)............................. 41 7.2 Multibuffered12-BitAnalog-to-DigitalConverter .. 116 5.4 RecommendedOperatingConditions............... 42 7.3 General-PurposeInput/Output..................... 127 5.5 SwitchingCharacteristicsforClockDomains....... 43 7.4 EnhancedHigh-EndTimer(N2HET) .............. 128 5.6 WaitStatesRequired ............................... 43 7.5 FlexRayInterface.................................. 133 5.7 PowerConsumption................................. 44 7.6 ControllerAreaNetwork(DCAN).................. 135 5.8 Input/OutputElectricalCharacteristics.............. 45 7.7 LocalInterconnectNetworkInterface(LIN)........ 136 5.9 ThermalResistanceCharacteristics................ 46 7.8 SerialCommunicationInterface(SCI)............. 137 5.10 OutputBufferDriveStrengths ...................... 47 7.9 Inter-IntegratedCircuit(I2C)....................... 138 ........................................ 7.10 Multibuffered/StandardSerialPeripheral 5.11 Input Timings 48 ............................................ ...................................... Interface 141 5.12 OutputTimings 48 ................. ............................ 7.11 EthernetMediaAccessController 153 5.13 Low-EMIOutputBuffers 50 8 DeviceandDocumentationSupport.............. 157 6 SystemInformationandElectrical ..................................... Specifications........................................... 52 8.1 DeviceSupport 157 ............................ ............................. 8.2 DocumentationSupport 159 6.1 DevicePowerDomains 52 ............................. ..................... 8.3 CommunityResources 159 6.2 VoltageMonitorCharacteristics 53 ........................................ ........... 8.4 Trademarks 159 6.3 PowerSequencingandPowerOnReset 54 ................... ................................. 8.5 ElectrostaticDischargeCaution 159 6.4 WarmReset(nRST) 56 ............................................ ......................... 8.6 Glossary 159 6.5 ARM-R4FCPUInformation 57 ............... ............................................... 8.7 DeviceIdentificationCodeRegister 160 6.6 Clocks 60 ....................... .................................... 8.8 DieIdentificationRegisters 161 6.7 ClockMonitoring 68 ............................... ......................................... 8.9 ModuleCertifications 161 6.8 GlitchFilters 70 ................................ 9 MechanicalPackagingandOrderable 6.9 DeviceMemoryMap 71 Information............................................. 168 ....................................... 6.10 FlashMemory 77 ............................. 9.1 PackagingInformation 168 6 TableofContents Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 2 Revision History This data manual revision history highlights the technical changes made to the SPNS162B device-specific datamanualtomakeitanSPNS162Crevision. Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS3137 devices, which are now in the production data (PD) stage of development have been incorporated. ChangesfromAugust1,2013toApril30,2015(fromBRevision(July2013)toCRevision) Page • Section1(DeviceOverview):Updated/Changedsectiontitle ................................................................. 1 • Updated/ChangedtheN2HETfeature............................................................................................. 1 • (DeviceInformation):Addedtable.................................................................................................. 4 • AddedSection3,DeviceComparison............................................................................................. 9 • Section4(TerminalConfigurationandFunctions):Updated/Changedsectiontitle........................................ 10 • Table4-2(PGEEnhancedHigh-EndTimerModules(N2HET1,N2HET2)):Updated/ChangedN2HET1time inputcaptureoroutputcomparepindescription................................................................................ 14 • Table4-2:AddedN2HET1_PIN_nDISsignalDESCRIPTION................................................................ 14 • Table4-2:Updated/ChangedN2HET2timeinputcaptureoroutputcomparepindescription........................... 15 • Table4-2:AddedN2HET2_PIN_nDISsignalDESCRIPTION................................................................ 15 • Table4-3UpdateddescriptionaboutusingGIOB[2]onpin55 .............................................................. 15 • Table4-16(PGETestandDebugModulesInterface):Updated/ChangedTESTpindescription........................ 19 • Table4-22(ZWTEnhancedHigh-EndTimer(N2HET)Modules):Updated/ChangedN2HET1timeinputcapture oroutputcomparepindescription ................................................................................................ 23 • Table4-22AddedalternateterminalsforN2HET1pins17,19,21,23,25,27,29and31............................... 23 • Table4-22:AddedN2HET1_PIN_nDISsignalDESCRIPTION............................................................... 23 • Table4-22:Updated/ChangedN2HET2timeinputcaptureoroutputcomparepindescription.......................... 24 • Table4-22:AddedN2HET2_PIN_nDISsignalDESCRIPTION............................................................... 24 • Table4-23UpdateddescriptionaboutusingGIOB[2]onballV10........................................................... 25 • Table4-32:Added"receive"totheRMII_CRS_DVpinDescription.......................................................... 29 • Table4-32:Added"receive"totheMII_CRSpinDescription................................................................. 29 • Table4-34(ExternalMemoryInterface(EMIF)):Global:DeletedEMIF_RNWpinfunction............................... 30 • Table4-40(ZWTTestandDebugModulesInterface):Updated/ChangedTESTpindescription ....................... 36 • Table4-42(NoConnects):DeletedNCpinsA8,B8,andB9;supportedonFlexRayInterfaceController............. 37 • Section5(Specifications):Updated/Changedsectiontitle.................................................................... 41 • Section5.1(AbsoluteMaximumRatings):Reformattedtable................................................................. 41 • Section5.1(AbsoluteMaximumRatings):Updated/ChangedV supplyvoltagerangeMAXvaluefrom"5.5" CCAD to"6.25"V............................................................................................................................ 41 • Section5.1:Updated/ChangedADCinputpinsinputvoltagerangeMAXvaluefrom"5.5"to"6.25"V................. 41 • Section5.2(ESDRatings):Addedtable(new).................................................................................. 41 • Section5.3(Power-OnHours(POH)):Addedtable(new).................................................................... 41 • Section5.8(Input/OutputElectricalCharacteristics):Updated/ChangedInputClampCurrentfromI toI ........... 45 IC IK • Section5.9(ThermalResistanceCharacteristics):Movedsectionandupdated/changedsubsectiontitle. ............ 46 • Table5-2(ThermalResistanceCharacteristics(PGEPackage)):AddedtestconditionsandaddedΨ rowfor JT PGEpackage........................................................................................................................ 46 • Table5-3(ThermalResistanceCharacteristics(ZWTPackage)):AddedtestconditionsandaddedΨ rowfor JT ZWTpackage........................................................................................................................ 46 • ClarifiedimpactofSPI2PC9registerondrivestrengthofSPI2SOMIpin .................................................. 47 • Updated/ChangedtheMINvalueoft to2256t ns .................................................................. 56 v(RST) c(OSC) • Section6.6.1(ClockSources):AddedTable6-8,AvailableClockSourcecross-references............................. 60 • Section6.6.1.1(MainOscillator):AddedFigure6-4,RecommendedCrystal/ClockConnectioncross-reference..... 60 • Table6-10AddedlimitsforHFLPOaftersoftwaretrim ...................................................................... 62 • Table6-13(ClockDomainDescriptions):Addedmissing"1"totheVCLKACONclocksourceselectionregister nameforVCLKA3row.............................................................................................................. 65 • Table6-20Correctedsizeofbank7OTPandbank7OTPECC............................................................ 72 • Figure6-10(TCRAMBlockDiagram):Updated/Changedfigure,deletedATCM.......................................... 80 • Table6-25AddedtablefootnotesidentifyingtheaddressrangesoftheESRAMPBISTgroups........................ 82 • Table6-25AddedRAMpowerdomaininformationinthetablenotes....................................................... 82 • Table6-26(MemoryInitialization):Updated/ChangedN2HET2RAMendingaddressfrom"0xFF57FFFF"to Copyright©2012–2015,TexasInstrumentsIncorporated RevisionHistory 7 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com "0xFF45FFFF"....................................................................................................................... 83 • Table6-38CorrectedbaseJTAGIDBaseValueFrom0xnD8A002Fto0xnB8A002F.................................. 106 • Table6-38(JTAGIDCode):AddedJTAGIdentificationCodeforSiliconRevision"RevD" ........................... 106 • Table7-7(MibADCRecommendedOperatingConditions):Updated/ChangedAnaloginputclampcurrentfrom I toI ............................................................................................................................ 121 AIC AIK • FlexRayInterface,Section7.5.1(Features):Updated/Changed"8KBofmessage..."bulletforclarification......... 133 • ControllerAreaNetwork(DCAN)Section7.6.1(Features):Updated/ChangedTRMreferencestothecorrect documenttitles .................................................................................................................... 135 • Table7-24(SPIMasterModeExternalTimingParameters(CLOCKPHASE=0,SPICLK=output,SPISIMO= output,andSPISOMI=input)):Updated/Changedtablefootnoteto"...CLOCKPHASEbit(SPIFMTx.16)is cleared" ............................................................................................................................. 145 • Section7.11.1(EthernetMIIElectricalandTimingSpecifications):Updated/ChangedtheMIIparameternames andparametricdescriptionsforthissection.................................................................................... 153 • Section7.11.2(EthernetRMIIElectricalandTimingSpecifications):Updated/Changedsectiontitlefor clarification.......................................................................................................................... 155 • Section7.11.2Updated/ChangedtheRMIIparameternamesandparametricdescriptionsforthissection.......... 155 • Section7.11.3(ManagementDataInput/Output(MDIO)ElectricalandTimingSpecifications):Updated/Changed sectiontitleforclarification ....................................................................................................... 156 • Table7-32(TimingRequirementsforMDIOInput):Updated/Changedtabletitleandformattingforclarification.... 156 • Section8(DeviceandDocumentationSupport):Updated/Changedsectiontomeetnewrequirements,including additionofseveralsubsections.................................................................................................. 157 • Section8.7(DeviceIdentificationCodeRegister):AddedDeviceIDcodevalueforsiliconRevD.................... 160 • Section8.8(DieIdentificationRegisters):Updated/Changedtheaddressofthetwodieidentificationregisters (DIEIDLandDIEIDH)topointtotheoriginalregistersatlocation0xFFFFFF7Cand0xFFFFFF80forthissection. 161 • Table8-2(Die-IDRegisters):Updated/ChangedtheBITLOCATIONcolumnforallITEMrows....................... 161 • Section9(MechanicalPackagingandOrderableInformation):Updated/Changedsectiontitle........................ 168 • Section9.1(PackagingInformation):Updated/Changedtheparagraph................................................... 168 8 RevisionHistory Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 3 Device Comparison liststhefeaturesofthedevices. Table3-1.TMS570LS3137DeviceComparison(1)(2) FEATURES DEVICES GenericPartNumber TMS570LC4357ZWT(3) TMS570LS3137ZWT(3) TMS570LS3137PGE(3) TMS570LS3135ZWT TMS570LS3135PGE TMS570LS1227ZWT(3) Package 337BGA 337BGA 144QFP 337BGA 144QFP 337BGA CPU ARMCortex-R5F ARMCortex-R4F ARMCortex-R4F ARMCortex-R4F ARMCortex-R4F ARMCortex-R4F Frequency(MHz) 300 180 160 180 160 180 32I Cache(KB) – – – – – 32D Flash(KB) 4096 3072 3072 3072 3072 1280 RAM(KB) 512 256 256 256 256 192 DataFlash[EEPROM] 128 64 64 64 64 64 (KB) EMAC 10/100 10/100 10/100 – – 10/100 FlexRay 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch CAN 4 3 3 3 3 3 MibADC 2(41ch) 2(24ch) 2(24ch) 2(24ch) 2(24ch) 2(24ch) 12-bit(Ch) N2HET(Ch) 2(64) 2(44) 2(40) 2(50) 2(50) 2(44) ePWMChannels 14 – – – – 14 eCAPChannels 6 – – – – 6 eQEPChannels 2 – – – – 2 MibSPI(CS) 5(4x6+2) 3(6+6+4) 3(5+6+1) 3(6+6+4) 3(5+6+1) 3(6+6+4) SPI(CS) – 2(2+1) 1(1) 2(2+1) 1(1) 2(2+1) SCI(LIN) 4(2withLIN) 2(1withLIN) 2(1withLIN) 2(1withLIN) 2(1withLIN) 2(1withLIN) I2C 2 1 1 1 1 1 GPIO(INT)(4) 168(with16interruptcapable) 144(with16interruptcapable) 58(with4interruptcapable) 144(with16interruptcapable) 58(with4interruptcapable) 101(with16interruptcapable) EMIF 16-bitdata 16-bitdata – 16-bitdata – 16-bitdata ETM(Trace) 32-bit 32-bit – 32-bit – – RTP/DMM 16/16 16/16 – 16/16 – – Operating -40ºCto125ºC -40ºCto125ºC -40ºCto125ºC -40ºCto125ºC -40ºCto125ºC -40ºCto125ºC Temperature CoreSupply(V) 1.14V–1.32V 1.14V–1.32V 1.14V–1.32V 1.14V–1.32V 1.14V–1.32V 1.14V–1.32V I/OSupply(V) 3.0V–3.6V 3.0V–3.6V 3.0V–3.6V 3.0V–3.6V 3.0V–3.6V 3.0V–3.6V (1) Foradditionaldevicevariants,seewww.ti.com/tms570 (2) Thistablereflectsthemaximumconfigurationforeachperipheral.Somefunctionsaremultiplexedandnotallpinsareavailableatthesametime. (3) Supersetdevice (4) Totalnumberofpinsthatcanbeusedasgeneral-purposeinputoroutputwhennotusedaspartofaperipheral Copyright©2012–2015,TexasInstrumentsIncorporated DeviceComparison 9 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4 Terminal Configuration and Functions 4.1 PGE QFP Package Pinout (144-Pin) 15]07]08]14]06] 13] 12] 11] N[N[N[N[N[ N[ N[ N[ TMSN2HET1[28]N2HET1[08]MIBSPI1NCS[0]VCCIOVSSVSSVCCMIBSPI5CLKMIBSPI5SIMO[0]MIBSPI5SOMI[0]MIBSPI5NENAMIBSPI1NENAMIBSPI1CLKMIBSPI1SOMIMIBSPI1SIMON2HET1[26]N2HET1[24]CAN1RXCAN1TXVSSVCCAD1EVTAD1IN[15] /AD2IAD1IN[23] /AD2IAD1IN[08] /AD2IAD1IN[14] /AD2IAD1IN[22] /AD2IAD1IN[06]AD1IN[13] /AD2IAD1IN[05]AD1IN[12] /AD2IAD1IN[04]AD1IN[11] /AD2IAD1IN[03]AD1IN[02] 108107106105104103102101100999897969594939291908988878685848382818079787776757473 nTRST 109 72 AD1IN[10] /AD2IN[10] TDI 110 71 AD1IN[01] TDO 111 70 AD1IN[09] /AD2IN[09] TCK 112 69 VCCAD RTCK 113 68 VSSAD VCC 114 67 ADREFLO VSS 115 66 ADREFHI nRST 116 65 AD1IN[21] /AD2IN[05] nERROR 117 64 AD1IN[20] /AD2IN[04] N2HET1[10] 118 63 AD1IN[19] /AD2IN[03] ECLK 119 62 AD1IN[18] /AD2IN[02] VCCIO 120 61 AD1IN[07] VSS 121 60 AD1IN[0] VSS 122 59 AD1IN[17] /AD2IN[01] VCC 123 58 AD1IN[16] /AD2IN[0] N2HET1[12] 124 57 VCC N2HET1[14] 125 56 VSS FRAYRX1 126 55 MIBSPI3NCS[0] N2HET1[30] 127 54 MIBSPI3NENA CAN2TX 128 53 MIBSPI3CLK CAN2RX 129 52 MIBSPI3SIMO MIBSPI1NCS[1] 130 51 MIBSPI3SOMI LINRX 131 50 VSS LINTX 132 49 VCC FRAYTX1 133 48 VCC VCCP 134 47 VSS VSS 135 46 nPORRST VCCIO 136 45 VCC VCC 137 44 VSS VSS 138 43 VSS N2HET1[16] 139 42 VCCIO N2HET1[18] 140 41 N2HET1[15] N2HET1[20] 141 40 MIBSPI1NCS[2] FRAYTXEN1 142 39 N2HET1[13] VCC 143 38 N2HET1[06] VSS 144 37 MIBSPI3NCS[1] 1234567891011121314151617181920212223232425262727282930313233343536 FRAYTX2FRAYRX2BSPI3NCS[3]BSPI3NCS[2]FRAYTXEN2N2HET1[11]FLTP1FLTP2GIOA[2]VCCIOVSSCAN3RXCAN3TXGIOA[5]N2HET1[22]GIOA[6]VCCOSCINKelvin_GNDOSCOUTVSSGIOA[7]N2HET1[01]N2HET1[03]N2HET1[0]VCCIOVSSVSSVCCN2HET1[02]N2HET1[05]BSPI5NCS[0]N2HET1[07]TESTN2HET1[09]N2HET1[4] MIMI MI A. Pinscanhavemultiplexedfunctions.Onlythedefaultfunctionisdepictedinthefigure. Figure4-1.PGEQFPPackagePinout(144-Pin)(A) 10 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array) A B C D E F G H J K L M N P R T U V W 19 VSS VSS TMS N2[H10E]T1 MNICBSS[P0I]5 MSIBIMSPOI1 MNIBESNPAI1 MICBLSKPI5 MSIIMBSOP[0I5] N2[H28E]T1 DDAMTAM[_0] CAN3RX AD1EVT AADD12II/NN[[1155]]AADD12II/NN[[2026]] A[D016I]N AADD12II/NN[[1111]] VSSAD VSSAD 19 18 VSS TCK TDO nTRST N2[H08E]T1 MICBLSKPI1 MSIBOSMPII1 MNIBESNPAI5 MSOIBMSIP[0I5] N2H[0E]T1 DDAMTAM[_1] CAN3TX NC AADD12II/NN[[0088]]AADD12II/NN[[1144]]AADD12II/NN[[1133]] A[D014I]N A[D012I]N VSSAD 18 17 TDI RST ADEDMRIF[2_1] EnMWIFE_ MSOIBMSIP[1I5] DCMLMK_ MSIIMBSOP[3I5] MSIIMBSOP[2I5] N2[H31E]T1 nECMSIF[3_] nECMSIF[2_] nECMSIF[4_] nECMSIF[0_] NC A[D015I]N A[D013I]N AADD12II/NN[[1100]] A[D011I]N AADD12II/NN[[0099]]17 16 RTCK TFXREANY1 ADEDMRIF[2_0] EBMAI[F1_] MSIIMBSOP[1I5] DNMENMA_ MSOIBMSIP[3I5] MSOIBMSIP[2I5] DSMYNMC_ NC NC NC NC NC AADD12II/NN[[2037]]AADD12II/NN[[1122]]AADD12II/NN[[1093]]ADREFLO VSSAD 16 15 FRRXA1Y FTRXA1Y ADEDMRIF[1_9]ADEDMRIF[1_8] DAETTAM[06] DAETTAM[05] DAETTAM[04] DAETTAM[03] DAETTAM[02] DDAEATEMATTAI[MF1[_06]] / DDAEATEMATTAI[MF1[_71]] / DDAEATEMATTAI[MF1[_28]] / DDAEATEMATTAI[MF1[_93]] / NC NC AADD12II/NN[[2015]]AADD12II/NN[[2004]] ADREFHI VCCAD 15 14 N2[H26E]T1 nERROR ADEDMRIF[1_7]ADEDMRIF[1_6] DAETTAM[07] VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO VCCIO NC NC AADD12II/NN[[1082]] A[D017I]N AD[01]IN 14 13 N2[H17E]T1 N2[H19E]T1 ADEDMRIF[1_5] NC EDMAITEFA_TB[M1A2[]0 /] VCCIO VCCIO DAETTAM[01] NC AADD12II/NN[[1071]]AADD12I/NIN[[106]] NC 13 12 ECLK N2[H04E]T1 ADEDMRIF[1_4] NC EDMATEIFAT_[Mn13O]E / VCCIO VSS VSS VCC VSS VSS VCCIO DAETTAM[0] MNICBSS[P3I]5 NC NC NC 12 11 N2[H14E]T1 N2[H30E]T1 ADEDMRIF[1_3] NC DnAEDTEMQATIM[MF1[_41]] / VCCIO VSS VSS VSS VSS VSS VCCPLL TERCTATMCLEE NC NC NC NC 11 10 CAN1TX CAN1RX ADEDMRIF[1_2] NC DnAEDTEMQATIM[MF1[_50]] / VCC VCC VSS VSS VSS VCC VCC CTLREKATOMCUET NC NC MNICBSS[P0I]3 GIOB[3] 10 9 N2[H27E]T1 TFXREANY2 ADEDMRIF[1_1] NC DAAEDTEMDATIR[MF0[_85]] / VCC VSS VSS VSS VSS VSS VCCIO TCRELATKMCINE NC NC MICBLSKPI3 MNIBESNPAI3 9 ETM ETM 8 FRRXA2Y FTRXA2Y ADEDMRIF[1_0] NC DAETMAI[F0_9] / VCCP VSS VSS VCC VSS VSS VCCIO DAETMAI[F3_1] / NC NC MSIBOSMPII3 MSIBIMSPOI3 8 ADDR[4] DATA[15] ETM ETM 7 LINRX LINTX AEDMDIRF[_9] NC DAETMAI[F1_0] / VCCIO VCCIO DAETMAI[F3_0] / NC NC N2[H09E]T1 nPORRST 7 ADDR[3] DATA[14] ETM ETM 6 GIOA[4] MNICBSS[P1I]5 AEDMDIRF[_8] NC DAETMAI[F1_1] / VCCIO VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO DAETMAI[F2_9] / NC NC N2[H05E]T1 MNICBSS[P2I]5 6 ADDR[2] DATA[13] ETM ETM ETM ETM ETM ETM ETM ETM ETM 5 GIOA[0] GIOA[5] AEDMDIRF[_7] AEDMDIRF[_1] DAETMAI[F2_0] / DAETMAI[F2_1] / DAETMAI[F2_2] / FLTP2 FLTP1 DAETMAI[F2_3] / DAETMAI[F2_4] / DAETMAI[F2_5] / DAETMAI[F2_6] / DAETMAI[F2_7] / DAETMAI[F2_8] / NC NC MNICBSS[P1I]3 N2[H02E]T1 5 DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] 4 N2[H16E]T1 N2[H12E]T1 AEDMDIRF[_6] AEDMDIRF[_0] NC NC NC N2[H21E]T1 N2[H23E]T1 NC NC NC NC NC EnMCAIFS_ NC NC NC NC 4 3 N2[H29E]T1 N2[H22E]T1 MNICBSS[P3I]3 NSEPNI2A N2[H11E]T1 MNICBSS[P1I]1 MNICBSS[P2I]1 GIOA[6] MNICBSS[P3I]1 ECMLIKF_ ECMKIFE_ N2[H25E]T1 NSCPSI[20] nEWMAIFI_T EnMRAIFS_ NC NC NC N2[H06E]T1 3 2 VSS MNICBSS[P2I]3 GIOA[1] SSOPMI2I SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1] KEGLNVDIN_ GIOB[0] N2[H13E]T1 N2[H20E]T1 MNICBSS[P0I]1 NC TEST N2[H01E]T1 VSS 2 1 VSS VSS GIOA[2] SSIPMIO2 GIOA[3] GIOB[7] GIOB[4] CAN2RX N2[H18E]T1 OSCIN OSCOUT GIOA[7] N2[H15E]T1 N2[H24E]T1 NC N2[H07E]T1 N2[H03E]T1 VSS VSS 1 A B C D E F G H J K L M N P R T U V W A. Ballscanhavemultiplexedfunctions.Onlythedefaultfunction,exceptfortheEMIFsignalsthataremultiplexedwith ETMsignals,isdepictedinthefigure. Figure4-2.ZWTPackagePinout.TopView(A) Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3 Terminal Functions Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal. The signal name in bold is the function being described. For information on how to select between different multiplexed functions, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller TechnicalReferenceManual(SPNU499). NOTE IntheTerminalFunctionstablebelow,the"ResetPullState"isthestateofthepullappliedto theterminalwhilenPORRSTis lowandimmediately afternPORRSTgoesHigh. The default pull direction may change when software configures the pin for an alternate function. The "PullType"isthetypeofpullassertedwhenthesignalnameinboldisenabledforthegiven terminalbytheIOMMcontrolregisters. All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers aredisabled,andtheoutputbuffersaredisabledwiththedefaultpullsenabled. All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediatelyafternPORRSTgoesHigh. 4.3.1 PGE Package 4.3.1.1 MultibufferedAnalog-to-DigitalConverters(MibADCs) Table4-1.PGEMultibufferedAnalog-to-DigitalConverters(MibADC1,MibADC2) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION ADREFHI(1) 66 Input ADChighreferencesupply ADREFLO(1) 67 Input ADClowreferencesupply N/A None VCCAD(1) 69 Power OperatingsupplyforADC VSSAD(1) 68 Ground AD1EVT/MII_RX_ER/RMII_RX_ER 86 I/O Pulldown Programmable,20µA ADC1eventtriggerinput,orGPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup Programmable,20µA ADC2eventtriggerinput,orGPIO AD1IN[0] 60 AD1IN[1] 71 AD1IN[2] 73 AD1IN[3] 74 Input N/A None ADC1analoginput AD1IN[4] 76 AD1IN[5] 78 AD1IN[6] 80 AD1IN[7] 61 (1) TheADREFHI,ADREFLO,VCCADandVSSADconnectionsarecommonforbothADCcores. 12 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table4-1.PGEMultibufferedAnalog-to-DigitalConverters(MibADC1,MibADC2)(continued) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION AD1IN[8]/AD2IN[8] 83 AD1IN[9]/AD2IN[9] 70 AD1IN[10]/AD2IN[10] 72 AD1IN[11]/AD2IN[11] 75 AD1IN[12]/AD2IN[12] 77 AD1IN[13]/AD2IN[13] 79 AD1IN[14]/AD2IN[14] 82 AD1IN[15]/AD2IN[15] 85 Input N/A None ADC1/ADC2sharedanaloginputs AD1IN[16]/AD2IN[0] 58 AD1IN[17]/AD2IN[1] 59 AD1IN[18]/AD2IN[2] 62 AD1IN[19]/AD2IN[3] 63 AD1IN[20]/AD2IN[4] 64 AD1IN[21]/AD2IN[5] 65 AD1IN[22]/AD2IN[6] 81 AD1IN[23]/AD2IN[7] 84 Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 13 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.1.2 EnhancedHigh-EndTimer(N2HET)Modules Table4-2.PGEEnhancedHigh-EndTimerModules(N2HET1,N2HET2) TERMINAL SIGNAL RESETPULL SIGNALNAME 144 TYPE STATE PULLTYPE DESCRIPTION PGE N2HET1[0]/SPI4CLK 25 N2HET1[1]/SPI4NENA/N2HET2[8] 23 N2HET1[2]/SPI4SIMO[0] 30 N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 N2HET1[4] 36 N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 N2HET1[6]/SCIRX 38 N2HET1[7]/N2HET2[14] 33 Programmable, N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 I/O Pulldown 20µA N2HET1[9]/N2HET2[16] 35 N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 N2HET1[12]/MII_CRS/RMII_CRS_DV 124 N2HET1[13]/SCITX 39 N2HET1[14] 125 N2HET1[15]/MIBSPI1NCS[4] 41 N2HET1[16] 139 Programmable, MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 I/O Pullup 20µA N2HET1timerinputcapture Programmable, oroutputcompare,orGIO. N2HET1[18] 140 I/O Pulldown 20µA Eachterminalhasa MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pullup Programmable, suppressionfilterwitha 20µA programmableduration. Programmable, N2HET1[20] 141 I/O Pulldown 20µA Programmable, N2HET1[22] 15 I/O Pulldown 20µA Programmable, MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 I/O Pullup 20µA Programmable, N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 I/O Pulldown 20µA Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 I/O Pullup 20µA Programmable, N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 I/O Pulldown 20µA Programmable, MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I/O Pullup 20µA Programmable, N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pulldown 20µA Programmable, MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Pullup 20µA Programmable, N2HET1[30]/MII_RX_DV 127 I/O Pulldown 20µA Programmable, MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 I/O Pullup 20µA Programmable, DisableselectedPWM GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 I/O Pulldown 20µA outputs 14 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table4-2.PGEEnhancedHigh-EndTimerModules(N2HET1,N2HET2)(continued) TERMINAL SIGNAL RESETPULL SIGNALNAME 144 TYPE STATE PULLTYPE DESCRIPTION PGE GIOA[2]/N2HET2[0] 9 GIOA[6]/N2HET2[4] 16 GIOA[7]/N2HET2[6] 22 N2HET2timeinputcapture N2HET1[1]/SPI4NENA/N2HET2[8] 23 oroutputcompare,orGPIO Programmable, N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 I/O Pulldown 20µA Eachterminalhasa N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 suppressionfilterwitha programmableduration. N2HET1[7]/N2HET2[14] 33 N2HET1[9]/N2HET2[16] 35 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Programmable, DisableselectedPWM MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup 20µA outputs 4.3.1.3 General-PurposeInput/Output(GPIO) Table4-3.PGEGeneral-PurposeInput/Output(GPIO) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION GIOA[2]/N2HET2[0] 9 General-purposeI/O. GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 Programmable, AllGPIOterminalsare GIOA[6]/N2HET2[4] 16 I/O Pulldown 20µA capableofgenerating interruptstotheCPUonrising GIOA[7]/N2HET2[6] 22 /falling/bothedges. Theapplicationcannotoutput alevelontothisterminal whenitisconfiguredas Programmable, GIOB[2].Apull-upisenabled MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup 20µA onthisinput.Thispullcannot bedisabled,andisnot programmableusingtheGIO modulepullcontrolregisters. 4.3.1.4 FlexRayInterfaceController(FlexRay) Table4-4.FlexRayInterfaceController(FlexRay) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION Fixed100µA FRAYRX1 126 Input Pullup FlexRaydatareceive(channel1) Pullup FRAYTX1 133 Output FlexRaydatatransmit(channel1) N/A None FRAYTXEN1 142 Output FlexRaytransmitenable(channel1) Fixed100µA FRAYRX2 2 Input Pullup FlexRaydatareceive(channel2) Pullup FRAYTX2 1 Output FlexRaydatatransmit(channel2) N/A None FRAYTXEN2 5 Output FlexRaytransmitenable(channel2) Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 15 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.1.5 ControllerAreaNetworkControllers(DCANs) Table4-5.PGEControllerAreaNetworkControllers(DCAN) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION CAN1RX 90 CAN1receive,orGPIO CAN1TX 89 CAN1transmit,orGPIO CAN2RX 129 Programmable, CAN2receive,orGPIO I/O Pullup CAN2TX 128 20µA CAN2transmit,orGPIO CAN3RX 12 CAN3receive,orGPIO CAN3TX 13 CAN3transmit,orGPIO 4.3.1.6 LocalInterconnectNetworkInterfaceModule(LIN) Table4-6.PGELocalInterconnectNetworkInterfaceModule(LIN) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION LINRX 131 Programmable, LINreceive,orGPIO I/O Pullup LINTX 132 20µA LINtransmit,orGPIO 4.3.1.7 StandardSerialCommunicationInterface(SCI) Table4-7.PGEStandardSerialCommunicationInterface(SCI) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION N2HET1[6]/SCIRX 38 Programmable, SCIreceive,orGPIO I/O Pulldown N2HET1[13]/SCITX 39 20µA SCItransmit,orGPIO 4.3.1.8 Inter-IntegratedCircuitInterfaceModule(I2C) Table4-8.PGEInter-IntegratedCircuitInterfaceModule(I2C) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 Programmable, I2Cserialdata,orGPIO I/O Pullup MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 20µA I2Cserialclock,orGPIO 4.3.1.9 StandardSerialPeripheralInterface(SPI) Table4-9.PGEStandardSerialPeripheralInterface(SPI) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION N2HET1[0]/SPI4CLK 25 SPI4clock,orGPIO N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 SPI4chipselect,orGPIO N2HET1[1]/SPI4NENA/N2HET2[8] 23 SPI4enable,orGPIO Programmable, I/O Pulldown 20µA SPI4slave-inputmaster- N2HET1[2]/SPI4SIMO[0] 30 output,orGPIO SPI4slave-outputmaster- N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 input,orGPIO 16 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.1.10 MultibufferedSerialPeripheralInterfaceModules(MibSPI) Table4-10.PGEMultibufferedSerialPeripheralInterfaceModules(MibSPI) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI1CLK 95 MibSPI1clock,orGPIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 Programmable, Pullup MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 20µA MibSPI1chipselect,orGPIO MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 N2HET1[15]/MIBSPI1NCS[4] 41 Programmable, Pulldown MibSPI1chipselect,orGPIO N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 20µA I/O MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 Programmable, MibSPI1enable,orGPIO Pullup MIBSPI1SIMO[0] 93 20µA MibSPI1slave-inmaster-out,orGPIO Programmable, N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown MibSPI1slave-inmaster-out,orGPIO 20µA MIBSPI1SOMI[0] 94 Programmable, Pullup MibSPI1slave-outmaster-in,orGPIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 20µA MIBSPI3CLK 53 MibSPI3clock,orGPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pullup 20µA MibSPI3chipselect,orGPIO MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Programmable, N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Pulldown MibSPI3chipselect,orGPIO 20µA MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3chipselect,orGPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 Programmable, MibSPI3enable,orGPIO Pullup MIBSPI3SIMO[0] 52 20µA MibSPI3slave-inmaster-out,orGPIO MIBSPI3SOMI[0] 51 MibSPI3slave-outmaster-in,orGPIO MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 MibSPI5clock,orGPIO MIBSPI5NCS[0] 32 MibSPI5chipselect,orGPIO Programmable, MIBSPI5NENA/MII_RXD[3] 97 I/O Pullup MibSPI5enable,orGPIO 20µA MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 MibSPI5slave-inmaster-out,orGPIO MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MibSPI5slave-outmaster-in,orGPIO 4.3.1.11 EthernetController Table4-11.PGEEthernetController:MDIOInterface TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output Pullup Serialclockoutput 20µA Fixed20µA MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pullup Serialdatainput/output Pullup Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 17 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table4-12.PGEEthernetController:ReducedMediaIndependentInterface(RMII) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION RMIIcarriersenseanddata N2HET1[12]/MII_CRS/RMII_CRS_DV 124 valid RMIIsynchronousreference N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 clockforreceive,transmitand Fixed20µA Input Pulldown controlinterface Pulldown AD1EVT/MII_RX_ER/RMII_RX_ER 86 RMIIreceiveerror N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 RMIIreceivedata N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 RMIItransmitdata MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 Output Pullup None MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 RMIItransmitenable Table4-13.PGEEthernetController:MediaIndependentInterface(MII) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 Pullup None Collisiondetect Input Fixed20µA Carriersenseandreceive N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Pulldown Pulldown valid N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pulldown None MIIoutputreceiveclock N2HET1[30]/MII_RX_DV 127 Receiveddatavalid Input AD1EVT/MII_RX_ER/RMII_RX_ER 86 Receiveerror Fixed20µA N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pulldown Receiveclock Pulldown N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 Input Receivedata MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 Fixed20µA Pullup MIBSPI5NENA/MII_RXD[3] 97 Pulldown N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 MIIoutputtransmitclock I/O Pulldown None N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 Transmitclock MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 Pullup None Transmitdata MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 Output N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown None MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 Pullup None Transmitenable 4.3.1.12 SystemModuleInterface Table4-14.PGESystemModuleInterface TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION Power-onreset,coldreset Externalpowersupplymonitor circuitrymustdrivenPORRST Fixed100µA lowwhenanyofthesupplies nPORRST 46 Input Pulldown Pulldown tothemicrocontrollerfallout ofthespecifiedrange.This terminalhasaglitchfilter. SeeSection6.8. 18 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table4-14.PGESystemModuleInterface(continued) TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION Systemreset,warmreset, bidirectional. Theinternalcircuitryindicates anyresetconditionbydriving nRSTlow. Theexternalcircuitrycan assertasystemresetby Fixed100µA nRST 116 I/O Pullup drivingnRSTlow.Toensure Pullup thatanexternalresetisnot arbitrarilygenerated,TI recommendsthatanexternal pullupresistorisconnectedto thisterminal. Thisterminalhasaglitch filter.SeeSection6.8. ESMErrorSignal Fixed20µA nERROR 117 I/O Pulldown Indicateserrorofhigh Pulldown severity.SeeSection6.18. 4.3.1.13 ClockInputsandOutputs Table4-15.PGEClockInputsandOutputs TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION Fromexternal OSCIN 18 Input crystal/resonator,orexternal clockinput N/A None KELVIN_GND 19 Input Kelvingroundforoscillator OSCOUT 20 Output Toexternalcrystal/resonator Programmable,20 Externalprescaledclock ECLK 119 I/O Pulldown µA output,orGIO. GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 Input Pulldown 20µA Externalclockinput#1 4.3.1.14 TestandDebugModulesInterface Table4-16.PGETestandDebugModulesInterface TERMINAL RESET SIGNAL SIGNALNAME 144 TYPE PULL PULLTYPE DESCRIPTION PGE STATE Testenable.Thisterminal mustbeconnectedtoground TEST 34 I/O Pulldown Fixed100µA directlyorviaapulldown Pulldown resistor. nTRST 109 Input JTAGtesthardwarereset RTCK 113 Output N/A None JTAGreturntestclock Fixed100µA TCK 112 Input Pulldown JTAGtestclock Pulldown Fixed100µA TDI 110 I/O Pullup JTAGtestdatain Pullup 100µA TDO 111 Output None JTAGtestdataout Pulldown Fixed100µA TMS 108 I/O Pullup JTAGtestselect Pullup Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 19 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.1.15 FlashSupplyandTestPads Table4-17.PGEFlashSupplyandTestPads TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION 3.3-V VCCP 134 N/A None Flashpumpsupply Power FLTP1 7 Flashtestpads.These terminalsarereservedforTI useonly.Forproperoperation N/A None theseterminalsmustconnect FLTP2 8 onlytoatestpadornotbe connectedatall[noconnect (NC)]. 4.3.1.16 SupplyforCoreLogic:1.2-VNominal Table4-18.PGESupplyforCoreLogic:1.2-VNominal TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION VCC 17 VCC 29 VCC 45 VCC 48 VCC 49 VCC 57 1.2-V N/A None 1.2-VCoresupply VCC 87 Power VCC 101 VCC 114 VCC 123 VCC 137 VCC 143 4.3.1.17 SupplyforI/OCells:3.3-VNominal Table4-19.PGESupplyforI/OCells:3.3-VNominal TERMINAL RESET SIGNAL SIGNALNAME 144 TYPE PULL PULLTYPE DESCRIPTION PGE STATE VCCIO 10 VCCIO 26 VCCIO 42 3.3-V 3.3-VOperatingsupplyfor N/A None VCCIO 104 Power I/Os VCCIO 120 VCCIO 136 20 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.1.18 GroundReferenceforAllSuppliesExceptVCCAD Table4-20.PGEGroundReferenceforAllSuppliesExceptVCCAD TERMINAL RESET SIGNAL SIGNALNAME P1G44E TYPE SPTUALTLE PULLTYPE DESCRIPTION VSS 11 Groundreference VSS 21 VSS 27 VSS 28 VSS 43 VSS 44 VSS 47 VSS 50 VSS 56 Ground N/A None VSS 88 VSS 102 VSS 103 VSS 115 VSS 121 VSS 122 VSS 135 VSS 138 VSS 144 Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 21 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2 ZWT Package 4.3.2.1 MultibufferedAnalog-to-DigitalConverters(MibADCs) Table4-21.ZWTMultibufferedAnalog-to-DigitalConverters(MibADC1,MibADC2) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION ADREFHI(1) V15 Input ADChighreferencesupply ADREFLO(1) V16 Input N/A None ADClowreferencesupply VCCAD(1) W15 Power OperatingsupplyforADC VSSAD V19 VSSAD W16 Ground N/A None ADCsupplypower VSSAD W18 VSSAD W19 Programmable, ADC1eventtriggerinput,or AD1EVT/MII_RX_ER/RMII_RX_ER N19 I/O Pulldown 20µA GPIO Programmable, ADC2eventtriggerinput,or MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup 20µA GPIO AD1IN[0] W14 AD1IN[1] V17 AD1IN[2] V18 AD1IN[3] T17 Input N/A None ADC1analoginput AD1IN[4] U18 AD1IN[5] R17 AD1IN[6] T19 AD1IN[7] V14 AD1IN[8]/AD2IN[8] P18 AD1IN[9]/AD2IN[9] W17 AD1IN[10]/AD2IN[10] U17 AD1IN[11]/AD2IN[11] U19 AD1IN[12]/AD2IN[12] T16 AD1IN[13]/AD2IN[13] T18 AD1IN[14]/AD2IN[14] R18 AD1IN[15]/AD2IN[15] P19 ADC1/ADC2sharedanalog Input N/A None AD1IN[16]/AD2IN[0] V13 inputs AD1IN[17]/AD2IN[1] U13 AD1IN[18]/AD2IN[2] U14 AD1IN[19]/AD2IN[3] U16 AD1IN[20]/AD2IN[4] U15 AD1IN[21]/AD2IN[5] T15 AD1IN[22]/AD2IN[6] R19 AD1IN[23]/AD2IN[7] R16 (1) TheADREFHI,ADREFLO,VCCADandVSSADconnectionsarecommonforbothADCcores. 22 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.2 EnhancedHigh-EndTimer(N2HET)Modules Table4-22.ZWTEnhancedHigh-EndTimer(N2HET)Modules TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION N2HET1[0]/SPI4CLK K18 N2HET1[1]/SPI4NENA/N2HET2[8] V2 N2HET1[2]/SPI4SIMO[0] W5 N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1 N2HET1[4] B12 N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6 N2HET1[6]/SCIRX W3 N2HET1[7]/N2HET2[14] T1 N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 N2HET1[9]/N2HET2[16] V7 N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 D19 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 N2HET1[12]/MII_CRS/RMII_CRS_DV B4 N2HET1[13]/SCITX N2 N2HET1[14] A11 N2HET1[15]/MIBSPI1NCS[4] N1 N2HET1[16] A4 N2HET1[17] A13 MIBSPI1NCS[1]/N2HET1[17]/MII_COL F3 N2HET1timeinputcaptureor outputcompare,orGIO. N2HET1[18] J1 Programmable, N2HET1[19] B13 I/O Pulldown 20µA Eachterminalhasa suppressionfilterwitha MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 programmableduration. N2HET1[20] P2 N2HET1[21] H4 MIBSPI1NCS[3]/N2HET1[21] J3 N2HET1[22] B3 N2HET1[23] J4 MIBSPI1NENA/N2HET1[23]/MII_RXD[2] G19 N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 N2HET1[25] M3 MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 N2HET1[27] A9 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2 N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 N2HET1[29] A3 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3 N2HET1[30]/MII_RX_DV B11 N2HET1[31] J17 MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 Programmable, DisableselectedPWM GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 I/O Pulldown 20µA outputs Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 23 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table4-22.ZWTEnhancedHigh-EndTimer(N2HET)Modules(continued) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION GIOA[2]/N2HET2[0] C1 EMIF_ADDR[0]/N2HET2[1] D4 GIOA[3]/N2HET2[2] E1 EMIF_ADDR[1]/N2HET2[3] D5 GIOA[6]/N2HET2[4] H3 EMIF_BA[1]/N2HET2[5] D16 GIOA[7]/N2HET2[6] M1 EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 N2HET2timeinputcaptureor outputcompare,orGIO. N2HET1[1]/SPI4NENA/N2HET2[8] V2 Programmable, EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 I/O Pulldown 20µA Eachterminalhasa suppressionfilterwitha N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1 programmableduration. EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6 EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 N2HET1[7]/N2HET2[14] T1 EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 N2HET1[9]/N2HET2[16] V7 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 Programmable, DisableselectedPWM MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup 20µA outputs 24 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.3 General-PurposeInput/Output(GPIO) Table4-23.ZWTGeneral-PurposeInput/Output(GPIO) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION GIOA[0] A5 GIOA[1] C2 GIOA[2]/N2HET2[0] C1 GIOA[3]/N2HET2[2] E1 GIOA[4] A6 GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 GIOA[6]/N2HET2[4] H3 General-purposeI/O. GIOA[7]/N2HET2[6] M1 Programmable, AllGPIOterminalsare Pulldown capableofgenerating GIOB[0] M2 20µA interruptstotheCPUonrising GIOB[1] K2 /falling/bothedges. GIOB[2] F2 I/O GIOB[3] W10 GIOB[4] G1 GIOB[5] G2 GIOB[6] J2 GIOB[7] F1 Theapplicationcannotoutput alevelontothisterminal whenitisconfiguredas Fixed20µA GIOB[2].Apull-upisenabled MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 Pullup Pulldown onthisinput.Thispullcannot bedisabled,andisnot programmableusingtheGIO modulepullcontrolregisters 4.3.2.4 FlexRayInterfaceController(FlexRay) Table4-24.FlexRayInterfaceController(FlexRay) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION Fixed100µA FlexRaydatareceive FRAYRX1 A15 Input Pullup Pullup (channel1) FlexRaydatatransmit FRAYTX1 B15 Output (channel1) None None FlexRaytransmitenable FRAYTXEN1 B16 Output (channel1) Fixed100µA FlexRaydatareceive FRAYRX2 A8 Input Pullup Pullup (channel2) FlexRaydatatransmit FRAYTX2 B8 Output (channel2) None None FlexRaytransmitenable FRAYTXEN2 B9 Output (channel2) Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 25 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.5 ControllerAreaNetworkControllers(DCANs) Table4-25.ZWTControllerAreaNetworkControllers(DCANs) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION CAN1RX B10 CAN1receive,orGPIO CAN1TX A10 CAN1transmit,orGPIO CAN2RX H1 Programmable, CAN2receive,orGPIO I/O Pullup CAN2TX H2 20µA CAN2transmit,orGPIO CAN3RX M19 CAN3receive,orGPIO CAN3TX M18 CAN3transmit,orGPIO 4.3.2.6 LocalInterconnectNetworkInterfaceModule(LIN) Table4-26.ZWTLocalInterconnectNetworkInterfaceModule(LIN) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION LINRX A7 Programmable, LINreceive,orGPIO I/O Pullup LINTX B7 20µA LINtransmit,orGPIO 4.3.2.7 StandardSerialCommunicationInterface(SCI) Table4-27.ZWTStandardSerialCommunicationInterface(SCI) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION N2HET1[6]/SCIRX W3 Programmable, SCIreceive,orGPIO I/O Pulldown N2HET1[13]/SCITX N2 20µA SCItransmit,orGPIO 26 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.8 Inter-IntegratedCircuitInterfaceModule(I2C) Table4-28.ZWTInter-IntegratedCircuitInterfaceModule(I2C) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2 Programmable, I2Cserialdata,orGPIO I/O Pullup MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3 20µA I2Cserialclock,orGPIO 4.3.2.9 StandardSerialPeripheralInterface(SPI) Table4-29.ZWTStandardSerialPeripheralInterface(SPI) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION SPI2CLK E2 SPI2clock,orGPIO SPI2NCS[0] N3 SPI2chipselect,orGPIO SPI2NENA/SPI2NCS[1] D3 SPI2chipselect,orGPIO SPI2NENA/SPI2NCS[1] D3 I/O Pullup Programmable, SPI2enable,orGPIO 20µA SPI2slave-inputmaster- SPI2SIMO[0] D1 output,orGPIO SPI2slave-outputmaster- SPI2SOMI[0] D2 input,orGPIO N2HET1[0]/SPI4CLK K18 SPI4clock,orGPIO N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1 SPI4chipselect,orGPIO N2HET1[1]/SPI4NENA/N2HET2[8] V2 SPI4enable,orGPIO Programmable, I/O Pulldown 20µA SPI4slave-inputmaster- N2HET1[2]/SPI4SIMO[0] W5 output,orGPIO SPI4slave-outputmaster- N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6 input,orGPIO Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 27 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.10 MultibufferedSerialPeripheralInterfaceModules(MibSPI) Table4-30.ZWTMultibufferedSerialPeripheralInterfaceModules(MibSPI) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI1CLK F18 MibSPI1clock,orGPIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] R2 Programmable, MIBSPI1NCS[1]/N2HET1[17]/MII_COL F3 Pullup 20µA MibSPI1chipselect,orGPIO MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 MIBSPI1NCS[3]/N2HET1[21] J3 N2HET1[15]/MIBSPI1NCS[4] N1 Programmable, Pulldown MibSPI1chipselect,orGPIO N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 I/O 20µA MIBSPI1NENA/N2HET1[23]/MII_RXD[2] G19 MibSPI1enable,orGPIO Programmable, MIBSPI1SIMO[0] F19 Pullup 20µA MibSPI1slave-inmaster-out, orGPIO Programmable, MibSPI1slave-inmaster-out, N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 Pulldown 20µA orGPIO MIBSPI1SOMI[0] G18 Programmable, MibSPI1slave-outmaster-in, Pullup MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] R2 20µA orGPIO MIBSPI3CLK V9 MibSPI3clock,orGPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Pullup 20µA MibSPI3chipselect,orGPIO MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3 Programmable, N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 I/O Pulldown 20µA MibSPI3chipselect,orGPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 MibSPI3chipselect,orGPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 MibSPI3enable,orGPIO MIBSPI3SIMO[0] W8 Pullup Prog2ra0mµmAable, MoribGSPPIOI3slave-inmaster-out, MibSPI3slave-outmaster-in, MIBSPI3SOMI[0] V8 orGPIO MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 MibSPI5clock,orGPIO MIBSPI5NCS[0]/DMM_DATA[5] E19 MIBSPI5NCS[1]/DMM_DATA[6] B6 MibSPI5chipselect,orGPIO MIBSPI5NCS[2]/DMM_DATA[2] W6 MIBSPI5NCS[3]/DMM_DATA[3] T12 MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3] H18 MibSPI5enable,orGPIO MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 Programmable, I/O Pullup MIBSPI5SIMO[1]/DMM_DATA[9] E16 20µA MIBSPI5SIMO[2]/DMM_DATA[10] H17 MIBSPI5SIMO[3]/DMM_DATA[11] G17 MibSPI5slave-inmaster-out, MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 orGPIO MIBSPI5SOMI[1]/DMM_DATA[13] E17 MIBSPI5SOMI[2]/DMM_DATA[14] H16 MIBSPI5SOMI[3]/DMM_DATA[15] G16 28 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.11 EthernetController Table4-31.ZWTEthernetController:MDIOInterface TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Output Pullup None Serialclockoutput MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 I/O Pullup Fixed,20µA Serialdatainput/output Table4-32.ZWTEthernetController:ReducedMediaIndependentInterface(RMII) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION RMIIcarriersenseand N2HET1[12]/MII_CRS/RMII_CRS_DV B4 receivedatavalid RMIIsynchronousreference N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 clockforreceive,transmitand Fixed12µA Input Pulldown controlinterface Pulldown AD1EVT/MII_RX_ER/RMII_RX_ER N19 RMIIreceiveerror N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 RMIIreceivedata N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 RMIItransmitdata MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 Output Pullup None MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 RMIItransmitenable Table4-33.ZWTEthernetController:MediaIndependentInterface(MII) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION MIBSPI1NCS[1]/N2HET1[17]/MII_COL F3 Pullup None Collisiondetect Input Fixed20µA Carriersenseandreceive N2HET1[12]/MII_CRS/RMII_CRS_DV B4 Pulldown Pulldown datavalid N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 I/O Pulldown None MIIoutputreceiveclock N2HET1[30]/MII_RX_DV B11 Receiveddatavalid Input AD1EVT/MII_RX_ER/RMII_RX_ER N19 Receiveerror Fixed20µA N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 I/O Pulldown Receiveclock Pulldown N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 Input Receivedata MIBSPI1NENA/N2HET1[23]/MII_RXD[2] G19 Fixed20µA Pullup MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3] H18 Pulldown N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 D19 MIIoutputtransmitclock I/O Pulldown None N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 D19 Transmitclock MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 Pullup None Transmitdata MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] R2 Output N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 Pulldown None MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 Pullup None Transmitenable Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 29 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.12 ExternalMemoryInterface(EMIF) Table4-34.ExternalMemoryInterface(EMIF) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION EMIF_CKE L3 Output None EMIFClockEnable EMIFclock.Thisisanoutput signalinfunctionalmode.Itis Pulldown gatedoffbydefault,sothat EMIF_CLK K3 I/O None thesignalistri-stated. PINMUX29[8]mustbe clearedtoenablethisoutput. ETMDATA[13]/EMIF_nOE E12 Pulldown None EMIFOutputEnable Fixed20µA EMIF_nWAIT P3 I/O Pullup EMIFExtendedWaitSignal Pullup EMIF_nWE D17 Output EMIFWriteEnable. EMIF_nCAS R4 Output Pullup EMIFcolumnaddressstrobe EMIF_nRAS R3 Output EMIFrowaddressstrobe EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 Output Pulldown EMIFchipselect,SDRAM EMIF_nCS[2] L17 Output Pullup EMIFchipselects, asynchronous EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 Output Pulldown Thisappliestochipselects2, EMIF_nCS[4]/RTP_DATA[7] M17 Output Pullup 3,and4 ETMDATA[15]/EMIF_nDQM[0] E10 Output EMIFDataMaskorWrite Strobe. DatamaskforSDRAM ETMDATA[14]/EMIF_nDQM[1] E11 Output devices,writestrobefor connectedasynchronous devices. EMIFbankaddressor ETMDATA[12]/EMIF_BA[0] E13 Output addressline EMIFbankaddressor EMIF_BA[1]/N2HET2[5] D16 Output addressline EMIF_ADDR[0]/N2HET2[1] D4 Output EMIF_ADDR[1]/N2HET2[3] D5 Output ETMDATA[11]/EMIF_ADDR[2] E6 Output ETMDATA[10]/EMIF_ADDR[3] E7 Output None ETMDATA[9]/EMIF_ADDR[4] E8 Output Pulldown ETMDATA[8]/EMIF_ADDR[5] E9 Output EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 Output EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 Output EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 Output EMIF_ADDR[9]/RTP_DATA[10] C7 Output EMIF_ADDR[10]/RTP_DATA[9] C8 Output EMIFaddress EMIF_ADDR[11]/RTP_DATA[8] C9 Output EMIF_ADDR[12]/RTP_DATA[6] C10 Output EMIF_ADDR[13]/RTP_DATA[5] C11 Output EMIF_ADDR[14]/RTP_DATA[4] C12 Output EMIF_ADDR[15]/RTP_DATA[3] C13 Output EMIF_ADDR[16]/RTP_DATA[2] D14 Output EMIF_ADDR[17]/RTP_DATA[1] C14 Output EMIF_ADDR[18]/RTP_DATA[0] D15 Output EMIF_ADDR[19]/RTP_nENA C15 Output Pulldown EMIF_ADDR[20]/RTP_nSYNC C16 Output EMIF_ADDR[21]/RTP_CLK C17 Output 30 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table4-34.ExternalMemoryInterface(EMIF)(continued) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION ETMDATA[16]/EMIF_DATA[0] K15 I/O ETMDATA[17]/EMIF_DATA[1] L15 I/O ETMDATA[18]/EMIF_DATA[2] M15 I/O ETMDATA[19]/EMIF_DATA[3] N15 I/O ETMDATA[20]/EMIF_DATA[4] E5 I/O ETMDATA[21]/EMIF_DATA[5] F5 I/O ETMDATA[22]/EMIF_DATA[6] G5 I/O ETMDATA[23]/EMIF_DATA[7] K5 I/O Fixed20µA Pulldown EMIFData ETMDATA[24]/EMIF_DATA[8] L5 I/O Pullup ETMDATA[25]/EMIF_DATA[9] M5 I/O ETMDATA[26]/EMIF_DATA[10] N5 I/O ETMDATA[27]/EMIF_DATA[11] P5 I/O ETMDATA[28]/EMIF_DATA[12] R5 I/O ETMDATA[29]/EMIF_DATA[13] R6 I/O ETMDATA[30]/EMIF_DATA[14] R7 I/O ETMDATA[31]/EMIF_DATA[15] R8 I/O Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 31 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.13 EmbeddedTraceMacrocellforCortex-R4FCPU(ETM-R4F) Table4-35.EmbeddedTraceMacrocellforCortex-R4FCPU(ETM-R4F) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION Fixed20µA ETMTRACECLKIN/EXTCLKIN2 R9 Input Pulldown ETMTraceClockInput Pullup ETMTRACECLKOUT R10 ETMTraceClockOutput ETMTRACECTL R11 ETMtracecontrol ETMDATA[0] R12 ETMDATA[1] R13 ETMDATA[2] J15 ETMDATA[3] H15 ETMDATA[4] G15 ETMDATA[5] F15 ETMDATA[6] E15 ETMDATA[7] E14 ETMDATA[8]/EMIF_ADDR[5] E9 ETMDATA[9]/EMIF_ADDR[4] E8 ETMDATA[10]/EMIF_ADDR[3] E7 ETMDATA[11]/EMIF_ADDR[2] E6 ETMDATA[12]/EMIF_BA[0] E13 ETMDATA[13]/EMIF_nOE E12 ETMDATA[14]/EMIF_nDQM[1] E11 Output Pulldown None ETMDATA[15]/EMIF_nDQM[0] E10 ETMdata ETMDATA[16]/EMIF_DATA[0] K15 ETMDATA[17]/EMIF_DATA[1] L15 ETMDATA[18]/EMIF_DATA[2] M15 ETMDATA[19]/EMIF_DATA[3] N15 ETMDATA[20]/EMIF_DATA[4] E5 ETMDATA[21]/EMIF_DATA[5] F5 ETMDATA[22]/EMIF_DATA[6] G5 ETMDATA[23]/EMIF_DATA[7] K5 ETMDATA[24]/EMIF_DATA[8] L5 ETMDATA[25]/EMIF_DATA[9] M5 ETMDATA[26]/EMIF_DATA[10] N5 ETMDATA[27]/EMIF_DATA[11] P5 ETMDATA[28]/EMIF_DATA[12] R5 ETMDATA[29]/EMIF_DATA[13] R6 ETMDATA[30]/EMIF_DATA[14] R7 ETMDATA[31]/EMIF_DATA[15] R8 32 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.14 RAMTracePort(RTP) Table4-36.RAMTracePort(RTP) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION EMIF_ADDR[21]/RTP_CLK C17 I/O RTPpacketclock,orGPIO RTPpackethandshake,or EMIF_ADDR[19]/RTP_nENA C15 I/O GPIO EMIF_ADDR[20]/RTP_nSYNC C16 I/O RTPsynchronization,orGPIO EMIF_ADDR[18]/RTP_DATA[0] D15 EMIF_ADDR[17]/RTP_DATA[1] C14 Pulldown Programmable, 20µA EMIF_ADDR[16]/RTP_DATA[2] D14 EMIF_ADDR[15]/RTP_DATA[3] C13 EMIF_ADDR[14]/RTP_DATA[4] C12 EMIF_ADDR[13]/RTP_DATA[5] C11 EMIF_ADDR[12]/RTP_DATA[6] C10 Programmable, EMIF_nCS[4]/RTP_DATA[7] M17 Pullup I/O 20µA RTPpacketdata,orGPIO EMIF_ADDR[11]/RTP_DATA[8] C9 EMIF_ADDR[10]/RTP_DATA[9] C8 EMIF_ADDR[9]/RTP_DATA[10] C7 EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 Programmable, Pulldown EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 20µA EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 33 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.15 DataModificationModule(DMM) Table4-37.DataModificationModule(DMM) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION DMM_CLK F17 DMMclock,orGPIO DMM_nENA F16 DMMhandshake,orGPIO DMMsynchronization,or DMM_SYNC J16 GPIO DMM_DATA[0] L19 DMM_DATA[1] L18 MIBSPI5NCS[2]/DMM_DATA[2] W6 MIBSPI5NCS[3]/DMM_DATA[3] T12 MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN H19 MIBSPI5NCS[0]/DMM_DATA[5] E19 Programmable, I/O Pullup MIBSPI5NCS[1]/DMM_DATA[6] B6 20µA MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3] H18 DMMdata,orGPIO MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1] J19 MIBSPI5SIMO[1]/DMM_DATA[9] E16 MIBSPI5SIMO[2]/DMM_DATA[10] H17 MIBSPI5SIMO[3]/DMM_DATA[11] G17 MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0] J18 MIBSPI5SOMI[1]/DMM_DATA[13] E17 MIBSPI5SOMI[2]/DMM_DATA[14] H16 MIBSPI5SOMI[3]/DMM_DATA[15] G16 34 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.16 SystemModuleInterface Table4-38.ZWTSystemModuleInterface TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION Power-onreset,coldreset Externalpowersupplymonitor circuitrymustdrivenPORRST Fixed100µA lowwhenanyofthesupplies nPORRST W7 Input Pulldown Pulldown tothemicrocontrollerfallout ofthespecifiedrange.This terminalhasaglitchfilter. SeeSection6.8. Systemreset,warmreset, bidirectional. Theinternalcircuitryindicates anyresetconditionbydriving nRSTlow. Theexternalcircuitrycan assertasystemresetby Fixed100µA nRST B17 I/O Pullup drivingnRSTlow.Toensure Pullup thatanexternalresetisnot arbitrarilygenerated,TI recommendsthatanexternal pullupresistorisconnectedto thisterminal. Thisterminalhasaglitch filter.SeeSection6.8. ESMErrorSignal Fixed20µA nERROR B14 I/O Pulldown Indicateserrorofhigh Pulldown severity.SeeSection6.18. 4.3.2.17 ClockInputsandOutputs Table4-39.ZWTClockInputsandOutputs TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION Fromexternal OSCIN K1 Input crystal/resonator,orexternal clockinput N/A None KELVIN_GND L2 Input Kelvingroundforoscillator OSCOUT L1 Output Toexternalcrystal/resonator Programmable, Externalprescaledclock ECLK A12 I/O Pulldown 20µA output,orGIO. GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 Input Fixed20µA Externalclockinput#1 Pulldown ETMTRACECLKIN/EXTCLKIN2 R9 Input Pulldown Externalclockinput#2 1.2-V Dedicatedcoresupplyfor VCCPLL P11 N/A None Power PLLs Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 35 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.18 TestandDebugModulesInterface Table4-40.ZWTTestandDebugModulesInterface TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION Testenable.Thisterminal mustbeconnectedtoground TEST U2 I/O Pulldown Fixed100µA directlyorviaapulldown Pulldown resistor. nTRST D18 Input JTAGtesthardwarereset RTCK A16 Output N/A None JTAGreturntestclock Fixed100µA TCK B18 Input Pulldown JTAGtestclock Pulldown Fixed100µA TDI A17 I/O Pullup JTAGtestdatain Pullup 100µA TDO C18 Output None JTAGtestdataout Pulldown Fixed100µA TMS C19 I/O Pullup JTAGtestselect Pullup 4.3.2.19 FlashSupplyandTestPads Table4-41.ZWTFlashSupplyandTestPads TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION 3.3-V VCCP F8 N/A None Flashpumpsupply Power FLTP1 J5 Flashtestpads.These terminalsarereservedforTI useonly.Forproperoperation – N/A None theseterminalsmustconnect FLTP2 H5 onlytoatestpadornotbe connectedatall[noconnect (NC)]. 36 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.20 NoConnects Table4-42.NoConnects TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION NC D6 – N/A None NC D7 – N/A None NC D8 – N/A None NC D9 – N/A None NC D10 – N/A None NC D11 – N/A None NC D12 – N/A None NC D13 – N/A None NC E4 – N/A None NC F4 – N/A None NC G4 – N/A None NC K4 – N/A None NC K16 – N/A None NC L4 – N/A None NC L16 – N/A None NC M4 – N/A None NC M16 – N/A None NC N4 – N/A None NC N16 – N/A None NoConnects.Theseballsare NC N18 – N/A None notconnectedtoanyinternal logicandcanbeconnectedto NC P4 – N/A None thePCBgroundwithout NC P15 – N/A None affectingthefunctionalityof thedevice. NC P16 – N/A None NC P17 – N/A None NC R1 – N/A None NC R14 – N/A None NC R15 – N/A None NC T2 – N/A None NC T3 – N/A None NC T4 – N/A None NC T5 – N/A None NC T6 – N/A None NC T7 – N/A None NC T8 – N/A None NC T9 – N/A None NC T10 – N/A None NC T11 – N/A None NC T13 – N/A None NC T14 – N/A None NC U3 – N/A None NC U4 – N/A None Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 37 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table4-42.NoConnects(continued) TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION NC U5 – N/A None NoConnects.Theseballsare notconnectedtoanyinternal NC U6 – N/A None logicandcanbeconnectedto NC U7 – N/A None thePCBgroundwithout affectingthefunctionalityof NC U8 – N/A None thedevice. NC U9 – N/A None NC U10 – N/A None NC U11 – N/A None NC U12 – N/A None NC V3 – N/A None NC V4 – N/A None NC V11 – N/A None NC V12 – N/A None NC W4 – N/A None NC W11 – N/A None NC W12 – N/A None NC W13 – N/A None 4.3.2.21 SupplyforCoreLogic:1.2-VNominal Table4-43.ZWTSupplyforCoreLogic:1.2-VNominal TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION VCC F9 VCC F10 VCC H10 VCC J14 VCC K6 1.2-V VCC K8 N/A None Coresupply Power VCC K12 VCC K14 VCC L6 VCC M10 VCC P10 38 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 4.3.2.22 SupplyforI/OCells:3.3-VNominal Table4-44.ZWTSupplyforI/OCells:3.3-VNominal TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION VCCIO F6 VCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 3.3-V VCCIO L14 N/A None OperatingsupplyforI/Os Power VCCIO M6 VCCIO M14 VCCIO N6 VCCIO N14 VCCIO P6 VCCIO P7 VCCIO P8 VCCIO P9 VCCIO P12 VCCIO P13 VCCIO P14 Copyright©2012–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 39 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 4.3.2.23 GroundReferenceforAllSuppliesExceptVCCAD Table4-45.ZWTGroundReferenceforAllSuppliesExceptVCCAD TERMINAL RESET SIGNAL SIGNALNAME Z3W37T TYPE SPTUALTLE PULLTYPE DESCRIPTION VSS A1 VSS A2 VSS A18 VSS A19 VSS B1 VSS B19 VSS H8 VSS H9 VSS H11 VSS H12 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 Ground N/A None Groundreference VSS K9 VSS K10 VSS K11 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS M8 VSS M9 VSS M11 VSS M12 VSS V1 VSS W1 VSS W2 40 TerminalConfigurationandFunctions Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 5 Specifications 5.1 Absolute Maximum Ratings (1) OverOperatingFree-AirTemperatureRange MIN MAX UNIT V (2) –0.3 1.43 CC Supplyvoltage V ,V (2) –0.3 4.6 V CCIO CCP V –0.3 6.25 CCAD Allinputpins –0.3 4.6 Inputvoltage V ADCinputpins –0.3 6.25 I (V <0orV >V ) IK I I CCIO –20 20 Allpins,exceptAD1IN[23:0]andAD2IN[15:0] mA Inputclampcurrent I (V <0orV >V ) IK I I CCAD –10 10 AD1IN[23:0]andAD2IN[15:0] Total –40 40 mA Operatingfree-airtemperature,T : –40 125 °C A Operatingjunctiontemperature,T : –40 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Allvoltagevaluesarewithrespecttotheirassociated grounds. 5.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perAECQ100-002(1) ±2 kV Allpins ±500 VESD E(EleScDtr)opsetartfiocrmdiasnchcea:rge Chargeddevicemodel(CDM), C(1o,r3n6e,r3p7in,s72o,n7134,41-0p8in,1P0G9E,144) ±750 V perAECQ100-011 Cornerballson337-ballZWT ±750 (A1,A19,W1,W19) (1) AECQ100-002indicatesHBMstressingisdoneinaccordancewiththeANSI/ESDA/JEDECJS‑001specification. 5.3 Power-On Hours (POH)(1)(2) JUNCTION NOMINALCOREVOLTAGE(V ) LIFETIMEPOH CC TEMPERATURE(Tj) 1.2 105ºC 100K (1) ThisinformationisprovidedsolelyforyourconvenienceanddoesnotextendormodifythewarrantyprovidedunderTI'sstandardterms andconditionsforTIsemiconductorproducts. (2) Toavoidsignificantdegradation,thedevicepower-onhours(POH)mustbelimitedtothosespecifiedinthistable.Toconvertto equivalentPOHforaspecifictemperatureprofile,seetheCalculatingEquivalentPower-on-HoursforHerculesSafetyMCUsApplication Report(SPNA207). Copyright©2012–2015,TexasInstrumentsIncorporated Specifications 41 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 5.4 Recommended Operating Conditions(1) MIN NOM MAX UNIT V Digitallogicsupplyvoltage(Core) 1.14 1.2 1.32 V CC V PLLSupplyVoltage 1.14 1.2 1.32 V CCPLL V Digitallogicsupplyvoltage(I/O) 3 3.3 3.6 V CCIO V MibADCsupplyvoltage 3 3.3/5.0 5.25 V CCAD V Flashpumpsupplyvoltage 3 3.3 3.6 V CCP V Digitallogicsupplyground 0 V SS V MibADCsupplyground –0.1 0.1 V SSAD V A-to-Dhigh-voltagereferencesource V V V ADREFHI SSAD CCAD V A-to-Dlow-voltagereferencesource V V V ADREFLO SSAD CCAD V MaximumpositiveslewrateforV ,V andV supplies 1 V/µs SLEW CCIO CCAD CCP T Operatingfree-airtemperature -40 125 °C A T Operatingjunctiontemperature(2) -40 150 °C J (1) AllvoltagesarewithrespecttoV ,exceptV ,whichiswithrespecttoV SS CCAD SSAD (2) Reliabilitydataisbaseduponatemperatureprofilethatisequivalentto100,000power-onhoursat105°Cjunctiontemperature. 42 Specifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 5.5 Switching Characteristics for Clock Domains OverRecommendedOperatingConditions Table5-1.ClockDomainTimingSpecifications PARAMET DESCRIPTION CONDITIONS MIN MAX UNIT ER Pipelinemodeenabled 160 PGE Pipelinemodedisabled 50 f HCLK-Systemclockfrequency MHz HCLK Pipelinemodeenabled 180 ZWT Pipelinemodedisabled 50 f GCLK-CPUclockfrequency f MHz GCLK HCLK f VCLK-Primaryperipheralclockfrequency 100 MHz VCLK VCLK2-Secondaryperipheralclock f 100 MHz VCLK2 frequency VCLK3-Secondaryperipheralclock f 100 MHz VCLK3 frequency VCLKA1-Primaryasynchronousperipheral f 100 MHz VCLKA1 clockfrequency VCLKA2-Secondaryasynchronous f 100 MHz VCLKA2 peripheralclockfrequency VCLKA4-Secondaryasynchronous f 50 MHz VCLKA4 peripheralclockfrequency f RTICLK-clockfrequency f MHz RTICLK VCLK 5.6 Wait States Required RAM Address Wait States 0 0MHz f HCLK(max) Data Wait States 0 0MHz f HCLK(max) Flash Address Wait States 0 1 0MHz 150MHz f HCLK(max) Data Wait States 0 1 2 3 0MHz 50MHz 100MHz 150MHz f HCLK(max) Figure5-1.WaitStatesScheme As shown in Figure 5-1, the TCM RAM can support program and data fetches at full CPU speed without any addressordatawaitstatesrequired. The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode.TheflashsupportsamaximumCPUclockspeedof160MHzinpipelinedmodeforthePGEPackageand 180MHzfortheZWTpackage,withoneaddresswaitstateandthreedatawaitstates. The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state. Copyright©2012–2015,TexasInstrumentsIncorporated Specifications 43 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 5.7 Power Consumption OverRecommendedOperatingConditions PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f =180MHz HCLK (ZWTPackageonly) VCCDigitalsupplycurrent(operating 220(1) 440(2) mode) f =90MHz, VCLK Flashinpipelinedmode,V CCmax V Digitalsupplycurrent(LBISTmode) LBISTclockrate=90MHz 700(3)(4) CC (ZWTPackageonly) PBISTROMclockfrequency=90 ICC,ICCPLL VCCDigitalsupplycurrent(PBISTmode) MHz 700(3)(4) mA (ZWTPackageonly) f =160MHz HCLK VmCoCdeD)igitalsupplycurrent(operating fVCLK=80MHz, 200(1) 420(2) Flashinpipelinedmode,V CCmax V Digitalsupplycurrent(LBISTmode) LBISTclockrate=80MHz 665(3)(4) CC V Digitalsupplycurrent(PBISTmode) PBISTROMclock 665(3)(4) CC frequency=80MHz I V supplycurrent(operatingmode) NoDCload,V 10 mA CCIO CCIO CCmax SingleADCoperational,V 15 CCADmax I V supplycurrent(operatingmode) mA CCAD CCAD BothADCsoperational,V 30 CCADmax SingleADCoperational,AD 3 REFHImax I AD supplycurrent(operatingmode) mA ADREFHI REFHI BothADCsoperational,AD 6 REFHImax Readfrom1bankandprogramor I V pumpsupplycurrent 60 mA CCP CCP eraseanotherbank,V CCPmax (1) Thetypicalvalueistheaveragecurrentforthenominalprocesscornerandjunctiontemperatureof25ºC. (2) ThemaximumI valuecanbederated CC, • linearlywithvoltage • by1ma/MHzforloweroperatingfrequencywhenf =2*f HCLK VCLK • forlowerjunctiontemperaturebytheequationbelowwhereT isthejunctiontemperatureinKelvinandtheresultisinmilliamperes. JK 235-0.15e0.0174T JK (3) ThemaximumI valuecanbederated CC, • linearlywithvoltage • by1.7ma/MHzforloweroperatingfrequencywhenf =2*f HCLK VCLK • forlowerjunctiontemperaturebytheequationbelowwhereT isthejunctiontemperatureinKelvinandtheresultisinmilliamperes. JK 235-0.15e0.0174T JK (4) LBISTandPBISTcurrentsareforashortduration,typicallylessthan10ms.Theyareusuallyignoredforthermalcalculationsforthe deviceandthevoltageregulator 44 Specifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 5.8 Input/Output Electrical Characteristics(1) OverRecommendedOperatingConditions PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Allinputsexcept FRAYRX1, 180 V Inputhysteresis FRAYRX2 mV hys FRAYRX1, 100 FRAYRX2 Allinputs(2)(except FRAYRX1, –0.3 0.8 V Low-levelinputvoltage FRAYRX2) V IL FRAYRX1, 0.4V FRAYRX2 CCIO Allinputs(2)(except FRAYRX1, 2 V +0.3 CCIO V High-levelinputvoltage FRAYRX2) V IH FRAYRX1, 0.6V FRAYRX2 CCIO I =I 0.2V OL OLmax CCIO I =50µA,standard OL 0.2 outputmode V Low-leveloutputvoltage V OL I =50µA,low-EMI OL outputmode(see 0.2V CCIO Section5.13) I =I 0.8V OH OHmax CCIO I =50µA,standard OH V –0.3 outputmode CCIO V High-leveloutputvoltage V OH I =50µA,low-EMI OH outputmode(see 0.8V CCIO Section5.13) V <V -0.3orV > I Inputclampcurrent(I/Opins) I SSIO I –3.5 3.5 mA IK V +0.3 CCIO I Pulldown20µA V =V 5 40 IH I CCIO I Pulldown100µA V =V 40 195 IH I CCIO I Inputcurrent(I/Opins) I Pullup20µA V =V –40 –5 µA I IL I SS I Pullup100µA V =V –195 –40 IL I SS Allotherpins Nopulluporpulldown –1 1 C Inputcapacitance 2 pF I C Outputcapacitance 3 pF O (1) Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive. (2) ThisdoesnotapplytothenPORRSTpin. Copyright©2012–2015,TexasInstrumentsIncorporated Specifications 45 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 5.9 Thermal Resistance Characteristics Table5-2showsthethermalresistancecharacteristicsfortheQFP-PGEmechanicalpackage. Table5-3showsthethermalresistancecharacteristicsfortheBGA-ZWTmechanicalpackage. Table5-2.ThermalResistanceCharacteristics(PGEPackage) °C/W Junction-to-freeairthermalresistance,StillairusingJEDEC2S2Ptest RΘ 39 JA board RΘ Junction-to-boardthermalresistance 26.3 JB RΘ Junction-to-casethermalresistance 6.7 JC Ψ Junction-to-packagetop,Stillair 0.10 JT Table5-3.ThermalResistanceCharacteristics(ZWTPackage) °C/W Junction-to-freeairthermalresistance,Stillair(includes5x5thermalvia RΘ 18.8 JA clusterin2s2pPCBconnectedto1stgroundplane) RΘ Junction-to-boardthermalresistance 14.1 JB RΘ Junction-to-casethermalresistance 7.1 JC Junction-to-packagetop,Stillair(includes5x5thermalviaclusterin2s2p Ψ 0.33 JT PCBconnectedto1stgroundplane) 46 Specifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 5.10 Output Buffer Drive Strengths Table5-4.OutputBufferDriveStrengths LOW-LEVELOUTPUTCURRENT, I forV=V OL I OLmax or SIGNALS HIGH-LEVELOUTPUTCURRENT, I forV=V OH I OHmin FRAYTX2,FRAYTX1,FRAYTXEN1,FRAYTXEN2, MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0],MIBSPI5SIMO[1],MIBSPI5SIMO[2],MIBSPI5SIMO[3], 8mA TMS,TDI,TDO,RTCK, SPI4CLK,SPI4SIMO,SPI4SOMI,nERROR, N2HET2[1],N2HET2[3], AllEMIFOutputsandI/Os,AllETMOutputs MIBSPI3SOMI,MIBSPI3SIMO,MIBSPI3CLK,MIBSPI1SIMO,MIBSPI1SOMI,MIBSPI1CLK, 4mA nRST AD1EVT, CAN1RX,CAN1TX,CAN2RX,CAN2TX,CAN3RX,CAN3TX, DMM_CLK,DMM_DATA[0],DMM_DATA[1],DMM_nENA,DMM_SYNC, GIOA[0-7],GIOB[0-7], 2mAzero-dominant LINRX,LINTX, MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3],MIBSPI5NENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15],N2HET2[16],N2HET2[18], SPI2NCS[0],SPI2NENA,SPI4NCS[0],SPI4NENA ECLK, selectable8mA/2mA SPI2CLK,SPI2SIMO,SPI2SOMI Thedefaultoutputbufferdrivestrengthis8mAforthesesignals. Table5-5.Selectable8mA/2mAControl SIGNAL CONTROLBIT ADDRESS 8mA 2mA ECLK SYSPC10[0] 0xFFFFFF78 0 1 SPI2CLK SPI2PC9[9](1) 0xFFF7F668 0 1 SPI2SIMO SPI2PC9[10](1) 0xFFF7F668 0 1 SPI2SOMI SPI2PC9[11](1) 0xFFF7F668 0 1 (1) EitherSPI2PC9[11]orSPI2PC9[24]canchangetheoutputstrengthoftheSPI2SOMIpin.Incaseofa32-bitwritewherethesetwobits differ,SPI2PC9[11]determinesthedrivestrength. Copyright©2012–2015,TexasInstrumentsIncorporated Specifications 47 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 5.11 Input Timings t pw V CCIO Input VIH VIH VIL VIL 0 Figure5-2.TTL-LevelInputs Table5-6.TimingRequirementsforInputs(1) MIN MAX UNIT t Inputminimumpulsewidth t +10(2) ns pw c(VCLK) (1) t =peripheralVBUSclockcycletime=1/f c(VCLK) (VCLK) (2) ThetimingshowninFigure5-2isonlyvalidforpinsusedinGPIOmode. 5.12 Output Timings Table5-7.SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance(C ) L PARAMETER MIN MAX UNIT CL=15pF 2.5 CL=50pF 4 Risetime,t ns r CL=100pF 7.2 8mAlowEMIpins CL=150pF 12.5 (seeTable5-4) CL=15pF 2.5 CL=50pF 4 Falltime,t ns f CL=100pF 7.2 CL=150pF 12.5 CL=15pF 5.6 CL=50pF 10.4 Risetime,t ns r CL=100pF 16.8 4mAlowEMIpins CL=150pF 23.2 (seeTable5-4) CL=15pF 5.6 CL=50pF 10.4 Falltime,t ns f CL=100pF 16.8 CL=150pF 23.2 2mA-zlowEMIpins CL=15pF 8 (seeTable5-4) CL=50pF 15 Risetime,t ns r CL=100pF 23 CL=150pF 33 CL=15pF 8 CL=50pF 15 Falltime,t ns f CL=100pF 23 CL=150pF 33 48 Specifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table5-7.SwitchingCharacteristicsforOutputTimingsversusLoadCapacitance(C )(continued) L PARAMETER MIN MAX UNIT CL=15pF 2.5 ns CL=50pF 4 Risetime,t r CL=100pF 7.2 CL=150pF 12.5 8mAmode CL=15pF 2.5 ns CL=50pF 4 Falltime,t f CL=100pF 7.2 Selectable8mA/2mA-z CL=150pF 12.5 pins (seeTable5-4) CL=15pF 8 ns CL=50pF 15 Risetime,t r CL=100pF 23 CL=150pF 33 2mA-zmode CL=15pF 8 ns CL=50pF 15 Falltime,t f CL=100pF 23 CL=150pF 33 tr tf V CCIO Output V V OH OH VOL VOL 0 Figure5-3.CMOS-LevelOutputs Table5-8.TimingRequirementsforOutputs(1) MIN MAX UNIT Delaybetweenlowtohigh,orhightolowtransitionofgeneral-purposeoutputsignals t thatcanbeconfiguredbyanapplicationinparallel,forexample,allsignalsina 5 ns d(parallel_out) GIOAport,orallN2HET1signals,andsoforth. (1) Thisspecificationdoesnotaccountforanyoutputbufferdrivestrengthdifferencesoranyexternalcapacitiveloadingdifferences.Check Table5-4foroutputbufferdrivestrengthinformationoneachsignal. Copyright©2012–2015,TexasInstrumentsIncorporated Specifications 49 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 5.13 Low-EMI Output Buffers The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of theoutputbuffer,andisparticularlyeffectivewithcapacitiveloads. This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in Table 5-9. The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO,respectively. Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer soastomaintaintheoutputvoltageatorbelowVREFLOW. Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer’s impedance will again increase to Hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedancesoastomaintaintheoutputvoltageatoraboveVREFHIGH. The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this manner,internalbusnoiseapproaching20%peak-to-peakofVCCIOcanberejected. Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6 V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6 V without opposition. This is not an issuebecausetheactualclampcurrentcapabilityisalwaysgreaterthantheIOH/IOLspecifications. The low-EMI output buffers are automatically configured to be in the standard buffer mode when the deviceentersalow-powermode. 50 Specifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table5-9.Low-EMIOutputBufferHookup CONTROLREGISTERTO MODULEORSIGNALNAME ENABLELOW-EMIMODE Module:MibSPI1 GPREG1.0 Module:SPI2 GPREG1.1 Module:MibSPI3 GPREG1.2 Reserved GPREG1.3 Module:MibSPI5 GPREG1.4 Module:FlexRay GPREG1.5 Module:EMIF GPREG1.6 Module:ETM GPREG1.7 Signal:TMS GPREG1.8 Signal:TDI GPREG1.9 Signal:TDO GPREG1.10 Signal:RTCK GPREG1.11 Signal:TEST GPREG1.12 Signal:nERROR GPREG1.13 Reserved GPREG1.14 Module:RTP GPREG1.15 Copyright©2012–2015,TexasInstrumentsIncorporated Specifications 51 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6 System Information and Electrical Specifications 6.1 Device Power Domains The device core logic is split up into multiple power domains in order to optimize the power for a given application use case. There are 8 core power domains in total: PD1, PD2, PD3, PD4, PD5, RAM_PD1, RAM_PD2andRAM_PD3. TheactualcontentsofthesepowerdomainsareindicatedinSection1.4. PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains can be turned ON/OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of TMS570LS31X/21X Technical Reference Manual (SPNU499)formoredetails. NOTE The clocks to a module must be turned off before powering down the core domain that containsthemodule. NOTE The logic in the modules that are powered down lose power completely. Any access to modules that are powered down results in an abort being generated. When power is restored,themodulespower-uptotheirdefaultstates(afternormalpower-up).Noregisteror memorycontentsarepreservedinthecoredomainsthatareturnedoff. 52 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.2 Voltage Monitor Characteristics A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirementforaspecificsequencewhenpoweringupthecoreandI/Ovoltagesupplies. 6.2.1 Important Considerations • The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the deviceisheldinresetwhenthevoltagesuppliesareoutofrange. • The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCPsupplies. 6.2.2 Voltage Monitor Operation The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal(PGIO)onthedevice.Duringpower-uporpower-down,thePGMCUandPGIOaredrivenlowwhen the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down ofthesupplies.ThisallowsthecoreandI/Osuppliestobepoweredupordowninanyorder. When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device entersalowpowermode. The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing informationonthisglitchfilter. Table6-1.VoltageMonitoringSpecifications PARAMETER MIN TYP MAX UNIT VCClow-VCClevelbelowthisthresholdisdetectedastoo 0.75 0.9 1.13 low. Voltagemonitoring VCChigh-VCClevelabovethisthresholdisdetectedas V 1.40 1.7 2.1 V MON thresholds toohigh. VCCIOlow-VCCIOlevelbelowthisthresholdisdetected 1.85 2.4 2.9 astoolow. 6.2.3 Supply Filtering TheVMONhasthecapabilitytofilterglitchesontheVCCandVCCIOsupplies. Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specificationcannotbefiltered. Table6-2.VMONSupplyGlitchFilteringCapability PARAMETER MIN MAX UNIT WidthofglitchonVCCthatcanbefiltered 250 1000 ns WidthofglitchonVCCIOthatcanbefiltered 250 1000 ns Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 53 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.3 Power Sequencing and Power On Reset 6.3.1 Power-Up Sequence There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power- up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset.Thehighfrequencyoscillatorwillstartupfirstanditsamplitudewillgrowtoanacceptablelevel.The oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The differentsuppliestothedevicecanbepoweredupinanyorder. Thedevicegoesthroughthefollowingsequentialphasesduringpowerup. Table6-3.Power-UpPhases Oscillatorstartupandvaliditycheck 1032oscillatorcycles eFuseautoload 1180oscillatorcycles Flashpumppower-up 688oscillatorcycles Flashbankpower-up 617oscillatorcycles Total 3517oscillatorcycles The CPU reset is released at the end of the sequence in Table 6-3 and fetches the first instruction from address0x00000000. 54 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.3.2 Power-Down Sequence Thedifferentsuppliestothedevicecanbepowereddowninanyorder. 6.3.3 Power-On Reset: nPORRST This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internalpulldown. 6.3.3.1 nPORRSTElectricalandTimingRequirements Table6-4.ElectricalRequirementsfornPORRST NO. PARAMETER MIN MAX UNIT V V lowsupplylevelwhennPORRSTmustbeactiveduringpower-up 0.5 V CCPORL CC V highsupplylevelwhennPORRSTmustremainactiveduringpower- V CC 1.14 V CCPORH upandbecomeactiveduringpowerdown V /V lowsupplylevelwhennPORRSTmustbeactiveduring V CCIO CCP 1.1 V CCIOPORL power-up V /V highsupplylevelwhennPORRSTmustremainactive V CCIO CCP 3.0 V CCIOPORH duringpower-upandbecomeactiveduringpowerdown V Low-levelinputvoltageofnPORRSTV >2.5V 0.2*V V IL(PORRST) CCIO CCIO Low-levelinputvoltageofnPORRSTV <2.5V 0.5 V CCIO Setuptime,nPORRSTactivebeforeV andV >V during 3 t CCIO CCP CCIOPORL 0 ms su(PORRST) power-up 6 t Holdtime,nPORRSTactiveafterV >V 1 ms h(PORRST) CC CCPORH 7 t Setuptime,nPORRSTactivebeforeV <V duringpowerdown 2 µs su(PORRST) CC CCPORH 8 t Holdtime,nPORRSTactiveafterV andV >V 1 ms h(PORRST) CCIO CCP CCIOPORH 9 t Holdtime,nPORRSTactiveafterV <V 0 ms h(PORRST) CC CCPORL FiltertimenPORRSTpin; t 500 2000 ns f(nPORRST) pulses less than MIN will be filtered out, pulses greater than MAX will generateareset. 3.3 V V V V / V CCIOPORH CCIOPORH 8 CCIO CCP 1.2 V VCCPORH 7 VCC VCCPORH 6 6 V 7 VCCIOPORL CCIOPORL VCCPORL VCCPORL V (1.2 V) CC V / V (3.3 V) CCIO CCP 3 9 nPORRST VIL(PORRST) VIL VIL VIL VIL(PORRST) NOTE:There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. Figure6-1.nPORRSTTimingDiagram Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 55 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.4 Warm Reset (nRST) This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarilygenerated,TIrecommendsthatanexternalpullupresistorisconnectedtothisterminal. Thisterminalhasaglitchfilter.Italsohasaninternalpullup 6.4.1 Causes of Warm Reset Table6-5.CausesofWarmReset DEVICEEVENT SYSTEMSTATUSFLAG Power-UpReset ExceptionStatusRegister,bit15 Oscillatorfail GlobalStatusRegister,bit0 PLLslip GlobalStatusRegister,bits8and9 Watchdogexception/Debuggerreset ExceptionStatusRegister,bit13 CPUReset(drivenbytheCPUSTC) ExceptionStatusRegister,bit5 SoftwareReset ExceptionStatusRegister,bit4 ExternalReset ExceptionStatusRegister,bit3 6.4.2 nRST Timing Requirements Table6-6.nRSTTimingRequirements MIN MAX UNIT t Validtime,nRSTactiveafternPORRSTinactive 2256t (1) v(RST) c(OSC) ns Validtime,nRSTactive(allotherSystemresetconditions) 32t c(VCLK) t FiltertimenRSTpin;pulseslessthanMINwillbefilteredout;pulsesgreater f(nRST) 475 2000 ns thanMAXwillgenerateareset.SeeSection6.8. (1) AssumestheoscillatorhasstartedupandstabilizedbeforenPORRSTisreleased. 56 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.5 ARM-R4F CPU Information 6.5.1 Summary of ARM Cortex-R4F CPU Features ThefeaturesoftheARMCortex-R4FCPUinclude: • AnintegerunitwithintegralEmbeddedICE-RTlogic. • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) forLeveltwo(L2)masterandslaveinterfaces. • FloatingPointCoprocessor • Dynamicbranchpredictionwithaglobalhistorybuffer,anda4-entryreturnstack • Lowinterruptlatency. • Nonmaskableinterrupt. • AHarvardLevelone(L1)memorysystemwith: – Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking memories – ARMv7-RarchitectureMemoryProtectionUnit(MPU)with12regions • Dualcorelogicforfaultdetectioninsafety-criticalapplications. • AnL2memoryinterface: – Single64-bitmasterAXIinterface – 64-bitslaveAXIinterfacetoTCMRAMblocks • AdebuginterfacetoaCoreSightDebugAccessPort(DAP). • AtraceinterfacetoaCoreSightETM-R4. • APerformanceMonitoringUnit(PMU). • AVectoredInterruptController(VIC)port. FormoreinformationontheARMCortex-R4FCPUseewww.arm.com. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software ThefollowingCPUfeaturesaredisabledonresetandmustbeenabledbytheapplicationifrequired. • ECCOnTightly-CoupledMemory(TCM)Accesses • HardwareVectoredInterrupt(VIC)Port • FloatingPointCoprocessor • MemoryProtectionUnit(MPU) 6.5.3 Dual Core Implementation The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM- R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two clockcyclesasshowninFigure6-3. TheCPUshaveadiverseCPUplacementgivenbyfollowingrequirements: • differentorientation;forexample,CPU1="north"orientation,CPU2="flipwest"orientation • dedicatedguardringforeachCPU North Flip West F F Figure6-2.Dual-CPUOrientation Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 57 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.5.4 Duplicate Clock Tree After GCLK The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU runningatthesamefrequencyandinphasetotheclockofCPU1.SeeFigure6-3. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety ThisdevicehastwoARMCortex-R4FCPUcores,wheretheoutputsignalsofbothCPUsarecomparedin theCCM-R4unit.ToavoidcommonmodeimpactsthesignalsoftheCPUstobecomparedaredelayedin adifferentwayasshowninFigure6-3. Output + Control CCM-R4 2 cycle delay CCM-R4 compare CPU1CLK compare error CPU1 CPU2 2 cycle delay CPU2CLK Input + Control Figure6-3.DualCoreImplementation To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed ontothestack. 6.5.6 CPU Self-Test The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the DeterministicLogicBISTControllerasthetestengine. Themainfeaturesoftheself-testcontrollerare: • Abilitytodividethecompletetestrunintoindependenttestintervals • Capableofrunningthecompletetestaswellasrunningfewintervalsatatime • Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning(Firsttestset) • Completeisolationoftheself-testedCPUcorefromrestofthesystemduringtheself-testrun • AbilitytocapturetheFailureintervalnumber • Time-outcounterfortheCPUself-testrunasafail-safefeature 58 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.5.6.1 ApplicationSequenceforCPUSelf-Test 1. Configureclockdomainfrequencies. 2. Selectnumberoftestintervalstoberun. 3. Configurethetime-outperiodfortheself-testrun. 4. Enableself-test. 5. WaitforCPUreset. 6. Intheresethandler,readCPUself-teststatustoidentifyanyfailures. 7. RetrieveCPUstateifrequired. Formoreinformationseethedevicespecifictechnicalreferencemanual. 6.5.6.2 CPUSelf-TestClockConfiguration The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock. ThisdividerisconfiguredbytheSTCCLKDIVregisterataddress0xFFFFE108. Formoreinformationseethedevicespecifictechnicalreferencemanual. 6.5.6.3 CPUSelf-TestCoverage Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test cycles.ThetesttimecanbecalculatedbymultiplyingthenumberoftestcycleswiththeSTCclockperiod. Table6-7.CPUSelf-TestCoverage INTERVALS TESTCOVERAGE,% TESTCYCLES 0 0 0 1 62.13 1365 2 70.09 2730 3 74.49 4095 4 77.28 5460 5 79.28 6825 6 80.90 8190 7 82.02 9555 8 83.10 10920 9 84.08 12285 10 84.87 13650 11 85.59 15015 12 86.11 16380 13 86.67 17745 14 87.16 19110 15 87.61 20475 16 87.98 21840 17 88.38 23205 18 88.69 24570 19 88.98 25935 20 89.28 27300 21 89.50 28665 22 89.76 30030 23 90.01 31395 24 90.21 32760 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 59 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.6 Clocks 6.6.1 Clock Sources Table 6-8 lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table correspondstothecontrolbitintheCSDISxregisterforthatclocksource. Table6-8alsoshowsthedefaultstateofeachclocksource. Table6-8.AvailableClockSources CLOCK DEFAULT NAME DESCRIPTION SOURCE# STATE 0 OSCIN MainOscillator Enabled 1 PLL1 OutputFromPLL1 Disabled 2 Reserved Reserved Disabled 3 EXTCLKIN1 ExternalClockInput#1 Disabled 4 CLK80K LowFrequencyOutputofInternalReferenceOscillator Enabled 5 CLK10M HighFrequencyOutputofInternalReferenceOscillator Enabled 6 PLL2 OutputFromPLL2 Disabled 7 EXTCLKIN2 ExternalClockInput#2 Disabled 6.6.1.1 MainOscillator The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurementandlowpowermodes. TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum startup and operation over temperature/voltageextremes. Anexternaloscillatorsourcecanbeusedbyconnectinga3.3-VclocksignaltotheOSCINpinandleaving theOSCOUTpinunconnected(open)asshowninFigure6-4. (see Note B) OSCIN Kelvin_GND OSCOUT OSCIN OSCOUT C1 C2 External (see NoteA) Clock Signal (toggling 0 V to 3.3 V) Crystal (a) (b) NoteA:The values of C1 and C2 should be provided by the resonator/crystal vendor. Note B: Kelvin_GND should not be connected to any other GND. Figure6-4.RecommendedCrystal/ClockConnection 60 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.6.1.1.1 TimingRequirementsforMainOscillator Table6-9.TimingRequirementsforMainOscillator MIN MAX UNIT t Cycletime,OSCIN(whenusingasine-waveinput) 50 200 ns c(OSC) t Cycletime,OSCIN,(wheninputtotheOSCINisasquarewave) 50 200 ns c(OSC_SQR) t Pulseduration,OSCINlow(wheninputtotheOSCINisasquarewave) 6 ns w(OSCIL) t Pulseduration,OSCINhigh(wheninputtotheOSCINisasquarewave) 6 ns w(OSCIH) Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 61 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.6.1.2 LowPowerOscillator The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro. 6.6.1.2.1 Features ThemainfeaturesoftheLPOare: • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4oftheGlobalClockModule. • Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5 oftheGlobalClockModule. • Providesacomparisonclockforthecrystaloscillatorfailuredetectioncircuit. BIAS_EN LFEN CLK80K LF_TRIM Low Power HFEN Oscillator CLK10M HF_TRIM CLK10M_VALID nPORRST Figure6-5.LPOBlockDiagram Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO) andprovidestwoclocksources:onenominally80kHzandonenominally10MHz. 6.6.1.2.2 LPOElectricalandTimingSpecifications Table6-10.LPOSpecifications PARAMETER MIN TYP MAX UNIT Oscillatorfailfrequency-lowerthreshold,using 1.375 2.4 4.875 MHz untrimmedLPOoutput ClockDetection Oscillatorfailfrequency-higherthreshold,using 22 38.4 78 MHz untrimmedLPOoutput Untrimmedfrequency 5.5 9 19.5 MHz Trimmedfrequency 8 9.6 11 MHz LPO-HFoscillator (fHFLPO) StartuptimefromSTANDBY(LPOBIAS_ENHighfor 10 µs atleast900µs) Coldstartuptime 900 µs Untrimmedfrequency 36 85 180 kHz LPO-LFoscillator StartuptimefromSTANDBY(LPOBIAS_ENHighfor 100 µs (f ) atleast900µs) LFLPO coldstartuptime 2000 µs 62 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.6.1.3 PhaseLockedLoop(PLL)ClockModules ThePLLisusedtomultiplytheinputfrequencytosomehigherfrequency. ThemainfeaturesofthePLLare: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequencymodulationcapabilityofPLL2ispermanentlydisabled. • Configurablefrequencymultipliersanddividers. • Built-inPLLSlipmonitoringcircuit. • OptiontoresetthedeviceonaPLLslipdetection. 6.6.1.3.1 BlockDiagram Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplieranddividersforPLL2. OSCIN /NR INTCLK VCOCLK /OD post_ODCLK /R PLLCLK /1 to /64 PLL /1 to /8 /1 to /32 f = (f / NR) * NF / (OD * R) PLLCLK OSCIN /NF /1 to /256 OSCIN /NR2 INTCLK2 VCOCLK2 /OD2 post_ODCLK2 /R2 PLL2CLK /1 to /64 PLL#2 /1 to /8 /1 to /32 /NF2 fPLL2CLK= (fOSCIN / NR2) * NF2 / (OD2 * R2) /1 to /256 Figure6-6.ZWTPLLxBlockDiagram 6.6.1.3.2 PLLTimingSpecifications Table6-11.PLLTimingSpecifications PARAMETER MIN MAX UNIT f PLL1ReferenceClockfrequency 1 20 MHz INTCLK f Post-ODCLK–PLL1Post-dividerinputclockfrequency 400 MHz post_ODCLK f VCOCLK–PLL1OutputDivider(OD)inputclockfrequency 150 550 MHz VCOCLK f PLL2ReferenceClockfrequency 1 20 MHz INTCLK2 f Post-ODCLK–PLL2Post-dividerinputclockfrequency 400 MHz post_ODCLK2 f VCOCLK–PLL2OutputDivider(OD)inputclockfrequency 150 550 MHz VCOCLK2 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 63 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.6.1.4 ExternalClockInputs The device supports up to two external clock inputs. This clock input must be a square wave input. The electrical and timing requirements for these clock inputs are specified in Table 6-12. The external clock sourcesarenotcheckedforvalidity.Theyareassumedvalidwhenenabled. Table6-12.ExternalClockTimingandElectricalSpecifications PARAMETER DESCRIPTION MIN MAX UNIT f Externalclockinputfrequency 80 MHz EXTCLKx t EXTCLKhigh-pulseduration 6 ns w(EXTCLKIN)H t EXTCLKlow-pulseduration 6 ns w(EXTCLKIN)L v Low-levelinputvoltage -0.3 0.8 V iL(EXTCLKIN) v High-levelinputvoltage 2 VCCIO+0.3 V iH(EXTCLKIN) 6.6.2 Clock Domains 6.6.2.1 ClockDomainDescriptions Table 6-13 lists the device clock domains and their default clock sources. The table also shows the systemmodulecontrolregisterthatisusedtoselectanavailableclocksourceforeachclockdomain. Table6-13.ClockDomainDescriptions CLOCKSOURCE CLOCKDOMAIN DEFAULTCLOCK SELECTION DESCRIPTION NAME SOURCE REGISTER HCLK OSCIN GHVSRC • IsdisabledviatheCDDISxregistersbit1 • UsedforallsystemmodulesincludingDMA,ESM GCLK OSCIN GHVSRC • AlwaysthesamefrequencyasHCLK • InphasewithHCLK • IsdisabledseparatelyfromHCLKviatheCDDISxregistersbit0 • Canbedividedby1upto8whenrunningCPUself-test(LBIST) usingtheCLKDIVfieldoftheSTCCLKDIVregisterataddress 0xFFFFE108 GCLK2 OSCIN GHVSRC • AlwaysthesamefrequencyasGCLK • 2cyclesdelayedfromGCLK • IsdisabledalongwithGCLK • GetsdividedbythesamedividersettingasthatforGCLKwhen runningCPUself-test(LBIST) VCLK OSCIN GHVSRC • DivideddownfromHCLK • CanbeHCLK/1,HCLK/2,...orHCLK/16 • IsdisabledseparatelyfromHCLKviatheCDDISxregistersbit2 VCLK2 OSCIN GHVSRC • DivideddownfromHCLK • CanbeHCLK/1,HCLK/2,...orHCLK/16 • FrequencymustbeanintegermultipleofVCLKfrequency • IsdisabledseparatelyfromHCLKviatheCDDISxregistersbit3 VCLK3 OSCIN GHVSRC • DivideddownfromHCLK • CanbeHCLK/1,HCLK/2,...orHCLK/16 • IsdisabledseparatelyfromHCLKviatheCDDISxregistersbit8 VCLKA1 VCLK VCLKASRC • DefaultstoVCLKasthesource • IsdisabledviatheCDDISxregistersbit4 VCLKA2 VCLK VCLKASRC • DefaultstoVCLKasthesource • IsdisabledviatheCDDISxregistersbit5 64 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-13.ClockDomainDescriptions(continued) CLOCKSOURCE CLOCKDOMAIN DEFAULTCLOCK SELECTION DESCRIPTION NAME SOURCE REGISTER VCLKA3 VCLK VCLKACON1 • DefaultstoVCLKasthesource • FrequencycanbeasfastasHCLKfrequency. • IsdisabledviatheCDDISxregistersbit10 VCLKA3_DIVR VCLK VCLKACON1 • DivideddownfromtheVCLKA3usingtheVCLKA3Rfieldofthe VCLKACON1registerataddress0xFFFFE140 • FrequencycanbeVCLKA3/1,VCLKA3/2,...,orVCLKA3/8 • DefaultfrequencyisVCLKA3/2 • IsdisabledseparatelyviatheVCLKACON1register VCLKA3_DIV_CDDISbitonlyiftheVCLKA3clockisnot disabled VCLKA4 VCLK VCLKACON1 • DefaultstoVCLKasthesource • IsdisabledviatheCDDISxregistersbit11 RTICLK VCLK RCLKSRC • DefaultstoVCLKasthesource • IfaclocksourceotherthanVCLKisselectedforRTICLK,then theRTICLKfrequencymustbelessthanorequaltoVCLK/3 – ApplicationcanensurethisbyprogrammingtheRTI1DIV fieldoftheRCLKSRCregister,ifnecessary • IsdisabledviatheCDDISxregistersbit6 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 65 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.6.2.2 MappingofClockDomainstoDeviceModules EachclockdomainhasadedicatedfunctionalityasshowninFigure6-7. GCM 0 OSCIN GCLK, GCLK2(to CPU) FMzPLL (SSPLL) HCLK(to SYSTEM) /1..64 X1..256 /1..8 /1..32 * 1 /1..16 VCLK_peri(VCLKtoperipheralson PCR1) VCLK_sys(VCLKtosystem modules) 80kHz 4 /1..16 VCLK2 (to N2HETx and HTUx) Low Power Oscillator 10MHz 5 /1..16 VCLK3 (to EMIF, and Ethernet) PLL# 2 (SSPLL) /1..64 X1..256 /1..8 /1..32 * 6 0 1 * the frequency at this node must not EXTCLKIN1 3 3 exceed the maximum HCLK specifiation. 4 VCLKA1(to DCANx) EXTCLKIN2 7 5 6 7 VCLK VCLK3 0 VCLKA4 1 3 4 VCLKA2 (to FlexRay) 5 6 7 VCLK Ethernet 0 1 3 4 5 VCLKA4 (to Ethernet, as alternate 6 forMIITXCLK and/orMIIRXCLK) 0 7 1 VCLK 3 4 /1, 2, 4, or 8 5 6 RTICLK(to RTI, DWWD) 7 EMIF VCLK VCLKA1 VCLK VCLK2 VCLKA2 VCLKA2 VCLK2 /1,2,..1024 /1,2,..4 /1,2,..256 /2,3..224 /1,2..32 /1,2..65536 /1,2..256 /1H.R.6P4 FlexRay N2HETx GTUC1,2 TU TU Prop_seg Phase_seg2 FlBReaxaRuteday BauSdP RIate BLaINud/ RSaCteI ADCLK ECLK Ir2aCte baud /2L0R..P25 Phase_seg1 SPIx,MibSPIx LIN, SCI MibADCx External Clock I2C High Loop FlexRay Resolution Clock EXTCLKIN1 CAN Baud Rate NTU[3] PLL#2 output NTU[2] N2HETx Startof cycle RTI DCANx MacroTick NTU[1] NTU[0] Figure6-7.DeviceClockDomains 66 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.6.3 Clock Test Mode The TMS570 platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured via the CLKTEST register in the system module. Table6-14.ClockTestModeOptions SEL_ECP_PIN SEL_GIO_PIN = SIGNALONECLK = SIGNALONN2HET1[12] CLKTEST[3-0] CLKTEST[11-8] 0000 Oscillator 0000 OscillatorValidStatus 0001 MainPLLfree-runningclockoutput 0001 MainPLLValidstatus 0010 Reserved 0010 Reserved 0011 EXTCLKIN1 0011 Reserved 0100 CLK80K 0100 Reserved 0101 CLK10M 0101 CLK10MValidstatus 0110 SecondaryPLLfree-runningclockoutput 0110 SecondaryPLLValidStatus 0111 EXTCLKIN2 0111 Reserved 1000 GCLK 1000 CLK80K 1001 RTIBase 1001 Reserved 1010 Reserved 1010 Reserved 1011 VCLKA1 1011 Reserved 1100 VCLKA2 1100 Reserved 1101 Reserved 1101 Reserved 1110 VCLKA4 1110 Reserved 1111 Reserved 1111 Reserved Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 67 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.7 Clock Monitoring The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low poweroscillator(LPO). TheLPOprovidestwodifferentclocksources –alowfrequency(LFLPO)andahighfrequency(HFLPO). The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp modeclock). ThevalidOSCINfrequencyrangeisdefinedas:f /4<f < f *4. HFLPO OSCIN HFLPO 6.7.1 Clock Monitor Timings FormoreinformationonLPOandClockdetection,refertoTable6-10. lower upper fail pass fail threshold threshold f[MHz] 1.375 4.875 22 78 Figure6-8.LPOandClockDetection,UntrimmedHFLPO 6.7.2 External Clock (ECLK) Output Functionality The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock. Thisoutputcanbeexternallymonitoredasasafetydiagnostic. 6.7.3 Dual Clock Comparators The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allowstheDCC1tomonitorthePLLoutputclockwhenVCLKisusingthePLLoutputasitssource. An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1 doesnotreach0withinthecountingwindowgeneratedbycounter0. 6.7.3.1 Features • Takestwodifferentclocksourcesasinputtotwoindependentcounterblocks. • Oneoftheclocksourcesistheknown-good,orreferenceclock;thesecondclocksourceisthe"clockundertest." • Eachcounterblockisprogrammablewithinitial,orseedvalues. • The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequencyfortheclockundertestgeneratesanerrorsignalwhichisusedtointerrupttheCPU. 68 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.7.3.2 MappingofDCCClockSourceInputs Table6-15.DCC1Counter0ClockSources CLOCKSOURCE[3:0] CLOCKNAME others oscillator(OSCIN) 0x5 highfrequencyLPO 0xA testclock(TCK) Table6-16.DCC1Counter1ClockSources KEY[3:0] CLOCKSOURCE[3:0] CLOCKNAME others - N2HET1[31] 0x0 MainPLLfree-runningclockoutput 0x1 PLL#2free-runningclockoutput 0x2 lowfrequencyLPO 0xA 0x3 highfrequencyLPO 0x4 flashHDpumposcillator 0x5 EXTCLKIN1 0x6 EXTCLKIN2 0x7 ringoscillator 0x8-0xF VCLK Table6-17.DCC2Counter0ClockSources CLOCKSOURCE[3:0] CLOCKNAME others oscillator(OSCIN) 0xA testclock(TCK) Table6-18.DCC2Counter1ClockSources KEY[3:0] CLOCKSOURCE[3:0] CLOCKNAME others - N2HET2[0] 0xA 00x0-0x7 Reserved 0x8-0xF VCLK Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 69 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.8 Glitch Filters Aglitchfilterispresentonthefollowingsignals. Table6-19.GlitchFilterTimingSpecifications PIN PARAMETER MIN MAX UNIT FiltertimenPORRSTpin; nPORRST t 475 2000 ns f(nPORRST) pulses less than MIN will be filtered out, pulses greater than MAXwillgenerateareset(1) FiltertimenRSTpin; nRST t 475 2000 ns f(nRST) pulses less than MIN will be filtered out, pulses greater than MAXwillgenerateareset FiltertimeTESTpin; TEST t 475 2000 ns f(TEST) pulses less than MIN will be filtered out, pulses greater than MAXwillpassthrough (1) TheglitchfilterdesignonthenPORRSTsignalisdesignedsuchthatnosizepulsewillresetanypartofthemicrocontroller(flashpump, I/Opins,andsoforth)withoutalsogeneratingavalidresetsignaltotheCPU. 70 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.9 Device Memory Map 6.9.1 Memory Map Diagram Figure6-9showsthedevicememorymap. 0xFFFFFFFF SYSTEM Modules 0xFFF80000 Peripherals- Frame 1 0xFF000000 CRC 0xFE000000 RESERVED 0xFCFFFFFF Peripherals- Frame 2 0xFC000000 RESERVED 0xF07FFFFF Flash Module Bus2 Interface (Flash ECC, OTPand EEPROM accesses) 0xF0000000 RESERVED 0x87FFFFFF EMIF (128MB) 0x80000000 CS0 SDRAM RESERVED 0x6FFFFFFF reserved 0x6C000000 EMIF (16MB * 3) CS4 0x68000000 CS3 0x64000000 Async RAM 0x60000000 CS2 RESERVED 0x202FFFFF Flash (3MB) (Mirrored Image) 0x20000000 RESERVED 0x0843FFFF RAM - ECC 0x08400000 RESERVED 0x0803FFFF RAM (256KB) 0x08000000 RESERVED 0x002FFFFF Flash (3MB) 0x00000000 Figure6-9.TMS570LS3137MemoryMap The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash imageis0x20000000. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 71 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.9.2 Memory Map Table Table6-20.DeviceMemoryMap FRAMEADDRESSRANGE RESPONSEFORACCESSTO FRAMECHIP FRAME ACTUAL MODULENAME UNIMPLEMENTEDLOCATIONSIN SELECT START END SIZE SIZE FRAME MEMORIESTIGHTLYCOUPLEDTOTHEARMCORTEX-R4FCPU TCMFlash CS0 0x00000000 0x00FFFFFF 16MB 3MB TCMRAM+RAM CSRAM0 0x08000000 0x0BFFFFFF 64MB 256KB Abort ECC MirroredFlash Flashmirrorframe 0x20000000 0x20FFFFFF 16MB 3MB EXTERNALMEMORYACCESSES EMIFChipSelect2 EMIFselect2 0x60000000 0x63FFFFFF 64MB 16MB (asynchronous) EMIFChipSelect3 EMIFselect3 0x64000000 0x67FFFFFF 64MB 16MB (asynchronous) Accessto"Reserved"spacewillgenerate EMIFChipSelect4 Abort EMIFselect4 0x68000000 0x6BFFFFFF 64MB 16MB (asynchronous) EMIFChipSelect0 EMIFselect0 0x80000000 0x87FFFFFF 128MB 128MB (synchronous) FLASHMODULEBUS2INTERFACE CustomerOTP, 0xF0000000 0xF0001FFF 8KB 4KB TCMFlashBank0 CustomerOTP, 0xF0002000 0xF0003FFF 8KB 4KB TCMFlashBank1 CustomerOTP, 0xF000E000 0xF000FFFF 8KB 2KB EEPROMBank7 Customer OTP–ECC,TCM 0xF0040000 0xF00403FF 1KB 512B FlashBank0 Customer OTP–ECC,TCM 0xF0040400 0xF00407FF 1KB 512B FlashBank1 Customer OTP–ECC, 0xF0041C00 0xF0041FFF 1KB 256B EEPROMBank7 TIOTP,TCMFlash 0xF0080000 0xF0081FFF 8KB 4KB Bank0 Abort TIOTP,TCMFlash 0xF0082000 0xF0083FFF 8KB 4KB Bank1 TIOTP,EEPROM 0xF008E000 0xF008FFFF 8KB 2KB Bank7 TIOTP–ECC,TCM 0xF00C0000 0xF00C03FF 1KB 512B FlashBank0 TIOTP–ECC,TCM 0xF00C0400 0xF00C07FF 1KB 512B FlashBank1 TIOTP–ECC, 0xF00C1C00 0xF00C1FFF 1KB 256B EEPROMBank7 EEPROM 0xF0100000 0xF013FFFF 256KB 8KB Bank–ECC EEPROMBank 0xF0200000 0xF03FFFFF 2MB 64KB FlashDataSpace 0xF0400000 0xF04FFFFF 1MB 384KB ECC ETHERNETANDEMIFSLAVEINTERFACES CPPIMemorySlave 0xFC520000 0xFC521FFF 8KB 8KB Abort (EthernetRAM) EMACSlave 0xFCF78000 0xFCF787FF 2KB 2KB Noerror (EthernetSlave) EMACSSWrapper 0xFCF78800 0xFCF788FF 256B 256B Noerror (EthernetWrapper) EthernetMDIO 0xFCF78900 0xFCF789FF 256B 256B Noerror Interface EMIFRegisters 0xFCFFE800 0xFCFFE8FF 256B 256B Abort 72 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-20.DeviceMemoryMap(continued) FRAMEADDRESSRANGE RESPONSEFORACCESSTO FRAMECHIP FRAME ACTUAL MODULENAME UNIMPLEMENTEDLOCATIONSIN SELECT START END SIZE SIZE FRAME CYCLICREDUNDANCYCHECKER(CRC)MODULEREGISTERS CRC CRCframe 0xFE000000 0xFEFFFFFF 16MB 512B Accessesabove0x200generateabort. PERIPHERALMEMORIES MIBSPI5RAM PCS[5] 0xFF0A0000 0xFF0BFFFF 128KB 2KB Abortforaccessesabove2KB MIBSPI3RAM PCS[6] 0xFF0C0000 0xFF0DFFFF 128KB 2KB Abortforaccessesabove2KB MIBSPI1RAM PCS[7] 0xFF0E0000 0xFF0FFFFF 128KB 2KB Abortforaccessesabove2KB Wraparoundforaccessesto unimplementedaddressoffsetslowerthan DCAN3RAM PCS[13] 0xFF1A0000 0xFF1BFFFF 128KB 2KB 0x7FF.Abortgeneratedforaccesses beyondoffset0x800. Wraparoundforaccessesto unimplementedaddressoffsetslowerthan DCAN2RAM PCS[14] 0xFF1C0000 0xFF1DFFFF 128KB 2KB 0x7FF.Abortgeneratedforaccesses beyondoffset0x800. Wraparoundforaccessesto unimplementedaddressoffsetslowerthan DCAN1RAM PCS[15] 0xFF1E0000 0xFF1FFFFF 128KB 2KB 0x7FF.Abortgeneratedforaccesses beyondoffset0x800. Wraparoundforaccessesto unimplementedaddressoffsetslowerthan MIBADC2RAM PCS[29] 0xFF3A0000 0xFF3BFFFF 128KB 8KB 0x1FFF.Abortgeneratedforaccesses beyond0x1FFF. Wraparoundforaccessesto unimplementedaddressoffsetslowerthan MIBADC1RAM PCS[31] 0xFF3E0000 0xFF3FFFFF 128KB 8KB 0x1FFF.Abortgeneratedforaccesses beyond0x1FFF. Wraparoundforaccessesto unimplementedaddressoffsetslowerthan N2HET2RAM PCS[34] 0xFF440000 0xFF45FFFF 128KB 16KB 0x3FFF.Abortgeneratedforaccesses beyond0x3FFF. Wraparoundforaccessesto unimplementedaddressoffsetslowerthan N2HET1RAM PCS[35] 0xFF460000 0xFF47FFFF 128KB 16KB 0x3FFF.Abortgeneratedforaccesses beyond0x3FFF. HTU2RAM PCS[38] 0xFF4C0000 0xFF4DFFFF 128KB 1KB Abort HTU1RAM PCS[39] 0xFF4E0000 0xFF4FFFFF 128KB 1KB Abort FTURAM PCS[40] 0xFF500000 0xFF51FFFF 128KB 1KB Abort DEBUGCOMPONENTS CoreSightDebug CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads:0,writes:noeffect ROM Cortex-R4FDebug CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads:0,writes:noeffect ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads:0,writes:noeffect CoreSightTPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads:0,writes:noeffect POM CSCS4 0xFFA04000 0xFFA04FFF 4KB 4KB Abort PERIPHERALCONTROLREGISTERS FTU PS[23] 0xFFF7A000 0xFFF7A1FF 512B 512B Reads:0,writes:noeffect HTU1 PS[22] 0xFFF7A400 0xFFF7A4FF 256B 256B Reads:0,writes:noeffect HTU2 PS[22] 0xFFF7A500 0xFFF7A5FF 256B 256B Reads:0,writes:noeffect N2HET1 PS[17] 0xFFF7B800 0xFFF7B8FF 256B 256B Reads:0,writes:noeffect N2HET2 PS[17] 0xFFF7B900 0xFFF7B9FF 256B 256B Reads:0,writes:noeffect GPIO PS[16] 0xFFF7BC00 0xFFF7BCFF 256B 256B Reads:0,writes:noeffect MIBADC1 PS[15] 0xFFF7C000 0xFFF7C1FF 512B 512B Reads:0,writes:noeffect MIBADC2 PS[15] 0xFFF7C200 0xFFF7C3FF 512B 512B Reads:0,writes:noeffect FlexRay PS[12]+PS[13] 0xFFF7C800 0xFFF7CFFF 2KB 2KB Reads:0,writes:noeffect I2C PS[10] 0xFFF7D400 0xFFF7D4FF 256B 256B Reads:0,writes:noeffect DCAN1 PS[8] 0xFFF7DC00 0xFFF7DDFF 512B 512B Reads:0,writes:noeffect DCAN2 PS[8] 0xFFF7DE00 0xFFF7DFFF 512B 512B Reads:0,writes:noeffect Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 73 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-20.DeviceMemoryMap(continued) FRAMEADDRESSRANGE RESPONSEFORACCESSTO FRAMECHIP FRAME ACTUAL MODULENAME UNIMPLEMENTEDLOCATIONSIN SELECT START END SIZE SIZE FRAME DCAN3 PS[7] 0xFFF7E000 0xFFF7E1FF 512B 512B Reads:0,writes:noeffect LIN PS[6] 0xFFF7E400 0xFFF7E4FF 256B 256B Reads:0,writes:noeffect SCI PS[6] 0xFFF7E500 0xFFF7E5FF 256B 256B Reads:0,writes:noeffect MibSPI1 PS[2] 0xFFF7F400 0xFFF7F5FF 512B 512B Reads:0,writes:noeffect SPI2 PS[2] 0xFFF7F600 0xFFF7F7FF 512B 512B Reads:0,writes:noeffect MibSPI3 PS[1] 0xFFF7F800 0xFFF7F9FF 512B 512B Reads:0,writes:noeffect SPI4 PS[1] 0xFFF7FA00 0xFFF7FBFF 512B 512B Reads:0,writes:noeffect MibSPI5 PS[0] 0xFFF7FC00 0xFFF7FDFF 512B 512B Reads:0,writes:noeffect SYSTEMMODULESCONTROLREGISTERSANDMEMORIES DMARAM PPCS0 0xFFF80000 0xFFF80FFF 4KB 4KB Abort Wraparoundforaccessesto VIMRAM PPCS2 0xFFF82000 0xFFF82FFF 4KB 1KB unimplementedaddressoffsetsbetween 1kBand4kB. RTPRAM PPCS3 0xFFF83000 0xFFF83FFF 4KB 4KB Abort FlashModule PPCS7 0xFFF87000 0xFFF87FFF 4KB 4KB Abort eFuseController PPCS12 0xFFF8C000 0xFFF8CFFF 4KB 4KB Abort PowerManagement PPSE0 0xFFFF0000 0xFFFF01FF 512B 512B Abort Module(PMM) TestController PPSE1 0xFFFF0400 0xFFFF07FF 1KB 1KB Reads:0,writes:noeffect (FMTM) PCRregisters PPS0 0xFFFFE000 0xFFFFE0FF 256B 256B Reads:0,writes:noeffect SystemModule- Frame2(seedevice PPS0 0xFFFFE100 0xFFFFE1FF 256B 256B Reads:0,writes:noeffect TRM) PBIST PPS1 0xFFFFE400 0xFFFFE5FF 512B 512B Reads:0,writes:noeffect Generatesaddresserrorinterrupt,if STC PPS1 0xFFFFE600 0xFFFFE6FF 256B 256B enabled IOMMMultiplexing PPS2 0xFFFFEA00 0xFFFFEBFF 512B 512B Reads:0,writes:noeffect ControlModule DCC1 PPS3 0xFFFFEC00 0xFFFFECFF 256B 256B Reads:0,writes:noeffect DMA PPS4 0xFFFFF000 0xFFFFF3FF 1KB 1KB Reads:0,writes:noeffect DCC2 PPS5 0xFFFFF400 0xFFFFF4FF 256B 256B Reads:0,writes:noeffect ESM PPS5 0xFFFFF500 0xFFFFF5FF 256B 256B Reads:0,writes:noeffect CCMR4 PPS5 0xFFFFF600 0xFFFFF6FF 256B 256B Reads:0,writes:noeffect DMM PPS5 0xFFFFF700 0xFFFFF7FF 256B 256B Reads:0,writes:noeffect RAMECCeven PPS6 0xFFFFF800 0xFFFFF8FF 256B 256B Reads:0,writes:noeffect RAMECCodd PPS6 0xFFFFF900 0xFFFFF9FF 256B 256B Reads:0,writes:noeffect RTP PPS6 0xFFFFFA00 0xFFFFFAFF 256B 256B Reads:0,writes:noeffect RTI+DWWD PPS7 0xFFFFFC00 0xFFFFFCFF 256B 256B Reads:0,writes:noeffect VIMParity PPS7 0xFFFFFD00 0xFFFFFDFF 256B 256B Reads:0,writes:noeffect VIM PPS7 0xFFFFFE00 0xFFFFFEFF 256B 256B Reads:0,writes:noeffect SystemModule- Frame1(seedevice PPS7 0xFFFFFF00 0xFFFFFFFF 256B 256B Reads:0,writes:noeffect TRM) 74 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.9.3 Master/Slave Access Privileges Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that caninitiateareadorawritetransactiononthedevice. Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed inthe"MASTERS"columncanaccessthatslavemodule. Table6-21.Master/SlaveAccessMatrix MASTERS ACCESSMODE SLAVESONMAINSCR FlashModule Non-CPU CRC EMIF,Ethernet Peripheral Bus2Interface: Accessesto SlaveInterfaces Control OTP,ECC, ProgramFlash Registers,All EEPROMBank andCPUData Peripheral RAM Memories,And AllSystem ModuleControl RegistersAnd Memories CPUREAD User/Privilege Yes Yes Yes Yes Yes CPUWRITE User/Privilege No Yes Yes Yes Yes DMA User Yes Yes Yes Yes Yes POM User Yes Yes Yes Yes Yes DMM User Yes Yes Yes Yes Yes DAP Privilege Yes Yes Yes Yes Yes HTU1 Privilege No Yes Yes Yes Yes HTU2 Privilege No Yes Yes Yes Yes FTU User No Yes Yes Yes Yes EMACDMA User No Yes No Yes No 6.9.3.1 SpecialNotesonAccessestoCertainSlaves Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (masterid=1).Theothermasterscanonlyreadfromtheseregisters. AdebuggercanalsowritetothePMMregisters.Themaster-idcheckisdisabledindebugmode. Thedevicecontainsdedicatedlogictogenerateabuserrorresponseonanyaccesstoamodulethatisin apowerdomainthathasbeenturnedOFF. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 75 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.9.4 POM Overlay Considerations • The POM overlay can map onto up to 8MB of the internal or external memory space. The starting address and the size of the memory overlay are configurable via the POM module control registers. Caremustbetakentoensurethattheoverlayismappedontoavailablememory. • ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors willbegenerated. • POM overlay must not be enabled when the flash and internal RAM memories are swapped via the MEMSWAPfieldoftheBusMatrixModuleControlRegister1(BMMCR1). • When POM is used to overlay the flash onto internal or external RAM, there is a bus contention possibilitywhenanothermasteraccessestheTCMflash.Thisresultsinasystemhang. – The POM module implements a time-out feature to detect this exact scenario. The time-out needs tobeenabledwheneverPOMoverlayisenabled. – The time-out can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Controlregister(POMGLBCTRL,address=0xFFA04000). – In case a read request by the POM cannot be completed within 32 HCLK cycles, the time-out (TO) flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a datafetch. – The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module is set. If so, then the application can assume that the time-out is caused by a bus contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been causedduetoatime-outfromthePOM. 76 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.10 Flash Memory 6.10.1 Flash Memory Configuration Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers,andcontrollogic. Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical constructionconstraints. Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasingtheflashbanks. FlashModule: InterfacecircuitryrequiredbetweenthehostCPUandtheflashbanksandpumpmodule. Table6-22.FlashMemoryBanksandSectors MEMORYARRAYS(ORBANKS)(1) SECTOR SEGMENT LOWADDRESS HIGHADDRESS NO. (BYTES) BANK0(1.5MB) 0 32KB 0x0000_0000 0x0000_7FFF 1 32KB 0x0000_8000 0x0000_FFFF 2 32KB 0x0001_0000 0x0001_7FFF 3 32KB 0x0001_8000 0x0001_FFFF 4 128KB 0x0002_0000 0x0003_FFFF 5 128KB 0x0004_0000 0x0005_FFFF 6 128KB 0x0006_0000 0x0007_FFFF 7 128KB 0x0008_0000 0x0009_FFFF 8 128KB 0x000A_0000 0x000B_FFFF 9 128KB 0x000C_0000 0x000D_FFFF 10 128KB 0x000E_0000 0x000F_FFFF 11 128KB 0x0010_0000 0x0011_FFFF 12 128KB 0x0012_0000 0x0013_FFFF 13 128KB 0x0014_0000 0x0015_FFFF 14 128KB 0x0016_0000 0x0017_FFFF BANK1(1.5MB) 0 128KB 0x0018_0000 0x0019_FFFF 1 128KB 0x001A_0000 0x001B_FFFF 2 128KB 0x001C_0000 0x001D_FFFF 3 128KB 0x001E_0000 0x001F_FFFF 4 128KB 0x0020_0000 0x0021_FFFF 5 128KB 0x0022_0000 0x0023_FFFF 6 128KB 0x0024_0000 0x0025_FFFF 7 128KB 0x0026_0000 0x0027_FFFF 8 128KB 0x0028_0000 0x0029_FFFF 9 128KB 0x002A_0000 0x002B_FFFF 10 128KB 0x002C_0000 0x002D_FFFF 11 128KB 0x002E_0000 0x002F_FFFF BANK7(64KB)forEEPROMemulation(2)(3) 0 16KB 0xF020_0000 0xF020_3FFF 1 16KB 0xF020_4000 0xF020_7FFF 2 16KB 0xF020_8000 0xF020_BFFF 3 16KB 0xF020_C000 0xF020_FFFF (1) TheFlashbanksare144-bit-widebankwithECCsupport. (2) Theflashbank7canbeprogrammedwhileexecutingcodefromflashbank0orbank1. (3) Codeexecutionisnotallowedfromflashbank7. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 77 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.10.2 Main Features of Flash Module • Supportformultipleflashbanksforprogramand/ordatastorage • Simultaneousreadaccessonabankwhileperformingprogramoreraseoperationonanyotherbank • Integratedstatemachinestoautomateflasheraseandprogramoperations • Softwareinterfaceforflashprogramanderaseoperations • Pipelinedmodeoperationtoimproveinstructionaccessinterfacebandwidth • SupportforSingleErrorCorrectionDoubleErrorDetection(SECDED)blockinsideCortex-R4FCPU – Erroraddressiscapturedforhostsystemdebugging • Supportforarichsetofdiagnosticfeatures 6.10.3 ECC Protection for Flash Accesses AllaccessestotheprogramflashmemoryareprotectedbySingleErrorCorrectionDoubleErrorDetection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the 'X'bitofthePerformanceMonitorControlRegister,c9. MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states ORR r1, r1, #0x00000010 MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register MRC p15,#0,r1,c9,c12,#0 The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bitsoftheSystemControlcoprocessor'sAuxiliaryControlRegister,c1. MRC p15, #0, r1, c1, c0, #1 ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs DMB MCR p15, #0, r1, c1, c0, #1 6.10.4 Flash Access Speeds Forinformationonflashmemoryaccessspeedsandtherelevantwaitstatesrequired,refertoSection5.6. 6.10.5 Flash Program and Erase Timings for Program Flash Table6-23.TimingSpecificationsforProgramFlash PARAMETER MIN NOM MAX UNIT t (144bit) WideWord(144bit)programming 40 300 µs prog time t (Total) 3-MBprogrammingtime(1) -40°Cto125°C 32 s prog 0°Cto60°C,forfirst 8 16 s 25cycles t Sector/Bankerasetime(2) -40°Cto125°C 0.03 4 s erase 0°Cto60°C,forfirst 16 100 ms 25cycles t Write/erasecycleswith15-year -40°Cto125°C 1000 cycles wec DataRetentionrequirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoesnotincludedatatransfertime.Theprogrammingtimeassumes programming144bitsatatimeatthemaximumspecifiedoperatingfrequency. (2) Duringbankerase,theselectedsectorsareerasedsimultaneously.Thetimetoerasethebankisspecifiedasequaltothetimetoerase asector. 78 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.10.6 Flash Program and Erase Timings for Data Flash Table6-24.TimingSpecificationsforDataFlash PARAMETER MIN NOM MAX UNIT WideWord(144bit)programming t (144bit) 40 300 µs prog time -40°Cto125°C 660 ms tprog(Total) 64-KBprogrammingtime(1) 0°Cto60°C,forfirst 165 330 ms 25cycles -40°Cto125°C 0.2 8 s terase Sector/Bankerasetime(2) 0°Cto60°C,forfirst 14 100 ms 25cycles Write/erasecycleswith15-year t -40°Cto125°C 100000 cycles wec DataRetentionrequirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoesnotincludedatatransfertime.Theprogrammingtimeassumes programming144bitsatatimeatthemaximumspecifiedoperatingfrequency. (2) Duringbankerase,theselectedsectorsareerasedsimultaneously.Thetimetoerasethebankisspecifiedasequaltothetimetoerase asector. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 79 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.11 Tightly Coupled RAM (TCRAM) Interface Module Figure6-10illustratestheconnectionoftheTightlyCoupledRAM(TCRAM)totheCortex-R4FCPU. 36 Bit 36 Bit Upper 32 bitsdata & 36 Bwitide Cortex-R4F 4 ECC bits wiwdeRidAeM RAM RAM TCM BUS TCRAM B0 Interface 1 36 Bit TCM 36 Bit 72 Bit data + ECC 3w6iwd BewRiditAiedMe Lower32 bitsdata & RARMAM 4 ECC bits 36 Bit 36 Bit Upper 32 bitsdata & 36 Bwitide B1 4 ECC bits wiwdeRidAeM TCM TCM BUS RARMAM TCRAM 72 Bit data + ECC Interface 2 363 6B iBtit 36 Bwitide wiwdeRidAeM Lower32 bitsdata & RARMAM 4 ECC bits Figure6-10.TCRAMBlockDiagram 6.11.1 Features ThefeaturesoftheTCRAMModuleare: • ActsasslavetotheCortex-R4FCPU'sBTCMinterface • SupportsCPU'sinternalECCschemebyproviding64-bitdataand8-bitECCcode • MonitorsCPUEventBusandgeneratessingleormultibiterrorinterrupts • Storesaddressesforsingleandmultibiterrors • SupportsRAMtracemodule • ProvidesCPUaddressbusintegritycheckingbysupportingparitycheckingontheaddressbus • PerformsredundantaddressdecodingfortheRAMbankchipselectandECCselectgenerationlogic • Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks andgeneratingindependentRAMaccesscontrolsignalstothetwobanks • Supportsauto-initializationoftheRAMbanksalongwiththeECCbits • Nosupportforbit-wiseRAMaccesses 6.11.2 TCRAM Interface ECC Support TheTCRAMinterfacepassesontheECCcodeforeachdatareadbytheCortex-R4FCPUfromtheRAM. It also stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The TCRAM interface monitors the CPU's event bus and provides registers for indicating singlebit or multibit errors and also for identifying the address that caused the single or multibit error. The event signaling and theECCcheckingfortheRAMaccessesmustbeenabledinsidetheCPU. Formoreinformationseethedevicespecifictechnicalreferencemanual. 6.12 Parity Protection for Peripheral RAMs Most peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAMaddressthatcausedtheparityerror. 80 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accessestoitsRAM. NOTE The CPU read access gets the actual data from the peripheral. The application can choose togenerateaninterruptwheneveraperipheralRAMparityerrorisdetected. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 81 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.13 On-Chip SRAM Initialization and Testing 6.13.1 On-Chip SRAM Self-Test Using PBIST 6.13.1.1 Features • Extensiveinstructionsettosupportvariousmemorytestalgorithms • ROM-basedalgorithmsallowapplicationtorunTIproduction-levelmemorytests • Independenttestingofallon-chipSRAM 6.13.1.2 PBISTRAMGroups Table6-25.PBISTRAMGrouping TESTPATTERN(ALGORITHM) MARCH13N(1) MARCH13N(1) TRIPLEREAD TRIPLEREAD TWOPORT SINGLEPORT MEMORY RAMGROUP TESTCLOCK MEMTYPE SLOWREAD FASTREAD (CYCLES) (CYCLES) ALGOMASK ALGOMASK ALGOMASK ALGOMASK 0x1 0x2 0x4 0x8 PBIST_ROM 1 ROMCLK ROM 24578 8194 STC_ROM 2 ROMCLK ROM 19586 6530 DCAN1 3 VCLK DualPort 25200 DCAN2 4 VCLK DualPort 25200 DCAN3 5 VCLK DualPort 25200 ESRAM1(2) 6 HCLK SinglePort 266280 MIBSPI1 7 VCLK DualPort 33440 MIBSPI3 8 VCLK DualPort 33440 MIBSPI5 9 VCLK DualPort 33440 VIM 10 VCLK DualPort 12560 MIBADC1 11 VCLK DualPort 4200 DMA 12 HCLK DualPort 18960 N2HET1 13 VCLK DualPort 31680 HTU1 14 VCLK DualPort 6480 RTP 15 HCLK DualPort 37800 16 VCLK DualPort 75400 FLEXRAY 17 SinglePort 133160 MIBADC2 18 VCLK DualPort 4200 N2HET2 19 VCLK DualPort 31680 HTU2 20 VCLK DualPort 6480 ESRAM5(3) 21 HCLK SinglePort 266280 ESRAM6(4) 22 HCLK SinglePort 266280 23 8700 DualPort ETHERNET 24 VCLK3 6360 25 SinglePort 133160 ESRAM8(5) 28 HCLK SinglePort 266280 (1) ThereareseveralmemorytestingalgorithmsstoredinthePBISTROM.However,TIrecommendstheMarch13Nalgorithmfor applicationtesting. (2) ESRAM1:Address0x08000000-0x0800FFFF(Alwaysonpowerdomain) (3) ESRAM5:Address0x08010000-0x0801FFFF(RAMpowerdomain1) (4) ESRAM6:Address0x08020000-0x0802FFFF(RAMpowerdomain2) (5) ESRAM8:Address0x08030000-0x0803FFFF(RAMpowerdomain3) 82 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 The PBIST ROM clock frequency is limited to 90 MHz, if 90 MHz < HCLK <= HCLKmax, or HCLK, if HCLK<=90MHz. ThePBISTROMclockisdivideddownfromHCLK.ThedividerisselectedbyprogrammingtheROM_DIV fieldoftheMemorySelf-TestGlobalControlRegister(MSTGCR)ataddress0xFFFFFF58. 6.13.2 On-Chip SRAM Auto Initialization This microcontroller allows some of the on-chip memories to be initialized to zero via the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detectionscheme(odd/evenparityorECC). The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects thememoriesthataretobeinitialized. Formoreinformationontheseregistersseethedevicespecifictechnicalreferencemanual. The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table6-26. Table6-26.MemoryInitialization ADDRESSRANGE CONNECTINGMODULE MSINENAREGISTERBIT# BASEADDRESS ENDINGADDRESS RAM(PD#1) 0x08000000 0x0800FFFF 0(1) RAM(RAM_PD#1) 0x08010000 0x0801FFFF 0(1) RAM(RAM_PD#2) 0x08020000 0x0802FFFF 0(1) RAM(RAM_PD#3) 0x08030000 0x0803FFFF 0(1) MIBSPI5RAM 0xFF0A0000 0xFF0BFFFF 12(2) MIBSPI3RAM 0xFF0C0000 0xFF0DFFFF 11(2) MIBSPI1RAM 0xFF0E0000 0xFF0FFFFF 7(2) DCAN3RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1RAM 0xFF1E0000 0xFF1FFFFF 5 FlexRayRAM RAMisnotCPU-Addressable n/a(3) MIBADC2RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1RAM 0xFF3E0000 0xFF3FFFFF 8 N2HET2RAM 0xFF440000 0xFF45FFFF 15 N2HET1RAM 0xFF460000 0xFF47FFFF 3 HTU2RAM 0xFF4C0000 0xFF4DFFFF 16 HTU1RAM 0xFF4E0000 0xFF4FFFFF 4 DMARAM 0xFFF80000 0xFFF80FFF 1 VIMRAM 0xFFF82000 0xFFF82FFF 2 RTPRAM 0xFFF83000 0xFFF83FFF n/a FTURAM 0xFF500000 0xFF51FFFF 13 EthernetRAM(CPPIMemory 0xFC520000 0xFC521FFF n/a Slave) (1) TheTCMRAMwrapperhasseparatecontrolbitstoselecttheRAMpowerdomainthatistobeauto-initialized. (2) TheMibSPIxmodulesperformaninitializationofthetransmitandreceiveRAMsassoonasthemoduleisreleasedfromitslocalreset viatheSPIGCR0register.ThisisindependentofwhethertheapplicationchoosestoinitializetheMibSPIxRAMsusingthesystem moduleauto-initializationmethod.BeforetheMibSPIRAMcanbeinitializedusingthesystemmoduleauto-initializationmethod:(I)The modulemustbereleasedfromitslocalreset,AND(ii)Theapplicationmustpollforthe"BUFINITACTIVE"statusflagintheSPIFLG registertobecomecleared(zero) (3) Reservedonly.TheFlexRayRAMhasitsowninitializationmechanism. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 83 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.14 External Memory Interface (EMIF) 6.14.1 Features The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronousmemoriesorSDRAMdevices.TheEMIFfeaturesincludessupportfor: • 3addressablechipselectforasynchronousmemoriesofupto16MBeach • 1addressablechipselectspaceforSDRAMsupto128MB • 8-or16-bitdatabuswidth • Programmablecycletimingssuchassetup,strobe,andholdtimesaswellasturnaroundtime • Selectstrobemode • ExtendedWaitmode • Databusparking 6.14.2 Electrical and Timing Specifications 6.14.2.1 AsynchronousRAM 3 1 EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nDQM[1:0] 4 5 8 9 6 7 29 30 10 EMIF_nOE 13 12 EMIF_DATA[15:0] EMIF_nWE Figure6-11.AsynchronousMemoryReadTiming 84 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 SETUP STROBE ExtendedDuetoEMIF_WAIT STROBE HOLD EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DATA[15:0] 14 11 EMIF_nOE 2 2 EMIF_WAIT Asserted Deasserted Figure6-12.EMIFnWAITReadTimingRequirements 15 1 EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_nDQM[1:0] 16 17 18 19 20 21 24 22 23 EMIF_nWE 27 26 EMIF_DATA[15:0] EMIF_nOE Figure6-13.AsynchronousMemoryWriteTiming Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 85 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com SETUP STROBE ExtendedDuetoEMIF_WAIT STROBE HOLD EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[21:0] EMIF_DATA[15:0] 28 25 EMIF_nWE 2 2 EMIF_WAIT Asserted Deasserted Figure6-14.EMIFnWAITWriteTimingRequirements Table6-27.EMIFAsynchronousMemoryTimingRequirements NO. MIN NOM MAX UNIT ReadsandWrites E EMIFclockperiod 11 ns 2 t Pulseduration,EMIFnWAIT 2E ns w(EM_WAIT) assertionanddeassertion Reads 12 t Setuptime,EMIFDATA[15:0] 30 ns su(EMDV-EMOEH) validbeforeEMIFnOEhigh 13 t Holdtime,EMIFDATA[15:0]valid 0.5 ns h(EMOEH-EMDIV) afterEMIFnOEhigh 14 t SetupTime,EMIFnWAIT 4E+30 ns su(EMOEL-EMWAIT) assertedbeforeendofStrobe Phase(1) Writes 28 t SetupTime,EMIFnWAIT 4E+30 ns su(EMWEL-EMWAIT) assertedbeforeendofStrobe Phase(1) (1) SetupbeforeendofSTROBEphase(ifnoextendedwaitstatesareinserted)bywhichEMIFnWAITmustbeassertedtoaddextended waitstates.FigureFigure6-12andFigureFigure6-14describeEMIFtransactionsthatincludeextendedwaitstatesinsertedduringthe STROBEphase.However,cyclesinsertedaspartofthisextendedwaitperiodshouldnotbecounted;the4Erequirementistothestart ofwheretheHOLDphasewouldbeginiftherewerenoextendedwaitcycles. Table6-28.EMIFAsynchronousMemorySwitchingCharacteristics(1)(2)(3) NO. PARAMETER MIN NOM MAX UNIT ReadsandWrites 1 t Turnaroundtime (TA)*E-4 (TA)*E (TA)*E+3 ns d(TURNAROUND) Reads (1) TA=Turnaround,RS=Readsetup,RST=Readstrobe,RH=Readhold,WS=Writesetup,WST=Writestrobe,WH=Writehold, MEWC=Maximumexternalwaitcycles.TheseparametersareprogrammedviatheAsynchronousBankandAsynchronousWaitCycle ConfigurationRegisters.Thesesupportthefollowingrangesofvalues:TA[4–1],RS[16–1],RST[64–1],RH[8–1],WS[16–1],WST[64–1], WH[8–1],andMEWC[1–256].SeetheTMS570LS31X/21XTechnicalReferenceManual(SPNU499)formoreinformation. (2) E=EMIF_CLKperiodinns. (3) EWC=externalwaitcyclesdeterminedbyEMIFnWAITinputsignal.EWCsupportsthefollowingrangeofvalues.EWC[256–1].Note thatthemaximumwaittimebeforetime-outisspecifiedbybitfieldMEWCintheAsynchronousWaitCycleConfigurationRegister.See theTMS570LS31X/21XTechnicalReferenceManual(SPNU499)formoreinformation. 86 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-28.EMIFAsynchronousMemorySwitchingCharacteristics(1)(2)(3)(continued) NO. PARAMETER MIN NOM MAX UNIT 3 t EMIFreadcycletime(EW=0) (RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)* ns c(EMRCYCLE) E-3 E E+3 EMIFreadcycletime(EW=1) (RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+( ns EWC*16))*E-3 EWC*16))*E EWC*16))*E+3 4 t Outputsetuptime,EMIFnCS[4:2] ns su(EMCEL-EMOEL) (RS)*E-4 (RS)*E (RS)*E+3 lowtoEMIFnOElow(SS=0) Outputsetuptime,EMIFnCS[4:2] ns -3 0 +3 lowtoEMIFnOElow(SS=1) 5 t Outputholdtime,EMIFnOEhigh ns h(EMOEH-EMCEH) (RH)*E-4 (RH)*E (RH)*E+3 toEMIFnCS[4:2]high(SS=0) Outputholdtime,EMIFnOEhigh ns -3 0 +3 toEMIFnCS[4:2]high(SS=1) 6 t Outputsetuptime,EMIFBA[1:0] ns su(EMBAV-EMOEL) (RS)*E-4 (RS)*E (RS)*E+3 validtoEMIFnOElow 7 t Outputholdtime,EMIFnOEhigh ns h(EMOEH-EMBAIV) (RH)*E-4 (RH)*E (RH)*E+3 toEMIFBA[1:0]invalid 8 t Outputsetuptime, ns su(EMAV-EMOEL) EMIFADDR[21:0]validto (RS)*E-4 (RS)*E (RS)*E+3 EMIFnOElow 9 t Outputholdtime,EMIFnOEhigh ns h(EMOEH-EMAIV) (RH)*E-4 (RH)*E (RH)*E+3 toEMIFADDR[21:0]invalid 10 t EMIFnOEactivelowwidth(EW ns w(EMOEL) (RST)*E-3 (RST)*E (RST)*E+3 =0) EMIFnOEactivelowwidth(EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16 ns =1) ))*E-3 ))*E ))*E+3 11 t DelaytimefromEMIFnWAIT ns d(EMWAITH-EMOEH) 3E-3 4E 4E+30 deassertedtoEMIFnOEhigh 29 t Outputsetuptime, ns su(EMDQMV-EMOEL) EMIFnDQM[1:0]validto (RS)*E-4 (RS)*E (RS)*E+3 EMIFnOElow 30 t Outputholdtime,EMIFnOEhigh ns h(EMOEH-EMDQMIV) (RH)*E-4 (RH)*E (RH)*E+3 toEMIFnDQM[1:0]invalid Writes 15 t EMIFwritecycletime(EW=0) (WS+WST+WH) (WS+WST+WH) (WS+WST+WH) ns c(EMWCYCLE) *E-3 *E *E+3 EMIFwritecycletime(EW=1) (WS+WST+WH (WS+WST+WH ns (WS+WST+WH +(EWC*16))*E +(EWC*16))*E +(EWC*16))*E -3 +3 16 t Outputsetuptime,EMIFnCS[4:2] ns su(EMCEL-EMWEL) (WS)*E-4 (WS)*E (WS)*E+3 lowtoEMIFnWElow(SS=0) Outputsetuptime,EMIFnCS[4:2] ns -4 0 +3 lowtoEMIFnWElow(SS=1) 17 t Outputholdtime,EMIFnWEhigh ns h(EMWEH-EMCEH) (WH)*E-4 (WH)*E (WH)*E+3 toEMIFnCS[4:2]high(SS=0) Outputholdtime,EMIFnWEhigh ns -4 0 +3 toEMIFCS[4:2]high(SS=1) 18 t Outputsetuptime,EMIFBA[1:0] ns su(EMDQMV-EMWEL) (WS)*E-4 (WS)*E (WS)*E+3 validtoEMIFnWElow 19 t Outputholdtime,EMIFnWEhigh ns h(EMWEH-EMDQMIV) (WH)*E-4 (WH)*E (WH)*E+3 toEMIFBA[1:0]invalid 20 t Outputsetuptime,EMIFBA[1:0] ns su(EMBAV-EMWEL) (WS)*E-4 (WS)*E (WS)*E+3 validtoEMIFnWElow 21 t Outputholdtime,EMIFnWEhigh ns h(EMWEH-EMBAIV) (WH)*E-4 (WH)*E (WH)*E+3 toEMIFBA[1:0]invalid 22 t Outputsetuptime, ns su(EMAV-EMWEL) EMIFADDR[21:0]validto (WS)*E-4 (WS)*E (WS)*E+3 EMIFnWElow Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 87 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-28.EMIFAsynchronousMemorySwitchingCharacteristics(1)(2)(3)(continued) NO. PARAMETER MIN NOM MAX UNIT 23 t Outputholdtime,EMIFnWEhigh ns h(EMWEH-EMAIV) (WH)*E-4 (WH)*E (WH)*E+3 toEMIFADDR[21:0]invalid 24 t EMIFnWEactivelowwidth(EW ns w(EMWEL) (WST)*E-3 (WST)*E (WST)*E+3 =0) EMIFnWEactivelowwidth(EW (WST+(EWC*16 (WST+(EWC*16 (WST+(EWC*16 ns =1) ))*E-3 ))*E ))*E+3 25 t DelaytimefromEMIFnWAIT ns d(EMWAITH-EMWEH) 3E-4 4E 4E+30 deassertedtoEMIFnWEhigh 26 t Outputsetuptime, ns su(EMDV-EMWEL) EMIFDATA[15:0]validto (WS)*E-4 (WS)*E (WS)*E+3 EMIFnWElow 27 t Outputholdtime,EMIFnWEhigh ns h(EMWEH-EMDIV) (WH)*E-4 (WH)*E (WH)*E+3 toEMIFDATA[15:0]invalid 31 t Outputsetuptime, ns su(EMDQMV-EMWEL) EMIFnDQM[1:0]validto (WH)*E-4 (WH)*E (WH)*E+3 EMIFnWElow 32 t Outputholdtime,EMIFnWEhigh ns h(EMWEH-EMDQMIV) (WH)*E-4 (WH)*E (WH)*E+3 toEMIFnDQM[1:0]invalid 6.14.2.2 SynchronousTiming BASICSDRAM 1 READOPERATION 2 2 EMIF_CLK 3 4 EMIF_nCS[0] 5 6 EMIF_nDQM[1:0] 7 8 EMIF_BA[1:0] 7 8 EMIF_ADDR[21:0] 19 2EM_CLKDelay 17 20 18 EMIF_DATA[15:0] 11 12 EMIF_nRAS 13 14 EMIF_nCAS EMIF_nWE Figure6-15.BasicSDRAMReadOperation 88 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 BASICSDRAM 1 WRITEOPERATION 2 2 EMIF_CLK 3 4 EMIF_CS[0] 5 6 EMIF_DQM[1:0] 7 8 EMIF_BA[1:0] 7 8 EMIF_ADDR[21:0] 9 10 EMIF_DATA[15:0] 11 12 EMIF_nRAS 13 EMIF_nCAS 15 16 EMIF_nWE Figure6-16.BasicSDRAMWriteOperation Table6-29.EMIFSynchronousMemoryTimingRequirements NO. MIN MAX UNIT Inputsetuptime,readdatavalidon 19 t 2 ns su(EMIFDV-EM_CLKH) EMIFDATA[15:0]beforeEMIF_CLKrising Inputholdtime,readdatavalidon 20 t 1.5 ns h(CLKH-DIV) EMIFDATA[15:0]afterEMIF_CLKrising Table6-30.EMIFSynchronousMemorySwitchingCharacteristics NO. PARAMETER MIN MAX UNIT 1 t Cycletime,EMIFclockEMIF_CLK 20 ns c(CLK) 2 t Pulsewidth,EMIFclockEMIF_CLKhighorlow 5 ns w(CLK) 3 t Delaytime,EMIF_CLKrisingtoEMIFnCS[0]valid 13 ns d(CLKH-CSV) Outputholdtime,EMIF_CLKrisingtoEMIFnCS[0] 4 t 1 ns oh(CLKH-CSIV) invalid Delaytime,EMIF_CLKrisingtoEMIFnDQM[1:0] 5 t 13 ns d(CLKH-DQMV) valid Outputholdtime,EMIF_CLKrisingto 6 t 1 ns oh(CLKH-DQMIV) EMIFnDQM[1:0]invalid Delaytime,EMIF_CLKrisingtoEMIFADDR[21:0] 7 t 13 ns d(CLKH-AV) andEMIFBA[1:0]valid Outputholdtime,EMIF_CLKrisingto 8 t 1 ns oh(CLKH-AIV) EMIFADDR[21:0]andEMIFBA[1:0]invalid Delaytime,EMIF_CLKrisingtoEMIFDATA[15:0] 9 t 13 ns d(CLKH-DV) valid Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 89 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-30.EMIFSynchronousMemorySwitchingCharacteristics(continued) NO. PARAMETER MIN MAX UNIT Outputholdtime,EMIF_CLKrisingto 10 t 1 ns oh(CLKH-DIV) EMIFDATA[15:0]invalid 11 t Delaytime,EMIF_CLKrisingtoEMIFnRASvalid 13 ns d(CLKH-RASV) Outputholdtime,EMIF_CLKrisingtoEMIFnRAS 12 t 1 ns oh(CLKH-RASIV) invalid 13 t Delaytime,EMIF_CLKrisingtoEMIFnCASvalid 13 ns d(CLKH-CASV) Outputholdtime,EMIF_CLKrisingtoEMIFnCAS 14 t 1 ns oh(CLKH-CASIV) invalid 15 t Delaytime,EMIF_CLKrisingtoEMIFnWEvalid 13 ns d(CLKH-WEV) Outputholdtime,EMIF_CLKrisingtoEMIFnWE 16 t 1 ns oh(CLKH-WEIV) invalid Delaytime,EMIF_CLKrisingtoEMIFDATA[15:0] 17 t 7 ns dis(CLKH-DHZ) tri-stated Outputholdtime,EMIF_CLKrisingto 18 t 1 ns ena(CLKH-DLZ) EMIFDATA[15:0]driving 90 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.15 Vectored Interrupt Manager The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to aninterruptserviceroutine(ISR). 6.15.1 VIM Features TheVIMmodulehasthefollowingfeatures: • Supports96interruptchannels. – Providesprogrammablepriorityandenableforinterruptrequestlines. • ProvidesadirecthardwaredispatchmechanismforfastestIRQdispatch. • ProvidestwosoftwaredispatchmechanismswhentheCPUVICportisnotused. – Indexinterrupt – Registervectoredinterrupt • Parityprotectedvectorinterrupttable 6.15.2 Interrupt Request Assignments Table6-31.InterruptRequestAssignments DEFAULTVIM MODULES INTERRUPTSOURCES INTERRUPTCHANNEL ESM ESMHighlevelinterrupt(NMI) 0 Reserved Reserved 1 RTI RTIcompareinterrupt0 2 RTI RTIcompareinterrupt1 3 RTI RTIcompareinterrupt2 4 RTI RTIcompareinterrupt3 5 RTI RTIoverflowinterrupt0 6 RTI RTIoverflowinterrupt1 7 RTI RTItimebaseinterrupt 8 GPIO GPIOinterruptA 9 N2HET1 N2HET1level0interrupt 10 HTU1 HTU1level0interrupt 11 MIBSPI1 MIBSPI1level0interrupt 12 LIN LINlevel0interrupt 13 MIBADC1 MIBADC1eventgroupinterrupt 14 MIBADC1 MIBADC1swgroup1interrupt 15 DCAN1 DCAN1level0interrupt 16 SPI2 SPI2level0interrupt 17 FlexRay FlexRaylevel0interrupt 18 CRC CRCInterrupt 19 ESM ESMLowlevelinterrupt 20 SYSTEM Softwareinterrupt(SSI) 21 CPU PMUInterrupt 22 GPIO GPIOinterruptB 23 N2HET1 N2HET1level1interrupt 24 HTU1 HTU1level1interrupt 25 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 91 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-31.InterruptRequestAssignments(continued) DEFAULTVIM MODULES INTERRUPTSOURCES INTERRUPTCHANNEL MIBSPI1 MIBSPI1level1interrupt 26 LIN LINlevel1interrupt 27 MIBADC1 MIBADC1swgroup2interrupt 28 DCAN1 DCAN1level1interrupt 29 SPI2 SPI2level1interrupt 30 MIBADC1 MIBADC1magnitudecompareinterrupt 31 FlexRay FlexRaylevel1interrupt 32 DMA FTCAinterrupt 33 DMA LFSAinterrupt 34 DCAN2 DCAN2level0interrupt 35 DMM DMMlevel0interrupt 36 MIBSPI3 MIBSPI3level0interrupt 37 MIBSPI3 MIBSPI3level1interrupt 38 DMA HBCAinterrupt 39 DMA BTCAinterrupt 40 EMIF AEMIFINT3 41 DCAN2 DCAN2level1interrupt 42 DMM DMMlevel1interrupt 43 DCAN1 DCAN1IF3interrupt 44 DCAN3 DCAN3level0interrupt 45 DCAN2 DCAN2IF3interrupt 46 FPU "OR"ofthesixCortexR4FFPUExceptions 47 FTU FTUTransferStatusinterrupt 48 SPI4 SPI4level0interrupt 49 MIBADC2 MibADC2eventgroupinterrupt 50 MIBADC2 MibADC2swgroup1interrupt 51 FlexRay FlexRayT0Cinterrupt 52 MIBSPI5 MIBSPI5level0interrupt 53 SPI4 SPI4level1interrupt 54 DCAN3 DCAN3level1interrupt 55 MIBSPI5 MIBSPI5level1interrupt 56 MIBADC2 MibADC2swgroup2interrupt 57 FTU FTUErrorinterrupt 58 MIBADC2 MibADC2magnitudecompareinterrupt 59 DCAN3 DCAN3IF3interrupt 60 FMC FSM_DONEinterrupt 61 FlexRay FlexRayT1Cinterrupt 62 N2HET2 N2HET2level0interrupt 63 SCI SCIlevel0interrupt 64 HTU2 HTU2level0interrupt 65 I2C I2Clevel0interrupt 66 Reserved Reserved 67-72 N2HET2 N2HET2level1interrupt 73 SCI SCIlevel1interrupt 74 HTU2 HTU2level1interrupt 75 Ethernet C0_MISC_PULSE 76 Ethernet C0_TX_PULSE 77 92 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-31.InterruptRequestAssignments(continued) DEFAULTVIM MODULES INTERRUPTSOURCES INTERRUPTCHANNEL Ethernet C0_THRESH_PULSE 78 Ethernet C0_RX_PULSE 79 HWAG1 HWA_INT_REQ_H 80 HWAG2 HWA_INT_REQ_H 81 DCC1 DCC1doneinterrupt 82 DCC2 DCC2doneinterrupt 83 Reserved Reserved 84 PBIST PBIST_DONE 85 Reserved Reserved 86 Reserved Reserved 87 HWAG1 HWA_INT_REQ_L 88 HWAG2 HWA_INT_REQ_L 89 Reserved Reserved 90-95 NOTE Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..94 can be used and are offset by 1 address in the VIMRAM. NOTE The EMIF_nWAIT signal has a pullup on it. The EMIF module generates a "Wait Rise" interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt condition is indicated as soon as the device is powered up. This can be ignored if the EMIF_nWAITsignalisnotusedintheapplication.IftheEMIF_nWAITsignalisactuallyused intheapplication,thentheexternalslavememorymustalwaysdrivetheEMIF_nWAITsignal suchthataninterruptisnotcausedduetothedefaultpulluponthissignal. NOTE Thelower-orderinterruptchannelsarehigherprioritychannelsthanthehigher-orderinterrupt channels. NOTE Theapplicationcanchangethemappingofinterruptsourcestotheinterruptchannelsviathe interruptchannelcontrolregisters(CHANCTRLx)insidetheVIMmodule. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 93 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.16 DMA Controller The DMA controller is used to transfer data between two locations in the memory map in the background ofCPUoperations.Typically,theDMAisusedto: • Transferblocksofdatabetweenexternalandinternaldatamemories • Restructureportionsofinternaldatamemory • Continuallyserviceaperipheral 6.16.1 DMA Features • CPUindependentdatatransfer • Onemasterport-PortB(64bitswide)thatinterfacestothe TMS570MemorySystem. • FIFObuffer(4entriesdeepandeach64bitswide) • ChannelcontrolinformationisstoredinRAMprotectedbyparity • 16channelswithindividualenable • Channelchainingcapability • 32peripheralDMArequests • HardwareandSoftwareDMArequests • 8-,16-,32-,or64-bittransactionssupported • Multipleaddressingmodesforsource/destination(fixed,increment,offset) • Auto-initiation • Power-managementmode • MemoryProtectionwithfourconfigurablememoryregions 94 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.16.2 Default DMA Request Map The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default,channel0ismappedtorequest0,channel1torequest1,andsoon. Some DMA requests have multiple sources, as shown in Table 6-32. The application must ensure that onlyoneoftheseDMArequestsourcesisenabledatanytime. Table6-32.DMARequestLineConnection Modules DMARequestSources DMARequest MIBSPI1 MIBSPI1[1](1) DMAREQ[0] MIBSPI1 MIBSPI1[0](2) DMAREQ[1] SPI2 SPI2receive DMAREQ[2] SPI2 SPI2transmit DMAREQ[3] MIBSPI1/MIBSPI3/DCAN2 MIBSPI1[2]/MIBSPI3[2]/DCAN2IF3 DMAREQ[4] MIBSPI1/MIBSPI3/DCAN2 MIBSPI1[3]/MIBSPI3[3]/DCAN2IF2 DMAREQ[5] DCAN1/MIBSPI5 DCAN1IF2/MIBSPI5[2] DMAREQ[6] MIBADC1/MIBSPI5 MIBADC1event/MIBSPI5[3] DMAREQ[7] MIBSPI1/MIBSPI3/DCAN1 MIBSPI1[4]/MIBSPI3[4]/DCAN1IF1 DMAREQ[8] MIBSPI1/MIBSPI3/DCAN2 MIBSPI1[5]/MIBSPI3[5]/DCAN2IF1 DMAREQ[9] MIBADC1/I2C/MIBSPI5 MIBADC1G1/I2Creceive/MIBSPI5[4] DMAREQ[10] MIBADC1/I2C/MIBSPI5 MIBADC1G2/I2Ctransmit/MIBSPI5[5] DMAREQ[11] RTI/MIBSPI1/MIBSPI3 RTIDMAREQ0/MIBSPI1[6]/MIBSPI3[6] DMAREQ[12] RTI/MIBSPI1/MIBSPI3 RTIDMAREQ1/MIBSPI1[7]/MIBSPI3[7] DMAREQ[13] MIBSPI3/MibADC2/MIBSPI5 MIBSPI3[1](1)/MibADC2event/MIBSPI5[6] DMAREQ[14] MIBSPI3/MIBSPI5 MIBSPI3[0](2)/MIBSPI5[7] DMAREQ[15] MIBSPI1/MIBSPI3/DCAN1/MibADC2 MIBSPI1[8]/MIBSPI3[8]/DCAN1IF3/MibADC2G1 DMAREQ[16] MIBSPI1/MIBSPI3/DCAN3/MibADC2 MIBSPI1[9]/MIBSPI3[9]/DCAN3IF1/MibADC2G2 DMAREQ[17] RTI/MIBSPI5 RTIDMAREQ2/MIBSPI5[8] DMAREQ[18] RTI/MIBSPI5 RTIDMAREQ3/MIBSPI5[9] DMAREQ[19] N2HET1/N2HET2/DCAN3 N2HET1DMAREQ[4]/N2HET2DMAREQ[4]/DCAN3 DMAREQ[20] IF2 N2HET1/N2HET2/DCAN3 N2HET1DMAREQ[5]/N2HET2DMAREQ[5]/DCAN3 DMAREQ[21] IF3 MIBSPI1/MIBSPI3/MIBSPI5 MIBSPI1[10]/MIBSPI3[10]/MIBSPI5[10] DMAREQ[22] MIBSPI1/MIBSPI3/MIBSPI5 MIBSPI1[11]/MIBSPI3[11]/MIBSPI5[11] DMAREQ[23] N2HET1/N2HET2/SPI4/MIBSPI5 N2HET1DMAREQ[6]/N2HET2DMAREQ[6]/SPI4 DMAREQ[24] receive/MIBSPI5[12] N2HET1/N2HET2/SPI4/MIBSPI5 N2HET1DMAREQ[7]/N2HET2DMAREQ[7]/SPI4 DMAREQ[25] transmit/MIBSPI5[13] CRC/MIBSPI1/MIBSPI3 CRCDMAREQ[0]/MIBSPI1[12]/MIBSPI3[12] DMAREQ[26] CRC/MIBSPI1/MIBSPI3 CRCDMAREQ[1]/MIBSPI1[13]/MIBSPI3[13] DMAREQ[27] LIN/MIBSPI5 LINreceive/MIBSPI5[14] DMAREQ[28] LIN/MIBSPI5 LINtransmit/MIBSPI5[15] DMAREQ[29] MIBSPI1/MIBSPI3/SCI/MIBSPI5 MIBSPI1[14]/MIBSPI3[14]/SCIreceive/ DMAREQ[30] MIBSPI5[1](1) MIBSPI1/MIBSPI3/SCI/MIBSPI5 MIBSPI1[15]/MIBSPI3[15]/SCItransmit/ DMAREQ[31] MIBSPI5[0](2) (1) SPI1,SPI3,SPI5receiveinstandardSPImode (2) SPI1,SPI3,SPI5transmitinstandardSPImode Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 95 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.17 Real Time Interrupt Module The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the timebases needed forschedulinganoperatingsystem. The timers also allow you to benchmark certain areas of code by reading the values of the counters at the beginningandtheendofthedesiredcoderangeandcalculatingthedifferencebetweenthevalues. In addition the RTI provides a mechanism to synchronize the operating system to the FlexRay communication cycle. Clock supervision can detect issues on the FlexRay bus with an automatic switch to aninternallygeneratedtimebase. 6.17.1 Features TheRTImodulehasthefollowingfeatures: • Twoindependent64bitcounterblocks • Four configurable compares for generating operating system ticks or DMA requests. Each event can bedrivenbyeithercounterblock0orcounterblock1. • One counter block usable for application synchronization to FlexRay network including clock supervision • Fastenabling/disablingofevents • Twotime-stamp(capture)functionsforsystemorperipheralinterrupts,oneforeachcounterblock 6.17.2 Block Diagrams Figure 6-17 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only availableastimebaseinputsforthecounterblock0. 31 0 Compare up counter RTICPUCx OVLINTx 31 0 Up counter 31 0 RTICLK = RTIUCx Free running counter To Compare NTU0 RTIFRCx Unit NTU1 NTU2 NTU3 31 0 31 0 Capture Capture up counter free running counter RTICAUCx RTICAFRCx CAPevent source 0 External CAPevent source 1 control Figure6-17.CounterBlockDiagram 96 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 31 0 Update compare RTIUDCPy + 31 0 Compare DMAREQy RTICOMPy From counter block 0 = From counter INTy block 1 Compare control Figure6-18.CompareBlockDiagram 6.17.3 Clock Source Options TheRTImoduleusestheRTI1CLKclockdomainforgeneratingtheRTItimebases. The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the Systemmoduleataddress0xFFFFFF50.ThedefaultsourceforRTI1CLKisVCLK. FormoreinformationonclocksourcesrefertoTable6-8andTable6-13. 6.17.4 Network Time Synchronization Inputs The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connectedasshowninTable6-33. Table6-33.NetworkTimeSynchronizationInputs NTUInput Source 0 Macrotick 1 StartofCycle 2 PLL2Clockoutput 3 EXTCLKIN1clockinput Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 97 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.18 Error Signaling Module The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used asanindicatortoanexternalmonitorcircuittoputthesystemintoasafestate. 6.18.1 Features ThefeaturesoftheErrorSignalingModuleare: • 128interrupt/errorchannelsaresupported,dividedinto3differentgroups – 64channelswithmaskableinterruptandconfigurableerrorpinbehavior – 32errorchannelswithnonmaskableinterruptandpredefinederrorpinbehavior – 32channelswithpredefinederrorpinbehavioronly • Errorpintosignalseveredevicefailure • Configurabletimebaseforerrorsignal • Errorforcingcapability 6.18.2 ESM Channel Assignments The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table6-35showsthechannelassignmentforeachgroup. Table6-34.ESMGroups ERRORGROUP INTERRUPTCHARACTERISTICS INFLUENCEONERRORPIN Group1 maskable,loworhighpriority configurable Group2 nonmaskable,highpriority fixed Group3 nointerruptgenerated fixed Table6-35.ESMChannelAssignments ERRORSOURCES GROUP CHANNELS Reserved Group1 0 MibADC2-parity Group1 1 DMA-MPU Group1 2 DMA-parity Group1 3 Reserved Group1 4 DMA/DMM-imprecisereaderror Group1 5 FMC-correctableerror:bus1andbus2interfaces Group1 6 (doesnotincludeaccessestoEEPROMbank) N2HET1/N2HET2-parity Group1 7 HTU1/HTU2-parity Group1 8 HTU1/HTU2-MPU Group1 9 PLL-Slip Group1 10 ClockMonitor-interrupt Group1 11 FlexRay-parity Group1 12 DMA/DMM-imprecisewriteerror Group1 13 FTU-parity Group1 14 VIMRAM-parity Group1 15 FTU-MPU Group1 16 MibSPI1-parity Group1 17 MibSPI3-parity Group1 18 98 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-35.ESMChannelAssignments(continued) ERRORSOURCES GROUP CHANNELS MibADC1-parity Group1 19 Reserved Group1 20 DCAN1-parity Group1 21 DCAN3-parity Group1 22 DCAN2-parity Group1 23 MibSPI5-parity Group1 24 Reserved Group1 25 RAMevenbank(B0TCM)-correctableerror Group1 26 CPU-selftest Group1 27 RAModdbank(B1TCM)-correctableerror Group1 28 Reserved Group1 29 DCC1-error Group1 30 CCM-R4-selftest Group1 31 Reserved Group1 32 Reserved Group1 33 Reserved Group1 34 FMC-correctableerror(EEPROMbankaccess) Group1 35 FMC-uncorrectableerror(EEPROMbankaccess) Group1 36 IOMM-Muxconfigurationerror Group1 37 Powerdomaincontrollercompareerror Group1 38 Powerdomaincontrollerself-testerror Group1 39 eFuseControllerError–thiserrorsignalisgeneratedwhenanybitintheeFuse controllererrorstatusregisterisset.Theapplicationcanchoosetogeneratean Group1 40 interruptwheneverthisbitissettoserviceanyeFusecontrollererrorconditions. eFuseController-SelfTestError.Thiserrorsignalisgeneratedonlywhenaself testontheeFusecontrollergeneratesanerrorcondition.WhenanECCselftest Group1 41 errorisdetected,group1channel40errorsignalwillalsobeset. PLL2-Slip Group1 42 EthernetControllermasterinterface Group1 43 Reserved Group1 44 Reserved Group1 45 Reserved Group1 46 Reserved Group1 47 Reserved Group1 48 Reserved Group1 49 Reserved Group1 50 Reserved Group1 51 Reserved Group1 52 Reserved Group1 53 Reserved Group1 54 Reserved Group1 55 Reserved Group1 56 Reserved Group1 57 Reserved Group1 58 Reserved Group1 59 Reserved Group1 60 Reserved Group1 61 DCC2-error Group1 62 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 99 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-35.ESMChannelAssignments(continued) ERRORSOURCES GROUP CHANNELS Reserved Group1 63 GROUP2 Reserved Group2 0 Reserved Group2 1 CCMR4-compare Group2 2 Reserved Group2 3 FMC-uncorrectableerror(addressparityonbus1accesses) Group2 4 Reserved Group2 5 RAMevenbank(B0TCM)-uncorrectableerror Group2 6 Reserved Group2 7 RAModdbank(B1TCM)-uncorrectableerror Group2 8 Reserved Group2 9 RAMevenbank(B0TCM)-addressbusparityerror Group2 10 Reserved Group2 11 RAModdbank(B1TCM)-addressbusparityerror Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 TCM-ECClivelockdetect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 RTI_WWD_NMI Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 GROUP3 Reserved Group3 0 eFuseController-autoloaderror Group3 1 Reserved Group3 2 RAMevenbank(B0TCM)-ECCuncorrectableerror Group3 3 Reserved Group3 4 RAModdbank(B1TCM)-ECCuncorrectableerror Group3 5 Reserved Group3 6 FMC-uncorrectableerror:bus1andbus2interfaces Group3 7 (doesnotincludeaddressparityerroranderrorsonaccessestoEEPROMbank) Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11 100 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-35.ESMChannelAssignments(continued) ERRORSOURCES GROUP CHANNELS Reserved Group3 12 Reserved Group3 13 Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 101 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.19 Reset / Abort / Error Sources Table6-36.Reset/Abort/ErrorSources ESMHOOKUP ERRORSOURCE SYSTEMMODE ERRORRESPONSE group.channel CPUTRANSACTIONS Precisewriteerror(NCNB/StronglyOrdered) User/Privilege PreciseAbort(CPU) n/a Precisereaderror(NCB/DeviceorNormal) User/Privilege PreciseAbort(CPU) n/a Imprecisewriteerror(NCB/DeviceorNormal) User/Privilege ImpreciseAbort(CPU) n/a UndefinedInstructionTrap Illegalinstruction User/Privilege (CPU)(1) n/a MPUaccessviolation User/Privilege Abort(CPU) n/a SRAM B0TCM(even)ECCsingleerror(correctable) User/Privilege ESM 1.26 Abort(CPU),ESM=> B0TCM(even)ECCdoubleerror(noncorrectable) User/Privilege 3.3 nERROR B0TCM(even)uncorrectableerror(forexample,redundant User/Privilege ESM=>NMI=>nERROR 2.6 addressdecode) B0TCM(even)addressbusparityerror User/Privilege ESM=>NMI=>nERROR 2.10 B1TCM(odd)ECCsingleerror(correctable) User/Privilege ESM 1.28 Abort(CPU),ESM=> B1TCM(odd)ECCdoubleerror(noncorrectable) User/Privilege 3.5 nERROR B1TCM(odd)uncorrectableerror(forexample,redundant User/Privilege ESM=>NMI=>nERROR 2.8 addressdecode) B1TCM(odd)addressbusparityerror User/Privilege ESM=>NMI=>nERROR 2.12 FLASH FMCcorrectableerror-Bus1andBus2interfaces(doesnot User/Privilege ESM 1.6 includeaccessestoEEPROMbank) FMCuncorrectableerror-Bus1accesses Abort(CPU),ESM=> User/Privilege 3.7 (doesnotincludeaddressparityerror) nERROR FMCuncorrectableerror-Bus2accesses (doesnotincludeaddressparityerrorandEEPROMbank User/Privilege ESM=>nERROR 3.7 accesses) FMCuncorrectableerror-addressparityerroronBus1 User/Privilege ESM=>NMI=>nERROR 2.4 accesses FMCcorrectableerror-AccessestoEEPROMbank User/Privilege ESM 1.35 FMCuncorrectableerror-AccessestoEEPROMbank User/Privilege ESM 1.36 DMATRANSACTIONS Externalimpreciseerroronread(Illegaltransactionwithok User/Privilege ESM 1.5 response) Externalimpreciseerroronwrite(Illegaltransactionwithok User/Privilege ESM 1.13 response) Memoryaccesspermissionviolation User/Privilege ESM 1.2 Memoryparityerror User/Privilege ESM 1.3 DMMTRANSACTIONS Externalimpreciseerroronread(Illegaltransactionwithok User/Privilege ESM 1.5 response) Externalimpreciseerroronwrite(Illegaltransactionwithok User/Privilege ESM 1.13 response) HTU1 NCNB(StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=>VIM n/a Externalimpreciseerror(Illegaltransactionwithokresponse) User/Privilege Interrupt=>VIM n/a Memoryaccesspermissionviolation User/Privilege ESM 1.9 (1) TheUndefinedInstructionTRAPisNOTdetectableoutsidetheCPU.Thetrapistakenonlyiftheinstructionreachestheexecutestage oftheCPU. 102 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table6-36.Reset/Abort/ErrorSources(continued) ESMHOOKUP ERRORSOURCE SYSTEMMODE ERRORRESPONSE group.channel Memoryparityerror User/Privilege ESM 1.8 HTU2 NCNB(StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=>VIM n/a Externalimpreciseerror(Illegaltransactionwithokresponse) User/Privilege Interrupt=>VIM n/a Memoryaccesspermissionviolation User/Privilege ESM 1.9 Memoryparityerror User/Privilege ESM 1.8 N2HET1 Memoryparityerror User/Privilege ESM 1.7 N2HET2 Memoryparityerror User/Privilege ESM 1.7 FLEXRAY Memoryparityerror User/Privilege ESM 1.12 FTU NCNB(StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=>VIM n/a Externalimpreciseerror(Illegaltransactionwithokresponse) User/Privilege Interrupt=>VIM n/a Memoryaccesspermissionviolation User/Privilege ESM 1.16 Memoryparityerror User/Privilege ESM 1.14 ETHERNETMASTERINTERFACE Anyerrorreportedbyslavebeingaccessed User/Privilege ESM 1.43 MIBSPI MibSPI1memoryparityerror User/Privilege ESM 1.17 MibSPI3memoryparityerror User/Privilege ESM 1.18 MibSPI5memoryparityerror User/Privilege ESM 1.24 MIBADC MibADC1Memoryparityerror User/Privilege ESM 1.19 MibADC2Memoryparityerror User/Privilege ESM 1.1 DCAN DCAN1memoryparityerror User/Privilege ESM 1.21 DCAN2memoryparityerror User/Privilege ESM 1.23 DCAN3memoryparityerror User/Privilege ESM 1.22 PLL PLLsliperror User/Privilege ESM 1.10 PLL#2sliperror User/Privilege ESM 1.42 CLOCKMONITOR Clockmonitorinterrupt User/Privilege ESM 1.11 DCC DCC1error User/Privilege ESM 1.30 DCC2error User/Privilege ESM 1.62 CCM-R4 Selftestfailure User/Privilege ESM 1.31 Comparefailure User/Privilege ESM=>NMI=>nERROR 2.2 VIM Memoryparityerror User/Privilege ESM 1.15 VOLTAGEMONITOR VMONoutofvoltagerange n/a Reset n/a CPUSELFTEST(LBIST) CPUSelftest(LBIST)error User/Privilege ESM 1.27 Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 103 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-36.Reset/Abort/ErrorSources(continued) ESMHOOKUP ERRORSOURCE SYSTEMMODE ERRORRESPONSE group.channel PINMULTIPLEXINGCONTROL Muxconfigurationerror User/Privilege ESM 1.37 POWERDOMAINCONTROL PSCONcompareerror User/Privilege ESM 1.38 PSCONself-testerror User/Privilege ESM 1.39 eFuseCONTROLLER eFuseControllerAutoloaderror User/Privilege ESM=>nERROR 3.1 eFuseController-Anybitsetintheerrorstatusregister User/Privilege ESM 1.40 eFuseControllerself-testerror User/Privilege ESM 1.41 WINDOWEDWATCHDOG WWDNonmaskableInterruptexception n/a ESM=>NMI=>nERROR 2.24 ERRORSREFLECTEDINTHESYSESRREGISTER Power-UpReset n/a Reset n/a Oscillatorfail/PLLslip(2) n/a Reset n/a Watchdogexception n/a Reset n/a CPUReset(drivenbytheCPUSTC) n/a Reset n/a SoftwareReset n/a Reset n/a ExternalReset n/a Reset n/a (2) Oscillatorfail/PLLslipcanbeconfiguredinthesystemregister(SYS.PLLCTL1)togenerateareset. 6.20 Digital Windowed Watchdog This device includes a digital windowed watchdog (DWWD) module that protects against runaway code execution. The DWWD module allows the application to configure the time window within which the DWWD module expectstheapplicationtoservicethewatchdog.Awatchdogviolationoccursiftheapplicationservicesthe watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generateasystemresetoranonmaskableinterrupttotheCPUincaseofawatchdogviolation. The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog canonlybedisableduponasystemreset. 104 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.21 Debug Subsystem 6.21.1 Block Diagram ThedevicecontainsanICEPICKmoduletoallowJTAGaccesstothescanchains. Boundary Scan Boundary Scan I/F BSR/BSDL Debug TRST TMS ROM1 TCK RTCK DebugAPB TDI DAP TDO Secondary Tap 0 APB Mux AHB-AP APB slave POM ETM TPIU Cortex R4F to SCR1 viaA2A from IC PCR1/Bridge E P IC K _ C RTP Secondary Tap 1 TAP0 DMM TAP1 Secondary Tap 2 AJSM Figure6-19.DebugSubsystemBlockDiagram NOTE TheETM,RTPandDMMexistinsilicon,butarenotsupportedinthePGEpackage. 6.21.2 Debug Components Memory Map Table6-37.DebugComponentsMemoryMap FRAMEADDRESSRANGE RESPONSEFORACCESSTO FRAMECHIP FRAME ACTUAL MODULENAME UNIMPLEMENTEDLOCATIONSIN SELECT START END SIZE SIZE FRAME CoreSightDebug CSCS0 0xFFA00000 0xFFA00FFF 4KB 4KB Reads:0,writes:noeffect ROM Cortex-R4F CSCS1 0xFFA01000 0xFFA01FFF 4KB 4KB Reads:0,writes:noeffect Debug ETM-R4 CSCS2 0xFFA02000 0xFFA02FFF 4KB 4KB Reads:0,writes:noeffect CoreSightTPIU CSCS3 0xFFA03000 0xFFA03FFF 4KB 4KB Reads:0,writes:noeffect 6.21.3 JTAG Identification Code TheJTAGIDcodeforthisdeviceisthesameasthedeviceICEPickIdentificationCode. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 105 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-38.JTAGIDCode SILICONREVISION ID RevA 0x0B8A002F RevB 0x2B8A002F RevC 0x3B8A002F RevD 0x4B8A002F 6.21.4 Debug ROM TheDebugROMstoresthelocationofthecomponentsontheDebugAPBbus: Table6-39.DebugROMtable ADDRESS DESCRIPTION VALUE 0x000 pointertoCortex-R4F 0x00001003 0x001 ETM-R4 0x00002003 0x002 TPIU 0x00003003 0x003 POM 0x00004003 0x004 endoftable 0x00000000 106 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.21.5 JTAG Scan Interface Timings Table6-40.JTAGScanInterfaceTiming(1) NO. PARAMETER MIN MAX UNIT fTCK TCKfrequency(atHCLKmax) 12 MHz fRTCK RTCKfrequency(atTCKmaxandHCLKmax) 10 MHz 1 td(TCK-RTCK) Delaytime,TCKtoRTCK 24 ns 2 tsu(TDI/TMS-RTCKr) Setuptime,TDI,TMSbeforeRTCKrise(RTCKr) 26 ns 3 th(RTCKr-TDI/TMS) Holdtime,TDI,TMSafterRTCKr 0 ns 4 th(RTCKr-TDO) Holdtime,TDOafterRTCKf 0 ns 5 td(TCKf-TDO) Delaytime,TDOvalidafterRTCKfall(RTCKf) 12 ns (1) TimingsforTDOarespecifiedforamaximumof50pFloadonTDO TCK RTCK 1 1 TMS TDI 2 3 TDO 4 5 Figure6-20.JTAGTiming Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 107 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 6.21.6 Advanced JTAG Security Module ThisdeviceincludesanAdvancedJTAGSecurityModule(AJSM)whichprovidesmaximumsecuritytothe memorycontentofthedevicebylettinguserssecurethedeviceafterprogramming. Flash Module Output OTPContents . . . H L H L H L L H (example) . . . Unlock By Scan Register Internal Tie-Offs L L H H H H L L (example only) UNLOCK 128-bit comparator Internal Tie-Offs H L L H H L L H (example only) Figure6-21.AJSMUnlock The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCKsignalbeingasserted,sothatthedeviceisnowunsecure. A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure thedevice. Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents andtheUnlock-By-Scanregistercontentsresultsintheoriginalvisibleunlockcode. TheUnlock-By-Scanregisterisresetonlyuponassertingpower-onreset(nPORRST). A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in thisstate. 108 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.21.7 Embedded Trace Macrocell (ETM-R4) The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see ARMCoreSightETM-R4TRMspecification. 6.21.7.1 ETMTRACECLKINSelection The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The selection is done by the EXTCTLOUT[1:0] control bits of the TPIU; the default is '00'. The address of this registerisTPIUbaseaddress+0x404. Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should bewrittentothisregister. Table6-41.TPIU/TRACECLKINSelection EXTCTLOUT[1:0] TPIU/TRACECLKIN 00 tied-zero 01 VCLK 10 ETMTRACECLKIN 11 tied-zero 6.21.7.2 TimingSpecifications t l(ETM) t tr(ETM) h(ETM) tf(ETM) t cyc(ETM) Figure6-22.ETMTRACECLKOUTTiming Table6-42.ETMTRACECLKTiming PARAMETER MIN MAX UNIT t Clockperiod t *4 ns cyc(ETM) (HCLK) t Lowpulsewidth 20 ns l(ETM) t Highpulsewidth 20 ns h(ETM) t Clockanddatarisetime 3 ns r(ETM) t Clockanddatafalltime 3 ns f(ETM) Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 109 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Figure6-23.ETMDATATiming Table6-43.ETMDATATiming PARAMETER MIN MAX UNIT Delaytime,ETMtraceclockhightoETM t 1.5 7 ns d(ETMTRACECLKH-ETMDATAV) datavalid Delaytime,ETMtraceclocklowtoETM t 1.5 7 ns d(ETMTRACECLKl-ETMDATAV) datavalid NOTE The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient temperaturelowerthan85°C. 110 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.21.8 RAM Trace Port (RTP) The RTP provides the ability to datalog the RAM contents of the TMS570 devices or accesses to peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmissionofthedata.Thetracedataistransmittedoveradedicatedexternalinterface. 6.21.8.1 Features TheRTPoffersthefollowingfeatures: • Twomodesofoperation-TraceModeandDirectDataMode – TraceMode • Nonintrusivedatatraceonwriteorreadoperation • VisibilityofRAMcontentatanytimeonexternalcapturehardware • Traceofperipheralaccesses • 2configurabletraceregionsforeachRAMmoduletolimitamountofdatatobetraced • FIFOtostoredataandaddressofdataofmultipleread/writeoperations • TraceofCPUand/orDMAaccesseswithindicationofthemasterinthetransmitteddatapacket – DirectDataMode • Directly write data with the CPU or trace read operations to a FIFO, without transmitting header andaddressinformation • Dedicatedsynchronousinterfacetotransmitdatatoexternaldevices • Free-runningclockgenerationorclockstopmodebetweentransmissions • Upto100Mbps/pintransferratefortransmittingdata • PinsnotusedinfunctionalmodecanbeusedasGIOs 6.21.8.2 TimingSpecifications t l(RTP) tr th(RTP) tf t cyc(RTP) Figure6-24.RTPCLKTiming Table6-44.RTPCLKTiming PARAMETER MIN MAX UNIT Clockperiod,prescaledfromHCLK;mustnotbe t 11(=90MHz) ns cyc(RTP) fasterthanHCLK/2 t Highpulsewidth ((t )/2)-((t+t)/2) ns h(RTP) cyc(RTP) r f t Lowpulsewidth ((t )/2)-((t+t)/2) ns l(RTP) cyc(RTP) r f Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 111 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Figure6-25.RTPDATATiming Table6-45.RTPDATATiming PARAMETER MIN MAX UNIT t Delaytime,RTPCLKhightoRTPSYNCvalid –5 4 ns d(RTPCLKH-RTPSYNCV) t Delaytime,RTPCLKhightoRTPDATAvalid –5 4 ns d(RTPCLKH-RTPDATAV) t t dis(RTP) ena(RTP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HCLK HHCCLLKK RTPCLK RRTTPPCCLLKK RTPnENA RRTTPPEENNAA RTPSYNC RRTTPPSSYYNNCC RTPRRDTTPPADDAATTTAAA d1 d2 d3 d4 d5 d6 d7 d8 Divide by 1 Figure6-26.RTPnENATiming Table6-46.RTPnENATiming PARAMETER MIN MAX UNIT timeRTPnENAmustgohighbeforewhatwould t bethenextRTPSYNC,toensuredelayingthe 3t +t +12 ns dis(RTP) c(HCLK) r(RTPSYNC) nextpacket timeafterRTPnENAgoeslowbeforeapacketthat t 4t +t 5t +t +12 ns ena(RTP) hasbeenhalted,resumes c(HCLK) r(RTPSYNC) c(HCLK) r(RTPSYNC) 112 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.21.9 Data Modification Module (DMM) The Data Modification Module (DMM) provides the capability to modify data in the entire 4-GB address spaceoftheTMS570devicesfromanexternalperipheral,withminimalinterruptionoftheapplication. 6.21.9.1 Features TheDMMmodulehasthefollowingfeatures: • Actsasabusmaster,thusenablingdirectwritestothe4-GBaddressspacewithoutCPUintervention • Writes to memory locations specified in the received packet (leverages packets defined by trace mode oftheRAMtraceport(RTP)module • Writes received data to consecutive addresses, which are specified by the DMM module (leverages packetsdefinedbydirectdatamodeofRTPmodule) • Configurableportwidth(1,2,4,8,16pins) • Upto100Mbit/spindatarate • UnusedpinsconfigurableasGPIOpins 6.21.9.2 TimingSpecifications t l(DMM) tr th(DMM) tf t cyc(DMM) Figure6-27.DMMCLKTiming Table6-47.TimingRequirementsforDMMCLK MIN MAX UNIT t Cycletime,DMMCLKperiod t *2 ns cyc(DMM) c(HCLK) t Pulseduration,DMMCLKhigh ((t )/2)-((t+t)/2) ns h(DMM) cyc(DMM) r f t Pulseduration,DMMCLKlow ((t )/2)-((t+t)/2) ns l(DMM) cyc(DMM) r f t t ssu(DMM) sh(DMM) DMMSYNC DMMCLK DMMDATA t t dsu(DMM) dh(DMM) Figure6-28.DMMDATATiming Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 113 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table6-48.TimingRequirementsforDMMDATA MIN MAX UNIT t SYNCactivetoclkfallingedgesetuptime 2 ns ssu(DMM) t clkfallingedgetoSYNCinactiveholdtime 3 ns sh(DMM) t DATAtoclkfallingedgesetuptime 2 ns dsu(DMM) t clkfallingedgetoDATAholdtime 3 ns dh(DMM) HCLK DMMCLK DMMSYNC DMMDATA D00 D01 D10 D11 D20 D21 D30 D31 D40 D41 D50 DMMnENA Figure6-29.DMMnENATiming Figure 6-29 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data width = 8, port width = 4) where none of the packets received by the DMM are sent out, leading to filling up of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x, D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets immediately(after0HCLKcycles). 114 SystemInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 6.21.10 Boundary Scan Chain The device supports IEEE1149.1-compliant boundary scan for testing pin-to-pin compatibility. The boundaryscanchainisconnectedtotheBoundaryScanInterfaceoftheICEPICKmodule. Device Pins (conceptual) TRST IC Boundary TDI TMS Boundary Scan Interface E Scan TCK P TDO RTCK IC TDI K BSDL TDO Figure6-30.BoundaryScanImplementation(ConceptualDiagram) Dataisseriallyshiftedintoallboundary-scanbuffersviaTDI,andoutviaTDO. Copyright©2012–2015,TexasInstrumentsIncorporated SystemInformationandElectricalSpecifications 115 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7 Peripheral Information and Electrical Specifications 7.1 Peripheral Legend Table7-1.PeripheralLegend ABBREVIATION FULLNAME MibADC AnalogToDigitalConverter CCM-R4F CPUCompareModule-CortexR4F CRC CyclicRedundancyCheck DCAN ControllerAreaNetwork DCC DualClockComparator DMA DirectMemoryAccess DMM DataModificationModule EMIF ExternalMemoryInterface ESM ErrorSignalingModule ETM-R4F EmbeddedTraceMacrocell-CortexR4F FTU FlexRayTransferUnit GPIO General-PurposeInput/Output HTU HighEndTimerTransferUnit I2C Inter-IntegratedCircuit LIN LocalInterconnectNetwork MIBSPI MultibufferSerialPeripheralInterface N2HET PlatformHigh-EndTimer POM ParameterOverlayModule RTI Real-TimeInterruptModule RTP RAMTracePort SCI SerialCommunicationsInterface SPI SerialPeripheralInterface VIM VectoredInterruptManager 7.2 Multibuffered 12-Bit Analog-to-Digital Converter The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on V and V from coupling into the A-to-D analog stage. All A-to-D specifications are given SS CC withrespecttoAD unlessotherwisenoted. REFLO Table7-2.MibADCOverview DESCRIPTION VALUE Resolution 12bits Monotonic Assured Outputconversioncode 00htoFFFh[00forV ≤AD ;FFFforV ≥AD ] AI REFLO AI REFHI 116 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.2.1 Features • 10-/12-bitresolution • AD andAD pins(highandlowreferencevoltages) REFHI REFLO • TotalSample/Hold/Converttime:600nsTypicalMinimumat30MHzADCLK • Onememoryregionperconversiongroupisavailable(event,group1,group2) • Allocationofchannelstoconversiongroupsiscompletelyprogrammable • MemoryregionsareservicedeitherbyinterruptorbyDMA • Programmableinterruptthresholdcounterisavailableforeachgroup • Programmablemagnitudethresholdinterruptforeachgroupforanyonechannel • Optiontoreadeither8-bit,10-bitor12-bitvaluesfrommemoryregions • Singleorcontinuousconversionmodes • Embeddedself-test • Embeddedcalibrationlogic • Enhancedpower-downmode – OptionalfeaturetoautomaticallypowerdownADCcorewhennoconversionisinprogress • Externaleventpin(ADEVT)programmableasgeneral-purposeI/O 7.2.2 Event Trigger Options The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3 groups can be configured to be hardware event-triggered. In that case, the application can select from among8eventsourcestobethetriggerforagroup'sconversions. 7.2.2.1 DefaultMIBADC1EventTriggerHookup Table7-3.MIBADC1EventTriggerHookup Event# SourceSelectBitsForG1,G2OrEvent Trigger (G1SRC[2:0],G2SRC[2:0]orEVSRC[2:0]) 1 000 ADEVT 2 001 N2HET1[8] 3 010 N2HET1[10] 4 011 RTIcompare0interrupt 5 100 N2HET1[12] 6 101 N2HET1[14] 7 110 GIOB[0] 8 111 GIOB[1] NOTE For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (via the mux control),orbydrivingthefunctionfromanexternaltriggersourceasinput.Ifthemuxcontrol module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there isnomultiplexingontheinputconnections. NOTE For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actualinterruptisnotsignaledtotheCPU. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 117 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.2.2.2 AlternateMIBADC1EventTriggerHookup Table7-4.AlternateMIBADC1EventTriggerHookup SOURCESELECTBITSFORG1,G2OREVENT EVENT# TRIGGER (G1SRC[2:0],G2SRC[2:0]orEVSRC[2:0]) 1 000 ADEVT 2 001 N2HET2[5] 3 010 N2HET1[27] 4 011 RTIcompare0interrupt 5 100 N2HET1[17] 6 101 N2HET1[19] 7 110 N2HET1[11] 8 111 N2HET2[13] TheselectionbetweenthedefaultMIBADC1eventtriggerhook-upversusthealternateeventtriggerhook- upisdonebymultiplexingcontrolmoduleregister30bits0and1. If30[0]=1,thenthedefaultMibADC1eventtriggerhook-upisused. If30[0]=0and30[1]=1,thenthealternateMibADC1eventtriggerhook-upisused. NOTE ForADEVTtriggersource,theconnectiontotheMibADC1moduletriggerinputismadefrom the output side of the input buffer. This way, a trigger condition can be generated either by configuring ADEVT as an output function on to the pad (via the mux control), or by driving theADEVTsignalfromanexternaltriggersourceasinput.Ifthemuxcontrolmoduleisused to select different functionality instead of the ADEVT signal, then care must be taken to disableADEVTfromtriggeringconversions;thereisnomultiplexingontheinputconnection. NOTE For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made from the input side of the output buffer (at the N2HETx module boundary). This way, a triggerconditioncanbegeneratedeveniftheN2HETxsignalisnotselectedtobeoutputon thepad. NOTE For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actualinterruptisnotsignaledtotheCPU. 118 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.2.2.3 DefaultMIBADC2EventTriggerHookup Table7-5.MIBADC2EventTriggerHookup SOURCESELECTBITSFORG1,G2OREVENT EVENT# TRIGGER (G1SRC[2:0],G2SRC[2:0]orEVSRC[2:0]) 1 000 AD2EVT 2 001 N2HET1[8] 3 010 N2HET1[10] 4 011 RTIcompare0 5 100 N2HET1[12] 6 101 N2HET1[14] 7 110 GIOB[0] 8 111 GIOB[1] NOTE For AD2EVT, N2HET1 and GIOB trigger sources, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (via the mux control),orbydrivingthefunctionfromanexternaltriggersourceasinput.Ifthemuxcontrol moduleisusedtoselectdifferentfunctionalityinsteadoftheAD2EVT,N2HET1[x]orGIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there isnomultiplexingontheinputconnections. NOTE For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actualinterruptisnotsignaledtotheCPU. 7.2.2.4 AlternateMIBADC2EventTriggerHookup Table7-6.AlternateMIBADC2EventTriggerHookup SOURCESELECTBITSFORG1,G2OREVENT EVENT# TRIGGER (G1SRC[2:0],G2SRC[2:0]orEVSRC[2:0]) 1 000 AD2EVT 2 001 N2HET2[5] 3 010 N2HET1[27] 4 011 RTIcompare0 5 100 N2HET1[17] 6 101 N2HET1[19] 7 110 N2HET1[11] 8 111 N2HET2[13] TheselectionbetweenthedefaultMIBADC2eventtriggerhook-upversusthealternateeventtriggerhook- upisdonebymultiplexingcontrolmoduleregister30bits0and1. If30[0]=1,thenthedefaultMibADC2eventtriggerhook-upisused. If30[0]=0and30[1]=1,thenthealternateMibADC2eventtriggerhook-upisused. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 119 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com NOTE For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made fromtheoutputsideoftheinputbuffer.Thisway,atriggerconditioncanbegeneratedeither by configuring AD2EVT as an output function on to the pad (via the mux control), or by drivingtheAD2EVTsignalfromanexternaltriggersourceasinput.Ifthemuxcontrolmodule is used to select different functionality instead of the AD2EVT signal, then care must be taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input connections. NOTE For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made from the input side of the output buffer (at the N2HETx module boundary). This way, a triggerconditioncanbegeneratedeveniftheN2HETxsignalisnotselectedtobeoutputon thepad. NOTE For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actualinterruptisnotsignaledtotheCPU. 120 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.2.3 ADC Electrical and Timing Specifications Table7-7.MibADCRecommendedOperatingConditions PARAMETER MIN MAX UNIT AD A-to-Dhigh-voltagereferencesource AD V (1) V REFHI REFLO CCAD AD A-to-Dlow-voltagereferencesource V (1) AD V REFLO SSAD REFHI V Analoginputvoltage AD AD V AI REFLO REFHI Analoginputclampcurrent(2) I -2 2 mA AIK (VAI<VSSAD–0.3orVAI>VCCAD+0.3) (1) ForV andV recommendedoperatingconditions,seeSection5.4. CCAD SSAD (2) InputcurrentsintoanyADCinputchanneloutsidethespecifiedlimitscouldaffectconversionresultsofotherchannels. Table7-8.MibADCElectricalCharacteristicsOverFullRangesofRecommendedOperatingConditions PARAMETER DESCRIPTION/CONDITIONS MIN MAX UNIT Analoginputmuxon- R SeeFigure7-1 250 Ω mux resistance ADCsampleswitchon- R SeeFigure7-1 250 Ω samp resistance C Inputmuxcapacitance SeeFigure7-1 16 pF mux C ADCsamplecapacitance SeeFigure7-1 13 pF samp V ≤V <V +100mV –300 200 SSAD IN SSAD Analogoff-stateinputleakage V =3.6V I CCAD V +100mV≤V ≤V -200mV –200 200 nA AIL current maximum SSAD IN CCAD V -200mV<V ≤V –200 500 CCAD IN CCAD V ≤V <V +300mV –1000 250 SSAD IN SSAD Analogoff-stateinputleakage V =5.5V I CCAD V +300mV≤V ≤V -300mV –250 250 nA AIL current maximum SSAD IN CCAD V -300mV<V ≤V –250 1000 CCAD IN CCAD V ≤V <V +100mV –8 2 SSAD IN SSAD I (1) ADC1Analogon-stateinput VCCAD=3.6V V +100mV<V <V -200mV –4 2 µA AOSB1 biascurrent maximum SSAD IN CCAD V -200mV<V <V –4 12 CCAD IN CCAD V ≤V <V +100mV –7 2 SSAD IN SSAD I (1) ADC2Analogon-stateinput VCCAD=3.6V V +100mV≤V ≤V -200mV –4 2 µA AOSB2 biascurrent maximum SSAD IN CCAD V -200mV<V ≤V –4 10 CCAD IN CCAD V ≤V <V +300 mV –10 3 SSAD IN SSAD I (1) ADC1Analogon-stateinput VCCAD=5.5V V +300mV≤V ≤V -300mV –5 3 µA AOSB1 biascurrent maximum SSAD IN CCAD V -300mV<V ≤V –5 14 CCAD IN CCAD V ≤V <V +300mV –8 3 SSAD IN SSAD I (1) ADC2Analogon-stateinput VCCAD=5.5V V +300mV≤V ≤V -300mV –5 3 µA AOSB2 biascurrent maximum SSAD IN CCAD V -300mV<V ≤V –5 12 CCAD IN CCAD I AD inputcurrent AD =V ,AD =V 3 mA ADREFHI REFHI REFHI CCAD REFLO SSAD Normaloperatingmode 15 mA I Staticsupplycurrent CCAD ADCcoreinpowerdownmode 5 µA (1) IfasharedchannelisbeingconvertedbybothADCconvertersatthesametime,theon-stateleakageisequaltoI +I AOSL1 AOSL2 Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 121 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Rext Pin Smux Rmux V S1 I AOSB On-State Cext Bias Current Rext Pin Smux Rmux V S2 I AIL Cext IAIL IAIL Off-State Leakages Rext Pin Smux Rmux Ssamp Rsamp V S24 I AIL Cmux Csamp Cext IAIL IAIL Figure7-1.MibADCInputEquivalentCircuit Table7-9.MibADCTimingSpecifications PARAMETER MIN NOM MAX UNIT t (1) Cycletime,MibADCclock 0.033 µs c(ADCLK) t (2) Delaytime,sampleandholdtime 0.2 µs d(SH) t DelaytimefromADCpoweronuntilfirstinputcanbesampled 1 µs d(PU-ADV) 12-BITMODE t Delaytime,conversiontime 0.4 µs d(c) t (3) Delaytime,totalsample/holdandconversiontime 0.6 µs d(SHC) 10-BITMODE t Delaytime,conversiontime 0.33 µs d(c) t (3) Delaytime,totalsample/holdandconversiontime 0.53 µs d(SHC) (1) TheMibADCclockistheADCLK,generatedbydividingdowntheVCLKbyaprescalefactordefinedbytheADCLOCKCRregisterbits 4:0. (2) ThesampleandholdtimefortheADCconversionsisdefinedbytheADCLKfrequencyandtheAD<GP>SAMPregisterforeach conversiongroup.Thesampletimeneedstobedeterminedbyaccountingfortheexternalimpedanceconnectedtotheinputchannelas wellastheADC’sinternalimpedance. (3) Thisistheminimumsample/holdandconversiontimethatcanbeachieved.Theseparametersaredependentonmanyfactors,for example,theprescalesettings. 122 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table7-10.MibADCOperatingCharacteristicsOverFullRangesofRecommendedOperatingConditions PARAMETER DESCRIPTION/CONDITIONS MIN NOM MAX UNIT CR Conversionrangeover AD -AD REFHI REFLO whichspecifiedaccuracyis 3 5.5 V maintained Z ZeroScaleOffset Differencebetweenthefirstidealtransition 10-bitmode 1 LSB(1) SET (fromcode000hto001h)andtheactual transition 12-bitmode 2 LSB(2) F FullScaleOffset Differencebetweentherangeofthe 10-bitmode 2 LSB SET measuredcodetransitions(fromfirsttolast) andtherangeoftheidealcodetransitions 12-bitmode 3 LSB E Differentialnonlinearity Differencebetweentheactualstepwidthand 10-bitmode ±1.5 LSB DNL error theidealvalue.(SeeFigure76) 12-bitmode ±2 LSB E Integralnonlinearityerror Maximumdeviationfromthebeststraightline 10-bitmode ±2 LSB INL throughtheMibADC.MibADCtransfer characteristics,excludingthequantization 12-bitmode ±2 LSB error. E Totalunadjustederror Maximumvalueofthedifferencebetweenan 10-bitmode ±2 LSB TOT analogvalueandtheidealmidstepvalue. 12-bitmode ±4 LSB (1) 1LSB=(AD –AD )/210for10-bitmode REFHI REFLO (2) 1LSB=(AD –AD )/212for12-bitmode REFHI REFLO Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 123 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.2.4 Performance (Accuracy) Specifications 7.2.4.1 MibADCNonlinearityErrors The differential nonlinearity error shown in Figure 7-2 (sometimes referred to as differential linearity) is the differencebetweenanactualstepwidthandtheidealvalueof1LSB. 0 ... 110 0 ... 101 0 ... 100 e d o C ut p ut 0 ... 011 O al 1 LSB Differential Linearity git Error (–½ LSB) Di 0 ... 010 Differential Linearity 0 ... 001 Error (–½ LSB) 1 LSB 0 ... 000 0 1 2 3 4 5 Analog Input Value (LSB) 12 NOTEA: 1 LSB = (AD –AD )/2 REFHI REFLO Figure7-2.DifferentialNonlinearity(DNL)Error 124 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 The integral nonlinearity error shown in Figure 7-3 (sometimes referred to as linearity error) is the deviationofthevaluesontheactualtransferfunctionfromastraightline. 0 ... 111 0 ... 110 Ideal 0 ... 101 Transition e Actual d Transition o C 0 ... 100 ut p ut At Transition O gital 0 ... 011 0(–1½1/ 1L0S0B) Di 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (–1/4 LSB) 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) 12 NOTEA: 1 LSB = (AD –AD )/2 REFHI REFLO Figure7-3.IntegralNonlinearity(INL)Error Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 125 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.2.4.2 MibADCTotalError The absolute accuracy or total error of an MibADC as shown in Figure 7-4 is the maximum value of the differencebetweenananalogvalueandtheidealmidstepvalue. 0 ... 111 0 ... 110 0 ... 101 e d o 0 ... 100 C ut Total Error p ut At Step 0 ... 101 O (–1 1/4 LSB) al 0 ... 011 git Di 0 ... 010 Total Error 0 ... 001 At Step 0 ... 001 (1/2 LSB) 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) 12 NOTEA: 1 LSB = (AD –AD )/2 REFHI REFLO Figure7-4.AbsoluteAccuracy(Total)Error 126 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.3 General-Purpose Input/Output The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable.BothGIOAandGIOBsupportexternalinterruptcapability. 7.3.1 Features TheGPIOmodulehasthefollowingfeatures: • EachIOpincanbeconfiguredas: – Input – Output – OpenDrain • Theinterruptshavethefollowingcharacteristics: – Programmableinterruptdetectioneitheronbothedgesoronasingleedge(setinGIOINTDET) – Programmableedge-detectionpolarity,eitherrisingorfallingedge(setinGIOPOLregister) – Individualinterruptflags(setinGIOFLGregister) – Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers respectively – Programmableinterruptpriority,setthroughGIOLVLSETandGIOLVLCLRregisters • Internalpullup/pulldownallowsunusedI/Opinstobeleftunconnected ForinformationoninputandoutputtimingsseeSection5.11 andSection5.12 Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 127 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.4 Enhanced High-End Timer (N2HET) The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiplesensorinformationanddriveactuatorswithcomplexandaccuratetimepulses. 7.4.1 Features TheN2HETmodulehasthefollowingfeatures: • Programmabletimerforinputandoutputtimingfunctions • Reducedinstructionset(30instructions)fordedicatedtimeandanglefunctions • 160wordsofinstructionRAMprotectedbyparity • Userdefinednumberof25-bitvirtualcountersfortimer,eventcountersandanglecounters • 7-bit hardware counters for some pins allow up to 32-bit resolution in conjunction with the 25-bit virtual counters • Upto32pinsusableforinputsignalmeasurementsoroutputsignalgeneration • Programmablesuppressionfilterforeachinputpinwithadjustablelimitingfrequency • LowCPUoverheadandinterruptload • Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU) orDMA • Diagnosticcapabilitieswithdifferentloopbackmechanismsandpinstatusreadbackfunctionality 7.4.2 N2HET RAM Organization The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one RAM address may be written while another address is read. The RAM words are 96 bits wide, which are splitintothree32-bitfields(program,control,anddata). 7.4.3 Input Timing Specifications TheN2HETinstructionsPCNTandWCAPimposesometimingconstraintsontheinputsignals. 1 N2HETx 3 4 2 Figure7-5.N2HETInputCaptureTimings 128 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table7-11.InputTimingRequirementsfortheN2HETInputCaptureFunctionality NO. MIN(1) (2) MAX(1) (2) UNIT 1 Inputsignalperiod,PCNTorWCAPforrisingedgetorising 2(hr)(lr)tc +2 225(hr)(lr)tc -2 ns edge (VCLK2) (VCLK2) 2 Inputsignalperiod,PCNTorWCAPforfallingedgetofalling 2(hr)(lr)tc +2 225(hr)(lr)tc -2 ns edge (VCLK2) (VCLK2) 3 Inputsignalhighphase,PCNTorWCAPforrisingedgeto (hr)(lr)tc +2 225(hr)(lr)tc -2 ns fallingedge (VCLK2) (VCLK2) 4 Inputsignallowphase,PCNTorWCAPforfallingedgeto (hr)(lr)tc +2 225(hr)(lr)tc -2 ns risingedge (VCLK2) (VCLK2) (1) hr=High-resolutionprescaler,configuredusingtheHRPFCfieldofthePrescaleFactorRegister(HETPFR). (2) lr=Loop-resolutionprescaler,configuredusingtheLFPRCfieldofthePrescaleFactorRegister(HETPFR). Both N2HET1 and N2HET2 have channels that are enhanced to be able to capture inputs with smaller pulse widths than that specified in Table 7-11. See Table 7-13 for a list of which pins support small pulse capture. TheinputcapturecapabilityforthesechannelsisspecifiedinTable7-12. Table7-12.InputTimingRequirementsforN2HETChannelswithEnhancedPulseCapture NO. MIN MAX UNIT 1 Inputsignalperiod,PCNTorWCAPforrisingedgetorising (hr)(lr)tc +2 225(hr)(lr)tc -2 ns edge (VCLK2) (VCLK2) 2 Inputsignalperiod,PCNTorWCAPforfallingedgetofalling (hr)(lr)tc +2 225(hr)(lr)tc -2 ns edge (VCLK2) (VCLK2) 3 Inputsignalhighphase,PCNTorWCAPforrisingedgeto 2(hr)tc +2 225(hr)(lr)tc -2 ns fallingedge (VCLK2) (VCLK2) 4 Inputsignallowphase,PCNTorWCAPforfallingedgeto 2(hr)tc +2 225(hr)(lr)tc -2 ns risingedge (VCLK2) (VCLK2) Table7-13.InputCapturePinCapability CHANNEL SUPPORTS32-BITCAPTURE ENHANCEDPULSECAPTURE N2HET1[00] Yes No N2HET1[01] Yes No N2HET1[02] Yes No N2HET1[03] Yes No N2HET1[04] Yes No N2HET1[05] Yes No N2HET1[06] Yes No N2HET1[07] Yes No N2HET1[08] Yes No N2HET1[09] Yes No N2HET1[10] Yes No N2HET1[11] Yes No N2HET1[12] Yes No N2HET1[13] Yes No N2HET1[14] Yes No N2HET1[15] Yes Yes N2HET1[16] Yes No N2HET1[17] Yes No N2HET1[18] Yes No N2HET1[19] Yes No N2HET1[20] Yes Yes Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 129 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table7-13.InputCapturePinCapability(continued) CHANNEL SUPPORTS32-BITCAPTURE ENHANCEDPULSECAPTURE N2HET1[21] Yes No N2HET1[22] Yes No N2HET1[23] Yes No N2HET1[24] Yes No N2HET1[25] Yes No N2HET1[26] Yes No N2HET1[27] Yes No N2HET1[28] Yes No N2HET1[29] Yes No N2HET1[30] Yes No N2HET1[31] Yes Yes N2HET2[00] Yes No N2HET2[01] No No N2HET2[02] No No N2HET2[03] No No N2HET2[04] Yes No N2HET2[05] No No N2HET2[06] Yes No N2HET2[07] No No N2HET2[08] No No N2HET2[09] No No N2HET2[10] No No N2HET2[11] No No N2HET2[12] Yes Yes N2HET2[13] No No N2HET2[14] Yes Yes N2HET2[15] No No N2HET2[16] Yes Yes N2HET2[18] No No 7.4.4 N2HET1-N2HET2 Interconnections In some applications the N2HET resolutions must be synchronized. Some other applications require a singletimebasetobeusedforallPWMoutputsandinputtimingcaptures. The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to the loop resolution signal sent by the master. The slave does not require this signal after it receives the first synchronization signal. However, anytime the slave receives the resynchronization signal from the master,theslavemustsynchronizeitselfagain.. N2HET1 N2HET2 EXT_LOOP_SYNC NHET_LOOP_SYNC NHET_LOOP_SYNC EXT_LOOP_SYNC Figure7-6.N2HET1 –N2HET2SynchronizationHookup 130 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.4.5 N2HET Checking 7.4.5.1 InternalMonitoring To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be used to monitor each other’s signals as shown in Figure 7-7. The direction of the monitoring is controlled bytheI/Omultiplexingcontrolmodule. N2HET1[1,3,5,7,9,11] IOMM mux control signal x N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18] N2HET1 N2HET2[8,10,12,14,16,18] N2HET2 Figure7-7.N2HETMonitoring 7.4.5.2 OutputMonitoringUsingDualClockComparator(DCC) N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure thefrequencyofthepulse-widthmodulated(PWM)signalonN2HET1[31]. Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to measurethefrequencyofthepulse-widthmodulated(PWM)signalonN2HET2[0]. Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection to the DCC module is made directly from the output of the N2HETx module (from the input of the output buffer). FormoreinformationonDCCseeSection6.7.3. 7.4.6 Disabling N2HET Outputs Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. See the device specifictechnicalreferencemanualformoredetailsonthe"N2HETPinDisable"feature. GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin Disable"inputforN2HET2. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 131 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.4.7 High-End Timer Transfer Unit (HTU) A High End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or frommainmemory.AMemoryProtectionUnit(MPU)isbuiltintotheHTU. 7.4.7.1 Features • CPUandDMAindependent • MasterPorttoaccesssystemmemory • 8controlpacketssupportingdualbufferconfiguration • ControlpacketinformationisstoredinRAMprotectedbyparity • Eventsynchronization(HETtransferrequests) • Supports32-or64-bittransactions • AddressingmodesforHETaddress(8byteor16byte)andsystemmemoryaddress(fixed,32bitor64bit) • Oneshot,circularandautoswitchbuffertransfermodes • Requestlostdetection 7.4.7.2 TriggerConnections Table7-14.HTU1RequestLineConnection MODULES REQUESTSOURCE HTU1REQUEST N2HET1 HTUREQ[0] HTU1DCP[0] N2HET1 HTUREQ[1] HTU1DCP[1] N2HET1 HTUREQ[2] HTU1DCP[2] N2HET1 HTUREQ[3] HTU1DCP[3] N2HET1 HTUREQ[4] HTU1DCP[4] N2HET1 HTUREQ[5] HTU1DCP[5] N2HET1 HTUREQ[6] HTU1DCP[6] N2HET1 HTUREQ[7] HTU1DCP[7] Table7-15.HTU2RequestLineConnection MODULES REQUESTSOURCE HTU2REQUEST N2HET2 HTUREQ[0] HTU2DCP[0] N2HET2 HTUREQ[1] HTU2DCP[1] N2HET2 HTUREQ[2] HTU2DCP[2] N2HET2 HTUREQ[3] HTU2DCP[3] N2HET2 HTUREQ[4] HTU2DCP[4] N2HET2 HTUREQ[5] HTU2DCP[5] N2HET2 HTUREQ[6] HTU2DCP[6] N2HET2 HTUREQ[7] HTU2DCP[7] 132 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.5 FlexRay Interface The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The sample clock bit rate can be programmed to values up to 10 Mbps. Additional bus driver (BD) hardware is requiredforconnectiontothephysicallayer. For communication on a FlexRay network, individual message buffers with up to 254 data bytes are configurable. The message storage consists of a single-ported message RAM that holds up to 128 message buffers. All functions concerning the handling of messages are implemented in the message handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay Channel Protocol Controllers and the message RAM, maintaining the transmission schedule, as well as providingmessagestatusinformation. The register set of the FlexRay module can be accessed directly by the CPU through the VBUS interface. These registers are used to control, configure, and monitor the FlexRay channel protocol controllers, message handler, global time unit, system universal control, frame/symbol processing, network management,interruptcontrol,andtoaccessthemessageRAMthroughtheI/Obuffer. 7.5.1 Features TheFlexRaymodulehasthefollowingfeatures: • ConformancewithFlexRayprotocolspecificationv2.1 • Dataratesofupto10Mbpsoneachchannel • Upto128messagebuffers • 8KB of message RAM for storage (for example, 128 message buffers with maximum of 48-byte data sectionorupto30messagebufferswith254-bytedatasection) • Configurationofmessagebufferswithdifferentpayloadlengths • OneconfigurablereceiveFIFO • Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive FIFO. • CPUaccesstomessagebuffersthroughinputandoutputbuffer • FlexRay Transfer Unit (FTU) for automatic data transfer between data memory and message buffers withoutCPUinteraction • Filteringforslotcounter,cyclecounter,andchannelID • Maskablemoduleinterrupts • SupportsNetworkManagement 7.5.2 Electrical and Timing Specifications Table7-16.TimingRequirementsforFlexRayInputs MIN MAX UNIT t InputminimumpulsewidthtomeettheFlexRaysampling t +2.5(1) ns pw requirement c(AVCLK2) (1) t parameter RxAsymDelay t pw V CCIO Input 0.6*V 0.6*V CCIO CCIO 0.4*VCCIO 0.4*VCCIO 0 Figure7-8.FlexRayInputs Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 133 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Table7-17.FlexRayJitterTiming PARAMETER MIN MAX UNIT t Clockjitterandsignalsymmetry 98 102 ns Tx1bit t FlexRayBSS(bytestartsequence)toBSS 999 1001 ns Tx10bit t Averageover10,000samples 999.5 1000.5 ns Tx10bitAvg DelaydifferencebetweenriseandfallfromRxpintosample t – 2.5 ns RxAsymDelay pointinFlexRaycore t Jitterforthe80-MHzSampleClockgeneratedbythePLL – 0.5 ns jit(SCLK) 7.5.3 FlexRay Transfer Unit The FTU can transfer data between the input buffer (IBF) and output buffer (OBF) of the communication controllerandthesystemmemorywithoutCPUinteraction. BecausetheFlexRaymoduleisaccessedthroughtheFTU,theFTUmustbepoweredupbysettingbit23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay module register. For more information on the FTU, see the TMS570LS31x/TMS570LS21x 16/32-Bit RISC Flash MicrocontrollerTechnicalReferenceManual(SPNU499). 134 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.6 Controller Area Network (DCAN) The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotiveandindustrialfields)thatrequirereliableserialcommunicationormultiplexedwiring. 7.6.1 Features FeaturesoftheDCANmoduleinclude: • SupportsCANprotocolversion2.0partA,B • Bitratesupto1Mbps • TheCANkernelcanbeclockedbytheoscillatorforbaud-rategeneration. • 64mailboxesoneachDCAN • Individualidentifiermaskforeachmessageobject • ProgrammableFIFOmodeformessageobjects • Programmableloop-backmodesforself-testoperation • AutomaticbusonafterBus-Offstatebyaprogrammable32-bittimer • MessageRAMprotectedbyparity • DirectaccesstoMessageRAMduringtestmode • CANRx/TxpinsconfigurableasgeneralpurposeIOpins • MessageRAMAutoInitialization • DMAsupport For more information on the DCAN, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller TechnicalReferenceManual(SPNU499). 7.6.2 Electrical and Timing Specifications Table7-18.DynamicCharacteristicsfortheDCANxTXandRXPins PARAMETER MIN MAX UNIT t Delaytime,transmitshiftregistertoCANnTXpin(1) 15 ns d(CANnTX) t Delaytime,CANnRXpintoreceiveshiftregister 5 ns d(CANnRX) (1) Thesevaluesdonotincluderise/falltimesoftheoutputbuffer. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 135 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.7 Local Interconnect Network Interface (LIN) The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is anSCI.ThehardwarefeaturesoftheSCIareaugmentedtoachieveLINcompatibility. The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K- line. The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-master/multiple-slave with a message identification for multicast transmission between any network nodes. 7.7.1 LIN Features ThefollowingarefeaturesoftheLINmodule: • CompatibletoLIN1.3,2.0,and2.1protocols • MultibufferedreceiveandtransmitunitsDMAcapabilityforminimalCPUintervention • Identificationmasksformessagefiltering • AutomaticMasterHeaderGeneration – ProgrammableSynchBreakField – SynchField – IdentifierField • SlaveAutomaticSynchronization – Synchbreakdetection – Optionalbaudrateupdate – SynchronizationValidation • 231programmabletransmissionrateswith7fractionalbits • Errordetection • 2Interruptlineswithpriorityencoding 136 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.8 Serial Communication Interface (SCI) 7.8.1 Features • Standarduniversalasynchronousreceiver-transmitter(UART)communication • Supportsfull-orhalf-duplexoperation • Standardnonreturntozero(NRZ)format • Double-bufferedreceiveandtransmitfunctions • Configurableframeformatof3to13bitspercharacterbasedonthefollowing: – Datawordlengthprogrammablefrom1to8bits – Additionaladdressbitinaddress-bitmode – Parityprogrammableforzeroor1paritybit,oddorevenparity – Stopprogrammablefor1or2stopbits • Asynchronousorisosynchronouscommunicationmodes • Twomultiprocessorcommunicationformatsallowcommunicationbetweenmorethantwodevices. • SleepmodeisavailabletofreeCPUresourcesduringmultiprocessorcommunication. • The24-bitprogrammablebaudratesupports224differentbaudratesprovidehighaccuracybaudrateselection. • FourerrorflagsandfivestatusflagsprovidedetailedinformationregardingSCIevents. • CapabilitytouseDMAfortransmitandreceivedata. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 137 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.9 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between the TMS570 microcontroller and devices compliant with Philips Semiconductor I2C-bus specificationversion2.1andconnectedbyanI2C-bus™.ThismodulewillsupportanyslaveormasterI2C compatibledevice. 7.9.1 Features TheI2Chasthefollowingfeatures: • Compliance to the Philips I2C-bus specification, v2.1 (The I2C Specification, Philips document number 939839340011) – Bit/Byteformattransfer – 7-bitand10-bitdeviceaddressingmodes – Generalcall – STARTbyte – Multimastertransmitter/slavereceivermode – Multimasterreceiver/slavetransmittermode – Combinedmastertransmit/receiveandreceive/transmitmode – Transferratesof10kbpsupto400kbps(Phillipsfast-moderate) • Freedataformat • TwoDMAevents(transmitandreceive) • DMAeventenable/disablecapability • SeveninterruptsthatcanbeusedbytheCPU • Moduleenable/disablecapability • TheSDAandSCLareoptionallyconfigurableasgeneral-purposeI/O • Slewratecontroloftheoutputs • Open-draincontroloftheoutputs • Programmablepullup/pulldowncapabilityontheinputs • SupportsIgnoreNACKmode NOTE ThisI2Cmoduledoesnotsupport: • High-speed(HS)mode • C-buscompatibilitymode • The combined format in 10-bit address mode (the I2C module sends the slave address secondbyteeverytimeitsendstheslaveaddressfirstbyte) 138 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.9.2 I2C I/O Timing Specifications Table7-19.I2CSignals(SDAandSCL)SwitchingCharacteristics(1) STANDARDMODE FASTMODE PARAMETER UNIT MIN MAX MIN MAX Cycletime,InternalModuleclockforI2C, t 75.2 149 75.2 149 ns c(I2CCLK) prescaledfromVCLK f SCLClockfrequency 0 100 0 400 kHz (SCL) t Cycletime,SCL 10 2.5 µs c(SCL) Setuptime,SCLhighbeforeSDAlow(fora t 4.7 0.6 µs su(SCLH-SDAL) repeatedSTARTcondition) Holdtime,SCLlowafterSDAlow(forarepeated t 4 0.6 µs h(SCLL-SDAL) STARTcondition) t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) t Setuptime,SDAvalidbeforeSCLhigh 250 100 ns su(SDA-SCLH) t Holdtime,SDAvalidafterSCLlow(forI2Cbus 0 3.45(2) 0 0.9 µs h(SDA-SCLL) devices) Pulseduration,SDAhighbetweenSTOPand t 4.7 1.3 µs w(SDAH) STARTconditions Setuptime,SCLhighbeforeSDAhigh(forSTOP t 4.0 0.6 µs su(SCLH-SDAH) condition) t Pulseduration,spike(mustbesuppressed) 0 50 ns w(SP) C (3) Capacitiveloadforeachbusline 400 400 pF b (1) TheI2CpinsSDAandSCLdonotfeaturefail-safeI/Obuffers.Thesepinscouldpotentiallydrawcurrentwhenthedeviceispowered down. (2) Themaximumt forI2Cbusdeviceshasonlytobemetifthedevicedoesnotstretchthelowperiod(t )oftheSCL h(SDA-SCLL) w(SCLL) signal. (3) C =ThetotalcapacitanceofonebuslineinpF. b SDA tw(SDAH) tsu(SDA-SCLH) tw(SP) t w(SCLL) tr(SCL) tw(SCLH) tsu(SCLH-SDAH) SCL tc(SCL) t tf(SCL) th(SCLL-SDAL) h(SDA-SCLL) t t su(SCLH-SDAL) h(SCLL-SDAL) Stop Start Repeated Start Stop Figure7-9.I2CTimings Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 139 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com NOTE • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edgeofSCL. • The maximum t has only to be met if the device does not stretch the LOW h(SDA-SCLL) period(t )oftheSCLsignal. w(SCLL) • A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirementt ≥250nsmustthen be met. Thiswillautomatically be thecase if su(SDA-SCLH) the device does not stretch the LOW period of the SCL signal. If such a device does stretchtheLOWperiodoftheSCLsignal,itmustoutputthenextdatabittotheSDAline trmax+t . su(SDA-SCLH) • C = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall- b timesareallowed. 140 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.10 Multibuffered / Standard Serial Peripheral Interface The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. TypicalapplicationsfortheSPIincludeinterfacingtoexternalperipherals,suchasI/Os,memories,display drivers,andanalog-to-digitalconverters. 7.10.1 Features BothStandardandMibSPImoduleshavethefollowingfeatures: • 16-bitshiftregister • Receivebufferregister • 5-bitbaudclockgenerator • SPICLK can be internally-generated (master mode) or received from an external clock source (slave mode) • Eachwordtransferredcanhaveauniqueformat • SPII/Osnotusedinthecommunicationcanbeusedasdigitalinput/outputsignals Table7-20.MibSPI/SPIConfigurations MibSPIx/SPIx I/Os MibSPI1 MIBSPI1SIMO[1:0],MIBSPI1SOMI[1:0],MIBSPI1CLK,MIBSPI1nCS[5:0],MIBSPI1nENA MibSPI3 MIBSPI3SIMO,MIBSPI3SOMI,MIBSPI3CLK,MIBSPI3nCS[5:0],MIBSPI3nENA MibSPI5 MIBSPI5SIMO[3:0],MIBSPI5SOMI[3:0],MIBSPI5CLK,MIBSPI5nCS[3:0],MIBSPI5nENA SPI2 SPI2SIMO,SPI2SOMI,SPI2CLK,SPI2nCS[1:0],SPI2nENA SPI4 SPI4SIMO,SPI4SOMI,SPI4CLK,SPI4nCS[0],SPI4nENA 7.10.2 MibSPI Transmit and Receive RAM Organization The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAMcanbepartitionedintomultipletransfergroupwithvariablenumberofbufferseach. 7.10.3 MibSPI Transmit Trigger Events Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low levelataselectabletriggersource.Forexample,upto15triggersourcesareavailablewhichcanbeused by each transfer group. These trigger options are listed in Table 7-21 for MIBSPI1, Section 7.10.3.2 for MIBSPI3andSection7.10.3.3forMibSPI5. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 141 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.10.3.1 MIBSPI1EventTriggerHookup Table7-21.MIBSPI1EventTriggerHookup EVENT# TGxCTRLTRIGSRC[3:0] TRIGGER Disabled 0000 Notriggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternalTickcounter NOTE For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a triggerconditioncanbegeneratedeveniftheN2HET1signalisnotselectedtobeoutputon thepad. NOTE For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting theGIOx pin asan outputpinplus selecting thepin to be aGIOx pin, orbydriving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx fromtriggeringMibSPI1transfers;thereisnomultiplexingontheinputconnections. 7.10.3.2 MIBSPI3EventTriggerHookup Table7-22.MIBSPI3EventTriggerHookup EVENT# TGxCTRLTRIGSRC[3:0] TRIGGER Disabled 0000 Notriggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 HET[8] EVENT9 1010 N2HET1[10] 142 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table7-22.MIBSPI3EventTriggerHookup(continued) EVENT# TGxCTRLTRIGSRC[3:0] TRIGGER EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternalTickcounter NOTE For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a triggerconditioncanbegeneratedeveniftheN2HET1signalisnotselectedtobeoutputon thepad. NOTE For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting theGIOx pin asan outputpinplus selecting thepin to be aGIOx pin, orbydriving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx fromtriggeringMibSPI3transfers;thereisnomultiplexingontheinputconnections. 7.10.3.3 MIBSPI5EventTriggerHookup Table7-23.MIBSPI5EventTriggerHookup EVENT# TGxCTRLTRIGSRC[3:0] TRIGGER Disabled 0000 Notriggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternalTickcounter NOTE For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a triggerconditioncanbegeneratedeveniftheN2HET1signalisnotselectedtobeoutputon thepad. Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 143 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com NOTE For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selectingtheGIOxpinasanoutputpin+selectingthepintobeaGIOxpin,orbydrivingthe GIOxpinfromanexternaltriggersource.Ifthemuxcontrolmoduleisusedtoselectdifferent functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggeringMibSPI5transfers;thereisnomultiplexingontheinputconnections. 144 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications Table7-24.SPIMasterModeExternalTimingParameters(CLOCKPHASE=0,SPICLK=output,SPISIMO =output,andSPISOMI=input)(1)(2)(3) NO. PARAMETER MIN MAX UNIT 1 t Cycletime,SPICLK(4) 40 256t ns c(SPC)M c(VCLK) Pulseduration,SPICLKhigh(clock t 0.5t –t –3 0.5t +3 w(SPCH)M polarity=0) c(SPC)M r(SPC)M c(SPC)M 2(5) ns Pulseduration,SPICLKlow(clock t 0.5t –t –3 0.5t +3 w(SPCL)M polarity=1) c(SPC)M f(SPC)M c(SPC)M Pulseduration,SPICLKlow(clock t 0.5t –t –3 0.5t +3 w(SPCL)M polarity=0) c(SPC)M f(SPC)M c(SPC)M 3(5) ns Pulseduration,SPICLKhigh(clock t 0.5t –t –3 0.5t +3 w(SPCH)M polarity=1) c(SPC)M r(SPC)M c(SPC)M Delaytime,SPISIMOvalidbefore t 0.5t –6 d(SPCH-SIMO)M SPICLKlow(clockpolarity=0) c(SPC)M 4(5) ns Delaytime,SPISIMOvalidbefore t 0.5t –6 d(SPCL-SIMO)M SPICLKhigh(clockpolarity=1) c(SPC)M Validtime,SPISIMOdatavalidafter t 0.5t –t –4 v(SPCL-SIMO)M SPICLKlow(clockpolarity=0) c(SPC)M f(SPC) 5(5) ns Validtime,SPISIMOdatavalidafter t 0.5t –t –4 v(SPCH-SIMO)M SPICLKhigh(clockpolarity=1) c(SPC)M r(SPC) Setuptime,SPISOMIbeforeSPICLK t t +2.2 su(SOMI-SPCL)M low(clockpolarity=0) f(SPC) 6(5) ns Setuptime,SPISOMIbeforeSPICLK t t +2.2 su(SOMI-SPCH)M high(clockpolarity=1) r(SPC) Holdtime,SPISOMIdatavalidafter t 10 h(SPCL-SOMI)M SPICLKlow(clockpolarity=0) 7(5) ns Holdtime,SPISOMIdatavalidafter t 10 h(SPCH-SOMI)M SPICLKhigh(clockpolarity=1) C2TDELAY*t +2*t (C2TDELAY+2)*t - SetuptimeCSactive CSHOLD=0 -tc(VCLK)+t c(VC–LK7) t +t c(VC+L5K).5 f(SPICS) r(SPC) f(SPICS) r(SPC) untilSPICLKhigh (clockpolarity=0) CSHOLD=1 C2TDELAY*tc(VCLK)+3*tc(VCLK) (C2TDELAY+3)*tc(VCLK)- -t +t –7 t +t +5.5 8(6) t f(SPICS) r(SPC) f(SPICS) r(SPC) ns C2TDELAY C2TDELAY*t +2*t (C2TDELAY+2)*t - SetuptimeCSactive CSHOLD=0 -tc(VCLK)+t c(VC–LK7) t +t c(VC+L5K).5 f(SPICS) f(SPC) f(SPICS) f(SPC) untilSPICLKlow (clockpolarity=1) CSHOLD=1 C2TDELAY*tc(VCLK)+3*tc(VCLK) (C2TDELAY+3)*tc(VCLK)- -t +t –7 t +t +5.5 f(SPICS) f(SPC) f(SPICS) f(SPC) 0.5*t + 0.5*t + HoldtimeSPICLKlowuntilCSinactive c(SPC)M c(SPC)M T2CDELAY*t +t - T2CDELAY*t +t - (clockpolarity=0) c(VCLK) c(VCLK) c(VCLK) c(VCLK) t +t -7 t +t +11 9(6) t f(SPC) r(SPICS) f(SPC) r(SPICS) ns T2CDELAY 0.5*t + 0.5*t + HoldtimeSPICLKhighuntilCS c(SPC)M c(SPC)M T2CDELAY*t +t - T2CDELAY*t +t - inactive(clockpolarity=1) c(VCLK) c(VCLK) c(VCLK) c(VCLK) t +tr(SPICS)-7 t +t +11 r(SPC) r(SPC) r(SPICS) (C2TDELAY+1)*t - ns 10 t SPIENAnSamplepoint c(VCLK) (C2TDELAY+1)*t SPIENA t –29 c(VCLK) f(SPICS) SPIENAnSamplepointfromwriteto ns 11 t (C2TDELAY+2)*t SPIENAW buffer c(VCLK) (1) TheMASTERbit(SPIGCR1.0)issetandtheCLOCKPHASEbit(SPIFMTx.16)iscleared. (2) t =interfaceclockcycletime=1/f c(VCLK) (VCLK) (3) Forriseandfalltimings,seeTable5-7. (4) WhentheSPIisinMastermode,thefollowingmustbetrue: ForPSvaluesfrom1to255:t ≥(PS+1)t ≥40ns,wherePSistheprescalevaluesetintheSPIFMTx.[15:8]registerbits. c(SPC)M c(VCLK) ForPSvaluesof0:t =2t ≥40ns. c(SPC)M c(VCLK) TheexternalloadontheSPICLKpinmustbelessthan60pF. (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). (6) C2TDELAYandT2CDELAYisprogrammedintheSPIDELAYregister Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 145 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 66 7 SPISOMI Master In Data Must Be Valid Figure7-10.SPIMasterModeExternalTiming(CLOCKPHASE=0) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure7-11.SPIMasterModeChipSelectTiming(CLOCKPHASE=0) 146 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table7-25.SPIMasterModeExternalTimingParameters(CLOCKPHASE=1,SPICLK=output,SPISIMO =output,andSPISOMI=input)(1)(2)(3) NO. PARAMETER MIN MAX UNIT 1 t Cycletime,SPICLK (4) 40 256t ns c(SPC)M c(VCLK) Pulseduration,SPICLKhigh(clock t 0.5t –t –3 0.5t +3 w(SPCH)M polarity=0) c(SPC)M r(SPC)M c(SPC)M 2(5) ns Pulseduration,SPICLKlow(clock t 0.5t –t –3 0.5t +3 w(SPCL)M polarity=1) c(SPC)M f(SPC)M c(SPC)M Pulseduration,SPICLKlow(clock t 0.5t –t –3 0.5t +3 w(SPCL)M polarity=0) c(SPC)M f(SPC)M c(SPC)M 3(5) ns Pulseduration,SPICLKhigh(clock t 0.5t –t –3 0.5t +3 w(SPCH)M polarity=1) c(SPC)M r(SPC)M c(SPC)M Validtime,SPICLKhighafter t SPISIMOdatavalid(clockpolarity= 0.5t –6 v(SIMO-SPCH)M c(SPC)M 0) 4(5) ns Validtime,SPICLKlowafter t SPISIMOdatavalid(clockpolarity= 0.5t –6 v(SIMO-SPCL)M c(SPC)M 1) Validtime,SPISIMOdatavalidafter t 0.5t –t –4 v(SPCH-SIMO)M SPICLKhigh(clockpolarity=0) c(SPC)M r(SPC) 5(5) ns Validtime,SPISIMOdatavalidafter t 0.5t –t –4 v(SPCL-SIMO)M SPICLKlow(clockpolarity=1) c(SPC)M f(SPC) Setuptime,SPISOMIbefore t t +2.2 su(SOMI-SPCH)M SPICLKhigh(clockpolarity=0) r(SPC) 6(5) ns Setuptime,SPISOMIbefore t t +2.2 su(SOMI-SPCL)M SPICLKlow(clockpolarity=1) f(SPC) Validtime,SPISOMIdatavalidafter t 10 v(SPCH-SOMI)M SPICLKhigh(clockpolarity=0) 7(5) ns Validtime,SPISOMIdatavalidafter t 10 v(SPCL-SOMI)M SPICLKlow(clockpolarity=1) 0.5*t + 0.5*t + c(SPC)M c(SPC)M SetuptimeCS CSHOLD=0 (C2TDELAY+2)*tc(VCLK)- (C2TDELAY+2)*tc(VCLK)- activeuntilSPICLK tf(SPICS)+tr(SPC)–7 tf(SPICS)+tr(SPC)+5.5 high(clockpolarity= 0.5*t + 0.5*t + c(SPC)M c(SPC)M 0) CSHOLD=1 (C2TDELAY+3)*t - (C2TDELAY+3)*t - c(VCLK) c(VCLK) t +t –7 t +t +5.5 8(6) t f(SPICS) r(SPC) f(SPICS) r(SPC) ns C2TDELAY 0.5*t + 0.5*t + c(SPC)M c(SPC)M SetuptimeCS CSHOLD=0 (C2TDELAY+2)*tc(VCLK)- (C2TDELAY+2)*tc(VCLK)- activeuntilSPICLK tf(SPICS)+tf(SPC)–7 tf(SPICS)+tf(SPC)+5.5 low(clockpolarity= 0.5*t + 0.5*t + c(SPC)M c(SPC)M 1) CSHOLD=1 (C2TDELAY+3)*t - (C2TDELAY+3)*t - c(VCLK) c(VCLK) t +t –7 t +t +5.5 f(SPICS) f(SPC) f(SPICS) f(SPC) T2CDELAY*t + T2CDELAY*t + HoldtimeSPICLKlowuntilCS c(VCLK) c(VCLK) t -t +t - t -t +t + inactive(clockpolarity=0) c(VCLK) f(SPC) r(SPICS) c(VCLK) f(SPC) r(SPICS) 7 11 9(6) t ns T2CDELAY T2CDELAY*t + T2CDELAY*t + HoldtimeSPICLKhighuntilCS c(VCLK) c(VCLK) t -t +t - t -t +t + inactive(clockpolarity=1) c(VCLK) r(SPC) r(SPICS) c(VCLK) r(SPC) r(SPICS) 7 11 (C2TDELAY+1)*t - ns 10 t SPIENAnSamplePoint c(VCLK) (C2TDELAY+1)*t SPIENA t –29 c(VCLK) f(SPICS) SPIENAnSamplepointfromwriteto ns 11 t (C2TDELAY+2)*t SPIENAW buffer c(VCLK) (1) TheMASTERbit(SPIGCR1.0)issetandtheCLOCKPHASEbit(SPIFMTx.16)isset. (2) t =interfaceclockcycletime=1/f c(VCLK) (VCLK) (3) Forriseandfalltimings,seetheTable5-7. (4) WhentheSPIisinMastermode,thefollowingmustbetrue: ForPSvaluesfrom1to255:t ≥(PS+1)t ≥40ns,wherePSistheprescalevaluesetintheSPIFMTx.[15:8]registerbits. c(SPC)M c(VCLK) ForPSvaluesof0:t =2t ≥40ns. c(SPC)M c(VCLK) TheexternalloadontheSPICLKpinmustbelessthan60pF. (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). (6) C2TDELAYandT2CDELAYisprogrammedintheSPIDELAYregister Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 147 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid Data Valid 6 7 Master In Data SPISOMI Must Be Valid Figure7-12.SPIMasterModeExternalTiming(CLOCKPHASE=1) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure7-13.SPIMasterModeChipSelectTiming(CLOCKPHASE=1) 148 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.10.5 SPI Slave Mode I/O Timings Table7-26.SPISlaveModeExternalTimingParameters(CLOCKPHASE=0,SPICLK=input,SPISIMO= input,andSPISOMI=output)(1)(2)(3)(4) NO. PARAMETER MIN MAX UNIT 1 t Cycletime,SPICLK(5) 40 ns c(SPC)S 2(6) t Pulseduration,SPICLKhigh(clockpolarity=0) 14 w(SPCH)S ns t Pulseduration,SPICLKlow(clockpolarity=1) 14 w(SPCL)S 3(6) t Pulseduration,SPICLKlow(clockpolarity=0) 14 w(SPCL)S ns t Pulseduration,SPICLKhigh(clockpolarity=1) 14 w(SPCH)S 4(6) Delaytime,SPISOMIvalidafterSPICLKhigh(clock t t +20 d(SPCH-SOMI)S polarity=0) rf(SOMI) ns Delaytime,SPISOMIvalidafterSPICLKlow(clockpolarity t t +20 d(SPCL-SOMI)S =1) rf(SOMI) 5(6) Holdtime,SPISOMIdatavalidafterSPICLKhigh(clock t 2 h(SPCH-SOMI)S polarity=0) ns Holdtime,SPISOMIdatavalidafterSPICLKlow(clock t 2 h(SPCL-SOMI)S polarity=1) 6(6) Setuptime,SPISIMObeforeSPICLKlow(clockpolarity= t 4 su(SIMO-SPCL)S 0) ns Setuptime,SPISIMObeforeSPICLKhigh(clockpolarity= t 4 su(SIMO-SPCH)S 1) Holdtime,SPISIMOdatavalidafterSPICLKlow(clock t 2 h(SPCL-SIMO)S polarity=0) 7(6) ns Holdtime,SPISIMOdatavalidafterSPICLKhigh(clock t 2 h(SPCH-SIMO)S polarity=1) Delaytime,SPIENAnhighafterlastSPICLKlow(clock 2.5t +t + t 1.5t c(VCLK) r(ENAn) d(SPCL-SENAH)S polarity=0) c(VCLK) 22 8 ns Delaytime,SPIENAnhighafterlastSPICLKhigh(clock 2.5t +t + t 1.5t c(VCLK) r(ENAn) d(SPCH-SENAH)S polarity=1) c(VCLK) 22 Delaytime,SPIENAnlowafterSPICSnlow(ifnewdata 9 t t t +t +27 ns d(SCSL-SENAL)S hasbeenwrittentotheSPIbuffer) f(ENAn) c(VCLK) f(ENAn) (1) TheMASTERbit(SPIGCR1.0)isclearedandtheCLOCKPHASEbit(SPIFMTx.16)iscleared. (2) IftheSPIisinslavemode,thefollowingmustbetrue:t ≥(PS+1)t ,wherePS=prescalevaluesetinSPIFMTx.[15:8]. c(SPC)S c(VCLK) (3) Forriseandfalltimings,seeTable5-7. (4) t =interfaceclockcycletime=1/f c(VCLK) (VCLK) (5) WhentheSPIisinSlavemode,thefollowingmustbetrue: ForPSvaluesfrom1to255:t ≥(PS+1)t ≥40ns,wherePSistheprescalevaluesetintheSPIFMTx.[15:8]registerbits. c(SPC)S c(VCLK) ForPSvaluesof0:t =2t ≥40ns. c(SPC)S c(VCLK) (6) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 149 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI SPISOMI Data Is Valid 666 7 SPISIMO SPISIMO Data Must Be Valid Figure7-14.SPISlaveModeExternalTiming(CLOCKPHASE=0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn Figure7-15.SPISlaveModeEnableTiming(CLOCKPHASE=0) 150 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Table7-27.SPISlaveModeExternalTimingParameters(CLOCKPHASE=1,SPICLK=input,SPISIMO= input,andSPISOMI=output)(1)(2)(3)(4) NO. PARAMETER MIN MAX UNIT 1 t Cycletime,SPICLK(5) 40 ns c(SPC)S t Pulseduration,SPICLKhigh(clockpolarity=0) 14 2(6) w(SPCH)S ns t Pulseduration,SPICLKlow(clockpolarity=1) 14 w(SPCL)S t Pulseduration,SPICLKlow(clockpolarity=0) 14 3(6) w(SPCL)S ns t Pulseduration,SPICLKhigh(clockpolarity=1) 14 w(SPCH)S Dealytime,SPISOMIdatavalidafterSPICLKlow t t +20 d(SOMI-SPCL)S (clockpolarity=0) rf(SOMI) 4(6) ns Delaytime,SPISOMIdatavalidafterSPICLKhigh t t +20 d(SOMI-SPCH)S (clockpolarity=1) rf(SOMI) Holdtime,SPISOMIdatavalidafterSPICLKhigh t 2 h(SPCL-SOMI)S (clockpolarity=0) 5(6) ns Holdtime,SPISOMIdatavalidafterSPICLKlow(clock t 2 h(SPCH-SOMI)S polarity=1) Setuptime,SPISIMObeforeSPICLKhigh(clock t 4 su(SIMO-SPCH)S polarity=0) 6(6) ns Setuptime,SPISIMObeforeSPICLKlow(clockpolarity t 4 su(SIMO-SPCL)S =1) Hightime,SPISIMOdatavalidafterSPICLKhigh t 2 v(SPCH-SIMO)S (clockpolarity=0) 7(6) ns Hightime,SPISIMOdatavalidafterSPICLKlow(clock t 2 v(SPCL-SIMO)S polarity=1) Delaytime,SPIENAnhighafterlastSPICLKhigh t 1.5t 2.5t +t +22 d(SPCH-SENAH)S (clockpolarity=0) c(VCLK) c(VCLK) r(ENAn) 8 ns Delaytime,SPIENAnhighafterlastSPICLKlow(clock t 1.5t 2.5t +t +22 d(SPCL-SENAH)S polarity=1) c(VCLK) c(VCLK) r(ENAn) Delaytime,SPIENAnlowafterSPICSnlow(ifnewdata 9 t t t +t +27 ns d(SCSL-SENAL)S hasbeenwrittentotheSPIbuffer) f(ENAn) c(VCLK) f(ENAn) Delaytime,SOMIvalidafterSPICSnlow(ifnewdata 10 t t 2t +t +28 ns d(SCSL-SOMI)S hasbeenwrittentotheSPIbuffer) c(VCLK) c(VCLK) rf(SOMI) (1) TheMASTERbit(SPIGCR1.0)isclearedandtheCLOCKPHASEbit(SPIFMTx.16)isset. (2) IftheSPIisinslavemode,thefollowingmustbetrue:tc(SPC)S≤(PS+1)tc(VCLK),wherePS=prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseandfalltimings,seeTable5-7. (4) t =interfaceclockcycletime=1/f c(VCLK) (VCLK) (5) WhentheSPIisinSlavemode,thefollowingmustbetrue: ForPSvaluesfrom1to255:t ≥(PS+1)t ≥40ns,wherePSistheprescalevaluesetintheSPIFMTx.[15:8]registerbits. c(SPC)S c(VCLK) ForPSvaluesof0:t =2t ≥40ns. c(SPC)S c(VCLK) (6) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPIFMTx.17). Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 151 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI SPISOMI Data Is Valid 666 7 SPISIMO SPISIMO Data Must Be Valid Figure7-16.SPISlaveModeExternalTiming(CLOCKPHASE=1) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out Data Is Valid Figure7-17.SPISlaveModeEnableTiming(CLOCKPHASE=1) 152 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.11 Ethernet Media Access Controller The Ethernet Media Access Controller (EMAC) provides an efficient interface between the CPU and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps ineitherhalf-orfull-duplexmode,withhardwareflowcontrolandqualityofservice(QoS)support. The EMAC controls the flow of packet data from the TMS570 device to the PHY. The MDIO module controlsPHYconfigurationandstatusmonitoring. Both the EMAC and the MDIO modules interface to the TMS570 device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplexandcontrolinterrupts. 7.11.1 Ethernet MII Electrical and Timing Specifications 1 2 MII_RX_CLK MII_RXD[3:0] MII_RX_DV VALID MII_RX_ER Figure7-18.MIIReceiveTiming Table7-28.TimingRequirementsforEMACMIIReceive NO. MIN MAX UNIT t Setuptime,MII_RXD[3:0]beforeMII_RX_CLKrisingedge 8 ns su(MIIRXD-MIIRXCLKH) 1 t Setuptime,MII_RX_DVbeforeMII_RX_CLKrisingedge 8 ns su(MIIRXDV-MIIRXCLKH) t Setuptime,MII_RX_ERbeforeMII_RX_CLKrisingedge 8 ns su(MIIRXER-MIIRXCLKH) t Holdtime,MII_RXD[3:0]validafterMII_RX_CLKrisingedge 8 ns h(MIIRXCLKH-MIIRXD) 2 t Holdtime,MII_RX_DVvalidafterMII_RX_CLKrisingedge 8 ns h(MIIRXCLKH-MIIRXDV) t Holdtime,MII_RX_ERvalidafterMII_RX_CLKrisingedge 8 ns h(MIIRXCLKH-MIIRXER) Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 153 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 1 MII_TX_CLK MII_TXD[3:0] VALID MII_TXEN Figure7-19.MIITransmitTiming Table7-29.SwitchingCharacteristicsOverRecommendedOperatingConditionsforEMACMIITransmit NO. PARAMETER MIN MAX UNIT t Delaytime,MII_TX_CLKrisingedgetoMII_TXD[3:0]valid 5 25 ns d(MIIRXCLKH-MIITXD) 1 t Delaytime,MII_TX_CLKrisingedgetoMII_TXENvalid 5 25 ns d(MIIRXCLKH-MIITXEN) 154 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 7.11.2 Ethernet RMII Electrical and Timing Specifications 1 2 3 RMII_REFCLK 5 5 RMII_TXEN 4 RMII_TXD[1:0] 6 7 RMII_RXD[1:0] 8 9 10 RMII_CRS_DV 11 RMII_RX_ER Figure7-20.RMIITimingDiagram Table7-30.TimingRequirementsforEMACRMIIReceiveandRMII_REFCLK NO. MIN NOM MAX UNIT 1 t Cycletime,RMII_REFCLK 20 ns c(REFCLK) 2 t Pulsewidth,RMII_REFCLKhigh 7 13 ns w(REFCLKH) 3 t Pulsewidth,RMII_REFCLKlow 7 13 ns w(REFCLKL) 6 t Inputsetuptime,RMII_RXD[1:0]validbeforeRMII_REFCLKhigh 4 ns su(RXD-REFCLK) 7 t Inputholdtime,RMII_RXD[1:0]validafterRMII_REFCLKhigh 2 ns h(REFCLK-RXD) 8 t Inputsetuptime,RMII_CRS_DVvalidbeforeRMII_REFCLKhigh 4 ns su(CRSDV-REFCLK) 9 t Inputholdtime,RMII_CRS_DVvalidafterRMII_REFCLKhigh 2 ns h(REFCLK-CRSDV) 10 t Inputsetuptime,RMII_RX_ERvalidbeforeRMII_REFCLKhigh 4 ns su(RXER-REFCLK) 11 t Inputholdtime,RMII_RX_ERvalidafterRMII_REFCLKhigh 2 ns h(REFCLK-RXER) Table7-31.SwitchingCharacteristicsOverRecommendedOperatingConditionsforEMACRMIITransmit NO. PARAMETER MIN MAX UNIT 4 t Outputdelaytime,RMII_REFCLKhightoRMII_TXD[1:0]valid 2 ns d(REFCLK-TXD) 5 t Outputdelaytime,RMII_REFCLKhightoRMII_TXENvalid 2 ns d(REFCLK-TXEN) Copyright©2012–2015,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 155 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 7.11.3 Management Data Input/Output (MDIO) Electrical and Timing Specifications 1 3 3 MDCLK 4 5 MDIO (input) Figure7-21.MDIOInputTiming Table7-32.TimingRequirementsforMDIOInput NO. MIN MAX UNIT 1 t Cycletime,MDCLK 400 - ns c(MDCLK) 2 t Pulseduration,MDCLKhighorlow 180 - ns w(MDCLK) 3 t Transitiontime,MDCLK - 5 ns t(MDCLK) 4 t Setuptime,MDIOdatainputvalidbefore 33(1) - ns su(MDIO-MDCLKH) MDCLKHigh Holdtime,MDIOdatainputvalidafter ns 5 t 10 - h(MDCLKH-MDIO) MDCLKHigh (1) ThisisadiscrepancytoIEEE802.3,butiscompatiblewithmanyPHYdevices. 1 MDCLK 7 MDIO (output) Figure7-22.MDIOOutputTiming Table7-33.MDIOOutputTimingRequirements NO. MIN MAX UNIT 1 tc(MDCLK) Cycletime,MDCLK 400 – ns Delaytime,MDCLKlowtoMDIOdataoutput 7 td(MDCLKL-MDIO) –7 100 ns valid 156 PeripheralInformationandElectricalSpecifications Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 8 Device and Documentation Support 8.1 Device Support 8.1.1 Development Support Texas Instruments (TI) offers an extensive line of development tools for the TMS570LSxRM48Lx family of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations,andfullyintegrateanddebugsoftwareandhardwaremodules. Thefollowingproductssupportdevelopment: SoftwareDevelopmentTools • CodeComposerStudio™(CCS)IntegratedDevelopmentEnvironment(IDE)– – C/C++Compiler – Codegenerationtools – Assembler/Linker – FPUOptimizedLibraries • Applicationalgorithms • Sampleapplicationscode HardwareDevelopmentTools • Developmentandevaluationboards • JTAG-basedemulators-XDS510™class,XDS560™emulator,XDS100v2,XDS110,XDS200 • Flashprogrammingtools Foracompletelistingofdevelopment-supporttools,visittheTexasInstrumentswebsiteatwww.ti.com. 8.1.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (for example, TMS570LS3137). These prefixes represent evolutionary stages of product development from engineering prototypes(TMX)throughfullyqualifiedproductiondevices(TMS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthasnotcompletedqualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. TMXandTMPdevicesareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devices have been characterized fully, and the quality and reliability of the device have been demonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production systembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobeused. Figure8-1showsthenumberingandsymbolnomenclaturefortheTMS570LS3137. For additional information on the device nomenclature markings, see the device-specific silicon errata documentlistedinSection8.2.1,RelatedDocumentationfromTexasInstruments. Copyright©2012–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 157 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com Full Part # TMS 570 LS 31 3 7 D ZWT Q Q1 R Orderable Part # TMS 570 31 3 7 D ZWT Q Q1 R Prefix:TM TMS = Fully Qualified TMP= Prototype TMX = Samples CoreTechnology: 570 = Cortex-R4F Architecture: LS = Dual CPUs in Lockstep (not included in orderable part #) Flash Memory Size: 31 = 3MB RAM MemorySize: 3 = 256KB Peripheral Set: 7 = FlexRay, Ethernet Die Revision: Blank = Initial Die A= 1st Die Revision B = 2nd Die Revision C = 3rd Die Revision D = 4th Die Revision PackageType: ZWT= 337-BGAPackage PGE = 144-Pin Package Temperature Range: Q =–40oC to 125oC Quality Designator: Q1 =Automotive Shipping Options: R =Tape and Reel Figure8-1. TMS570LS3137 DeviceNumberingConventions 158 DeviceandDocumentationSupport Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 8.2 Documentation Support 8.2.1 Related Documentation from Texas Instruments Thefollowingdocumentsdescribethe TMS570LS3137microcontroller.. SPNU499 TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheralandsubsysteminthedevice. SPNZ195 TMS570LS31x/21x Microcontroller, Silicon Revision C, Silicon Errata describes the usage notes andknownexceptionstothefunctionalspecificationsforthedevicesiliconrevisionC. SPNZ222 TMS570LS31x/21x Microcontroller, Silicon Revision D, Silicon Errata describes the usage notes andknownexceptionstothefunctionalspecificationsforthedevicesiliconrevisionD. SPNA207 Calculating Equivalent Power-on-Hours for Hercules™ Safety MCUs details how to use the spreadsheettocalculatetheagingeffectoftemperatureonTexasInstrumentsHerculesSafetyMCUs. 8.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI'sTermsofUse. TIE2E™OnlineCommunity TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problemswithfellowengineers. TIEmbeddedProcessorsWiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of generalknowledgeaboutthehardwareandsoftwaresurroundingthesedevices. 8.4 Trademarks CodeComposerStudio,XDS510,XDS560,E2EaretrademarksofTexasInstruments. CoreSightisatrademarkofARMLimited. ARM,CortexareregisteredtrademarksofARMLimited(oritssubsidiaries)intheEUand/orelsewhere. Allrightsreserved. I2C-busisatrademarkofNXPSemiconductorsN.V. Allothertrademarksarethepropertyoftheirrespectiveowners. 8.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 8.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2012–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 159 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 8.7 Device Identification Code Register The device identification code register identifies several aspects of the device including the silicon version. ThedetailsofthedeviceidentificationcoderegisterareshowninTable8-1.Thedeviceidentificationcode registervalueforthisdeviceis: • RevA=0x802AAD05 • RevB=0x802AAD15 • RevC=0x802AAD1D • RevD=0x802AAD25 Figure8-2.DeviceIDBitAllocationRegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUEID TECH R-1 R-00000000010101 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TECH I/O PERIPH FLASHECC RAM VERSION 1 0 1 VOLT PARITY ECC AGE R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table8-1.DeviceIDBitAllocationRegisterFieldDescriptions BIT FIELD VALUE DESCRIPTION 31 CP15 Indicatesthepresenceofcoprocessor15 1 CP15present 30-17 UNIQUEID 10101 Siliconversion(revision)bits. Thisbitfieldholdsauniquenumberforadedicateddeviceconfiguration(die). 16-13 TECH Processtechnologyonwhichthedeviceismanufactured. 0101 F021 12 I/OVOLTAGE I/Ovoltageofthedevice. 0 I/Oare3.3V 11 PERIPHERAL PeripheralParity PARITY 1 Parityonperipheralmemories 10-9 FLASHECC FlashECC 10 ProgrammemorywithECC 8 RAMECC IndicatesifRAMmemoryECCispresent. 1 ECCimplemented 7-3 REVISION Revisionofthedevice. 2-0 101 TheplatformfamilyIDisalways0b101 160 DeviceandDocumentationSupport Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 8.8 Die Identification Registers The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit die ID with the informationasshowninTable8-2. Table8-2.Die-IDRegisters ITEM NUMBEROFBITS BITLOCATION XCoord.onWafer 12 0xFFFFFF7C[11:0] YCoord.onWafer 12 0xFFFFFF7C[23:12] Wafer# 8 0xFFFFFF7C[31:24] Lot# 24 0xFFFFFF80[23:0] Reserved 8 0xFFFFFF80[31:24] 8.9 Module Certifications Thefollowingcommunicationsmoduleshavereceivedcertificationofadherencetoastandard. Copyright©2012–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 161 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 8.9.1 FlexRay™ Certifications Figure8-3.FlexRayCertificationforZWTPackage 162 DeviceandDocumentationSupport Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 Figure8-4.FlexRayCertificationforPGEPackage Copyright©2012–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 163 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 8.9.2 DCAN Certification Figure8-5.DCANCertification 164 DeviceandDocumentationSupport Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 8.9.3 LIN Certification 8.9.3.1 LINMasterMode Figure8-6.LINCertification-MasterMode Copyright©2012–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 165 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 8.9.3.2 LINSlaveMode-FixedBaudRate Figure8-7.LINCertification-SlaveMode-FixedBaudRate 166 DeviceandDocumentationSupport Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

TMS570LS3137 www.ti.com SPNS162C–APRIL2012–REVISEDAPRIL2015 8.9.3.3 LINSlaveMode-AdaptiveBaudRate Figure8-8.LINCertification-SlaveMode-AdaptiveBaudRate Copyright©2012–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 167 SubmitDocumentationFeedback

TMS570LS3137 SPNS162C–APRIL2012–REVISEDAPRIL2015 www.ti.com 9 Mechanical Packaging and Orderable Information 9.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 168 MechanicalPackagingandOrderableInformation Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS5703137CGWTMEP ACTIVE NFBGA GWT 337 90 TBD SNPB Level-3-220C-168 HR -55 to 125 TMS570 LS3137CGWTMEP TMS5703137CGWTQEP ACTIVE NFBGA GWT 337 90 TBD SNPB Level-3-220C-168 HR -40 to 125 TMS570 LS3137CGWTQEP TMS5703137DPGEQQ1 ACTIVE LQFP PGE 144 60 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS & no Sb/Br) 3137DPGEQQ1 TMS5703137DZWTQQ1 ACTIVE NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS570LS & no Sb/Br) 3137DZWTQQ1 V62/13629-01XE ACTIVE NFBGA GWT 337 90 TBD SNPB Level-3-220C-168 HR -40 to 125 TMS570 LS3137CGWTQEP V62/13629-02XE ACTIVE NFBGA GWT 337 90 TBD SNPB Level-3-220C-168 HR -55 to 125 TMS570 LS3137CGWTMEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS570LS3137, TMS570LS3137-EP : •Catalog: TMS570LS3137 •Enhanced Product: TMS570LS3137-EP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE OUTLINE ZWT0337A NFBGA - 1.4 mm max height SCALE 0.950 PLASTIC BALL GRID ARRAY B 16.1 A 15.9 BALL A1 CORNER 16.1 15.9 1.4 MAX C SEATING PLANE 0.45 0.35 TYP BALL TYP 0.12 C 14.4 TYP SYMM (0.8) TYP W V U (0.8) TYP T R P N M 14.4 L SYMM TYP K J H G 0.55 337X F 0.45 E 0.15 C A B D 0.05 C C B A 0.8 TYP 1 2 3 4 5 6 7 8 9 10 111213141516171819 0.8 TYP BALL A1 CORNER 4223381/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT ZWT0337A NFBGA - 1.4 mm max height PLASTIC BALL GRID ARRAY (0.8) TYP 337X ( 0.4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B (0.8) TYP C D E F G H J SYMM K L M N P R T U V W SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:7X ( 0.4) 0.05 MAX 0.05 MIN METAL UNDER SOLDER MASK METAL EXPOSED METAL ( 0.4) SOLDER MASK EXPOSED METAL SOLDER MASK OPENING OPENING NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4223381/A 02/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com

EXAMPLE STENCIL DESIGN ZWT0337A NFBGA - 1.4 mm max height PLASTIC BALL GRID ARRAY ( 0.4) TYP (0.8) TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B (0.8) TYP C D E F G H J SYMM K L M N P R T U V W SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:7X 4223381/A 02/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,08 M 0,17 0,50 144 37 0,13 NOM 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 0,25 22,20 0,05 MIN 0°–7° SQ 21,80 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040147/C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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