Product Order Technical Tools & Support & Folder Now Documents Software Community TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors 1 Device Overview 1.1 Features 1 • High-performancestaticCMOStechnology • Enhancedcontrolperipherals – 100MHz(10-nscycletime) – Upto16PWMoutputs – 60MHz(16.67-nscycletime) – Upto6HRPWMoutputswith150-psMEP – Low-power(1.8-Vcore,3.3-VI/O)design resolution • JTAGboundaryscansupport – Uptofourcaptureinputs – IEEEStandard1149.1-1990StandardTest – Uptotwoquadratureencoderinterfaces AccessPortandBoundaryScanArchitecture – Uptosix32-bit/six16-bittimers • High-performance32-bitCPU(TMS320C28x) • Serialportperipherals – 16× 16and32×32MACoperations – Upto4SPImodules – 16× 16dualMAC – Upto2SCI(UART)modules – Harvardbusarchitecture – Upto2CANmodules – Atomicoperations – OneInter-Integrated-Circuit(I2C)bus – Fastinterruptresponseandprocessing • 12-bitADC, 16channels – Unifiedmemoryprogrammingmodel – 2 ×8channelinputmultiplexer – Code-efficient(inC/C++andAssembly) – Twosample-and-hold • On-chipmemory – Single/simultaneousconversions – F2809:128K ×16flash,18K × 16SARAM – Fastconversionrate: F2808:64K ×16flash,18K × 16SARAM 80ns-12.5MSPS(F2809only) F2806:32K ×16flash,10K × 16SARAM 160ns-6.25MSPS(280x) F2802:32K ×16flash,6K ×16SARAM 267ns-3.75MSPS(F2801x) F2801:16K ×16flash,6K ×16SARAM – Internalorexternalreference F2801x:16K ×16flash,6K ×16SARAM • Upto35individuallyprogrammable,multiplexed – 1K× 16OTPROM(flashdevicesonly) GPIOpinswithinputfiltering – C2802:32K× 16ROM,6K× 16SARAM • Advancedemulationfeatures C2801:16K×16ROM,6K ×16SARAM – Analysisandbreakpointfunctions • BootROM(4K× 16) – Real-timedebugviahardware – Withsoftwarebootmodes(viaSCI,SPI,CAN, • Developmentsupportincludes I2C,andparallelI/O) – ANSIC/C++compiler/assembler/linker – Standardmathtables – CodeComposerStudio™IDE • Clockandsystemcontrol – SYS/BIOS – On-chiposcillator – Digitalmotorcontrolanddigitalpowersoftware – Watchdogtimermodule libraries • AnyGPIOApincanbeconnectedtooneofthe • Low-powermodesandpowersavings threeexternalcoreinterrupts – IDLE,STANDBY,HALTmodessupported • PeripheralInterruptExpansion(PIE)blockthat – Disableindividualperipheralclocks supportsall43peripheralinterrupts • Packageoptions • Endianness:Littleendian – Thinquadflatpack(PZ) • 128-bitsecuritykey/lock – MicroStarBGA™(GGM,ZGM) – Protectsflash/OTP/L0/L1blocks • Temperatureoptions – Preventsfirmwarereverse-engineering – A: –40°Cto85°C(PZ,GGM,ZGM) • Three32-bitCPUtimers – S: –40°Cto125°C(PZ,GGM,ZGM) – Q: –40°Cto125°C(PZ) (AEC-Q100qualificationforautomotive applications) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 1.2 Applications • Motordriveandcontrol • Digitalpower 1.3 Description The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015, TMS320F28016, TMS320C2802, and TMS320C2801 devices, members of the TMS320C28x DSP generation,arehighlyintegrated,high-performancesolutionsfordemandingcontrolapplications. Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS320F28016 are abbreviated as F2809, F2808, F2806, F2802, F2801, C2802, C2801, F28015, and F28016, respectively. TMS320F28015 and TMS320F28016 are abbreviated as F2801x. Device Comparison (100-MHz Devices) and Device Comparison(60-MHzDevices)provideasummaryoffeaturesforeachdevice. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE TMS320F2809ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2808ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2806ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2802ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2801ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320C2802ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320C2801ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F28016ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F28015ZGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2809GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2808GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2806GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2802GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2801GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320C2802GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320C2801GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F28016GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F28015GGM BGAMicroStar(100) 10.0mm×10.0mm TMS320F2809PZ LQFP(100) 14.0mm×14.0mm TMS320F2808PZ LQFP(100) 14.0mm×14.0mm TMS320F2806PZ LQFP(100) 14.0mm×14.0mm TMS320F2802PZ LQFP(100) 14.0mm×14.0mm TMS320F2801PZ LQFP(100) 14.0mm×14.0mm TMS320C2802PZ LQFP(100) 14.0mm×14.0mm TMS320C2801PZ LQFP(100) 14.0mm×14.0mm TMS320F28016PZ LQFP(100) 14.0mm×14.0mm TMS320F28015PZ LQFP(100) 14.0mm×14.0mm (1) Formoreinformationonthesedevices,seeMechanical,Packaging,andOrderableInformation. 2 DeviceOverview Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 1.4 Functional Block Diagram Memory Bus TINT0 Real-Time JTAG 32-bit CPU TIMER 0 (TDI, TDO,TRST, TCK, TINT1 7 TMS, EMU0, EMU1) 32-bit CPU TIMER 1 TINT2 32-bit CPU TIMER 2 INT14 M0 SARAM 1K x 16 PIE (A) M1 SARAM (96 Interrupts) INT[12:1] 1K x 16 NMI, INT13 L0 SARAM External Interrupt 4K x 16 Control 32 (0-wait) 4 (B) SCI-A/B FIFO L1 SARAM 4K x 16 16 (0-wait) SPI-A/B/C/D FIFO (C) 2 H0 SARAM I2C-A FIFO 8K x 16 4 (0-wait) eCAN-A/B (32 mbox) X 8 U eQEP1/2 GPIOs M (35) O PI 4 eCAP1/2/3/4 C28x CPU ROM G (4 32-bit Timers) (100 MHz) 32K x 16 (C2802) 16K x 16 (C2801) 12 ePWM1/2/3/4/5/6 6 (12 PWM Outputs, 6 Trip Zones, 6 16-bit Timers) FLASH 128K x 16 (F2809) 64K x 16 (F2808) 32K x 16 (F2806) 32 SYSCLKOUT 32K x 16 (F2802) 16K x 16 (F2801) 16K x 16 (F2801x) System Control RS XCLKOUT XRS (Oscillator, PLL, XCLKIN Peripheral Clocking, CLKIN Low-Power Modes, X1 Watchdog) OTP(D) X2 1K x 16 ADCSOCA/B SOCA/B Boot ROM 4K x 16 12-BitADC (1-wait state) 16 Channels Protected by the code-security module. Peripheral Bus Copyright © 2016,Texas Instruments Incorporated A. 43ofthepossible96interruptsareusedonthedevices. B. NotavailableinF2802,F2801,C2802,andC2801. C. NotavailableinF2806,F2802,F2801,C2802,andC2801. D. The1Kx16OTPhasbeenreplacedwith1Kx16ROMforC280xdevices. Figure1-1.FunctionalBlockDiagram Copyright©2003–2019,TexasInstrumentsIncorporated DeviceOverview 3 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table of Contents 1 DeviceOverview......................................... 1 5.13 ThermalDesignConsiderations .................... 33 .............................................. ............... 1.1 Features 1 5.14 TimingandSwitchingCharacteristics 34 ........................................... ................ 1.2 Applications 2 5.15 On-ChipAnalog-to-DigitalConverter 60 ............................................ .. 1.3 Description 2 5.16 MigratingFromF280xDevicestoC280xDevices 66 ............................ .......................... 1.4 FunctionalBlockDiagram 3 5.17 ROMTiming(C280xonly) 67 2 Revision History......................................... 5 6 DetailedDescription................................... 68 3 DeviceComparison ..................................... 7 6.1 BriefDescriptions.................................... 68 ..................................... .......................................... 3.1 RelatedProducts 9 6.2 Peripherals 75 4 TerminalConfigurationandFunctions............ 10 6.3 MemoryMaps...................................... 109 ........................................ ....................................... 4.1 PinDiagrams 10 6.4 RegisterMap 117 .................................. ........................................... 4.2 SignalDescriptions 15 6.5 Interrupts 120 5 Specifications........................................... 21 6.6 SystemControl..................................... 125 ........................ .......................... 5.1 AbsoluteMaximumRatings 21 6.7 Low-PowerModesBlock 131 5.2 ESDRatings–Automotive ......................... 22 7 Applications,Implementation,andLayout...... 132 ......................... .................... 5.3 ESDRatings–Commercial 22 7.1 TIDesignorReferenceDesign 132 5.4 RecommendedOperatingConditions............... 22 8 DeviceandDocumentationSupport.............. 133 ..................... ..................................... 5.5 PowerConsumptionSummary 23 8.1 Getting Started 133 5.6 ElectricalCharacteristics ........................... 30 8.2 DeviceandDevelopmentSupportTool ...................................... 5.7 ThermalResistanceCharacteristicsforF280x100- Nomenclature 134 .................................. ................................ BallGGMPackage 31 8.3 ToolsandSoftware 136 5.8 ThermalResistanceCharacteristicsforF280x100- 8.4 DocumentationSupport............................ 137 ..................................... PinPZPackage 31 ...................................... 8.5 RelatedLinks 139 5.9 ThermalResistanceCharacteristicsforC280x100- ............................. .................................. 8.6 CommunityResources 139 BallGGMPackage 32 ........................................ 8.7 Trademarks 139 5.10 ThermalResistanceCharacteristicsforC280x100- PinPZPackage..................................... 32 8.8 ElectrostaticDischargeCaution................... 140 ............................................ 5.11 ThermalResistanceCharacteristicsforF2809100- 8.9 Glossary 140 .................................. BallGGMPackage 33 9 Mechanical,Packaging,andOrderable 5.12 ThermalResistanceCharacteristicsforF2809100- Information............................................. 141 PinPZPackage..................................... 33 9.1 PackagingInformation............................. 141 4 TableofContents Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 2 Revision History ChangesfromMay31,2012toMarch11,2019(fromNRevision(May2012)toORevision) Page • Global:Restructureddocument. .................................................................................................. 1 • Global:Replaced"DSP/BIOS"with"SYS/BIOS". ............................................................................... 1 • Global:Changed"CAN2.0B"to"ISO11898-1(CAN2.0B)". .................................................................. 1 • Global:RemovedreferencestotheReliabilityDataforTMS320LF24xxandTMS320F28xxDevicesApplication Report(SPRA963).................................................................................................................... 1 • Section1(DeviceOverview):Changedsectiontitlefrom"F280x,F2801x,C280xDSPs"to"DeviceOverview". ..... 1 • Section1.1(Features):Removed"DynamicPLLRatioChangesSupported"feature. ..................................... 1 • Section1.1:Added"(AEC-Q100QualificationforAutomotiveApplications)"toQtemperatureoption................... 1 • Section1.2(Applications):Addedsection. ....................................................................................... 2 • Section1.3(Description):Addedsection. ........................................................................................ 2 • Section1.4(FunctionalBlockDiagram):Addedsection. ....................................................................... 3 • Section3(DeviceComparison):Addedsection. ................................................................................ 7 • Table3-1(DeviceComparison(100-MHzDevices)):Changedtitlefrom"HardwareFeatures(100-MHz Devices)"to"DeviceComparison(100-MHzDevices)". ........................................................................ 7 • Table3-1:Changed"PWMoutputs"to"PWMchannels". ...................................................................... 7 • Table3-1:Added"(AEC-Q100Qualification)"afterQtemperaturerange. .................................................. 7 • Table3-1:Removed"Productstatus"row. ....................................................................................... 7 • Table3-2(DeviceComparison(60-MHzDevices)):Changedtitlefrom"HardwareFeatures(60-MHzDevices)" to"DeviceComparison(60-MHzDevices)". ...................................................................................... 8 • Table3-2:Changed"PWMoutputs"to"PWMchannels". ...................................................................... 8 • Table3-2:Added"(AEC-Q100Qualification)"afterQtemperaturerange. .................................................. 8 • Table3-2:Removed"Productstatus"row. ....................................................................................... 8 • Section3.1(RelatedProducts):Addedsection. ................................................................................. 9 • Section4(TerminalConfigurationandFunctions):Addedsection. ......................................................... 10 • Section4.1(PinDiagrams):Changedsectiontitlefrom"PinAssignments"to"PinDiagrams". ......................... 10 • Table4-1(SignalDescriptions):UpdatedDESCRIPTIONofXRS........................................................... 15 • Section5.2(ESDRatings–Automotive):Addedsection...................................................................... 22 • Section5.3(ESDRatings–Commercial):Addedsection. ................................................................... 22 • Section5.4(RecommendedOperatingConditions):Changed"Qversion(Q100Qualification)"to"Qversion (AEC-Q100Qualification)". ........................................................................................................ 22 • Section5.5(PowerConsumptionSummary):Changedsectiontitlefrom"CurrentConsumption"to"Power ConsumptionSummary". .......................................................................................................... 23 • Section5.13(ThermalDesignConsiderations):Addedsection. ............................................................. 33 • Section5.14(TimingandSwitchingCharacteristics):Addedsection. ...................................................... 34 • Section5.14.2(PowerSequencing):Updated"Novoltagelargerthanadiodedrop..."paragraph. ................... 36 • Section5.14.2:Removed"PowerManagementandSupervisoryCircuitSolutions"section. ............................ 36 • Figure5-12(General-PurposeInputTiming):ChangedXCLKOUTtoSYSCLK. .......................................... 44 • Figure5-16(PWMHi-ZCharacteristics):ChangedXCLKOUTtoSYSCLK. ............................................... 48 • Table5-24(High-ResolutionPWMCharacteristicsatSYSCLKOUT=60–100MHz):Updatedfootnote. ............. 49 • Section5.14.4.5.1(SPIMasterModeTiming):Updatedsection. ............................................................ 52 • Section5.14.4.5.2(SPISlaveModeTiming):Updatedsection. ............................................................. 55 • Table5-39(FlashParametersat100-MHzSYSCLKOUT):AddedMAXProgramTimevaluesandMAXErase Timevalues.Updatedandaddedfootnotes..................................................................................... 58 • Table5-41(FlashDataRetentionDuration):Addedtable. ................................................................... 59 • Section5.16.1(MigrationIssues):AddedNOTEaboutROMversionsofF280xdevicenotbeingacceptedbyTI anymore. ............................................................................................................................. 66 • Section6(DetailedDescription):Changedsectiontitlefrom"FunctionalOverview"to"DetailedDescription". ....... 68 • Section6.1.6(ROM):AddedNOTE. ............................................................................................. 69 • Section6.2.6(EnhancedAnalog-to-DigitalConverter(ADC)Module):Updatedequationsbywhichthedigital valueoftheinputanalogvoltageisderived. .................................................................................... 85 • Section6.2.9(SerialPeripheralInterface(SPI)Modules(SPI-A,SPI-B,SPI-C,SPI-D)):Updated"Risingedge withphasedelay"clockngscheme............................................................................................... 99 • Table6-27(DeviceEmulationRegisters):UpdatedREVID:AddedSiliconrev.AforF2809only. .................... 119 • Table6-28(PIEPeripheralInterrupts):AddedfootnoteaboutADCINT. .................................................. 122 • Figure6-30(WatchdogModule):Updatedfigure. ............................................................................ 130 • Section7(Applications,Implementation,andLayout):Addedsection..................................................... 132 Copyright©2003–2019,TexasInstrumentsIncorporated RevisionHistory 5 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com • Section8(DeviceandDocumentationSupport):Addedsection. .......................................................... 133 • Figure8-1(ExampleofTMS320x280x/2801xDeviceNomenclature):Changed"(Q100qualification)"to"(AEC- Q100qualification)"................................................................................................................ 135 • Section8.3(ToolsandSoftware):Addedsection. ........................................................................... 136 • Section8.4(DocumentationSupport):Updatedsection. .................................................................... 137 • Section8.5(RelatedLinks):Addedsection. .................................................................................. 139 6 RevisionHistory Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 3 Device Comparison Table3-1.DeviceComparison(100-MHzDevices) FEATURE TYPE(1) F2809 F2808 F2806 F2802 F2801 C2802 C2801 Instructioncycle(at100MHz) – 10ns 10ns 10ns 10ns 10ns 10ns 10ns 18K 18K 10K 6K 6K 6K 6K Single-accessRAM(SARAM)(16-bitword) – (L0,L1,M0,M1, (L0,L1,M0,M1, (L0,L1,M0,M1) (L0,M0,M1) (L0,M0,M1) (L0,M0,M1) (L0,M0,M1) H0) H0) 3.3-Von-chipflash(16-bitword) – 128K 64K 32K 32K 16K – – On-chipROM(16-bitword) – – – – – – 32K 16K Codesecurityforon-chipflash/SARAM/OTPblocks – Yes Yes Yes Yes Yes Yes Yes BootROM(4Kx16) – Yes Yes Yes Yes Yes Yes Yes One-timeprogrammable(OTP)ROM – 1K 1K 1K 1K 1K – – (16-bitword) PWMchannels 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1A/2A/3A/ ePWM1A/2A/ ePWM1A/2A/ HRPWMchannels 0 ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A 4A/5A/6A 3A/4A 3A/4A 32-bitCAPTUREinputsorauxiliaryPWMoutputs 0 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2 32-bitQEPchannels(fourinputs/channel) 0 eQEP1/2 eQEP1/2 eQEP1/2 eQEP1 eQEP1 eQEP1 eQEP1 Watchdogtimer – Yes Yes Yes Yes Yes Yes Yes 12-Bit,16-channelADCconversiontime 1 80ns 160ns 160ns 160ns 160ns 160ns 160ns 32-BitCPUtimers – 3 3 3 3 3 3 3 SerialPeripheralInterface(SPI) 0 SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B SPI-A/B SPI-A/B SerialCommunicationsInterface(SCI) 0 SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A SCI-A SCI-A EnhancedControllerAreaNetwork(eCAN) 0 eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A eCAN-A eCAN-A Inter-IntegratedCircuit(I2C) 0 I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A DigitalI/Opins(shared) – 35 35 35 35 35 35 35 Externalinterrupts – 3 3 3 3 3 3 3 Supplyvoltage 1.8-VCore,3.3-VI/O – Yes Yes Yes Yes Yes Yes Yes 100-PinPZ – Yes Yes Yes Yes Yes Yes Yes Packaging 100-BallGGM,ZGM – Yes Yes Yes Yes Yes Yes Yes A:–40°Cto85°C – (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) S:–40°Cto125°C – (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) Temperatureoptions Q:–40°Cto125°C – (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (AEC-Q100Qualification) (1) Atypechangerepresentsamajorfunctionalfeaturedifferenceinaperipheralmodule.Withinaperipheraltype,theremaybeminordifferencesbetweendevicesthatdonotaffectthe basicfunctionalityofthemodule.Thesedevice-specificdifferencesarelistedintheC2000real-timecontrolperipheralsreferenceguideandintheperipheralreferenceguides. Copyright©2003–2019,TexasInstrumentsIncorporated DeviceComparison 7 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table3-2.DeviceComparison(60-MHzDevices) FEATURE TYPE(1) F2802-60 F2801-60 F28016 F28015 Instructioncycle(at60MHz) – 16.67ns 16.67ns 16.67ns 16.67ns 6K 6K 6K 6K Single-accessRAM(SARAM)(16-bitword) – (L0,M0,M1) (L0,M0,M1) (L0,M0,M1) (L0,M0,M1) 3.3-Von-chipflash(16-bitword) – 32K 16K 16K 16K On-chipROM(16-bitword) – – – – – Codesecurityforon-chipflash/SARAM/OTPblocks – Yes Yes Yes Yes BootROM(4Kx16) – Yes Yes Yes Yes One-timeprogrammable(OTP)ROM – 1K 1K 1K 1K (16-bitword) PWMchannels 0 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3/4 ePWM1/2/3/4 HRPWMchannels 0 ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A 32-bitCAPTUREinputsorauxiliaryPWMoutputs 0 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2 32-bitQEPchannels(fourinputs/channel) 0 eQEP1 eQEP1 - - Watchdogtimer – Yes Yes Yes Yes No.ofchannels 16 16 16 16 12-BitADC MSPS 1 3.75 3.75 3.75 3.75 Conversiontime 267ns 267ns 267ns 267ns 32-BitCPUtimers – 3 3 3 3 SerialPeripheralInterface(SPI) 0 SPI-A/B SPI-A/B SPI-A SPI-A SerialCommunicationsInterface(SCI) 0 SCI-A SCI-A SCI-A SCI-A EnhancedControllerAreaNetwork(eCAN) 0 eCAN-A eCAN-A eCAN-A - Inter-IntegratedCircuit(I2C) 0 I2C-A I2C-A I2C-A I2C-A DigitalI/Opins(shared) – 35 35 35 35 Externalinterrupts – 3 3 3 3 1.8-VCore, 1.8-VCore, 1.8-VCore, 1.8-VCore, Supplyvoltage – 3.3-VI/O 3.3-VI/O 3.3-VI/O 3.3-VI/O 100-PinPZ – Yes Yes Yes Yes Packaging 100-BallGGM,ZGM – Yes Yes Yes Yes A:–40°Cto85°C – (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) S:–40°Cto125°C – (PZGGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) (PZ,GGM,ZGM) Temperatureoptions Q:–40°Cto125°C – (PZ) (PZ) (PZ) (PZ) (AEC-Q100Qualification) (1) Atypechangerepresentsamajorfunctionalfeaturedifferenceinaperipheralmodule.Withinaperipheraltype,theremaybeminordifferencesbetweendevicesthatdonotaffectthe basicfunctionalityofthemodule.Thesedevice-specificdifferencesarelistedintheC2000real-timecontrolperipheralsreferenceguideandintheperipheralreferenceguides. 8 DeviceComparison Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 3.1 Related Products Forinformationaboutotherdevicesinthisfamilyofproducts,seethefollowinglinks: TMS320F2837xSDelfino™Microcontrollers The Delfino™ TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications. Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVEinitiatives. Copyright©2003–2019,TexasInstrumentsIncorporated DeviceComparison 9 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin assignmentsareshowninFigure4-1,Figure4-2,Figure4-3,andFigure4-4.The100-ballGGMandZGM ball grid array (BGA) terminal assignments are shown in Figure 4-5. Table 4-1 describes the function(s) of eachpin. O C N O Y TCK TMS TDIGPIO23/EQEP1I/SPISTEC/SCIRXDB GPIO22/EQEP1S/SPICLKC/SCITXDB GPIO11/EPWM6B/SCIRXDB/ECAP4VSSVDDGPIO21/EQEP1B/SPISOMIC/CANRXB XCLKOUTVDDIOGPIO10/EPWM6A/CANRXB/ADCSOCBGPIO20/EQEP1A/SPISIMOC/CANTXBVSSGPIO9/EPWM5B/SCITXDB/ECAP3 GPIO8/EPWM5A/CANTXB/ADCSOCAOVDDGPIO7/EPWM4B/SPISTED/ECAP2 GPIO19/SPISTEA/SCIRXDB GPIO6/EPWM4A/EPWMSYNCI/EPWMSVSSGPIO18/SPICLKA/SCITXDB GPIO5/EPWM3B/SPICLKD/ECAP1 GPIO17/SPISOMIA/CANRXB/TZ6 GPIO4/EPWM3A TDO 7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150 GPIO16/SPISIMOA/CANTXB/TZ5 VSS 77 49 VSS XRS 78 48 GPIO3/EPWM2B/SPISOMID GPIO27/ECAP4/EQEP2S/SPISTEB 79 47 GPIO0/EPWM1A EMU0 80 46 VDDIO EMU1 81 45 GPIO2/EPWM2A VDDIO 82 44 GPIO1/EPWM1B/SPISIMOD GPIO24/ECAP1/EQEP2A/SPISIMOB 83 43 GPIO34 TRST 84 42 VDD VDD 85 41 VSS X2 86 40 VDD2A18 VSS 87 39 VSS2AGND X1 88 38 ADCRESEXT VSS 89 37 ADCREFP XCLKIN 90 36 ADCREFM GPIO25/ECAP2/EQEP2B/SPISOMIB 91 35 ADCREFIN GPIO28/SCIRXDA/TZ5 92 34 ADCINB7 VDD 93 33 ADCINB6 VSS 94 32 ADCINB5 GPIO13/TZ2/CANRXB/SPISOMIB 95 31 ADCINB4 VDD3VFL 96 30 ADCINB3 TEST1 97 29 ADCINB2 TEST2 98 28 ADCINB1 GPIO26/ECAP3/EQEP2I/SPICLKB 99 27 ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO 100 26 VDDAIO 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 GPIO12//TZ1CANTXB/SPISIMOBVSSVDDIOGPIO29/SCITXDA//TZ6 CLA/EPWMSYNCO/ADCSOCBOGPIO30/CANRXA GPIO31/CANTXA GPIO14/TZ3/SCITXDB/SPICLKB GPIO15/TZ4/SCIRXDB/SPISTEBVDDVSSVDD1A18VSS1AGNDVSSA2VDDA2ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLOVSSAIO S 3/ 3 O PI G Figure4-1. TMS320F2809,TMS320F2808100-PinPZLQFP(TopView) 10 TerminalConfigurationandFunctions Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 O C N Y S TCK TMS TDIGPIO23/EQEP1I/SPISTEC/SCIRXDB GPIO22/EQEP1S/SPICLKC/SCITXDB GPIO11/EPWM6B/SCIRXDB/ECAP4VSSVDDGPIO21/EQEP1B/SPISOMIC XCLKOUTVDDIOGPIO10/EPWM6A/ADCSOCBOGPIO20/EQEP1A/SPISIMOCVSSGPIO9/EPWM5B/SCITXDB/ECAP3 GPIO8/EPWM5A/ADCSOCAOVDDGPIO7/EPWM4B/SPISTED/ECAP2 GPIO19/SPISTEA/SCIRXDB GPIO6/EPWM4A/EPWMSYNCI/EPWMVSSGPIO18/SPICLKA/SCITXDB GPIO5/EPWM3B/SPICLKD/ECAP1 GPIO17/SPISOMIA/TZ6 GPIO4/EPWM3A TDO 7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150 GPIO16/SPISIMOA/TZ5 VSS 77 49 VSS XRS 78 48 GPIO3/EPWM2B/SPISOMID GPIO27/ECAP4/EQEP2S/SPISTEB 79 47 GPIO0/EPWM1A EMU0 80 46 VDDIO EMU1 81 45 GPIO2/EPWM2A VDDIO 82 44 GPIO1/EPWM1B/SPISIMOD GPIO24/ECAP1/EQEP2A/SPISIMOB 83 43 GPIO34 TRST 84 42 VDD VDD 85 41 VSS X2 86 40 VDD2A18 VSS 87 39 VSS2AGND X1 88 38 ADCRESEXT VSS 89 37 ADCREFP XCLKIN 90 36 ADCREFM GPIO25/ECAP2/EQEP2B/SPISOMIB 91 35 ADCREFIN GPIO28/SCIRXDA/TZ5 92 34 ADCINB7 VDD 93 33 ADCINB6 VSS 94 32 ADCINB5 GPIO13/TZ2/SPISOMIB 95 31 ADCINB4 VDD3VFL 96 30 ADCINB3 TEST1 97 29 ADCINB2 TEST2 98 28 ADCINB1 GPIO26/ECAP3/EQEP2I/SPICLKB 99 27 ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO 100 26 VDDAIO 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 O12//SPISTZ1IMOBVSSVDDIOO29/SCITXDA//TZ6 YNCO/ADCSOCBOGPIO30/CANRXA GPIO31/CANTXA SCITXDB/SPICLKB SCIRXDB/SPISTEBVDDVSSVDD1A18VSS1AGNDVSSA2VDDA2ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLOVSSAIO GPI GPI WMS TZ3/ TZ4/ CLA/EP GPIO14/ GPIO15/ S 3/ 3 O PI G Figure4-2. TMS320F2806100-PinPZLQFP(TopView) Copyright©2003–2019,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com O C N Y S M W TCK TMS TDIGPIO23/EQEP1I GPIO22/EQEP1S GPIO11VSSVDDGPIO21/EQEP1B XCLKOUTVDDIOGPIO10/ADCSOCBOGPIO20/EQEP1AVSSGPIO9 GPIO8/ADCSOCAOVDDGPIO7/ECAP2 GPIO19/SPISTEA GPIO6/EPWMSYNCI/EPVSSGPIO18/SPICLKA GPIO5/EPWM3B/ECAP1 GPIO17/SPISOMIA/TZ6 GPIO4/EPWM3A TDO 7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150 GPIO16/SPISIMOA/TZ5 VSS 77 49 VSS XRS 78 48 GPIO3/EPWM2B SPISTEB/GPIO27 79 47 GPIO0/EPWM1A EMU0 80 46 VDDIO EMU1 81 45 GPIO2/EPWM2A VDDIO 82 44 GPIO1/EPWM1B SPISIMOB/GPIO24/ECAP1 83 43 GPIO34 TRST 84 42 VDD VDD 85 41 VSS X2 86 40 VDD2A18 VSS 87 39 VSS2AGND X1 88 38 ADCRESEXT VSS 89 37 ADCREFP XCLKIN 90 36 ADCREFM GPIO25/ECAP2/SPISOMIB 91 35 ADCREFIN GPIO28/SCIRXDA/TZ5 92 34 ADCINB7 VDD 93 33 ADCINB6 VSS 94 32 ADCINB5 SPISOMIB/GPIO13/TZ2 95 31 ADCINB4 VDD3VFL(A) 96 30 ADCINB3 TEST1 97 29 ADCINB2 TEST2 98 28 ADCINB1 SPICLKB/GPIO26 99 27 ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO 100 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 526 VDDAIO 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 SPISIMOB/GPIO12/TZ1VSSVDDIOGPIO29/SCITXDA//TZ6 WMSYNCO/ADCSOCBOGPIO30/CANRXA GPIO31/CANTXA SPICLKB/GPIO14/TZ3 SPISTEB/GPIO15/TZ4VDDVSSVDD1A18VSS1AGNDVSSA2VDDA2ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLOVSSAIO P E A/ L C S 3/ 3 O PI G A. OntheC280xdevices,theV pinisV . DD3VFL DDIO Figure4-3.TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801100-PinPZLQFP(TopView) 12 TerminalConfigurationandFunctions Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 O C N Y S M W P E CI/ N Y TCK TMS TDIGPIO23 GPIO22 GPIO11VSSVDDGPIO21 XCLKOUTVDDIOGPIO10/ADCSOCBOGPIO20VSSGPIO9 GPIO8/ADCSOCAOVDDGPIO7/EPWM4B/ECAP2 GPIO19/SPISTEA GPIO6/EPWM4A/EPWMSVSSGPIO18/SPICLKA GPIO5/EPWM3B/ECAP1 GPIO17/SPISOMIA/TZ6 GPIO4/EPWM3A TDO 7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150 GPIO16/SPISIMOA/TZ5 VSS 77 49 VSS XRS 78 48 GPIO3/EPWM2B GPIO27 79 47 GPIO0/EPWM1A EMU0 80 46 VDDIO EMU1 81 45 GPIO2/EPWM2A VDDIO 82 44 GPIO1/EPWM1B GPIO24/ECAP1 83 43 GPIO34 TRST 84 42 VDD VDD 85 41 VSS X2 86 40 VDD2A18 VSS 87 39 VSS2AGND X1 88 38 ADCRESEXT VSS 89 37 ADCREFP XCLKIN 90 36 ADCREFM GPIO25/ECAP2 91 35 ADCREFIN GPIO28/SCIRXDA/TZ5 92 34 ADCINB7 VDD 93 33 ADCINB6 VSS 94 32 ADCINB5 GPIO13/TZ2 95 31 ADCINB4 VDD3VFL 96 30 ADCINB3 TEST1 97 29 ADCINB2 TEST2 98 28 ADCINB1 GPIO26 99 27 ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO 100 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 526 VDDAIO 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 GPIO12/TZ1VSSVDDIOGPIO29/SCITXDA//TZ6 MSYNCO/ADCSOCBO(A)GPIO30/CANRXA(A)GPIO31/CANTXAGPIO14/TZ3 GPIO15/TZ4VDDVSSVDD1A18VSS1AGNDVSSA2VDDA2ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLOVSSAIO W P E A/ L C S 3/ 3 O PI G A. CANTXA(pin7)andCANRXA(pin6)pinsarenotapplicablefortheTMS320F28015. Figure4-4.TMS320F2801x100-PinPZLQFP(TopView) Copyright©2003–2019,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 13 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com K VSSAIO ADCINB0 ADCINB3 ADCINB5 ADCINB7 VSS2AGND GPIO1 GPIO0 VSS GPIO16 J ADCLO VDDAIO ADCINB1 ADCINB4 ADCREFIN VDD2A18 GPIO2 GPIO3 GPIO4 GPIO17 H ADCINA1 ADCINA0 ADCINB2 ADCINB6 ADCREFM VSS VDDIO GPIO18 GPIO5 VSS G ADCINA4 ADCINA3 ADCINA2 ADCINA5 ADCREFP VDD GPIO34 GPIO7 GPIO6 GPIO19 F VSSA2 VDDA2 ADCINA7 ADCINA6 ADCRESEXT GPIO20 VSS GPIO9 GPIO8 VDD E GPIO15 VDD VSS VDD1A18 VSS1AGND X1 GPIO21 XCLKOUT VDDIO GPIO10 D GPIO31 GPIO30 GPIO14 VDD GPIO28 VSS VDD GPIO22 GPIO11 VSS C GPIO33 VDDIO GPIO29 VDD3VFL GPIO25 X2 GPIO24 GPIO27 TDI GPIO23 B VSS GPIO12 TEST2 GPIO13 XCLKIN VDD EMU1 XRS TDO TMS A GPIO32 GPIO26 TEST1 VSS VSS TRST VDDIO EMU0 VSS TCK 1 2 3 4 5 6 7 8 9 10 Bottom View Figure4-5.TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801, TMS320F28016,TMS320F28015,TMS320C2802,TMS320C2801 100-BallGGMandZGMMicroStarBGA™(BottomView) 14 TerminalConfigurationandFunctions Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 4.2 Signal Descriptions Table 4-1 describes the signals. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels.Inputsarenot5-Vtolerant. Table4-1.SignalDescriptions PINNO. NAME PZ GGM/ DESCRIPTION (1) ZGM PIN# BALL# JTAG JTAGtestresetwithinternalpulldown.TRST,whendrivenhigh,givesthescansystemcontrolof theoperationsofthedevice.Ifthissignalisnotconnectedordrivenlow,thedeviceoperatesinits functionalmode,andthetestresetsignalsareignored. NOTE:DonotusepullupresistorsonTRST;ithasaninternalpull-downdevice.TRSTisanactive TRST 84 A6 hightestpinandmustbemaintainedlowatalltimesduringnormaldeviceoperation.Anexternal pulldownresistorisrequiredonthispin.Thevalueofthisresistorshouldbebasedondrivestrength ofthedebuggerpodsapplicabletothedesign.A2.2-kΩresistorgenerallyoffersadequate protection.Sincethisisapplication-specific,itisrecommendedthateachtargetboardbevalidated forproperoperationofthedebuggerandtheapplication.(I,↓) TCK 75 A10 JTAGtestclockwithinternalpullup(I,↑) JTAGtest-modeselect(TMS)withinternalpullup.ThisserialcontrolinputisclockedintotheTAP TMS 74 B10 controllerontherisingedgeofTCK.(I,↑) JTAGtestdatainput(TDI)withinternalpullup.TDIisclockedintotheselectedregister(instruction TDI 73 C9 ordata)onarisingedgeofTCK.(I,↑) JTAGscanout,testdataoutput(TDO).Thecontentsoftheselectedregister(instructionordata) TDO 76 B9 areshiftedoutofTDOonthefallingedgeofTCK.(O/Z8mAdrive) Emulatorpin0.WhenTRSTisdrivenhigh,thispinisusedasaninterrupttoorfromtheemulator systemandisdefinedasinput/outputthroughtheJTAGscan.Thispinisalsousedtoputthe deviceintoboundary-scanmode.WiththeEMU0pinatalogic-highstateandtheEMU1pinata logic-lowstate,arisingedgeontheTRSTpinwouldlatchthedeviceintoboundary-scanmode. EMU0 80 A8 (I/O/Z,8mAdrive↑) NOTE:Anexternalpullupresistorisrecommendedonthispin.Thevalueofthisresistorshouldbe basedonthedrivestrengthofthedebuggerpodsapplicabletothedesign.A2.2-kΩto4.7-kΩ resistorisgenerallyadequate.Sincethisisapplication-specific,itisrecommendedthateachtarget boardbevalidatedforproperoperationofthedebuggerandtheapplication. Emulatorpin1.WhenTRSTisdrivenhigh,thispinisusedasaninterrupttoorfromtheemulator systemandisdefinedasinput/outputthroughtheJTAGscan.Thispinisalsousedtoputthe deviceintoboundary-scanmode.WiththeEMU0pinatalogic-highstateandtheEMU1pinata logic-lowstate,arisingedgeontheTRSTpinwouldlatchthedeviceintoboundary-scanmode. EMU1 81 B7 (I/O/Z,8mAdrive↑) NOTE:Anexternalpullupresistorisrecommendedonthispin.Thevalueofthisresistorshouldbe basedonthedrivestrengthofthedebuggerpodsapplicabletothedesign.A2.2-kΩto4.7-kΩ resistorisgenerallyadequate.Sincethisisapplication-specific,itisrecommendedthateachtarget boardbevalidatedforproperoperationofthedebuggerandtheapplication. FLASH 3.3-VFlashCorePowerPin.Thispinshouldbeconnectedto3.3Vatalltimes.OntheROM V 96 C4 DD3VFL parts(C280x),thispinshouldbeconnectedtoV . DDIO TEST1 97 A3 TestPin.ReservedforTI.Mustbeleftunconnected.(I/O) TEST2 98 B3 TestPin.ReservedforTI.Mustbeleftunconnected.(I/O) CLOCK OutputclockderivedfromSYSCLKOUT.XCLKOUTiseitherthesamefrequency,one-halfthe frequency,orone-fourththefrequencyofSYSCLKOUT.Thisiscontrolledbythebits1,0 XCLKOUT 66 E8 (XCLKOUTDIV)intheXCLKregister.Atreset,XCLKOUT=SYSCLKOUT/4.TheXCLKOUTsignal canbeturnedoffbysettingXCLKOUTDIVto3.UnlikeotherGPIOpins,theXCLKOUTpinisnot placedinhigh-impedancestateduringareset.(O/Z,8mAdrive). ExternalOscillatorInput.Thispinisusedtofeedaclockfromanexternal3.3-Voscillator.Inthis XCLKIN 90 B5 case,tietheX1pintoGND.Alternately,whenacrystal/resonatorisused(orifanexternal1.8-V oscillatorisfedintotheX1pin),tietheXCLKINpintoGND.(I) (1) I=Input,O=Output,Z=Highimpedance,OD=Opendrain,↑=Pullup,↓=Pulldown Copyright©2003–2019,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 15 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table4-1.SignalDescriptions(continued) PINNO. NAME PZ GGM/ DESCRIPTION (1) ZGM PIN# BALL# Internal/ExternalOscillatorInput.Tousetheinternaloscillator,aquartzcrystaloraceramic resonatormaybeconnectedacrossX1andX2.TheX1pinisreferencedtothe1.8-Vcoredigital X1 88 E6 powersupply.A1.8-VexternaloscillatormaybeconnectedtotheX1pin.Inthiscase,theXCLKIN pinmustbeconnectedtoground.Ifa3.3-VexternaloscillatorisusedwiththeXCLKINpin,X1must betiedtoGND.(I) InternalOscillatorOutput.AquartzcrystaloraceramicresonatormaybeconnectedacrossX1and X2 86 C6 X2.IfX2isnotuseditmustbeleftunconnected.(O) RESET DeviceReset(in)andWatchdogReset(out). Devicereset.XRScausesthedevicetoterminateexecution.ThePCwillpointtotheaddress containedatthelocation0x3FFFC0.WhenXRSisbroughttoahighlevel,executionbeginsatthe locationpointedtobythePC.ThispinisdrivenlowbytheDSPwhenawatchdogresetoccurs. XRS 78 B8 Duringwatchdogreset,theXRSpinisdrivenlowforthewatchdogresetdurationof512OSCCLK cycles.(I/OD,↑) Theoutputbufferofthispinisanopen-drainwithaninternalpullup.Ifthispinisdrivenbyan externaldevice,itshouldbedoneusinganopen-draindevice. ADCSIGNALS ADCINA7 16 F3 ADCGroupA,Channel7input(I) ADCINA6 17 F4 ADCGroupA,Channel6input(I) ADCINA5 18 G4 ADCGroupA,Channel5input(I) ADCINA4 19 G1 ADCGroupA,Channel4input(I) ADCINA3 20 G2 ADCGroupA,Channel3input(I) ADCINA2 21 G3 ADCGroupA,Channel2input(I) ADCINA1 22 H1 ADCGroupA,Channel1input(I) ADCINA0 23 H2 ADCGroupA,Channel0input(I) ADCINB7 34 K5 ADCGroupB,Channel7input(I) ADCINB6 33 H4 ADCGroupB,Channel6input(I) ADCINB5 32 K4 ADCGroupB,Channel5input(I) ADCINB4 31 J4 ADCGroupB,Channel4input(I) ADCINB3 30 K3 ADCGroupB,Channel3input(I) ADCINB2 29 H3 ADCGroupB,Channel2input(I) ADCINB1 28 J3 ADCGroupB,Channel1input(I) ADCINB0 27 K2 ADCGroupB,Channel0input(I) ADCLO 24 J1 LowReference(connecttoanalogground)(I) ADCRESEXT 38 F5 ADCExternalCurrentBiasResistor.Connecta22-kΩresistortoanalogground. ADCREFIN 35 J5 Externalreferenceinput(I) InternalReferencePositiveOutput.RequiresalowESR(under1.5Ω)ceramicbypasscapacitorof 2.2μFtoanalogground.(O) ADCREFP 37 G5 NOTE:UsetheADCClockratetoderivetheESRspecificationfromthecapacitordatasheetthatis usedinthesystem. InternalReferenceMediumOutput.RequiresalowESR(under1.5Ω)ceramicbypasscapacitorof 2.2μFtoanalogground.(O) ADCREFM 36 H5 NOTE:UsetheADCClockratetoderivetheESRspecificationfromthecapacitordatasheetthatis usedinthesystem. 16 TerminalConfigurationandFunctions Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table4-1.SignalDescriptions(continued) PINNO. NAME PZ GGM/ DESCRIPTION (1) ZGM PIN# BALL# CPUANDI/OPOWERPINS V 15 F2 ADCAnalogPowerPin(3.3V) DDA2 V 14 F1 ADCAnalogGroundPin SSA2 V 26 J2 ADCAnalogI/OPowerPin(3.3V) DDAIO V 25 K1 ADCAnalogI/OGroundPin SSAIO V 12 E4 ADCAnalogPowerPin(1.8V) DD1A18 V 13 E5 ADCAnalogGroundPin SS1AGND V 40 J6 ADCAnalogPowerPin(1.8V) DD2A18 V 39 K6 ADCAnalogGroundPin SS2AGND V 10 E2 DD V 42 G6 DD V 59 F10 DD CPUandLogicDigitalPowerPins(1.8V) V 68 D7 DD V 85 B6 DD V 93 D4 DD V 3 C2 DDIO V 46 H7 DDIO DigitalI/OPowerPin(3.3V) V 65 E9 DDIO V 82 A7 DDIO V 2 B1 SS V 11 E3 SS V 41 H6 SS V 49 K9 SS V 55 H10 SS V 62 F7 DigitalGroundPins SS V 69 D10 SS V 77 A9 SS V 87 D6 SS V 89 A5 SS V 94 A4 SS GPIOAANDPERIPHERALSIGNALS(2)(3) GPIO0 General-purposeinput/output0(I/O/Z) (4) EPWM1A EnhancedPWM1OutputAandHRPWMchannel(O) 47 K8 - - - - GPIO1 General-purposeinput/output1(I/O/Z)(4) EPWM1B EnhancedPWM1OutputB(O) 44 K7 SPISIMOD SPI-Dslavein,masterout(I/O)(notavailableon2801,2802) - - GPIO2 General-purposeinput/output2(I/O/Z)(4) EPWM2A EnhancedPWM2OutputAandHRPWMchannel(O) 45 J7 - - - - (2) SomeperipheralfunctionsmaynotbeavailableinTMS320F2801xdevices.SeeTable3-2fordetails. (3) AllGPIOpinsareI/O/Z,4-mAdrivetypical(unlessotherwiseindicated),andhaveaninternalpullup,whichcanbeselectively enabled/disabledonaper-pinbasis.ThisfeatureonlyappliestotheGPIOpins.TheGPIOfunction(showninItalics)isthedefaultat reset.Theperipheralsignalsthatarelistedunderthemarealternatefunctions. (4) ThepullupsonGPIO0-GPIO11pinsarenotenabledatreset. Copyright©2003–2019,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 17 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table4-1.SignalDescriptions(continued) PINNO. NAME PZ GGM/ DESCRIPTION (1) ZGM PIN# BALL# GPIO3 General-purposeinput/output3(I/O/Z)(4) EPWM2B EnhancedPWM2OutputB(O) 48 J8 SPISOMID SPI-Dslaveout,masterin(I/O)(notavailableon2801,2802) - - GPIO4 General-purposeinput/output4(I/O/Z)(4) EPWM3A EnhancedPWM3outputAandHRPWMchannel(O) 51 J9 - - - - GPIO5 General-purposeinput/output5(I/O/Z)(4) EPWM3B EnhancedPWM3outputB(O) 53 H9 SPICLKD SPI-Dclock(I/O)(notavailableon2801,2802) ECAP1 Enhancedcaptureinput/output1(I/O) GPIO6 General-purposeinput/output6(I/O/Z)(4) EPWM4A EnhancedPWM4outputAandHRPWMchannel(O)(notavailableon2801,2802) 56 G9 EPWMSYNCI ExternalePWMsyncpulseinput(I) EPWMSYNCO ExternalePWMsyncpulseoutput(O) GPIO7 General-purposeinput/output7(I/O/Z)(4) EPWM4B EnhancedPWM4outputB(O)(notavailableon2801,2802) 58 G8 SPISTED SPI-Dslavetransmitenable(I/O)(notavailableon2801,2802) ECAP2 Enhancedcaptureinput/output2(I/O) GPIO8 General-purposeinput/output8(I/O/Z)(4) EPWM5A EnhancedPWM5outputAandHRPWMchannel(O)(notavailableon2801,2802) 60 F9 CANTXB EnhancedCAN-Btransmit(O)(notavailableon2801,2802,F2806) ADCSOCAO ADCstart-of-conversionA(O) GPIO9 General-purposeinput/output9(I/O/Z)(4) EPWM5B EnhancedPWM5outputB(O)(notavailableon2801,2802) 61 F8 SCITXDB SCI-Btransmitdata(O)(notavailableon2801,2802) ECAP3 Enhancedcaptureinput/output3(I/O)(notavailableon2801,2802) GPIO10 General-purposeinput/output10(I/O/Z)(4) EPWM6A EnhancedPWM6outputAandHRPWMchannel(O)(notavailableon2801,2802) 64 E10 CANRXB EnhancedCAN-Breceive(I)(notavailableon2801,2802,F2806) ADCSOCBO ADCstart-of-conversionB(O) GPIO11 General-purposeinput/output11(I/O/Z)(4) EPWM6B EnhancedPWM6outputB(O)(notavailableon2801,2802) 70 D9 SCIRXDB SCI-Breceivedata(I)(notavailableon2801,2802) ECAP4 EnhancedCAPInput/Output4(I/O)(notavailableon2801,2802) GPIO12 General-purposeinput/output12(I/O/Z)(5) TZ1 TripZoneinput1(I) 1 B2 CANTXB EnhancedCAN-Btransmit(O)(notavailableon2801,2802,F2806) SPISIMOB SPI-BSlavein,Masterout(I/O) GPIO13 General-purposeinput/output13(I/O/Z)(5) TZ2 Tripzoneinput2(I) 95 B4 CANRXB EnhancedCAN-Breceive(I)(notavailableon2801,2802,F2806) SPISOMIB SPI-Bslaveout,masterin(I/O) GPIO14 General-purposeinput/output14(I/O/Z)(5) TZ3 Tripzoneinput3(I) 8 D3 SCITXDB SCI-Btransmit(O)(notavailableon2801,2802) SPICLKB SPI-Bclockinput/output(I/O) GPIO15 General-purposeinput/output15(I/O/Z)(5) TZ4 Tripzoneinput4(I) 9 E1 SCIRXDB SCI-Breceive(I)(notavailableon2801,2802) SPISTEB SPI-Bslavetransmitenable(I/O) GPIO16 General-purposeinput/output16(I/O/Z)(5) SPISIMOA SPI-Aslavein,masterout(I/O) 50 K10 CANTXB EnhancedCAN-Btransmit(O)(notavailableon2801,2802,F2806) TZ5 Tripzoneinput5(I) (5) ThepullupsonGPIO12-GPIO34areenableduponreset. 18 TerminalConfigurationandFunctions Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table4-1.SignalDescriptions(continued) PINNO. NAME PZ GGM/ DESCRIPTION (1) ZGM PIN# BALL# GPIO17 General-purposeinput/output17(I/O/Z)(5) SPISOMIA SPI-Aslaveout,masterin(I/O) 52 J10 CANRXB EnhancedCAN-Breceive(I)(notavailableon2801,2802,F2806) TZ6 Tripzoneinput6(I) GPIO18 General-purposeinput/output18(I/O/Z)(5) SPICLKA SPI-Aclockinput/output(I/O) SCITXDB 54 H8 SCI-Btransmit(O)(notavailableon2801,2802) - - - - GPIO19 General-purposeinput/output19(I/O/Z)(5) SPISTEA SPI-Aslavetransmitenableinput/output(I/O) SCIRXDB 57 G10 SCI-Breceive(I)(notavailableon2801,2802) - - - - GPIO20 General-purposeinput/output20(I/O/Z)(5) EQEP1A EnhancedQEP1inputA(I) 63 F6 SPISIMOC SPI-Cslavein,masterout(I/O)(notavailableon2801,2802) CANTXB EnhancedCAN-Btransmit(O)(notavailableon2801,2802,F2806) GPIO21 General-purposeinput/output21(I/O/Z)(5) EQEP1B EnhancedQEP1inputA(I) 67 E7 SPISOMIC SPI-Cmasterin,slaveout(I/O)(notavailableon2801,2802) CANRXB EnhancedCAN-Breceive(I)(notavailableon2801,2802,F2806) GPIO22 General-purposeinput/output22(I/O/Z)(5) EQEP1S EnhancedQEP1strobe(I/O) 71 D8 SPICLKC SPI-Cclock(I/O)(notavailableon2801,2802) SCITXDB SCI-Btransmit(O)(notavailableon2801,2802) GPIO23 General-purposeinput/output23(I/O/Z)(5) EQEP1I EnhancedQEP1index(I/O) 72 C10 SPISTEC SPI-Cslavetransmitenable(I/O)(notavailableon2801,2802) SCIRXDB SCI-Breceive(I)(notavailableon2801,2802) GPIO24 General-purposeinput/output24(I/O/Z)(5) ECAP1 Enhancedcapture1(I/O) 83 C7 EQEP2A EnhancedQEP2inputA(I)(notavailableon2801,2802) SPISIMOB SPI-Bslavein,masterout(I/O) GPIO25 General-purposeinput/output25(I/O/Z)(5) ECAP2 Enhancedcapture2(I/O) 91 C5 EQEP2B EnhancedQEP2inputB(I)(notavailableon2801,2802) SPISOMIB SPI-Bmasterin,slaveout(I/O) GPIO26 General-purposeinput/output26(I/O/Z)(5) ECAP3 Enhancedcapture3(I/O)(notavailableon2801,2802) 99 A2 EQEP2I EnhancedQEP2index(I/O)(notavailableon2801,2802) SPICLKB SPI-Bclock(I/O) GPIO27 General-purposeinput/output27(I/O/Z)(5) ECAP4 Enhancedcapture4(I/O)(notavailableon2801,2802) 79 C8 EQEP2S EnhancedQEP2strobe(I/O)(notavailableon2801,2802) SPISTEB SPI-Bslavetransmitenable(I/O) GPIO28 General-purposeinput/output28.Thispinhasan8-mA(typical)outputbuffer.(I/O/Z)(5) SCIRXDA SCIreceivedata(I) 92 D5 - - TZ5 Tripzoneinput5(I) GPIO29 General-purposeinput/output29.Thispinhasan8-mA(typical)outputbuffer.(I/O/Z)(5) SCITXDA SCItransmitdata(O) 4 C3 - - TZ6 Tripzone6input(I) Copyright©2003–2019,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 19 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table4-1.SignalDescriptions(continued) PINNO. NAME PZ GGM/ DESCRIPTION (1) ZGM PIN# BALL# GPIO30 General-purposeinput/output30.Thispinhasan8-mA(typical)outputbuffer.(I/O/Z)(5) CANRXA EnhancedCAN-Areceivedata(I) 6 D2 - - - - GPIO31 General-purposeinput/output31.Thispinhasan8-mA(typical)outputbuffer.(I/O/Z)(5) CANTXA EnhancedCAN-Atransmitdata(O) 7 D1 - - - - GPIO32 General-purposeinput/output32(I/O/Z)(5) SDAA I2Cdataopen-drainbidirectionalport(I/OD) 100 A1 EPWMSYNCI EnhancedPWMexternalsyncpulseinput(I) ADCSOCAO ADCstart-of-conversion(O) GPIO33 General-PurposeInput/Output33(I/O/Z)(5) SCLA I2Cclockopen-drainbidirectionalport(I/OD) 5 C1 EPWMSYNCO EnhancedPWMexternalsynchpulseoutput(O) ADCSOCBO ADCstart-of-conversion(O) GPIO34 General-PurposeInput/Output34(I/O/Z)(5) - - 43 G7 - - - - NOTE Some peripheral functions may not be available in TMS320F2801x devices. See Table 3-2 fordetails. 20 TerminalConfigurationandFunctions Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5 Specifications Thissectionprovidestheabsolutemaximumratingsandtherecommendedoperatingconditions. 5.1 Absolute Maximum Ratings(1)(2) Unlessotherwisenoted,thelistofabsolutemaximumratingsarespecifiedoveroperatingtemperatureranges. MIN MAX UNIT V ,V withrespecttoV –0.3 4.6 DDIO DD3VFL SS V ,V withrespecttoV –0.3 4.6 DDA2 DDAIO SSA V withrespecttoV –0.3 2.5 Supplyvoltage DD SS V V ,V withrespecttoV –0.3 2.5 DD1A18 DD2A18 SSA V ,V ,V ,V withrespect SSA2 SSAIO SS1AGND SS2AGND –0.3 0.3 toV SS Inputvoltage V –0.3 4.6 V IN Outputvoltage V –0.3 4.6 V O Inputclampcurrent I (V <0orV >V )(3) –20 20 mA IK IN IN DDIO Outputclampcurrent I (V <0orV >V ) –20 20 mA OK O O DDIO Aversion(GGM,ZGM,PZ)(4) –40 85 Operatingambienttemperature,T Sversion(GGM,ZGM,PZ)(4) –40 125 °C A Qversion(PZ)(4) –40 125 Junctiontemperature T (4) –40 150 °C J Storagetemperature T (4) –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderSection5.4isnotimplied. Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttoV ,unlessotherwisenoted. SS (3) Continuousclampcurrentperpinis±2mA.Thisincludestheanaloginputswhichhaveaninternalclampingcircuitthatclampsthe voltagetoadiodedropaboveV orbelowV . DDA2 SSA2 (4) Long-termhigh-temperaturestorageand/orextendeduseatmaximumtemperatureconditionsmayresultinareductionofoveralldevice life.Foradditionalinformation,seeSemiconductorandICpackagethermalmetrics. Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 21 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.2 ESD Ratings – Automotive VALUE UNIT TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801,TMS320F28016,and TMS320F28015in100-pinPZpackage Humanbodymodel(HBM),perAEC-Q100-002(1) ±2000 Chargeddevicemodel(CDM), Allpins ±500 V Electrostaticdischarge V (ESD) perAEC-Q100-011 Cornerpinson100-pinPZ: ±750 1,25,26,50,51,75,76,100 (1) AEC-Q100-002indicatesHBMstressingisdoneinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 5.3 ESD Ratings – Commercial VALUE UNIT TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801,TMS320F28016,and TMS320F28015in100-ballZGMpackage Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801,TMS320F28016,and TMS320F28015in100-ballGGMpackage Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 5.4 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Devicesupplyvoltage,I/O,V 3.14 3.3 3.47 V DDIO DevicesupplyvoltageCPU,V 1.71 1.8 1.89 V DD Supplyground,V ,V 0 V SS SSIO ADCsupplyvoltage(3.3V),V ,V 3.14 3.3 3.47 V DDA2 DDAIO ADCsupplyvoltage(1.8V),V ,V 1.71 1.8 1.89 V DD1A18 DD2A18 Flashsupplyvoltage,V 3.14 3.3 3.47 V DD3VFL Deviceclockfrequency(systemclock), 100-MHzdevices 2 100 MHz f SYSCLKOUT 60-MHzdevices 2 60 MHz High-levelinputvoltage,V AllinputsexceptX1 2 V +0.3 V IH DDIO X1 0.7*V –0.05 V DD DD Low-levelinputvoltage,V AllinputsexceptX1 V –0.3 0.8 V IL SS X1 0.3*V +0.05 DD High-leveloutputsourcecurrent, AllI/OsexceptGroup2 –4 mA VOH=2.4V,IOH Group2(1) –8 Low-leveloutputsinkcurrent, AllI/OsexceptGroup2 4 mA VOL=VOLMAX,IOL Group2(1) 8 Aversion –40 85 °C Sversion –40 125 Ambienttemperature,T A Qversion –40 125 (AEC-Q100 Qualification) (1) Group2pinsareasfollows:GPIO28,GPIO29,GPIO30,GPIO31,TDO,XCLKOUT,EMU0,andEMU1 22 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.5 Power Consumption Summary Table5-1.TMS320F2809,TMS320F2808 CurrentConsumptionbyPower-SupplyPinsat 100-MHz SYSCLKOUT IDD IDDIO(1) IDD3VFL(2) IDDA18(3) IDDA33(4) MODE TESTCONDITIONS TYP(5) MAX(6) TYP(5) MAX(6) TYP MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) Thefollowingperipheral clocksareenabled: • ePWM1/2/3/4/5/6 • eCAP1/2/3/4 • eQEP1/2 • eCAN-A • SCI-A/B • SPI-A • ADC Operational • I2C (Flash) AllPWMpinsaretoggled 195mA 230mA 15mA 27mA 35mA 40mA 30mA 38mA 1.5mA 2mA at100kHz. AllI/Opinsareleft unconnected. Dataiscontinuously transmittedoutofthe SCI-A,SCI-B,and eCAN-Aports.The hardwaremultiplieris exercised. Codeisrunningoutof flashwith3wait-states. XCLKOUTisturnedoff. Flashispowereddown. XCLKOUTisturnedoff. Thefollowingperipheral clocksareenabled: IDLE • eCAN-A 75mA 90mA 500μA 2mA 2μA 10μA 5μA 50μA 15μA 30μA • SCI-A • SPI-A • I2C Flashispowereddown. STANDBY 6mA 12mA 100μA 500μA 2μA 10μA 5μA 50μA 15μA 30μA Peripheralclocksareoff. Flashispowereddown. HALT Peripheralclocksareoff. 70μA 60μA 120μA 2μA 10μA 5μA 50μA 15μA 30μA Inputclockisdisabled. (1) I currentisdependentontheelectricalloadingontheI/Opins. DDIO (2) TheI currentindicatedinthistableistheflashread-currentanddoesnotincludeadditionalcurrentforerase/writeoperations. DD3VFL Duringflashprogramming,extracurrentisdrawnfromtheV andV rails,asindicatedinTable5-39.Iftheuserapplication DD DD3VFL involveson-boardflashprogramming,thisextracurrentmustbetakenintoaccountwhilearchitectingthepower-supplystage. (3) I includescurrentintoV andV pins.InordertorealizetheI currentsshownforIDLE,STANDBY,andHALT, DDA18 DD1A18 DD2A18 DDA18 clocktotheADCmodulemustbeturnedoffexplicitlybywritingtothePCLKCR0register. (4) I includescurrentintoV andV pins. DDA33 DDA2 DDAIO (5) TYPnumbersareapplicableoverroomtemperatureandnominalvoltage. (6) MAXnumbersareat125°CandMAXvoltage. NOTE The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumptiontables. Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 23 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table5-2.TMS320F2806CurrentConsumptionbyPower-SupplyPinsat100-MHzSYSCLKOUT IDD IDDIO(1) IDD3VFL(2) IDDA18(3) IDDA33(4) MODE TESTCONDITIONS TYP(5) MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) Thefollowingperipheral clocksareenabled: • ePWM1/2/3/4/5/6 • eCAP1/2/3/4 • eQEP1/2 • eCAN-A • SCI-A/B • SPI-A • ADC Operational • I2C 195mA 230mA 15mA 27mA 35mA 40mA 30mA 38mA 1.5mA 2mA (Flash) AllPWMpinsaretoggledat 100kHz. AllI/Opinsareleft unconnected. Dataiscontinuously transmittedoutoftheSCI- A,SCI-B,andeCAN-A ports.Thehardware multiplierisexercised. Codeisrunningoutofflash with3wait-states. XCLKOUTisturnedoff Flashispowereddown. XCLKOUTisturnedoff. Thefollowingperipheral clocksareenabled: IDLE • eCAN-A 75mA 90mA 500μA 2mA 2μA 10μA 5μA 50μA 15μA 30μA • SCI-A • SPI-A • I2C Flashispowereddown. STANDBY 6mA 12mA 100μA 500μA 2μA 10μA 5μA 50μA 15μA 30μA Peripheralclocksareoff. Flashispowereddown. HALT Peripheralclocksareoff. 70μA 60μA 120μA 2μA 10μA 5μA 50μA 15μA 30μA Inputclockisdisabled. (1) I currentisdependentontheelectricalloadingontheI/Opins. DDIO (2) TheI currentindicatedinthistableistheflashread-currentanddoesnotincludeadditionalcurrentforerase/writeoperations. DD3VFL Duringflashprogramming,extracurrentisdrawnfromtheV andV rails,asindicatedinTable5-39.Iftheuserapplication DD DD3VFL involveson-boardflashprogramming,thisextracurrentmustbetakenintoaccountwhilearchitectingthepower-supplystage. (3) I includescurrentintoV andV pins.InordertorealizetheI currentsshownforIDLE,STANDBY,andHALT, DDA18 DD1A18 DD2A18 DDA18 clocktotheADCmodulemustbeturnedoffexplicitlybywritingtothePCLKCR0register. (4) I includescurrentintoV andV pins. DDA33 DDA2 DDAIO (5) TYPnumbersareapplicableoverroomtemperatureandnominalvoltage. (6) MAXnumbersareat125°CandMAXvoltage. NOTE The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumptiontables. 24 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table5-3.TMS320F2802,TMS320F2801CurrentConsumptionbyPower-SupplyPinsat100-MHz SYSCLKOUT IDD IDDIO(1) IDD3VFL(2) IDDA18(3) IDDA33(4) MODE TESTCONDITIONS TYP(5) MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) TYP(5) MAX(6) Thefollowingperipheral clocksareenabled: • ePWM1/2/3 • eCAP1/2 • eQEP1 • eCAN-A • SCI-A • SPI-A • ADC Operational • I2C 180mA 210mA 15mA 27mA 35mA 40mA 30mA 38mA 1.5mA 2mA (Flash) AllPWMpinsaretoggledat 100kHz. AllI/Opinsareleft unconnected. Dataiscontinuously transmittedoutoftheSCI-A, SCI-B,andeCAN-Aports. Thehardwaremultiplieris exercised. Codeisrunningoutofflash with3wait-states. XCLKOUTisturnedoff. Flashispowereddown. XCLKOUTisturnedoff. Thefollowingperipheral clocksareenabled: IDLE • eCAN-A 75mA 90mA 500μA 2mA 2μA 10μA 5μA 50μA 15μA 30μA • SCI-A • SPI-A • I2C Flashispowereddown. STANDBY 6mA 12mA 100μA 500μA 2μA 10μA 5μA 50μA 15μA 30μA Peripheralclocksareoff. Flashispowereddown. HALT Peripheralclocksareoff. 70μA 60μA 120μA 2μA 10μA 5μA 50μA 15μA 30μA Inputclockisdisabled. (1) I currentisdependentontheelectricalloadingontheI/Opins. DDIO (2) TheI currentindicatedinthistableistheflashread-currentanddoesnotincludeadditionalcurrentforerase/writeoperations. DD3VFL Duringflashprogramming,extracurrentisdrawnfromtheV andV rails,asindicatedinTable5-39.Iftheuserapplication DD DD3VFL involveson-boardflashprogramming,thisextracurrentmustbetakenintoaccountwhilearchitectingthepower-supplystage. (3) I includescurrentintoV andV pins.InordertorealizetheI currentsshownforIDLE,STANDBY,andHALT, DDA18 DD1A18 DD2A18 DDA18 clocktotheADCmodulemustbeturnedoffexplicitlybywritingtothePCLKCR0register. (4) I includescurrentintoV andV pins. DDA33 DDA2 DDAIO (5) TYPnumbersareapplicableoverroomtemperatureandnominalvoltage. (6) MAXnumbersareat125°CandMAXvoltage. NOTE The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumptiontables. Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 25 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table5-4.TMS320C2802,TMS320C2801CurrentConsumptionbyPower-SupplyPinsat 100-MHzSYSCLKOUT IDD IDDIO(1) IDDA18(2) IDDA33(3) MODE TESTCONDITIONS TYP(4) MAX(5) TYP(4) MAX(5) TYP(4) MAX(5) TYP(4) MAX(5) Thefollowingperipheralclocks areenabled: • ePWM1/2/3 • eCAP1/2 • eQEP1 • eCAN-A • SCI-A • SPI-A Operational • ADC 150mA 165mA 5mA 10mA 30mA 38mA 1.5mA 2mA (ROM) • I2C AllPWMpinsaretoggledat 100kHz. AllI/Opinsareleftunconnected. Dataiscontinuouslytransmitted outoftheSCI-A,SCI-B,and eCAN-Aports.Thehardware multiplierisexercised. CodeisrunningoutofROMwith 3wait-states. XCLKOUTisturnedoff. XCLKOUTisturnedoff. Thefollowingperipheralclocks areenabled: IDLE • eCAN-A 75mA 90mA 500μA 2mA 5μA 50μA 15μA 30μA • SCI-A • SPI-A • I2C STANDBY Peripheralclocksareoff. 6mA 12mA 100μA 500μA 5μA 50μA 15μA 30μA Peripheralclocksareoff. HALT 70μA 80μA 120μA 5μA 50μA 15μA 30μA Inputclockisdisabled. (1) I currentisdependentontheelectricalloadingontheI/Opins. DDIO (2) I includescurrentintoV andV pins.InordertorealizetheI currentsshownforIDLE,STANDBY,andHALT, DDA18 DD1A18 DD2A18 DDA18 clocktotheADCmodulemustbeturnedoffexplicitlybywritingtothePCLKCR0register. (3) I includescurrentintoV andV pins. DDA33 DDA2 DDAIO (4) TYPnumbersareapplicableoverroomtemperatureandnominalvoltage. (5) MAXnumbersareat125°CandMAXvoltage. NOTE The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumptiontables. 26 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.5.1 Reducing Current Consumption 280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been removed,thefollowingnewperipheralshavebeenaddedonthe280x: • 3SPImodules • 1CANmodule • 1I2Cmodule The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6), eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs incorporate a unique method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 5-5 indicatesthetypicalreductionincurrentconsumptionachievedbyturningofftheclocks. Table5-5.TypicalCurrentConsumptionbyVarious Peripherals(at100MHz)(1) PERIPHERAL I CURRENT DD MODULE REDUCTION(mA)(2) ADC 8(3) I2C 5 eQEP 5 ePWM 5 eCAP 2 SCI 4 SPI 5 eCAN 11 (1) Allperipheralclocksaredisableduponreset.Writingto/readingfrom peripheralregistersispossibleonlyaftertheperipheralclocksare turnedon. (2) Forperipheralswithmultipleinstances,thecurrentquotedisper module.Forexample,the5mAnumberquotedforePWMisforone ePWMmodule. (3) Thisnumberrepresentsthecurrentdrawnbythedigitalportionof theADCmodule.TurningofftheclocktotheADCmoduleresultsin theeliminationofthecurrentdrawnbytheanalogportionoftheADC (I )aswell. DDA18 NOTE I currentconsumptionisreducedby15mA(typical)whenXCLKOUTisturnedoff. DDIO NOTE The baseline I current (current when the core is executing a dummy loop with no DD peripherals enabled) is 110 mA, typical. To arrive at the I current for a given application, DD the current-drawn by the peripherals (enabled by that application) must be added to the baselineI current. DD Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 27 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.5.2 Current Consumption Graphs 250.0 200.0 A) m 150.0 nt ( e rr 100.0 u C 50.0 0.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) IDD IDDA18 1.8-V current IDDIO IDD3VFL 3.3-V current Figure5-1.TypicalOperationalCurrentVersusFrequency (F2808) 600.0 500.0 400.0 W) 300.0 m r ( e 200.0 w o P e 100.0 c vi e D 0.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) TOTAL POWER Figure5-2.TypicalOperationalPowerVersusFrequency (F2808) NOTE Typical operational current for 60-MHz devices can be estimated from Figure 5-1. For I DD current alone, subtract the current contribution of non-existent peripherals after scaling the peripheralcurrentsfor60MHz.Forexample,tocomputethecurrentofF2801-60device,the contributionbythefollowingperipheralsmustbe subtractedfromI :ePWM4/5/6,eCAP3/4, DD eQEP2,SCI-B. 28 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Current VsSYSCLKOUT 200 180 160 140 A) m 120 ( t 100 n e r 80 r u C 60 40 20 0 10 20 30 40 50 60 70 80 90 10 SYSCLKOUT (MHz) IDD IDDA18 1.8vcurrent IDDIO IDD3VFL 3.3vcurrent Figure5-3.TypicalOperationalCurrentVersusFrequency(C280x) Device PowerVs SYSCLKOUT 400.0 ) W m 300.0 ( r e w 200.0 o P e 100.0 c vi e D 0.0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT (MHz) TOTALPOWER Figure5-4.TypicalOperationalPowerVersusFrequency(C280x) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 29 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.6 Electrical Characteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I =I MAX 2.4 OH OH V High-leveloutputvoltage V OH I =50μA V –0.2 OH DDIO V Low-leveloutputvoltage I =I MAX 0.4 V OL OL OL Pinwithpullup V =3.3V,V =0V AllI/Os(includingXRS) –80 –140 –190 Inputcurrent enabled DDIO IN I μA IL (lowlevel) Pinwithpulldown V =3.3V,V =0V ±2 enabled DDIO IN Pinwithpullup V =3.3V,V =V ±2 enabled DDIO IN DDIO Inputcurrent Pinwithpulldown I V =3.3V,V =V (F280x) 28 50 80 μA IH (highlevel) enabled DDIO IN DDIO Pinwithpulldown V =3.3V,V =V (C280x) 80 140 190 enabled DDIO IN DDIO Outputcurrent,pullupor I V =V or0V ±2 μA OZ pulldowndisabled O DDIO C Inputcapacitance 2 pF I 30 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.7 Thermal Resistance Characteristics for F280x 100-Ball GGM Package °C/W(1) AIRFLOW(lfm)(2) RΘ Junction-to-casethermalresistance 12.08 N/A JC RΘ Junction-to-boardthermalresistance 16.46 N/A JB 30.58 0 RΘ 29.31 150 JA Junction-to-freeairthermalresistance (HighkPCB) 28.09 250 26.62 500 0.4184 0 0.32 150 Psi Junction-to-packagetop JT 0.3725 250 0.4887 500 (1) ThesevaluesarebasedonaJEDECdefined2S2Psystem(withtheexceptionoftheThetaJC[RΘ ]value,whichisbasedona JC JEDECdefined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) lfm=linearfeetperminute 5.8 Thermal Resistance Characteristics for F280x 100-Pin PZ Package °C/W(1) AIRFLOW(lfm)(2) RΘ Junction-to-casethermalresistance 12.89 N/A JC RΘ Junction-to-boardthermalresistance 29.58 N/A JB 48.16 0 RΘ 40.06 150 JA Junction-to-freeairthermalresistance (HighkPCB) 37.96 250 35.17 500 0.3425 0 0.85 150 Psi Junction-to-packagetop JT 1.0575 250 1.410 500 (1) ThesevaluesarebasedonaJEDECdefined2S2Psystem(withtheexceptionoftheThetaJC[RΘ ]value,whichisbasedona JC JEDECdefined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) lfm=linearfeetperminute Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 31 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.9 Thermal Resistance Characteristics for C280x 100-Ball GGM Package °C/W(1) AIRFLOW(lfm)(2) RΘ Junction-to-casethermalresistance 14.18 N/A JC RΘ Junction-to-boardthermalresistance 21.36 N/A JB 36.33 0 RΘ 35.01 150 JA Junction-to-freeairthermalresistance (HighkPCB) 33.81 250 32.31 500 0.57 0 0.43 150 Psi Junction-to-packagetop JT 0.52 250 0.67 500 (1) ThesevaluesarebasedonaJEDECdefined2S2Psystem(withtheexceptionoftheThetaJC[RΘ ]value,whichisbasedona JC JEDECdefined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) lfm=linearfeetperminute 5.10 Thermal Resistance Characteristics for C280x 100-Pin PZ Package °C/W(1) AIRFLOW(lfm)(2) RΘ Junction-to-casethermalresistance 13.52 N/A JC RΘ Junction-to-boardthermalresistance 54.78 N/A JB 69.81 0 RΘ 60.34 150 JA Junction-to-freeairthermalresistance (HighkPCB) 57.46 250 53.63 500 0.42 0 1.23 150 Psi Junction-to-packagetop JT 1.54 250 2.11 500 (1) ThesevaluesarebasedonaJEDECdefined2S2Psystem(withtheexceptionoftheThetaJC[RΘ ]value,whichisbasedona JC JEDECdefined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) lfm=linearfeetperminute 32 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.11 Thermal Resistance Characteristics for F2809 100-Ball GGM Package °C/W(1) AIRFLOW(lfm)(2) RΘ Junction-to-casethermalresistance 10.36 N/A JC RΘ Junction-to-boardthermalresistance 13.3 N/A JB 28.15 0 RΘ 26.89 150 JA Junction-to-freeairthermalresistance (HighkPCB) 25.68 250 24.22 500 0.38 0 0.35 150 Psi Junction-to-packagetop JT 0.33 250 0.44 500 (1) ThesevaluesarebasedonaJEDECdefined2S2Psystem(withtheexceptionoftheThetaJC[RΘ ]value,whichisbasedona JC JEDECdefined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) lfm=linearfeetperminute 5.12 Thermal Resistance Characteristics for F2809 100-Pin PZ Package °C/W(1) AIRFLOW(lfm)(2) RΘ Junction-to-casethermalresistance 7.06 N/A JC RΘ Junction-to-boardthermalresistance 28.76 N/A JB 44.02 0 RΘ 28.34 150 JA Junction-to-freeairthermalresistance (HighkPCB) 36.28 250 33.68 500 0.2 0 0.56 150 Psi Junction-to-packagetop JT 0.7 250 0.95 500 (1) ThesevaluesarebasedonaJEDECdefined2S2Psystem(withtheexceptionoftheThetaJC[RΘ ]value,whichisbasedona JC JEDECdefined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) lfm=linearfeetperminute 5.13 Thermal Design Considerations Based on the end application design and operational profile, the I and I currents could vary. DD DDIO Systemswithmorethan1Wattpowerdissipationmayrequireaproductlevelthermaldesign.Careshould be taken to keep T within specified limits. In the end applications, T should be measured to estimate j case the operating junction temperature T. T is normally measured at the center of the package top side j case surface. The thermal application note Semiconductor and IC package thermal metrics helps to understand thethermalmetricsanddefinitions. Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 33 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14 Timing and Switching Characteristics 5.14.1 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,someofthepinnamesandotherrelatedterminologyhavebeenabbreviatedasfollows: Lowercasesubscriptsandtheir Lettersandsymbolsandtheir meanings: meanings: a accesstime H High c cycletime(period) L Low d delaytime V Valid Unknown,changing,ordon'tcare f falltime X level h holdtime Z Highimpedance r risetime su setuptime t transitiontime v validtime w pulseduration(width) 5.14.1.1 GeneralNotesonTimingParameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that alloutputtransitionsforagivenhalf-cycleoccurwithaminimumofskewingrelativetoeachother. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.Foractualcycleexamples,seetheappropriatecycledescriptionsectionofthisdocument. 5.14.1.2 TestLoadCircuit Thistestloadcircuitisusedtomeasureallswitchingcharacteristicsprovidedinthisdocument. Tester Pin Electronics Data Sheet Timing Reference Point 42W 3.5 nH Output Transmission Line Under Test Z0 = 50W(A) (B) Device Pin 4.0 pF 1.85 pF A. Inputrequirementsinthisdatasheetaretestedwithaninputslewrateof<4Voltspernanosecond(4V/ns)atthe devicepin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmissionlineeffectsmustbetakenintoaccount.Atransmissionlinewithadelayof2nsorlongercanbeusedto producethedesiredtransmission line effect.The transmission line is intendedas a loadonly. Itis notnecessary to addorsubtractthetransmissionlinedelay(2nsorlonger)fromthedatasheettiming. Figure5-5.3.3-VTestLoadCircuit 34 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.14.1.3 DeviceClockTable This section provides the timing requirements and switching characteristics for the various clock options availableonthe280xDSPs.Table5-6andTable5-7listthecycletimesofvariousclocks. Table5-6.TMS320x280xClockTableandNomenclature(100-MHzDevices) MIN NOM MAX UNIT On-chiposcillator tc(OSC),Cycletime 28.6 50 ns clock Frequency 20 35 MHz t ,Cycletime 10 250 ns XCLKIN(1) c(CI) Frequency 4 100 MHz t ,Cycletime 10 500 ns c(SCO) SYSCLKOUT Frequency 2 100 MHz t ,Cycletime 10 2000 ns c(XCO) XCLKOUT Frequency 0.5 100 MHz t ,Cycletime 10 20(3) ns HSPCLK(2) c(HCO) Frequency 50(3) 100 MHz t ,Cycletime 10 40(3) ns LSPCLK(2) c(LCO) Frequency 25(3) 100 MHz t ,Cycletime(AlldevicesexceptF2809) 80 ns c(ADCCLK) Frequency(AlldevicesexceptF2809) 12.5 MHz ADCclock t ,Cycletime(F2809) 40 ns c(ADCCLK) Frequency(F2809) 25 MHz (1) ThisalsoappliestotheX1pinifa1.8-Voscillatorisused. (2) LowerLSPCLKandHSPCLKwillreducedevicepowerconsumption. (3) ThisisthedefaultresetvalueifSYSCLKOUT=100MHz. Table5-7.TMS320x280x/2801xClockTableandNomenclature(60-MHzDevices) MIN NOM MAX UNIT On-chiposcillator tc(OSC),Cycletime 28.6 50 ns clock Frequency 20 35 MHz t ,Cycletime 16.67 250 ns XCLKIN(1) c(CI) Frequency 4 60 MHz t ,Cycletime 16.67 500 ns c(SCO) SYSCLKOUT Frequency 2 60 MHz t ,Cycletime 16.67 2000 ns c(XCO) XCLKOUT Frequency 0.5 60 MHz t ,Cycletime 16.67 33.3(3) ns HSPCLK(2) c(HCO) Frequency 30(3) 60 MHz t ,Cycletime 16.67 66.7(3) ns LSPCLK(2) c(LCO) Frequency 15(3) 60 MHz t ,Cycletime 133.33 ns c(ADCCLK) ADCclock Frequency 7.5 MHz (1) ThisalsoappliestotheX1pinifa1.8-Voscillatorisused. (2) LowerLSPCLKandHSPCLKwillreducedevicepowerconsumption. (3) ThisisthedefaultresetvalueifSYSCLKOUT=60MHz. Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 35 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.2 Power Sequencing No requirements are placed on the power up/down sequence of the various power pins to ensure the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the V (core voltage) DD pins prior to or simultaneously with the V (input/output voltage) pins, ensuring that the V pins have DDIO DD reached0.7VbeforetheV pinsreach0.7V. DDIO TherearesomerequirementsontheXRSpin: 1. Duringpowerup,theXRSpinmustbeheldlowfort aftertheinputclockisstable(seeTable5- w(RSL1) 8).Thisistoenabletheentiredevicetostartfromaknowncondition. 2. Duringpowerdown,theXRSpinmustbepulledlowatleast8μspriortoV reaching1.5V.Thisisto DD enhanceflashreliability. No voltage larger than a diode drop (0.7 V) above V should be applied to any digital pin (for analog DDIO pins, it is 0.7 V above V ) prior to powering up the device. Voltages applied to pins on an unpowered DDA devicecanbiasinternalp-njunctionsinunintendedwaysandproduceunpredictableresults. 36 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 VDDIO, VDD3VFL VDDA2, VDDAIO (3.3 V) VDD, VDD1A18, VDD2A18 (1.8 V) XCLKIN X1/X2 XCLKOUT OSCCLK/8(A) User-Code Dependent tOSCST tw(RSL1) XRS Address/Data Valid. Internal Boot-ROM Code Execution Phase Address/Data/ Control (Internal) td(EX) User-Code Execution Phase th(boot-mode)(B) User-Code Dependent Boot-Mode GPIO Pins as Input Pins Peripheral/GPIO Function Boot-ROM Execution Starts Based on Boot Code I/O Pins(C) GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent A. Uponpowerup,SYSCLKOUTisOSCCLK/2.SincetheXCLKOUTDIVbitsintheXCLKregistercomeupwithareset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/8duringthisphase. B. Afterreset,thebootROMcodesamplesBootModepins.BasedonthestatusoftheBootModepin,thebootcode branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debuggerenvironment),thebootcodeexecutiontimeisbasedonthecurrentSYSCLKOUTspeed.TheSYSCLKOUT willbebasedonuserenvironmentandcouldbewithorwithoutPLLenabled. C. SeeSection5.14.2forrequirementstoensureahigh-impedancestateforGPIOpinsduringpower-up. Figure5-6.Power-onReset Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 37 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table5-8.Reset(XRS)TimingRequirements MIN NOM MAX UNIT t (1) Pulseduration,stableXCLKINtoXRShigh 8t cycles w(RSL1) c(OSCCLK) t Pulseduration,XRSlow Warmreset 8t cycles w(RSL2) c(OSCCLK) Pulseduration,resetpulsegeneratedby t 512t cycles w(WDRS) watchdog c(OSCCLK) t Delaytime,address/datavalidafterXRShigh 32t cycles d(EX) c(OSCCLK) t (2) Oscillatorstart-uptime 1 10 ms OSCST t Holdtimeforboot-modepins 200t cycles h(boot-mode) c(OSCCLK) (1) Inadditiontothet requirement,XRShastobelowatleastfor1msafterV reaches1.5V. w(RSL1) DD (2) Dependentoncrystal/resonatorandboarddesign. XCLKIN X1/X2 XCLKOUT OSCCLK/8 OSCCLK * 5 User-Code Dependent tw(RSL2) XRS User-Code Execution Phase td(EX) Address/Data/ Control User-Code Execution (Don’t Care) (Internal) Boot-ROM Execution Starts th(boot-mode)(A) Boot-Mode Peripheral/GPIO Function GPIO Pins as Input Peripheral/GPIO Function Pins User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent A. Afterreset,theBootROMcodesamplesBOOTModepins.BasedonthestatusoftheBootModepin,thebootcode branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUTwillbebasedonuserenvironmentandcouldbewithorwithoutPLLenabled. Figure5-7.WarmReset 38 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Figure 5-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency,OSCCLKx4. OSCCLK Write to PLLCR SYSCLKOUT OSCCLK * 2 OSCCLK/2 OSCCLK * 4 (Current CPU (CPU Frequency While PLL is Stabilizing (Changed CPU Frequency) Frequency) With the Desired Frequency. This Period (PLL Lock-up Time, tp) is 131072 OSCCLK Cycles Long.) Figure5-8.ExampleofEffectofWritingIntoPLLCRRegister Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 39 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.3 Clock Requirements and Characteristics Table5-9.InputClockFrequency PARAMETER MIN TYP MAX UNIT Resonator(X1/X2) 20 35 Crystal(X1/X2) 20 35 f Inputclockfrequency MHz x Externaloscillator/clock 100-MHzdevice 4 100 source(XCLKINorX1pin) 60-MHzdevice 4 60 f LimpmodeSYSCLKOUTfrequencyrange(with/2enabled) 1–5 MHz l Table5-10.XCLKIN(1)TimingRequirements-PLLEnabled NO. MIN MAX UNIT C8 t Cycletime,XCLKIN 33.3 200 ns c(CI) C9 t Falltime,XCLKIN 6 ns f(CI) C10 t Risetime,XCLKIN 6 ns r(CI) C11 t Pulseduration,XCLKINlowasapercentageoft 45% 55% w(CIL) c(OSCCLK) C12 t Pulseduration,XCLKINhighasapercentageoft 45% 55% w(CIH) c(OSCCLK) (1) ThisappliestotheX1pinalso. Table5-11.XCLKIN(1)TimingRequirements-PLLDisabled NO. MIN MAX UNIT 100-MHzdevice 10 250 C8 t Cycletime,XCLKIN ns c(CI) 60-MHzdevice 16.67 250 Upto20MHz 6 ns C9 t Falltime,XCLKIN f(CI) 20MHzto100MHz 2 ns Upto20MHz 6 ns C10 t Risetime,XCLKIN r(CI) 20MHzto100MHz 2 ns C11 t Pulseduration,XCLKINlowasapercentageoft 45% 55% w(CIL) c(OSCCLK) C12 t Pulseduration,XCLKINhighasapercentageoft 45% 55% w(CIH) c(OSCCLK) (1) ThisappliestotheX1pinalso. ThepossibleconfigurationmodesareshowninTable6-33. Table5-12.XCLKOUTSwitchingCharacteristics(PLLBypassedorEnabled)(1) (2) NO. PARAMETER MIN TYP MAX UNIT 100-MHzdevice 10 C1 t Cycletime,XCLKOUT ns c(XCO) 60-MHzdevice 16.67 C3 t Falltime,XCLKOUT 2 ns f(XCO) C4 t Risetime,XCLKOUT 2 ns r(XCO) C5 t Pulseduration,XCLKOUTlow H–2 H+2 ns w(XCOL) C6 t Pulseduration,XCLKOUThigh H–2 H+2 ns w(XCOH) t PLLlocktime 131072t (3) cycles p c(OSCCLK) (1) Aloadof40pFisassumedfortheseparameters. (2) H=0.5t c(XCO) (3) OSCCLKiseithertheoutputoftheon-chiposcillatorortheoutputfromanexternaloscillator. 40 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 C10 C9 C8 XCLKIN(A) C3 C6 C1 C4 C5 XCLKOUT(B) A. TherelationshipofXCLKINtoXCLKOUTdependsonthedividefactorchosen.Thewaveformrelationshipshownis intendedtoillustratethetimingparametersonlyandmaydifferbasedonactualconfiguration. B. XCLKOUTconfiguredtoreflectSYSCLKOUT. Figure5-9.ClockTiming Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 41 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.4 Peripherals 5.14.4.1 General-PurposeInput/Output(GPIO) 5.14.4.1.1 GPIO-OutputTiming Table5-13.General-PurposeOutputSwitchingCharacteristics PARAMETER MIN MAX UNIT t Risetime,GPIOswitchinglowtohigh AllGPIOs 8 ns r(GPO) t Falltime,GPIOswitchinghightolow AllGPIOs 8 ns f(GPO) t Togglingfrequency,GPOpins 25 MHz fGPO GPIO tr(GPO) tf(GPO) Figure5-10. General-PurposeOutputTiming 5.14.4.1.2 GPIO-InputTiming Table5-14. General-PurposeInputTimingRequirements MIN MAX UNIT QUALPRD=0 1t cycles c(SCO) t Samplingperiod w(SP) QUALPRD≠0 2t *QUALPRD cycles c(SCO) t Inputqualifiersamplingwindow t *(n(1)–1) cycles w(IQSW) w(SP) Synchronousmode 2t cycles t (2) Pulseduration,GPIOlow/high c(SCO) w(GPI) Withinputqualifier t +t +1t cycles w(IQSW) w(SP) c(SCO) (1) "n"representsthenumberofqualificationsamplesasdefinedbyGPxQSELnregister. (2) Fort ,pulsewidthismeasuredfromV toV foranactivelowsignalandV toV foranactivehighsignal. w(GPI) IL IL IH IH 42 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 (A) GPIO Signal GPxQSELn = 1,0 (6 samples) 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 tw(SP) Sampling Period determined by GPxCTRL[QUALPRD](B) tw(IQSW) Sampling Window (SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)) SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (D) Output From Qualifier A. Thisglitchwillbeignoredbytheinputqualifier.TheQUALPRDbitfieldspecifiesthequalificationsamplingperiod.It canvaryfrom00to0xFF.IfQUALPRD=00,thenthesamplingperiodis1SYSCLKOUTcycle.Foranyothervalue "n", thequalificationsampling periodin2n SYSCLKOUT cycles(thatis,atevery2n SYSCLKOUT cycles,theGPIO pinwillbesampled). B. ThequalificationperiodselectedviatheGPxCTRLregisterappliestogroupsof8GPIOpins. C. Thequalificationblockcantakeeitherthreeorsixsamples.TheGPxQSELnRegisterselectswhichsamplemodeis used. D. Intheexampleshown,forthequalifiertodetectthechange,theinputshouldbestablefor10SYSCLKOUTcyclesor greater.Inotherwords,theinputsshouldbestablefor(5xQUALPRDx2)SYSCLKOUTcycles.Thiswouldensure 5samplingperiodsfordetectiontooccur.Sinceexternalsignalsaredrivenasynchronously,an13-SYSCLKOUT-wide pulseensuresreliablerecognition. Figure5-11.SamplingMode Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 43 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.4.1.3 SamplingWindowWidthforInputSignals The following section summarizes the sampling window width for input signals for various input qualifier configurations. SamplingfrequencydenoteshowoftenasignalissampledwithrespecttoSYSCLKOUT. Samplingfrequency=SYSCLKOUT/(2*QUALPRD),ifQUALPRD ≠ 0 Samplingfrequency=SYSCLKOUT,ifQUALPRD=0 Samplingperiod=SYSCLKOUTcyclex2xQUALPRD,ifQUALPRD ≠ 0 Intheaboveequations,SYSCLKOUTcycleindicatesthetimeperiodofSYSCLKOUT. Samplingperiod=SYSCLKOUTcycle,ifQUALPRD=0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of thesignal.ThisisdeterminedbythevaluewrittentoGPxQSELnregister. Case1: Qualificationusing3samples Samplingwindowwidth=(SYSCLKOUTcyclex2xQUALPRD)x2,ifQUALPRD ≠ 0 Samplingwindowwidth=(SYSCLKOUTcycle)x2,ifQUALPRD=0 Case2: Qualificationusing6samples Samplingwindowwidth=(SYSCLKOUTcyclex2xQUALPRD)x5,ifQUALPRD ≠ 0 Samplingwindowwidth=(SYSCLKOUTcycle)x5,ifQUALPRD=0 SYSCLK GPIOxn t w(GPI) Figure5-12.General-PurposeInputTiming NOTE Thepulse-widthrequirementforgeneral-purposeinputisapplicablefortheXINT2_ADCSOC signalaswell. 44 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.14.4.1.4 Low-PowerModeWakeupTiming Table 5-15 shows the timing requirements, Table 5-16 shows the switching characteristics, and Figure 5- 13showsthetimingdiagramforIDLEmode. Table5-15.IDLEModeTimingRequirements(1) MIN MAX UNIT Withoutinputqualifier 2t c(SCO) t Pulseduration,externalwake-upsignal cycles w(WAKE-INT) Withinputqualifier 5t +t c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. Table5-16.IDLEModeSwitchingCharacteristics(1) PARAMETER TESTCONDITIONS MIN MAX UNIT Delaytime,externalwakesignaltoprogram executionresume (2) • Wake-upfromFlash Withoutinputqualifier 20tc(SCO) cycles – Flashmoduleinactivestate Withinputqualifier 20t +t c(SCO) w(IQSW) t d(WAKE-IDLE) • Wake-upfromFlash Withoutinputqualifier 1050tc(SCO) cycles – Flashmoduleinsleepstate Withinputqualifier 1050t +t c(SCO) w(IQSW) • Wake-upfromSARAM Withoutinputqualifier 20tc(SCO) cycles Withinputqualifier 20t +t c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. (2) ThisisthetimetakentobeginexecutionoftheinstructionthatimmediatelyfollowstheIDLEinstruction.executionofanISR(triggered bythewakeup)signalinvolvesadditionallatency. td(WAKE−IDLE) Address/Data (internal) XCLKOUT tw(WAKE−INT) WAKE INT(A) A. WAKEINTcanbeanyenabledinterrupt,WDINT,XNMI,orXRS. Figure5-13.IDLEEntryandExitTiming Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 45 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table5-17.STANDBYModeTimingRequirements TESTCONDITIONS MIN MAX UNIT Pulseduration,external Withoutinputqualification 3tc(OSCCLK) t cycles w(WAKE-INT) wake-upsignal Withinputqualification(1) (2+QUALSTDBY)*t c(OSCCLK) (1) QUALSTDBYisa6-bitfieldintheLPMCR0register. Table5-18.STANDBYModeSwitchingCharacteristics PARAMETER TESTCONDITIONS MIN MAX UNIT Delaytime,IDLEinstruction t 32t 45t cycles d(IDLE-XCOL) executedtoXCLKOUTlow c(SCO) c(SCO) Delaytime,externalwakesignalto programexecutionresume(1) • Wakeupfromflash Withoutinputqualifier 100tc(SCO) cycles – Flashmoduleinactivestate Withinputqualifier 100t +t c(SCO) w(WAKE-INT) t d(WAKE-STBY) • Wakeupfromflash Withoutinputqualifier 1125tc(SCO) cycles – Flashmoduleinsleepstate Withinputqualifier 1125t +t c(SCO) w(WAKE-INT) Withoutinputqualifier 100t c(SCO) • WakeupfromSARAM cycles Withinputqualifier 100t +t c(SCO) w(WAKE-INT) (1) ThisisthetimetakentobeginexecutionoftheinstructionthatimmediatelyfollowstheIDLEinstruction.executionofanISR(triggered bythewakeupsignal)involvesadditionallatency. (A) (C) (E) (B) (D) (F) Device STANDBY STANDBY Normal Execution Status Flushing Pipeline Wake−up Signal tw(WAKE-INT) td(WAKE-STBY) X1/X2 or X1 or XCLKIN XCLKOUT td(IDLE−XCOL) A. IDLEinstructionisexecutedtoputthedeviceintoSTANDBYmode. B. ThePLLblockrespondstotheSTANDBYsignal.SYSCLKOUTisheldforapproximately32cycles(ifCLKINDIV=0) or 64 cycles (if CLKINDIV = 1) before being turned off. This delay enables the CPU pipe and any other pending operationstoflushproperly. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBYmode. D. Theexternalwake-upsignalisdrivenactive. E. Afteralatencyperiod,theSTANDBYmodeisexited. F. Normalexecutionresumes.Thedevicewillrespondtotheinterrupt(ifenabled). Figure5-14.STANDBYEntryandExitTimingDiagram 46 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table5-19.HALTModeTimingRequirements MIN MAX UNIT t Pulseduration,GPIOwake-upsignal t +2t (1) cycles w(WAKE-GPIO) oscst c(OSCCLK) t Pulseduration,XRSwakeupsignal t +8t cycles w(WAKE-XRS) oscst c(OSCCLK) (1) SeeTable5-8foranexplanationoft . oscst Table5-20.HALTModeSwitchingCharacteristics PARAMETER MIN MAX UNIT t Delaytime,IDLEinstructionexecutedtoXCLKOUTlow 32t 45t cycles d(IDLE-XCOL) c(SCO) c(SCO) t PLLlock-uptime 131072t cycles p c(OSCCLK) Delaytime,PLLlocktoprogramexecutionresume • Wakeupfromflash 1125tc(SCO) cycles t d(WAKE-HALT) – Flashmoduleinsleepstate • WakeupfromSARAM 35tc(SCO) cycles (A) (C) (E) (G) (B) (D) (F) Device Status HALT HALT Flushing Pipeline PLL Lock-up Time Normal Wake-up Latency Execution GPIOn td(WAKE−HALT) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) A. IDLEinstructionisexecutedtoputthedeviceintoHALTmode. B. ThePLLblockrespondstotheHALTsignal.SYSCLKOUT is heldfor approximately32 cycles(if CLKINDIV=0)or 64 cycles (if CLKINDIV = 1) before the oscillator is turned off and the CLKIN to the core is stopped. This delay enablestheCPUpipeandanyotherpendingoperationstoflushproperly. C. ClockstotheperipheralsareturnedoffandthePLLisshutdown.Ifaquartzcrystalorceramicresonatorisusedas the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absoluteminimumpower. D. WhentheGPIOnpin(usedtobringthedeviceoutofHALT)isdrivenlow,theoscillatoristurnedonandtheoscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to enteringandduringHALTmode. E. Oncetheoscillatorhasstabilized,thePLLlocksequenceisinitiated,whichtakes131,072OSCCLK(X1/X2orX1or XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code executionwillbedelayedbythisdurationevenwhenthePLLisdisabled). F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt(ifenabled),afteralatency. G. Normaloperationresumes. Figure5-15.HALTWake-UpUsingGPIOn Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 47 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.4.2 EnhancedControlPeripherals 5.14.4.2.1 EnhancedPulseWidthModulator(ePWM)Timing PWM refers to PWM outputs on ePWM1–6. Table 5-21shows the PWM timing requirements and Table 5- 22,switchingcharacteristics. Table5-21.ePWMTimingRequirements(1) TESTCONDITIONS MIN MAX UNIT t Syncinputpulsewidth Asynchronous 2t cycles w(SYCIN) c(SCO) Synchronous 2t cycles c(SCO) Withinputqualifier 1t +t cycles c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. Table5-22.ePWMSwitchingCharacteristics PARAMETER TESTCONDITIONS MIN MAX UNIT t Pulseduration,PWMxoutputhigh/low 20 ns w(PWM) t Syncoutputpulsewidth 8t cycles w(SYNCOUT) c(SCO) t Delaytime,tripinputactivetoPWMforcedhigh nopinload d(PWM)tza 25 ns Delaytime,tripinputactivetoPWMforcedlow t Delaytime,tripinputactivetoPWMHi-Z 20 ns d(TZ-PWM)HZ 5.14.4.2.2 Trip-ZoneInputTiming Table5-23.Trip-ZoneinputTimingRequirements(1) MIN MAX UNIT Asynchronous 1t cycles c(SCO) t Pulseduration,TZxinputlow Synchronous 2t cycles w(TZ) c(SCO) Withinputqualifier 1t +t cycles c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. SYSCLK t w(TZ) (A) TZ t d(TZ-PWM)HZ (B) PWM A. TZ:TZ1,TZ2,TZ3,TZ4,TZ5,TZ6 B. PWMreferstoallthePWMpinsinthedevice.ThestateofthePWMpinsafterTZistakenhighdependsonthePWM recoverysoftware. Figure5-16.PWMHi-ZCharacteristics 48 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.14.4.2.3 High-ResolutionPWMTiming Table5-24showsthehigh-resolutionPWMswitchingcharacteristics. Table5-24.High-ResolutionPWMCharacteristicsatSYSCLKOUT= 60–100MHz MIN TYP MAX UNIT MicroEdgePositioning(MEP)stepsize(1) 150 310 ps (1) TheMEPstepsizewillbelargestathightemperatureandminimumvoltageonV .MEPstepsizewillincreasewithhigher DD temperatureandlowervoltageanddecreasewithlowertemperatureandhighervoltage. ApplicationsthatusetheHRPWMfeatureshoulduseMEPScaleFactorOptimizer(SFO)estimationsoftwarefunctions.SeetheTI softwarelibrariesfordetailsofusingSFOfunctioninendapplications.SFOfunctionshelptoestimatethenumberofMEPstepsper SYSCLKOUTperioddynamicallywhiletheHRPWMisinoperation. 5.14.4.2.4 EnhancedCapture(eCAP)Timing Table5-25showstheeCAPtimingrequirementandTable5-26showstheeCAPswitchingcharacteristics. Table5-25.EnhancedCapture(eCAP)TimingRequirement(1) TESTCONDITIONS MIN MAX UNIT Asynchronous 2t c(SCO) t Captureinputpulsewidth Synchronous 2t cycles w(CAP) c(SCO) Withinputqualifier 1t +t c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. Table5-26.eCAPSwitchingCharacteristics PARAMETER TESTCONDITIONS MIN MAX UNIT t Pulseduration,APWMxoutputhigh/low 20 ns w(APWM) 5.14.4.2.5 EnhancedQuadratureEncoderPulse(eQEP)Timing Table 5-27 shows the eQEP timing requirement and Table 5-28 shows the eQEP switching characteristics. Table5-27.EnhancedQuadratureEncoderPulse(eQEP)TimingRequirements(1) TESTCONDITIONS MIN MAX UNIT Asynchronous(2)/synchronous 2t c(SCO) t QEPinputperiod cycles w(QEPP) Withinputqualifier 2[1t +t ] c(SCO) w(IQSW) Asynchronous(2)/synchronous 2t c(SCO) t QEPIndexInputHightime cycles w(INDEXH) Withinputqualifier 2t +t c(SCO) w(IQSW) Asynchronous(2)/synchronous 2t c(SCO) t QEPIndexInputLowtime cycles w(INDEXL) Withinputqualifier 2t +t c(SCO) w(IQSW) Asynchronous(2)/synchronous 2t c(SCO) t QEPStrobeHightime cycles w(STROBH) Withinputqualifier 2t +t c(SCO) w(IQSW) Asynchronous(2)/synchronous 2t c(SCO) t QEPStrobeInputLowtime cycles w(STROBL) Withinputqualifier 2t +t c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. (2) RefertotheTMS320F280x,TMS320C280x,TMS320F2801xDSPssiliconerrataforlimitationsintheasynchronousmode. Table5-28.eQEPSwitchingCharacteristics PARAMETER TESTCONDITIONS MIN MAX UNIT t Delaytime,externalclocktocounterincrement 4t cycles d(CNTR)xin c(SCO) t Delaytime,QEPinputedgetopositioncomparesyncoutput 6t cycles d(PCS-OUT)QEP c(SCO) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 49 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.4.2.6 ADCStart-of-ConversionTiming Table5-29. ExternalADCStart-of-ConversionSwitchingCharacteristics PARAMETER MIN MAX UNIT t Pulseduration,ADCSOCAOlow 32t cycles w(ADCSOCAL) c(HCO) tw(ADCSOCAL) ADCSOCAO or ADCSOCBO Figure5-17. ADCSOCAOor ADCSOCBOTiming 5.14.4.3 ExternalInterruptTiming Table5-30.ExternalInterruptTimingRequirements(1) MIN MAX UNIT Synchronous 1t t (2) Pulseduration,INTinputlow/high c(SCO) cycles w(INT) Withqualifier 1t +t c(SCO) w(IQSW) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. (2) ThistimingisapplicabletoanyGPIOpinconfiguredforADCSOCfunctionality. Table5-31. ExternalInterruptSwitchingCharacteristics(1) PARAMETER MIN MAX UNIT t Delaytime,INTlow/hightointerrupt-vectorfetch t +12t cycles d(INT) w(IQSW) c(SCO) (1) Foranexplanationoftheinputqualifierparameters,seeTable5-14. tw(INT) XNMI, XINT1, XINT2 td(INT) Address bus Interrupt Vector (internal) Figure5-18.ExternalInterruptTiming 50 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.14.4.4 I2CElectricalSpecificationandTiming Table5-32.I2CTiming TESTCONDITIONS MIN MAX UNIT I2Cclockmodulefrequencyisbetween 7MHzand12MHzandI2Cprescalerand f SCLclockfrequency 400 kHz SCL clockdividerregistersareconfigured appropriately V Lowlevelinputvoltage 0.3V V il DDIO V Highlevelinputvoltage 0.7V V ih DDIO V Inputhysteresis 0.05V V hys DDIO V Lowleveloutputvoltage 3mAsinkcurrent 0 0.4 V ol I2Cclockmodulefrequencyisbetween 7MHzand12MHzandI2Cprescalerand t LowperiodofSCLclock 1.3 μs LOW clockdividerregistersareconfigured appropriately I2Cclockmodulefrequencyisbetween 7MHzand12MHzandI2Cprescalerand t HighperiodofSCLclock 0.6 μs HIGH clockdividerregistersareconfigured appropriately Inputcurrentwithaninputvoltage l –10 10 μA I between0.1V and0.9V MAX DDIO DDIO Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 51 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.4.5 SerialPeripheralInterface(SPI)Timing ThissectioncontainsbothMasterModeandSlaveModetimingdata. 5.14.4.5.1 SPIMasterModeTiming Table 5-33 lists the master mode timing (clock phase = 0) and Table 5-34 lists the master mode timing (clockphase=1).Figure5-19andFigure5-20showthetimingwaveforms. Table5-33.SPIMasterModeExternalTiming(ClockPhase=0)(1)(2)(3)(4)(5) BRREVEN BRRODD NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycletime,SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns 2 tw(SPC1)M Ppuullsseeduration,SPICLKfirst 0.5tc(SPC)M–10 0.5tc(SPC)M+10 0.5tc(0L.S5PtCc(LSKP)C–)M1+0 0.5tc(0L.S5PtCc(LSKP)C+)M1+0 ns 3 tw(SPC2)M Ppuullsseeduration,SPICLKsecond 0.5tc(SPC)M–10 0.5tc(SPC)M+10 0.5tc(0L.S5PtCc(LSKP)C–)M10– 0.5tc(0LS.5PtCcL(SKP)C+)M1–0 ns Delaytime,SPICLKto 4 td(SIMO)M SPISIMOvalid 10 10 ns 5 tv(SIMO)M VSaPlIiCdLtiKme,SPISIMOvalidafter 0.5tc(SPC)M–10 0.5tc(0L.S5PtCc(LSKP)C–)M10– ns Setuptime,SPISOMIbefore 8 tsu(SOMI)M SPICLK 35 35 ns Holdtime,SPISOMIvalidafter 9 th(SOMI)M SPICLK 0 0 ns 23 td(SPC)M DSPelIaCyLtKime,SPISTEactiveto 3tc(1S.Y5StCc(LSKP)C–)M10– 3tc(1S.Y5StCc(LSKP)C–)M10– ns 24 td(STE)M Dinealcatyivetime,SPICLKtoSPISTE 0.5tc(SPC)M–10 0.5tc(0L.S5PtCc(LSKP)C–)M10– ns (1) TheMASTER/SLAVEbit(SPICTL.2)issetandtheCLOCKPHASEbit(SPICTL.3)iscleared. (2) t =SPIclockcycletime=LSPCLK/4orLSPCLK/(SPIBRR+1) c(SPC) (3) t =LSPCLKcycletime c(LCO) (4) InternalclockprescalersmustbeadjustedsuchthattheSPIclockspeedislimitedtothefollowingSPIclockrate: Mastermodetransmit25-MHzMAX,mastermodereceive12.5-MHzMAX Slavemodetransmit12.5-MAX,slavemodereceive12.5-MHzMAX. (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheclockpolaritybit(SPICCR.6). 52 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 Master In Data SPISOMI Must Be Valid 23 24 SPISTE Figure5-19.SPIMasterModeExternalTiming(ClockPhase=0) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 53 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table5-34.SPIMasterModeExternalTiming(ClockPhase=1)(1)(2)(3)(4)(5) BRREVEN BRRODD NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycletime,SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns 2 tw(SPC1)M Ppuullsseeduration,SPICLKfirst 0.5tc(SPC)M–10 0.5tc(SPC)M+10 0.5tc(0L.S5PtCc(LSKP)C–)M10– 0.5tc(0LS.5PtCcL(SKP)C+)M1–0 ns 3 tw(SPC2)M Ppuullsseeduration,SPICLKsecond 0.5tc(SPC)M–10 0.5tc(SPC)M+10 0.5tc(0L.S5PtCc(LSKP)C–)M1+0 0.5tc(0L.S5PtCc(LSKP)C+)M1+0 ns 6 td(SIMO)M DSPelIaCyLtKime,SPISIMOvalidto 0.5tc(SPC)M–10 0.5tc(0L.S5PtCc(LSKP)C–)M1+0 ns 7 tv(SIMO)M VSaPlIiCdLtiKme,SPISIMOvalidafter 0.5tc(SPC)M–10 0.5tc(0L.S5PtCc(LSKP)C–)M10– ns Setuptime,SPISOMIbefore 10 tsu(SOMI)M SPICLK 35 35 ns Holdtime,SPISOMIvalidafter 11 th(SOMI)M SPICLK 0 0 ns 23 td(SPC)M DSPelIaCyLtKime,SPISTEactiveto 3tc(SY2StCc(LSKP)C–)M10– 3tc(SY2StCc(LSKP)C–)M10– ns 24 td(STE)M Dinealcatyivetime,SPICLKtoSPISTE 0.5tc(SPC)–10 0.5tc(LS0P.5CtLcK(S)P–C1)0– ns (1) TheMASTER/SLAVEbit(SPICTL.2)issetandtheCLOCKPHASEbit(SPICTL.3)isset. (2) t =SPIclockcycletime=LSPCLK/4orLSPCLK/(SPIBRR+1) c(SPC) (3) InternalclockprescalersmustbeadjustedsuchthattheSPIclockspeedislimitedtothefollowingSPIclockrate: Mastermodetransmit25MHzMAX,mastermodereceive12.5MHzMAX Slavemodetransmit12.5MHzMAX,slavemodereceive12.5MHzMAX. (4) t =LSPCLKcycletime c(LCO) (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPICCR.6). 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 SPISIMO Master Out Data Is Valid 10 11 SPISOMI Master In Data Must Be Valid 24 23 SPISTE Figure5-20.SPIMasterModeExternalTiming(ClockPhase=1) 54 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.14.4.5.2 SPISlaveModeTiming Table 5-35 lists the slave mode timing (clock phase = 0) and Table 5-36 lists the slave mode timing (clock phase=1).Figure5-21andFigure5-22showthetimingwaveforms. Table5-35.SPISlaveModeExternalTiming(ClockPhase=0)(1)(2)(3)(4)(5) NO. PARAMETER MIN MAX UNIT 12 t Cycletime,SPICLK 4t ns c(SPC)S c(SYSCLK) 13 t Pulseduration,SPICLKfirstpulse 2t –1 ns w(SPC1)S c(SYSCLK) 14 t Pulseduration,SPICLKsecondpulse 2t –1 ns w(SPC2)S c(SYSCLK) 15 t Delaytime,SPICLKtoSPISOMIvalid 35 ns d(SOMI)S 16 t Validtime,SPISOMIdatavalidafterSPICLK 0 ns v(SOMI)S 19 t Setuptime,SPISIMOvalidbeforeSPICLK 1.5t ns su(SIMO)S c(SYSCLK) 20 t Holdtime,SPISIMOdatavalidafterSPICLK 1.5t ns h(SIMO)S c(SYSCLK) 25 t Setuptime,SPISTEactivebeforeSPICLK 1.5t ns su(STE)S c(SYSCLK) 26 t Holdtime,SPISTEinactiveafterSPICLK 1.5t ns h(STE)S c(SYSCLK) (1) TheMASTER/SLAVEbit(SPICTL.2)isclearedandtheCLOCKPHASEbit(SPICTL.3)iscleared. (2) t =SPIclockcycletime=LSPCLK/4orLSPCLK/(SPIBRR+1) c(SPC) (3) InternalclockprescalersmustbeadjustedsuchthattheSPIclockspeedislimitedtothefollowingSPIclockrate: Mastermodetransmit25-MHzMAX,mastermodereceive12.5-MHzMAX Slavemodetransmit12.5-MHzMAX,slavemodereceive12.5-MHzMAX. (4) t =LSPCLKcycletime c(LCO) (5) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI Data Is Valid 19 20 SPISIMO Data SPISIMO Must Be Valid 25 26 SPISTE Figure5-21.SPISlaveModeExternalTiming(ClockPhase=0) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 55 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table5-36.SPISlaveModeExternalTiming(ClockPhase=1)(1)(2)(3)(4) NO. PARAMETER MIN MAX UNIT 12 t Cycletime,SPICLK 4t ns c(SPC)S c(SYSCLK) 13 t Pulseduration,SPICLKfirstpulse 2t –1 ns w(SPC1)S c(SYSCLK) 14 t Pulseduration,SPICLKsecondpulse 2t –1 ns w(SPC2)S c(SYSCLK) 17 t Delaytime,SPICLKtoSPISOMIvalid 35 ns d(SOMI)S 18 t Validtime,SPISOMIdatavalidafterSPICLK 0 ns v(SOMI)S 21 t Setuptime,SPISIMOvalidbeforeSPICLK 1.5t ns su(SIMO)S c(SYSCLK) 22 t Holdtime,SPISIMOdatavalidafterSPICLK 1.5t ns h(SIMO)S c(SYSCLK) 25 t Setuptime,SPISTEactivebeforeSPICLK 1.5t ns su(STE)S c(SYSCLK) 26 t Holdtime,SPISTEinactiveafterSPICLK 1.5t ns h(STE)S c(SYSCLK) (1) TheMASTER/SLAVEbit(SPICTL.2)isclearedandtheCLOCKPHASEbit(SPICTL.3)iscleared. (2) t =SPIclockcycletime=LSPCLK/4orLSPCLK/(SPIBRR+1) c(SPC) (3) InternalclockprescalersmustbeadjustedsuchthattheSPIclockspeedislimitedtothefollowingSPIclockrate: Mastermodetransmit25-MHzMAX,mastermodereceive12.5-MHzMAX Slavemodetransmit12.5-MHzMAX,slavemodereceive12.5-MHzMAX. (4) TheactiveedgeoftheSPICLKsignalreferencediscontrolledbytheCLOCKPOLARITYbit(SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 17 SPISOMI SPISOMI Data Is Valid Data Valid Data Valid 21 18 22 SPISIMO SPISIMO Data Must Be Valid 25 26 SPISTE Figure5-22.SPISlaveModeExternalTiming(ClockPhase=1) 56 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.14.5 Emulator Connection Without Signal Buffering for the DSP Figure 5-23 shows the connection between the DSP and JTAG header for a single-processor configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 5-23 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section4.2. 6 inches or less V V DDIO DDIO 13 5 EMU0 EMU0 PD 14 EMU1 EMU1 2 4 TRST TRST GND 1 6 TMS TMS GND 3 8 TDI TDI GND 7 10 TDO TDO GND 11 12 TCK TCK GND 9 TCK_RET DSP JTAG Header Figure5-23.EmulatorConnectionWithoutSignalBufferingfortheDSP Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 57 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.14.6 Flash Timing Table5-37.FlashEndurancefor Aand STemperatureMaterial(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE N Flashenduranceforthearray(write/erasecycles) 0°Cto85°C(ambient) 20000 50000 cycles f N OTPenduranceforthearray(writecycles) 0°Cto85°C(ambient) 1 write OTP (1) Write/eraseoperationsoutsideofthetemperaturerangesindicatedarenotspecifiedandmayaffecttheendurancenumbers. Table5-38.FlashEnduranceforQTemperatureMaterial(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE N Flashenduranceforthearray(write/erasecycles) –40°Cto125°C(ambient) 20000 50000 cycles f N OTPenduranceforthearray(writecycles) –40°Cto125°C(ambient) 1 write OTP (1) Write/eraseoperationsoutsideofthetemperaturerangesindicatedarenotspecifiedandmayaffecttheendurancenumbers. Table5-39.FlashParametersat100-MHzSYSCLKOUT PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 16-BitWord 50 μs Program 16KSector 500 2000(2) ms Time(1) 8KSector 250 2000(2) ms 4KSector 125 2000(2) ms 16KSector 2 15(2) s ETirmasee(3) 8KSector 2 15(2) s 4KSector 2 15(2) s I (4) VDD3VFLcurrentconsumptionduringthe Erase 75 mA DD3VFLP Erase/Programcycle Program 35 mA I (4) VDDcurrentconsumptionduring 140 mA DDP Erase/Programcycle I (4) VDDIOcurrentconsumptionduring 20 mA DDIOP Erase/Programcycle (1) Programtimeisatthemaximumdevicefrequency.Theprogrammingtimeindicatedinthistableisapplicableonlywhenalltherequired code/dataisavailableinthedeviceRAM,readyforprogramming.Programtimeincludesoverheadoftheflashstatemachinebutdoes notincludethetimetotransferthefollowingintoRAM: • thecodethatusesflashAPItoprogramtheflash • theFlashAPIitself • Flashdatatobeprogrammed (2) TheparametersmentionedintheMAXcolumnareforthefirst100Erase/Programcycles. (3) Theon-chipflashmemoryisinanerasedstatewhenthedeviceisshippedfromTI.Assuch,erasingtheflashmemoryisnotrequired beforeprogramming,whenprogrammingthedeviceforthefirsttime.However,theeraseoperationisneededonallsubsequent programmingoperations. (4) Typicalparametersasseenatroomtemperatureincludingfunctioncalloverhead,withallperipheralsoff.Itisimportanttomaintaina stablepowersupplyduringtheentireflashprogrammingprocess.Itisconceivablethatdevicecurrentconsumptionduringflash programmingcouldbehigherthannormaloperatingconditions.ThepowersupplyusedshouldensureV onthesupplyrailsatall MIN times,asspecifiedintheRecommendedOperatingConditionsofthedatasheet.Anybrownoutorinterruptiontopowerduring erasing/programmingcouldpotentiallycorruptthepasswordlocationsandlockthedevicepermanently.Poweringatargetboard(during flashprogramming)throughtheUSBportisnotrecommended,astheportmaybeunabletorespondtothepowerdemandsplaced duringtheprogrammingprocess. Table5-40.Flash/OTPAccessTiming PARAMETER MIN MAX UNIT t Pagedflashaccesstime 36 ns a(fp) t Randomflashaccesstime 36 ns a(fr) t OTPaccesstime 60 ns a(OTP) 58 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table5-41.FlashDataRetentionDuration PARAMETER TESTCONDITIONS MIN MAX UNIT t Dataretentionduration T =55°C 15 years retention J Table5-42.MinimumRequiredFlash/OTPWait-StatesatDifferentFrequencies SYSCLKOUT FLASHPAGE FLASHRANDOM (MHz) SYSCLKOUT(ns) WAIT-STATE WAIT-STATE(1) OTPWAIT-STATE 100 10 3 3 5 75 13.33 2 2 4 60 16.67 2 2 3 50 20 1 1 2 30 33.33 1 1 1 25 40 0 1 1 15 66.67 0 1 1 4 250 0 1 1 (1) Randomwait-statemustbegreaterthanorequalto1. EquationstocomputetheFlashpagewait-stateandrandomwait-stateinTable5-42 areasfollows: Flash Page Wait-State(cid:2)(cid:3)(cid:5)tta(fp) (cid:6)(cid:1)1(cid:4)(round up to the next highest integer) or 0, whichever is larger c(SCO) Flash Random Wait-State(cid:2)(cid:3)(cid:5)tta(fr) (cid:6)(cid:1)1(cid:4)(round up to the next highest integer) or 1, whichever is larger c(SCO) EquationtocomputetheOTPwait-stateinTable5-42 isasfollows: OTP Wait-State(cid:2)(cid:3)(cid:5)tta(OTP) (cid:6)(cid:1)1(cid:4)(round up to the next highest integer) or 1, whichever is larger c(SCO) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 59 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.15 On-Chip Analog-to-Digital Converter Table5-43.ADCElectricalCharacteristics(1)(2) overrecommendedoperatingconditions PARAMETER MIN TYP MAX UNIT DCSPECIFICATIONS Resolution 12 Bits 60-MHzdevice 0.001 7.5 ADCclock 100-MHzdevice 0.001 12.5 MHz 100-MHzdevice(F2809only) 0.001 25 ACCURACY 1–12.5MHzADCclock(6.25MSPS) ±1.5 INL(Integralnonlinearity) LSB 12.5–25MHzADCclock(12.5MSPS) ±2 DNL(Differentialnonlinearity)(3) ±1 LSB Offseterror(4) –60 +60 LSB Offseterrorwithhardwaretrimming ±4 LSB Overallgainerrorwithinternalreference(5) –60 +60 LSB Overallgainerrorwithexternalreference –60 +60 LSB Channel-to-channeloffsetvariation ±4 LSB Channel-to-channelgainvariation ±4 LSB ANALOGINPUT Analoginputvoltage(ADCINxtoADCLO)(6) 0 3 V ADCLO –5 0 5 mV Inputcapacitance 10 pF Inputleakagecurrent ±5 μA INTERNALVOLTAGEREFERENCE(5) V -ADCREFPoutputvoltageatthepin ADCREFP 1.275 V basedoninternalreference V -ADCREFMoutputvoltageatthepin ADCREFM 0.525 V basedoninternalreference Voltagedifference,ADCREFP-ADCREFM 0.75 V Temperaturecoefficient 50 PPM/°C EXTERNALVOLTAGEREFERENCE(5) (7) ADCREFSEL[15:14]=11b 1.024 V V -Externalreferencevoltageinputon ADCREFIN ADCREFINpin0.2%orbetteraccurate ADCREFSEL[15:14]=10b 1.500 V referencerecommended ADCREFSEL[15:14]=01b 2.048 V ACSPECIFICATIONS SINAD(100kHz)Signal-to-noiseratio+ 67.5 dB distortion SNR(100kHz)Signal-to-noiseratio 68 dB THD(100kHz)Totalharmonicdistortion –79 dB ENOB(100kHz)Effectivenumberofbits 10.9 Bits SFDR(100kHz)Spuriousfreedynamicrange 83 dB (1) Testedat12.5MHzADCCLK. (2) AllvoltageslistedinthistablearewithrespecttoV . SSA2 (3) TIspecifiesthattheADCwillhavenomissingcodes. (4) 1LSBhastheweightedvalueof3.0/4096=0.732mV. (5) Asingleinternal/externalbandgapreferencesourcesbothADCREFPandADCREFMsignals,andhence,thesevoltagestrack together.TheADCconverterusesthedifferencebetweenthesetwoasitsreference.Thetotalgainerrorlistedfortheinternalreference isinclusiveofthemovementoftheinternalbandgapovertemperature.Gainerrorovertemperaturefortheexternalreferenceoptionwill dependonthetemperatureprofileofthesourceused. (6) VoltagesaboveV +0.3VorbelowV -0.3Vappliedtoananaloginputpinmaytemporarilyaffecttheconversionofanotherpin. DDA SS Toavoidthis,theanaloginputsshouldbekeptwithintheselimits. (7) TIrecommendsusinghighprecisionexternalreferenceTIpartREF3020/3120orequivalentfor2.048-Vreference. 60 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.15.1 ADC Power-Up Control Bit Timing ADC Power Up Delay ADC Ready for Conversions PWDNBG PWDNREF td(BGR) PWDNADC td(PWD) Request for ADC Conversion Figure5-24. ADCPower-UpControlBitTiming Table5-44. ADCPower-UpDelays PARAMETER(1) MIN TYP MAX UNIT Delaytimeforbandgapreferencetobestable.Bits7and6oftheADCTRL3 t 5 ms d(BGR) register(ADCBGRFDN1/0)mustbesetto1beforethePWDNADCbitisenabled. Delaytimeforpower-downcontroltobestable.Bitdelaytimeforband-gap 20 50 μs referencetobestable.Bits7and6oftheADCTRL3register(ADCBGRFDN1/0) t d(PWD) mustbesetto1beforethePWDNADCbitisenabled.Bit5oftheADCTRL3 1 ms register(PWDNADC)mustbesetto1beforeanyADCconversionsareinitiated. (1) Timingsmaintaincompatibilitytothe281xADCmodule.The280xADCalsosupportsdrivingall3bitsatthesametimeandwaiting t msbeforefirstconversion. d(BGR) Table5-45.CurrentConsumptionforDifferentADCConfigurations(at 12.5-MHzADCCLK)(1) (2) ADCOPERATINGMODE CONDITIONS V V UNIT DDA18 DDA3.3 • BGandREFenabled ModeA(OperationalMode): 30 2 mA • PWDdisabled • ADCclockenabled ModeB: • BGandREFenabled 9 0.5 mA • PWDenabled • ADCclockenabled ModeC: • BGandREFdisabled 5 20 μA • PWDenabled • ADCclockdisabled ModeD: • BGandREFdisabled 5 15 μA • PWDenabled (1) TestConditions: SYSCLKOUT=100MHz ADCmoduleclock=12.5MHz ADCperformingacontinuousconversionofall16channelsinModeA (2) V includescurrentintoV andV .V includescurrentintoV andV . DDA18 DD1A18 DD2A18 DDA3.3 DDA2 DDAIO Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 61 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Ron Switch Rs ADCIN0 1 kW Source Cp Ch ac 10 pF 1.64 pF Signal 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): 1 kW Sampling Capacitor (Ch): 1.64 pF Parasitic Capacitance (Cp): 10 pF Source Resistance (Rs): 50 W Figure5-25.ADCAnalogInputImpedanceModel 5.15.2 Definitions ReferenceVoltage Theon-chipADChasabuilt-inreference,whichprovidesthereferencevoltagesfortheADC. AnalogInputs The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at atime.Theseinputsaresoftware-selectable. Converter The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with lowpowerconsumption. ConversionModes Theconversioncanbeperformedintwodifferentconversionmodes: • Sequentialsamplingmode(SMODE=0) • Simultaneoussamplingmode(SMODE=1) 62 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse widthcanbeprogrammedtobe1ADCclockwide(minimum)or16ADCclockswide(maximum). Sample n+2 Sample n+1 Analog Input on Sample n Channel Ax or Bx ADC Clock Sample and Hold SH Pulse SMODE Bit td(SH) tdschx_n+1 tdschx_n ADC Event Trigger from ePWM or Other Sources tSH Figure5-26.SequentialSamplingMode(Single-Channel)Timing Table5-46.SequentialSamplingModeTiming AT12.5MHz SAMPLEn SAMPLEn+1 ADCCLOCK, REMARKS t =80ns c(ADCCLK) Delaytimefromeventtriggerto t 2.5t d(SH) sampling c(ADCCLK) Sample/Holdwidth/Acquisition (1+Acqps)* Acqpsvalue=0–15 t 80nswithAcqps=0 SH Width t ADCTRL1[8:11] c(ADCCLK) Delaytimeforfirstresulttoappear t 4t 320ns d(schx_n) inResultregister c(ADCCLK) Delaytimeforsuccessiveresultsto (2+Acqps)* t 160ns d(schx_n+1) appearinResultregister t c(ADCCLK) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 63 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected channels on every Sample/Hold pulse. The conversion time and latency of the result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clockswide(maximum). NOTE In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7, andnotinothercombinations(suchasA1/B3,andsoforth). Sample n Sample n+1 Sample n+2 Analog Input on Channel Ax Analog Input on Channel Bx ADC Clock Sample and Hold SH Pulse SMODE Bit td(SH) tdschA0_n+1 ADC Event Trigger from tSH ePWM or Other Sources tdschA0_n tdschB0_n+1 tdschB0_n Figure5-27.SimultaneousSamplingModeTiming Table5-47.SimultaneousSamplingModeTiming AT12.5MHz SAMPLEn SAMPLEn+1 ADCCLOCK, REMARKS t =80ns c(ADCCLK) Delaytimefromeventtriggerto t 2.5t d(SH) sampling c(ADCCLK) Sample/Holdwidth/Acquisition (1+Acqps)* Acqpsvalue=0–15 t 80nswithAcqps=0 SH Width t ADCTRL1[8:11] c(ADCCLK) Delaytimeforfirstresultto t 4t 320ns d(schA0_n) appearinResultregister c(ADCCLK) Delaytimeforfirstresultto t 5t 400ns d(schB0_n) appearinResultregister c(ADCCLK) Delaytimeforsuccessiveresults t (3+Acqps)*t 240ns d(schA0_n+1) toappearinResultregister c(ADCCLK) Delaytimeforsuccessiveresults t (3+Acqps)*t 240ns d(schB0_n+1) toappearinResultregister c(ADCCLK) 64 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.15.5 Detailed Descriptions IntegralNonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition. The deviation is measured from the center ofeachparticularcodetothetruestraightlinebetweenthesetwopoints. DifferentialNonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.Adifferentialnonlinearityerroroflessthan ±1LSBensuresnomissingcodes. ZeroOffset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviationoftheactualtransitionfromthatpoint. GainError The first code transition should occur at an analog value one-half LSB above negative full scale. The last transitionshouldoccuratananalogvalueoneandone-halfLSBbelowthenominalfullscale.Gainerroris the deviation of the actual difference between first and last code transitions and the ideal difference betweenfirstandlastcodetransitions. Signal-to-NoiseRatio+Distortion(SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressedindecibels. EffectiveNumberofBits(ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, (SINAD(cid:1)1.76) N(cid:2) 6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculateddirectlyfromitsmeasuredSINAD. TotalHarmonicDistortion(THD) THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured inputsignalandisexpressedasapercentageorindecibels. SpuriousFreeDynamicRange(SFDR) SFDRisthedifferenceindBbetweenthermsamplitudeoftheinputsignalandthepeakspurioussignal. Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 65 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 5.16 Migrating From F280x Devices to C280x Devices 5.16.1 Migration Issues The migration issues to be considered while migrating from the F280x devices to C280x devices are as follows: • The1KOTPmemoryavailableinF280xdeviceshasbeenreplacedby1KROMC280xdevices. • Current consumption differs for F280x and C280x devices for all four possible modes. See the appropriateelectricalsectionforexactnumbers. • The V pin is the 3.3-V Flash core power pin in F280x devices but is a V pin in C280x DD3VFL DDIO devices. • F280x and C280x devices are pin-compatible and code-compatible; however, they are electrically different with different EMI/ESD profiles. Before ramping production with C280x devices, evaluate performanceofthehardwaredesignwithbothdevices. • Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF0 through 0x3F 7FF5 in the main ROM array are reserved for ROM part-specific information and are not available for user applications. • The paged and random wait-state specifications for the Flash and ROM parts are different. While migrating from Flash to ROM parts, the same wait-state values must be used for best-performance compatibility (for example, in applications that use software delay loops or where precise interrupt latenciesarecritical). • The analog input switch resistance is smaller in C280x devices compared to F280x devices. While migrating from a Flash to a ROM device care should be taken to design the analog input circuits to meettheapplicationperformancerequiredbythesamplingnetwork. • ThePART-IDregistervalueisdifferentforFlashandROMparts. • From a silicon functionality/errata standpoint, rev A ROM devices are equivalent to rev C flash devices. Seetheerrataapplicableto280xdevicesfordetails. • As part of the ROM code generation process, all unused memory locations in the customer application are automatically filled with 0xFFFF. Unused locations should not be manually filled with any other data. NOTE RequestsforROMversionsoftheF280xdevicearenotacceptedbyTIanymore. For errata applicable to 280x devices, see the TMS320F280x, TMS320C280x, TMS320F2801x DSPs siliconerrata. 66 Specifications Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 5.17 ROM Timing (C280x only) Table5-48. ROM/OTPAccessTiming PARAMETER MIN MAX UNIT t PagedROMaccesstime 19 ns a(rp) t RandomROMaccesstime 19 ns a(rr) t ROM(OTParea)accesstime (1) 60 ns a(ROM) (1) InC280xdevices,a1KX16ROMblockreplacestheOTPblockfoundinFlashdevices. Table5-49.ROM/ROM(OTParea)MinimumRequired Wait-StatesatDifferentFrequencies SYSCLKOUT SYSCLKOUT PAGEWAIT- RANDOMWAIT- (MHz) (ns) STATE STATE(1) 100 10 1 1 75 13.33 1 1 50 20 0 1 30 33.33 0 1 25 40 0 1 15 66.67 0 1 4 250 0 1 (1) Randomwait-statemustbegreaterthanorequalto1. Equationstocomputethepagewait-stateandrandomwait-stateinTable5-49 areasfollows: (cid:3)(cid:5) ta(rp) (cid:6) (cid:4) ROM Page Wait-State(cid:2) t (cid:1)1 (round up to the next highest integer) or 0, whichever is larger c(SCO) (cid:3)(cid:5) ta(rr) (cid:6) (cid:4) ROM Random Wait-State(cid:2) t (cid:1)1 (round up to the next highest integer) or 1, whichever is larger c(SCO) Copyright©2003–2019,TexasInstrumentsIncorporated Specifications 67 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6 Detailed Description 6.1 Brief Descriptions 6.1.1 C28x CPU The C28x DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high- levellanguage,butalsoenablesmathalgorithmstobedevelopedusingC/C++.TheC28xisasefficientin DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. 6.1.2 Memory Bus (Harvard Bus Architecture) As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory busaccessescanbesummarizedasfollows: Highest: DataWrites (Simultaneousdataandprogramwritescannotoccuronthe memorybus.) ProgramWrites (Simultaneousdataandprogramwritescannotoccuronthe memorybus.) DataReads Program (Simultaneousprogramreadsandfetchescannotoccuronthe Reads memorybus.) Lowest: Fetches (Simultaneousprogramreadsandfetchescannotoccuronthe memorybus.) 6.1.3 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the 280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2). Theotherversionsupportsboth16-and32-bitaccesses(calledperipheralframe1). 68 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.1.4 Real-Time JTAG and Analysis The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the 280x, no software monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user-selectable break eventswhenamatchoccurs. 6.1.5 Flash The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K x 16 sectors. The F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K x 16 sectors. The F2806 and F2802 have 32K x 16 of embedded flash, segregated into four 8K x 16 sectors. The F2801 device contains 16K x 16 of embedded flash, segregated into four 4K x 16 sectors. All five devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables and shouldnotcontainprogramcode. NOTE The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to usefewerwait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, seetheTMS320x280x,2801x,2804xDSPsystemcontrolandinterruptsreferenceguide. 6.1.6 ROM TheC2802contains32Kx16ofROM,whiletheC2801contains16Kx16ofROM. NOTE RequestsforROMdevicesarenotacceptedbyTIanymore. 6.1.7 M0, M1 SARAMs All 280x devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.1.8 L0, L1, H0 SARAMs The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into three blocks (L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into two blocks (L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16 of single-access RAM (L0-4K). Each block can be independently accessed to minimize CPU pipeline stalls.Eachblockismappedtobothprogramanddataspace. 6.1.9 Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use inmathrelatedalgorithms. Table6-1.BootModeSelection GPIO18 GPIO29 MODE DESCRIPTION SPICLKA GPIO34 SCITXDA SCITXDB JumptoFlash/ROMaddress0x3F7FF6 BoottoFlash/ROM Youmusthaveprogrammedabranchinstructionhereprior 1 1 1 toresettoredirectcodeexecutionasdesired. SCI-ABoot LoadadatastreamfromSCI-A 1 1 0 SPI-ABoot LoadfromanexternalserialSPIEEPROMonSPI-A 1 0 1 LoaddatafromanexternalEEPROMataddress0x50on I2CBoot 1 0 0 theI2Cbus eCAN-ABoot CallCAN_BoottoloadfromeCAN-Amailbox1. 0 1 1 BoottoM0SARAM JumptoM0SARAMaddress0x000000. 0 1 0 BoottoOTP JumptoOTPaddress0x3D7800 0 0 1 ParallelI/OBoot LoaddatafromGPIO0-GPIO15 0 0 0 70 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.1.10 Security The 280x devices support high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which matches the value stored in the password locations within the Flash. NOTE The128-bitpassword(at0x3F7FF8–0x3F7FFF)mustnotbeprogrammedtozeros.Doing sowouldpermanentlylockthedevice. DISCLAIMER CodeSecurityModuleDisclaimer THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THISDEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIESOFMERCHANTABILITYORFITNESSFORAPARTICULARPURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES.EXCLUDEDDAMAGESINCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTIONOFBUSINESSOROTHERECONOMICLOSS. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.1.11 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12CPUinterruptlines(INT1toINT12).Eachofthe96interruptsissupportedbyitsownvectorstoredina dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardwareandsoftware.Eachindividualinterruptcanbeenabled/disabledwithinthePIEblock. 6.1.12 External Interrupts (XINT1, XINT2, XNMI) The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be configuredtotriggeranyexternalinterrupt. 6.1.13 Oscillator and PLL The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. SeeSection5fortimingdetails.ThePLLblockcanbesetinbypassmode. 6.1.14 Watchdog The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog canbedisabledifnecessary. 6.1.15 Peripheral Clocking The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupledfromincreasingCPUclockspeeds. 6.1.16 Low-Power Modes The280xdevicesarefullstaticCMOSdevices.Threelow-powermodesareprovided: IDLE: PlaceCPUintolow-powermode.Peripheralclocksmaybeturnedoffselectivelyand onlythoseperipheralsthatneedtofunctionduringIDLEareleftoperating.An enabledinterruptfromanactiveperipheralorthewatchdogtimerwillwakethe processorfromIDLEmode. STANDBY: TurnsoffclocktoCPUandperipherals.ThismodeleavestheoscillatorandPLL functional.Anexternalinterrupteventwillwaketheprocessorandtheperipherals. Executionbeginsonthenextvalidcycleafterdetectionoftheinterruptevent HALT: Turnsofftheinternaloscillator.Thismodebasicallyshutsdownthedeviceand placesitinthelowestpossiblepowerconsumptionmode.Aresetorexternalsignal canwakethedevicefromthismode. 72 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.1.17 Peripheral Frames 0, 1, 2 (PFn) The280xsegregateperipheralsintothreesections.Themappingofperipheralsisasfollows: PF0: PIE: PIEInterruptEnableandControlRegistersPlusPIEVectorTable Flash: FlashControl,Programming,Erase,VerifyRegisters Timers: CPU-Timers0,1,2Registers CSM: CodeSecurityModuleKEYRegisters ADC: ADCResultRegisters(dual-mapped) PF1: eCAN: eCANMailboxandControlRegisters GPIO: GPIOMUXConfigurationandControlRegisters ePWM: EnhancedPulseWidthModulatorModuleandRegisters eCAP: EnhancedCaptureModuleandRegisters eQEP: EnhancedQuadratureEncoderPulseModuleandRegisters PF2: SYS: SystemControlRegisters SCI: SerialCommunicationsInterface(SCI)ControlandRX/TXRegisters SPI: SerialPortInterface(SPI)ControlandRX/TXRegisters ADC: ADCStatus,Control,andResultRegister I2C: Inter-IntegratedCircuitModuleandRegisters 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. 6.1.19 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the SYS/BIOS Real-Time OS, and is connected to INT14 of the CPU. If SYS/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connectedtoINT13oftheCPU.CPU-Timer0isalsoforgeneraluseandisconnectedtothePIEblock. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.1.20 Control Peripherals The 280x devices support the following peripherals which are used for embedded control and communication: ePWM: TheenhancedPWMperipheralsupportsindependent/complementaryPWM generation,adjustabledead-bandgenerationforleading/trailingedges, latched/cycle-by-cycletripmechanism.SomeofthePWMpinssupportHRPWM features. eCAP: Theenhancedcaptureperipheralusesa32-bittimebaseandregistersuptofour programmableeventsincontinuous/one-shotcapturemodes. ThisperipheralcanalsobeconfiguredtogenerateanauxiliaryPWMsignal. eQEP: TheenhancedQEPperipheralusesa32-bitpositioncounter,supportslow-speed measurementusingcaptureunitandhigh-speedmeasurementusinga32-bitunit timer. Thisperipheralhasawatchdogtimertodetectmotorstallandinputerrordetection logictoidentifysimultaneousedgetransitioninQEPsignals. ADC: TheADCblockisa12-bitconverter,single-ended,16-channels.Itcontainstwo sample-and-holdunitsforsimultaneoussampling. 6.1.21 Serial Port Peripherals The280xdevicessupportthefollowingserialcommunicationperipherals: eCAN: ThisistheenhancedversionoftheCANperipheral.Itsupports32mailboxes,time stampingofmessages,andiscompliantwithISO11898-1(CAN2.0B). SPI: TheSPIisahigh-speed,synchronousserialI/Oportthatallowsaserialbitstreamof programmedlength(onetosixteenbits)tobeshiftedintoandoutofthedeviceata programmablebit-transferrate.Normally,theSPIisusedforcommunications betweentheDSPcontrollerandexternalperipheralsoranotherprocessor.Typical applicationsincludeexternalI/Oorperipheralexpansionthroughdevicessuchas shiftregisters,displaydrivers,andADCs.Multi-devicecommunicationsare supportedbythemaster/slaveoperationoftheSPI.Onthe280x,theSPIcontainsa 16-levelreceiveandtransmitFIFOforreducinginterruptservicingoverhead. SCI: Theserialcommunicationsinterfaceisatwo-wireasynchronousserialport, commonlyknownasUART.Onthe280x,theSCIcontainsa16-levelreceiveand transmitFIFOforreducinginterruptservicingoverhead. I2C: Theinter-integratedcircuit(I2C)moduleprovidesaninterfacebetweenaDSPand otherdevicescompliantwithPhilipsSemiconductorsInter-ICbus(I2C-bus) specificationversion2.1andconnectedbywayofanI2C-bus.Externalcomponents attachedtothis2-wireserialbuscantransmit/receiveupto8-bitdatato/fromthe DSPthroughtheI2Cmodule.Onthe280x,theI2Ccontainsa16-levelreceiveand transmitFIFOforreducinginterruptservicingoverhead. 74 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2 Peripherals Theintegratedperipheralsofthe280xaredescribedinthefollowingsubsections: • Three32-bitCPU-Timers • UptosixenhancedPWMmodules(ePWM1,ePWM2,ePWM3,ePWM4,ePWM5,ePWM6) • Uptofourenhancedcapturemodules(eCAP1,eCAP2,eCAP3,eCAP4) • UptotwoenhancedQEPmodules(eQEP1,eQEP2) • Enhancedanalog-to-digitalconverter(ADC)module • Uptotwoenhancedcontrollerareanetwork(eCAN)modules(eCAN-A,eCAN-B) • Uptotwoserialcommunicationsinterfacemodules(SCI-A,SCI-B) • Uptofourserialperipheralinterface(SPI)modules(SPI-A,SPI-B,SPI-C,SPI-D) • Inter-integratedcircuitmodule(I2C) • DigitalI/Oandsharedpinfunctions 6.2.1 32-Bit CPU-Timers 0/1/2 Therearethree32-bitCPU-timersonthe280xdevices(CPU-TIMER0/1/2). CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for SYS/BIOS. ThesetimersaredifferentfromthetimersthatarepresentintheePWMmodules. NOTE IftheapplicationisnotusingSYS/BIOS,thenCPU-Timer2canbeusedintheapplication. Reset Timer Reload 16-Bit Timer Divide-Down 32-Bit Timer Period TDDRH:TDDR PRDH:PRD SYSCLKOUT 16-Bit Prescale Counter PSCH:PSC TCR.4 32-Bit Counter (Timer Start Status) Borrow TIMH:TIM Borrow TINT Figure6-1.CPU-Timers Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure6-2. INT1 TINT0 to PIE CPU-TIMER 0 INT12 C28x TINT1 INT13 CPU-TIMER 1 XINT13 TINT2 CPU-TIMER 2 INT14 (Reserved for SYS/BIOS) A. ThetimerregistersareconnectedtothememorybusoftheC28xprocessor. B. ThetimingofthetimersissynchronizedtoSYSCLKOUToftheprocessorclock. Figure6-2.CPU-TimerInterruptSignalsandOutputSignal The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registerslistedinTable6-2areusedtoconfigurethetimers.Formoreinformation,seethe TMS320x280x, 2801x,2804xDSPsystemcontrolandinterruptsreferenceguide. Table6-2.CPU-Timers0,1,2ConfigurationandControlRegisters NAME ADDRESS SIZE(x16) DESCRIPTION TIMER0TIM 0x0C00 1 CPU-Timer0,CounterRegister TIMER0TIMH 0x0C01 1 CPU-Timer0,CounterRegisterHigh TIMER0PRD 0x0C02 1 CPU-Timer0,PeriodRegister TIMER0PRDH 0x0C03 1 CPU-Timer0,PeriodRegisterHigh TIMER0TCR 0x0C04 1 CPU-Timer0,ControlRegister Reserved 0x0C05 1 Reserved TIMER0TPR 0x0C06 1 CPU-Timer0,PrescaleRegister TIMER0TPRH 0x0C07 1 CPU-Timer0,PrescaleRegisterHigh TIMER1TIM 0x0C08 1 CPU-Timer1,CounterRegister TIMER1TIMH 0x0C09 1 CPU-Timer1,CounterRegisterHigh TIMER1PRD 0x0C0A 1 CPU-Timer1,PeriodRegister TIMER1PRDH 0x0C0B 1 CPU-Timer1,PeriodRegisterHigh TIMER1TCR 0x0C0C 1 CPU-Timer1,ControlRegister Reserved 0x0C0D 1 Reserved TIMER1TPR 0x0C0E 1 CPU-Timer1,PrescaleRegister TIMER1TPRH 0x0C0F 1 CPU-Timer1,PrescaleRegisterHigh TIMER2TIM 0x0C10 1 CPU-Timer2,CounterRegister TIMER2TIMH 0x0C11 1 CPU-Timer2,CounterRegisterHigh TIMER2PRD 0x0C12 1 CPU-Timer2,PeriodRegister TIMER2PRDH 0x0C13 1 CPU-Timer2,PeriodRegisterHigh TIMER2TCR 0x0C14 1 CPU-Timer2,ControlRegister Reserved 0x0C15 1 Reserved 76 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table6-2.CPU-Timers0,1,2ConfigurationandControlRegisters(continued) NAME ADDRESS SIZE(x16) DESCRIPTION TIMER2TPR 0x0C16 1 CPU-Timer2,PrescaleRegister TIMER2TPRH 0x0C17 1 CPU-Timer2,PrescaleRegisterHigh 0x0C18– Reserved 40 Reserved 0x0C3F 6.2.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) The 280x device contains up to six enhanced PWM modules (ePWM). Figure 6-3 shows a block diagram of multiple ePWM modules. Figure 6-4 shows the signal interconnections with the ePWM. See the TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide for more details. EPWM1SYNCI EPWM1SYNCI EPWM1INT EPWM1A EPWM1SOC ePWM1 Module EPWM1B TZ1toTZ6 To eCAP1 EPWM1SYNCO EPWM1SYNCO Module (Sync in) EPWM2SYNCI EPWM2INT EPWM2A EPWM2SOC PIE ePWM2 Module EPWM2B GPIO TZ1toTZ6 MUX EPWM2SYNCO EPWMxSYNCI EPWMxINT EPWMxA EPWMxSOC ePWMx Module EPWMxB TZ1toTZ6 EPWMxSYNCO ADCSOCx0 Peripheral Bus ADC Copyright © 2016,Texas Instruments Incorporated Figure6-3.MultiplePWMModulesina280xSystem Table6-3showsthecompleteePWMregistersetpermodule. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table6-3.ePWMControlandStatusRegisters SIZE(x16)/ NAME ePWM1 ePWM2 ePWM3 ePWM4 ePWM5 ePWM6 DESCRIPTION #SHADOW TBCTL 0x6800 0x6840 0x6880 0x68C0 0x6900 0x6940 1/0 TimeBaseControlRegister TBSTS 0x6801 0x6841 0x6881 0x68C1 0x6901 0x6941 1/0 TimeBaseStatusRegister TBPHSHR 0x6802 0x6842 0x6882 0x68C2 N/A N/A 1/0 TimeBasePhaseHRPWMRegister TBPHS 0x6803 0x6843 0x6883 0x68C3 0x6903 0x6943 1/0 TimeBasePhaseRegister TBCTR 0x6804 0x6844 0x6884 0x68C4 0x6904 0x6944 1/0 TimeBaseCounterRegister TBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1/1 TimeBasePeriodRegisterSet CMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1/0 CounterCompareControlRegister CMPAHR 0x6808 0x6848 0x6888 0x68C8 N/A N/A 1/1 TimeBaseCompareAHRPWMRegister CMPA 0x6809 0x6849 0x6889 0x68C9 0x6909 0x6949 1/1 CounterCompareARegisterSet CMPB 0x680A 0x684A 0x688A 0x68CA 0x690A 0x694A 1/1 CounterCompareBRegisterSet AQCTLA 0x680B 0x684B 0x688B 0x68CB 0x690B 0x694B 1/0 ActionQualifierControlRegisterForOutputA AQCTLB 0x680C 0x684C 0x688C 0x68CC 0x690C 0x694C 1/0 ActionQualifierControlRegisterForOutputB AQSFRC 0x680D 0x684D 0x688D 0x68CD 0x690D 0x694D 1/0 ActionQualifierSoftwareForceRegister AQCSFRC 0x680E 0x684E 0x688E 0x68CE 0x690E 0x694E 1/1 ActionQualifierContinuousS/WForceRegisterSet DBCTL 0x680F 0x684F 0x688F 0x68CF 0x690F 0x694F 1/1 Dead-BandGeneratorControlRegister DBRED 0x6810 0x6850 0x6890 0x68D0 0x6910 0x6950 1/0 Dead-BandGeneratorRisingEdgeDelayCountRegister DBFED 0x6811 0x6851 0x6891 0x68D1 0x6911 0x6951 1/0 Dead-BandGeneratorFallingEdgeDelayCountRegister TZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1/0 TripZoneSelectRegister(1) TZCTL 0x6814 0x6854 0x6894 0x68D4 0x6914 0x6954 1/0 TripZoneControlRegister(1) TZEINT 0x6815 0x6855 0x6895 0x68D5 0x6915 0x6955 1/0 TripZoneEnableInterruptRegister(1) TZFLG 0x6816 0x6856 0x6896 0x68D6 0x6916 0x6956 1/0 TripZoneFlagRegister TZCLR 0x6817 0x6857 0x6897 0x68D7 0x6917 0x6957 1/0 TripZoneClearRegister(1) TZFRC 0x6818 0x6858 0x6898 0x68D8 0x6918 0x6958 1/0 TripZoneForceRegister(1) ETSEL 0x6819 0x6859 0x6899 0x68D9 0x6919 0x6959 1/0 EventTriggerSelectionRegister ETPS 0x681A 0x685A 0x689A 0x68DA 0x691A 0x695A 1/0 EventTriggerPrescaleRegister ETFLG 0x681B 0x685B 0x689B 0x68DB 0x691B 0x695B 1/0 EventTriggerFlagRegister ETCLR 0x681C 0x685C 0x689C 0x68DC 0x691C 0x695C 1/0 EventTriggerClearRegister ETFRC 0x681D 0x685D 0x689D 0x68DD 0x691D 0x695D 1/0 EventTriggerForceRegister PCCTL 0x681E 0x685E 0x689E 0x68DE 0x691E 0x695E 1/0 PWMChopperControlRegister HRCNFG 0x6820 0x6860 0x68A0 0x68E0 0x6920(2) 0x6960(2) 1/0 HRPWMConfigurationRegister(1) (1) RegistersthatareEALLOWprotected. (2) ApplicabletoF2809only 78 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Time-Base (TB) Sync TBPRD Shadow (16) CTR = ZERO In/Out EPWMxSYNCO CTR = CMPB Select TBPRDActive (16) Mux Disabled CTR = PRD TBCTL[SYNCOSEL] TBCTL[PHSEN] Counter EPWMxSYNCI Up/Down TBCTL[SWFSYNC] (16-Bit) (Software-Forced Sync) CTR = ZERO TBCNT Active (16) CTR_Dir TBPHSHR (8) 16 8 CTR = PRD TBPHSActive (24) Phase Event EPWMxINT Control CTR = ZERO Trigger CTR = CMPA and EPWMxSOCA Interrupt CTR = CMPB (ET) EPWMxSOCB CTR_Dir Counter Compare (CC) Action CTR = CMPA Qualifier (AQ) CMPAHR (8) 16 8 HiRes PWM (HRPWM) CMPAActive (24) EPWMA EPWMxAO CMPAShadow (24) Dead PWM Band Chopper Trip CTR = CMPB (DB) (PC) Zone (TZ) 16 EPWMB EPWMxBO CMPBActive (16) EPWMxTZINT CMPB Shadow (16) CTR = ZERO TZ1toTZ6 Copyright © 2016,Texas Instruments Incorporated Figure6-4.ePWMSub-ModulesShowingCriticalInternalSignalInterconnections Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 79 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.2.3 Hi-Resolution PWM (HRPWM) The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are: • SignificantlyextendsthetimeresolutioncapabilitiesofconventionallyderiveddigitalPWM • TypicallyusedwheneffectivePWMresolutionfallsbelow~9–10bits.ThisoccursatPWMfrequencies greaterthan~200kHzwhenusingaCPU/Systemclockof 100MHz. • Thiscapabilitycanbeutilizedinbothdutycycleandphase-shiftcontrolmethods. • Finer time granularity control or edge positioning is controlled via extensions to the Compare A and PhaseregistersoftheePWMmodule. • HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the EPWMxAoutput).EPWMxBoutputhasconventionalPWMcapabilities. 80 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.4 Enhanced CAP Modules (eCAP1/2/3/4) The 280x device contains up to four enhanced capture (eCAP) modules. Figure 6-5 shows a functional block diagram of a module. See the TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module referenceguide formoredetails. CTRPHS (Phase Register - 32-bit) APWM Mode SYNCIn C N Y OVF CTR_OVF CTR [0-31] S TSCTR SYNCOut PWM (Counter - 32-bit) Delta Mode PRD [0-31] Compare RST Logic CMP[0-31] 32 CTR=PRD CTR [0-31] CTR=CMP 32 PRD [0-31] T C 32 CAP1 LD1 Polarity E eCAPx LD L (APRDActive) Select E S E D APRD O Shadow 32 M CMP[0-31] 32 32 CAP2 LD2 Polarity (ACMPActive) LD Select Event ACMP Event Qualifier 32 Shadow Prescale Polarity 32 CAP3 LD3 LD Select (APRD Shadow) 32 CAP4 LD LD4 Polarity (ACMPShadow) Select 4 Capture Events 4 CEVT[1:4] Interrupt Continuous/ Trigger One-Shot to PIE and CTR_OVF Capture Control Flag CTR=PRD Control CTR=CMP Copyright © 2016,Texas Instruments Incorporated Figure6-5.eCAPFunctionalBlockDiagram Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 81 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com TheeCAPmodulesareclockedattheSYSCLKOUTrate. The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK,andECAP4ENCLKaresettolow,indicatingthattheperipheralclockisoff. Table6-4.eCAPControlandStatusRegisters SIZE NAME eCAP1 eCAP2 eCAP3 eCAP4 DESCRIPTION (x16) TSCTR 0x6A00 0x6A20 0x6A40 0x6A60 2 Time-StampCounter CTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 2 CounterPhaseOffsetValueRegister CAP1 0x6A04 0x6A24 0x6A44 0x6A64 2 Capture1Register CAP2 0x6A06 0x6A26 0x6A46 0x6A66 2 Capture2Register CAP3 0x6A08 0x6A28 0x6A48 0x6A68 2 Capture3Register CAP4 0x6A0A 0x6A2A 0x6A4A 0x6A6A 2 Capture4Register 0x6A0C– 0x6A2C– 0x6A4C– 0x6A6C– Reserved 8 Reserved 0x6A12 0x6A32 0x6A52 0x6A72 ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 1 CaptureControlRegister1 ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 1 CaptureControlRegister2 ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 1 CaptureInterruptEnableRegister ECFLG 0x6A17 0x6A37 0x6A57 0x6A77 1 CaptureInterruptFlagRegister ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 1 CaptureInterruptClearRegister ECFRC 0x6A19 0x6A39 0x6A59 0x6A79 1 CaptureInterruptForceRegister 0x6A1A– 0x6A3A– 0x6A5A– 0x6A7A– Reserved 6 Reserved 0x6A1F 0x6A3F 0x6A5F 0x6A7F 82 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.5 Enhanced QEP Modules (eQEP1/2) The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide for moredetails. System Control Registers To CPU EQEPxENCLK SYSCLKOUT s u B a at D QCPRD QCAPCTL QCTMR 16 16 16 Quadrature Capture Unit QCTMRLAT (QCAP) QCPRDLAT Registers QUTMR QWDTMR Used by QUPRD QWDPRD Multiple Units 32 16 QEPCTL QEPSTS UTOUT UTIME QWDOG QDECCTL QFLG 16 WDTOUT EQEPxAIN EQEPxINT QCLK EQEPxBIN EQEPxA/XCLK PIE QDIR EQEPxIIN 16 Position Counter/ QI EQEPxB/XDIR EQEPxIOUT Control Unit QS Quadrature GPIO QPOSLAT (PCCU) PHE D(eQcDoUde)r EQEPxIOE MUX EQEPxI EQEPxSIN QPOSSLAT PCSOUT EQEPxSOUT QPOSILAT EQEPxS EQEPxSOE 32 32 16 QPOSCNT QPOSCMP QEINT QPOSINIT QFRC QPOSMAX QCLR QPOSCTL Enhanced QEP(eQEP) Peripheral Copyright © 2016,Texas Instruments Incorporated Figure6-6.eQEPFunctionalBlockDiagram Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 83 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table6-5providesasummaryoftheeQEPregisters. Table6-5.eQEPControlandStatusRegisters eQEP1 eQEP1 eQEP2 NAME SIZE(x16)/ REGISTERDESCRIPTION ADDRESS ADDRESS #SHADOW QPOSCNT 0x6B00 0x6B40 2/0 eQEPPositionCounter QPOSINIT 0x6B02 0x6B42 2/0 eQEPInitializationPositionCount QPOSMAX 0x6B04 0x6B44 2/0 eQEPMaximumPositionCount QPOSCMP 0x6B06 0x6B46 2/1 eQEPPosition-compare QPOSILAT 0x6B08 0x6B48 2/0 eQEPIndexPositionLatch QPOSSLAT 0x6B0A 0x6B4A 2/0 eQEPStrobePositionLatch QPOSLAT 0x6B0C 0x6B4C 2/0 eQEPPositionLatch QUTMR 0x6B0E 0x6B4E 2/0 eQEPUnitTimer QUPRD 0x6B10 0x6B50 2/0 eQEPUnitPeriodRegister QWDTMR 0x6B12 0x6B52 1/0 eQEPWatchdogTimer QWDPRD 0x6B13 0x6B53 1/0 eQEPWatchdogPeriodRegister QDECCTL 0x6B14 0x6B54 1/0 eQEPDecoderControlRegister QEPCTL 0x6B15 0x6B55 1/0 eQEPControlRegister QCAPCTL 0x6B16 0x6B56 1/0 eQEPCaptureControlRegister QPOSCTL 0x6B17 0x6B57 1/0 eQEPPosition-compareControlRegister QEINT 0x6B18 0x6B58 1/0 eQEPInterruptEnableRegister QFLG 0x6B19 0x6B59 1/0 eQEPInterruptFlagRegister QCLR 0x6B1A 0x6B5A 1/0 eQEPInterruptClearRegister QFRC 0x6B1B 0x6B5B 1/0 eQEPInterruptForceRegister QEPSTS 0x6B1C 0x6B5C 1/0 eQEPStatusRegister QCTMR 0x6B1D 0x6B5D 1/0 eQEPCaptureTimer QCPRD 0x6B1E 0x6B5E 1/0 eQEPCapturePeriodRegister QCTMRLAT 0x6B1F 0x6B5F 1/0 eQEPCaptureTimerLatch QCPRDLAT 0x6B20 0x6B60 1/0 eQEPCapturePeriodLatch 0x6B21– 0x6B61– Reserved 31/0 Reserved 0x6B3F 0x6B7F 84 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.6 Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 6-7. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include: • 12-bitADCcorewithbuilt-inS/H • Analoginput:0.0Vto3.0V(Voltagesabove3.0Vproducefull-scaleconversionresults.) • Fastconversionrate:Upto 80nsat25-MHzADCclock,12.5MSPS • 16-channel,MUXedinputs • Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion canbeprogrammedtoselectanyoneof 16input channels • Sequencer can be operated as two independent 8-channel sequencers or as one large 16-channel sequencer(thatis,twocascaded8-channelsequencers) • Sixteenresultregisters(individuallyaddressable)tostoreconversionvalues – Thedigitalvalueoftheinputanalogvoltageisderivedby: Digital Value = 0 , whenADCIN£ADCLO Digital Value = floor(4096´ ADCIN-ADCLO( , whenADCLO<ADCIN<3 V 3 Digital Value = 4095 , whenADCIN³3 V A. Allfractionalvaluesaretruncated. • Multipletriggersassourcesforthestart-of-conversion(SOC)sequence – S/W-softwareimmediatestart – ePWMstartofconversion – XINT2ADCstartofconversion • Flexibleinterruptcontrolallowsinterruptrequestoneveryend-of-sequence(EOS)oreveryotherEOS. • Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronizeconversions. • SOCAandSOCBtriggerscanoperateindependentlyindual-sequencermode. • Sample-and-hold(S/H)acquisitiontimewindowhasseparateprescalecontrol. The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25- MHz ADC clock. The ADC module has a 16-channel sequencer, configurable as two independent 8- channel sequencers. The two independent 8-channel sequencers can be cascaded to form a 16-channel sequencer. Although there are multiple input channels and two sequencers, there is only one converter in theADCmodule.Figure6-7showstheblockdiagramoftheADCmodule. The two 8-channel sequencer modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single- sampledconversionresults. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 85 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com System High-Speed SYSCLKOUT DSP Control Block Prescaler ADCENCLK HALT HSPCLK Analog MUX Result Registers ADCINA0 Result Reg 0 70A8h Result Reg 1 S/H ADCINA7 12-Bit Result Reg 7 70AFh ADC Module Result Reg 8 70B0h ADCINB0 S/H ADCINB7 Result Reg 15 70B7h ADC Control Registers S/W S/W EPWMSOCA SOC Sequencer 1 Sequencer 2 SOC EPWMSOCB GPIO/XINT2_ ADCSOC Figure6-7.BlockDiagramoftheADCModule To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (V , DD1A18 V , V , V ) from the digital supply. Figure 6-8 and Figure 6-9 show the ADC pin connections DD2A18 DDA2 DDAIO forthe280xdevices. NOTE 1. TheADCregistersareaccessedattheSYSCLKOUTrate.Theinternaltimingofthe ADCmoduleiscontrolledbythehigh-speedperipheralclock(HSPCLK). 2. ThebehavioroftheADCmodulebasedonthestateoftheADCENCLKandHALT signalsisasfollows: – ADCENCLK:Onreset,thissignalwillbelow.Whileresetisactive-low(XRS)the clocktotheregisterwillstillfunction.Thisisnecessarytomakesureallregistersand modesgointotheirdefaultresetstate.Theanalogmodule,however,willbeinalow- powerinactivestate.Assoonasresetgoeshigh,thentheclocktotheregisterswill bedisabled.WhentheusersetstheADCENCLKsignalhigh,thentheclockstothe registerswillbeenabledandtheanalogmodulewillbeenabled.Therewillbea certaintimedelay(msrange)beforetheADCisstableandcanbeused. – HALT:Thismodeonlyaffectstheanalogmodule.Itdoesnotaffecttheregisters.In thismode,theADCmodulegoesintolow-powermode.Thismodealsowillstopthe clocktotheCPU,whichwillstoptheHSPCLK;therefore,theADCregisterlogicwill beturnedoffindirectly. 86 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Figure 6-8 shows the ADC pin-biasing for internal reference and Figure 6-9 shows the ADC pin-biasing for externalreference. ADCINA[7:0] ADC 16-ChannelAnalog Inputs Analog input 0-3 V with respect to ADCLO ADCINB[7:0] ADCLO Connect to analog ground ADCREFIN Float or ground if internal reference is used 22 k ADC External Current Bias Resistor ADCRESEXT 2.2μF(A) ADC Reference Positive Output ADCREFP ADCREFPandADCREFM should not ADC Reference Medium Output ADCREFM 2.2μF(A) be loaded by external circuitry V ADCAnalog Power Pin (1.8 V) DD1A18 V ADCAnalog Power Pin (1.8 V) ADC Power V DD2A18 ADCAnalog Ground Pin SS1AGND V ADCAnalog Ground Pin SS2AGND V ADCAnalog Power Pin (3.3 V) DDA2 V ADCAnalog Ground Pin SSA2 ADCAnalog and Reference I/O Power V ADCAnalog Power Pin (3.3 V) DDAIO V ADCAnalog I/O Ground Pin SSAIO A. TAIYOYUDENLMK212BJ225MG-Torequivalent B. Externaldecouplingcapacitorsarerecommendedonallpowerpins. C. AnaloginputsmustbedrivenfromanoperationalamplifierthatdoesnotdegradetheADCperformance. Figure6-8.ADCPinConnectionsWithInternalReference Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 87 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com ADCINA[7:0] ADC 16-ChannelAnalog Inputs Analog input 0-3 V with respect to ADCLO ADCINB[7:0] ADCLO Connect toAnalog Ground ADCREFIN Connect to 1.500, 1.024, or 2.048-V precision source(D) 22 k ADC External Current Bias Resistor ADCRESEXT 2.2μF(A) ADC Reference Positive Output ADCREFP ADCREFPandADCREFM should not ADC Reference Medium Output ADCREFM 2.2μF(A) be loaded by external circuitry V ADCAnalog Power Pin (1.8 V) DD1A18 V ADCAnalog Power Pin (1.8 V) ADCAnalog Power V DD2A18 ADCAnalog Ground Pin SS1AGND V ADCAnalog Ground Pin SS2AGND V ADCAnalog Power Pin (3.3 V) DDA2 V ADCAnalog Ground Pin SSA2 V ADCAnalog Power Pin (3.3 V) ADCAnalog and Reference I/O Power DDAIO V ADCAnalog I/O Ground Pin SSAIO A. TAIYOYUDENLMK212BJ225MG-Torequivalent B. Externaldecouplingcapacitorsarerecommendedonallpowerpins. C. AnaloginputsmustbedrivenfromanoperationalamplifierthatdoesnotdegradetheADCperformance. D. ExternalvoltageonADCREFINisenabledbychangingbits15:14intheADCReferenceSelectregisterdependingon the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracywillbedeterminedbyaccuracyofthisvoltagesource. Figure6-9.ADCPinConnectionsWithExternalReference NOTE The temperature rating of any recommended component must match the rating of the end product. 88 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.6.1 ADCConnectionsiftheADCIsNotUsed It is recommended to keep the connections for the analog power pins, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application: • V /V –ConnecttoV DD1A18 DD2A18 DD • V ,V –ConnecttoV DDA2 DDAIO DDIO • V /V ,V ,V –ConnecttoV SS1AGND SS2AGND SSA2 SSAIO SS • ADCLO– ConnecttoV SS • ADCREFIN –ConnecttoV SS • ADCREFP/ADCREFM –Connecta100-nFcaptoV SS • ADCRESEXT –Connecta20-kΩ resistor(veryloosetolerance)toV . SS • ADCINAn,ADCINBn-ConnecttoV SS When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings. When the ADC module is used in an application, unused ADC input pins should be connected to analog ground(V /V ) SS1AGND SS2AGND Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 89 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.2.6.2 ADCRegisters TheADCoperationisconfigured,controlled,andmonitoredbytheregisterslistedinTable6-6. Table6-6.ADCRegisters(1) NAME ADDRESS(1) ADDRESS(2) SIZE(x16) DESCRIPTION ADCTRL1 0x7100 1 ADCControlRegister1 ADCTRL2 0x7101 1 ADCControlRegister2 ADCMAXCONV 0x7102 1 ADCMaximumConversionChannelsRegister ADCCHSELSEQ1 0x7103 1 ADCChannelSelectSequencingControlRegister1 ADCCHSELSEQ2 0x7104 1 ADCChannelSelectSequencingControlRegister2 ADCCHSELSEQ3 0x7105 1 ADCChannelSelectSequencingControlRegister3 ADCCHSELSEQ4 0x7106 1 ADCChannelSelectSequencingControlRegister4 ADCASEQSR 0x7107 1 ADCAuto-SequenceStatusRegister ADCRESULT0 0x7108 0x0B00 1 ADCConversionResultBufferRegister0 ADCRESULT1 0x7109 0x0B01 1 ADCConversionResultBufferRegister1 ADCRESULT2 0x710A 0x0B02 1 ADCConversionResultBufferRegister2 ADCRESULT3 0x710B 0x0B03 1 ADCConversionResultBufferRegister3 ADCRESULT4 0x710C 0x0B04 1 ADCConversionResultBufferRegister4 ADCRESULT5 0x710D 0x0B05 1 ADCConversionResultBufferRegister5 ADCRESULT6 0x710E 0x0B06 1 ADCConversionResultBufferRegister6 ADCRESULT7 0x710F 0x0B07 1 ADCConversionResultBufferRegister7 ADCRESULT8 0x7110 0x0B08 1 ADCConversionResultBufferRegister8 ADCRESULT9 0x7111 0x0B09 1 ADCConversionResultBufferRegister9 ADCRESULT10 0x7112 0x0B0A 1 ADCConversionResultBufferRegister10 ADCRESULT11 0x7113 0x0B0B 1 ADCConversionResultBufferRegister11 ADCRESULT12 0x7114 0x0B0C 1 ADCConversionResultBufferRegister12 ADCRESULT13 0x7115 0x0B0D 1 ADCConversionResultBufferRegister13 ADCRESULT14 0x7116 0x0B0E 1 ADCConversionResultBufferRegister14 ADCRESULT15 0x7117 0x0B0F 1 ADCConversionResultBufferRegister15 ADCTRL3 0x7118 1 ADCControlRegister3 ADCST 0x7119 1 ADCStatusRegister 0x711A– Reserved 2 Reserved 0x711B ADCREFSEL 0x711C 1 ADCReferenceSelectRegister ADCOFFTRIM 0x711D 1 ADCOffsetTrimRegister 0x711E– Reserved 2 Reserved 0x711F (1) TheregistersinthiscolumnarePeripheralFrame2Registers. (2) TheADCresultregistersaredualmappedinthe280xDSP.LocationsinPeripheralFrame2(0x7108-0x7117)are2wait-statesandleft justified.LocationsinPeripheralframe0space(0x0B00-0x0B0F)are0waitsatesandrightjustified.Duringhigh-speed/continuous conversionuseoftheADC,usethe0wait-statelocationsforfasttransferofADCresultstousermemory. 90 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) TheCANmodulehasthefollowingfeatures: • FullycompliantwithCANprotocol,version2.0B • Supportsdataratesupto1Mbps • Thirty-twomailboxes,eachwiththefollowingproperties: – Configurableasreceiveortransmit – Configurablewithstandardorextendedidentifier – Hasaprogrammablereceivemask – Supportsdataandremoteframe – Composedof0to8bytesofdata – Usesa32-bittimestamponreceiveandtransmitmessage – Protectsagainstreceptionofnewmessage – Holdsthedynamicallyprogrammablepriorityoftransmitmessage – Employsaprogrammableinterruptschemewithtwointerruptlevels – Employsaprogrammablealarmontransmissionorreceptiontime-out • Low-powermode • Programmablewake-uponbusactivity • Automaticreplytoaremoterequestmessage • Automaticretransmissionofaframeincaseoflossofarbitrationorerror • 32-bit local network time counter synchronized by a specific message (communication in conjunction withmailbox16) • Self-testmode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, therebyeliminatingtheneedforanothernodetoprovidetheacknowledgebit. NOTE ForaSYSCLKOUTof100MHz,thesmallestbitratepossibleis15.625kbps. ForaSYSCLKOUTof60MHz,thesmallestbitratepossibleis9.375kbps. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 91 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com eCAN0INT eCAN1INT Controls Address Data Enhanced CAN Controller 32 Message Controller Mailbox RAM Memory Management (512 Bytes) Unit eCAN Memory (512 Bytes) CPU Interface, Registers and 32-Message Mailbox 32 Receive Control Unit, 32 Message Objects Control of 4 x 32-Bit Words Timer Management Unit 32 eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3.3-V CAN Transceiver CAN Bus Figure6-10.eCANBlockDiagramandInterfaceCircuit Table6-7.3.3-VeCANTransceivers SUPPLY LOW-POWER SLOPE PARTNUMBER VREF OTHER T VOLTAGE MODE CONTROL A SN65HVD230 3.3V Standby Adjustable Yes – –40°Cto85°C SN65HVD230Q 3.3V Standby Adjustable Yes – –40°Cto125°C SN65HVD231 3.3V Sleep Adjustable Yes – –40°Cto85°C SN65HVD231Q 3.3V Sleep Adjustable Yes – –40°Cto125°C SN65HVD232 3.3V None None None – –40°Cto85°C SN65HVD232Q 3.3V None None None – –40°Cto125°C SN65HVD233 3.3V Standby Adjustable None Diagnostic –40°Cto125°C Loopback SN65HVD234 3.3V Standby&Sleep Adjustable None – –40°Cto125°C SN65HVD235 3.3V Standby Adjustable None Autobaud –40°Cto125°C Loopback 92 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 eCAN-AControl and Status Registers Mailbox Enable - CANME Mailbox Direction - CANMD Transmission Request Set - CANTRS Transmission Request Reset - CANTRR TransmissionAcknowledge - CANTA eCAN-AMemory (512 Bytes) AbortAcknowledge - CANAA 6000h Received Message Pending - CANRMP Control and Status Registers Received Message Lost - CANRML 603Fh 6040h Remote Frame Pending - CANRFP LocalAcceptance Masks (LAM) (32 x 32-Bit RAM) GlobalAcceptance Mask - CANGAM 607Fh 6080h Master Control - CANMC Message Object Time Stamps (MOTS) (32 x 32-Bit RAM) Bit-Timing Configuration - CANBTC 60BFh 60C0h Error and Status - CANES Message Object Time-Out (MOTO) (32 x 32-Bit RAM) Transmit Error Counter - CANTEC 60FFh Receive Error Counter - CANREC Global Interrupt Flag 0 - CANGIF0 Global Interrupt Mask - CANGIM Global Interrupt Flag 1 - CANGIF1 eCAN-AMemory RAM (512 Bytes) Mailbox Interrupt Mask - CANMIM 6100h-6107h Mailbox 0 Mailbox Interrupt Level - CANMIL 6108h-610Fh Mailbox 1 Overwrite Protection Control - CANOPC 6110h-6117h Mailbox 2 TX I/O Control - CANTIOC 6118h-611Fh Mailbox 3 RX I/O Control - CANRIOC 6120h-6127h Mailbox 4 Time Stamp Counter - CANTSC Time-Out Control - CANTOC Time-Out Status - CANTOS 61E0h-61E7h Mailbox 28 Reserved 61E8h-61EFh Mailbox 29 61F0h-61F7h Mailbox 30 61F8h-61FFh Mailbox 31 Message Mailbox (16 Bytes) 61E8h-61E9h Message Identifier - MSGID 61EAh-61EBh Message Control - MSGCTRL 61ECh-61EDh Message Data Low - MDL 61EEh-61EFh Message Data High - MDH Figure6-11.eCAN-AMemoryMap NOTE If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, andmailboxRAM)canbeusedasgeneral-purposeRAM.TheCANmoduleclockshouldbe enabledforthis. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 93 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com eCAN-B Control and Status Registers Mailbox Enable - CANME Mailbox Direction - CANMD Transmission Request Set - CANTRS Transmission Request Reset - CANTRR TransmissionAcknowledge - CANTA eCAN-B Memory (512 Bytes) AbortAcknowledge - CANAA 6200h Received Message Pending - CANRMP Control and Status Registers Received Message Lost - CANRML 623Fh 6240h Remote Frame Pending - CANRFP LocalAcceptance Masks (LAM) (32 x 32-Bit RAM) GlobalAcceptance Mask - CANGAM 627Fh 6280h Master Control - CANMC Message Object Time Stamps (MOTS) (32 x 32-Bit RAM) Bit-Timing Configuration - CANBTC 62BFh 62C0h Error and Status - CANES Message Object Time-Out (MOTO) (32 x 32-Bit RAM) Transmit Error Counter - CANTEC 62FFh Receive Error Counter - CANREC Global Interrupt Flag 0 - CANGIF0 Global Interrupt Mask - CANGIM Global Interrupt Flag 1 - CANGIF1 eCAN-B Memory RAM (512 Bytes) Mailbox Interrupt Mask - CANMIM 6300h-6307h Mailbox 0 Mailbox Interrupt Level - CANMIL 6308h-630Fh Mailbox 1 Overwrite Protection Control - CANOPC 6310h-6317h Mailbox 2 TX I/O Control - CANTIOC 6318h-631Fh Mailbox 3 RX I/O Control - CANRIOC 6320h-6327h Mailbox 4 Time Stamp Counter - CANTSC Time-Out Control - CANTOC Time-Out Status - CANTOS 63E0h-63E7h Mailbox 28 Reserved 63E8h-63EFh Mailbox 29 63F0h-63F7h Mailbox 30 63F8h-63FFh Mailbox 31 Message Mailbox (16 Bytes) 63E8h-63E9h Message Identifier - MSGID 63EAh-63EBh Message Control - MSGCTRL 63ECh-63EDh Message Data Low - MDL 63EEh-63EFh Message Data High - MDH Figure6-12.eCAN-BMemoryMap 94 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 The CAN registers listed in Table 6-8 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM canbeaccessedas16bitsor32bits.32-bitaccessesarealignedtoanevenboundary. Table6-8.CANRegisterMap(1) eCAN-A eCAN-B SIZE REGISTERNAME DESCRIPTION ADDRESS ADDRESS (x32) CANME 0x6000 0x6200 1 Mailboxenable CANMD 0x6002 0x6202 1 Mailboxdirection CANTRS 0x6004 0x6204 1 Transmitrequestset CANTRR 0x6006 0x6206 1 Transmitrequestreset CANTA 0x6008 0x6208 1 Transmissionacknowledge CANAA 0x600A 0x620A 1 Abortacknowledge CANRMP 0x600C 0x620C 1 Receivemessagepending CANRML 0x600E 0x620E 1 Receivemessagelost CANRFP 0x6010 0x6210 1 Remoteframepending CANGAM 0x6012 0x6212 1 Globalacceptancemask CANMC 0x6014 0x6214 1 Mastercontrol CANBTC 0x6016 0x6216 1 Bit-timingconfiguration CANES 0x6018 0x6218 1 Errorandstatus CANTEC 0x601A 0x621A 1 Transmiterrorcounter CANREC 0x601C 0x621C 1 Receiveerrorcounter CANGIF0 0x601E 0x621E 1 Globalinterruptflag0 CANGIM 0x6020 0x6220 1 Globalinterruptmask CANGIF1 0x6022 0x6222 1 Globalinterruptflag1 CANMIM 0x6024 0x6224 1 Mailboxinterruptmask CANMIL 0x6026 0x6226 1 Mailboxinterruptlevel CANOPC 0x6028 0x6228 1 Overwriteprotectioncontrol CANTIOC 0x602A 0x622A 1 TXI/Ocontrol CANRIOC 0x602C 0x622C 1 RXI/Ocontrol CANTSC 0x602E 0x622E 1 Timestampcounter(ReservedinSCCmode) CANTOC 0x6030 0x6230 1 Time-outcontrol(ReservedinSCCmode) CANTOS 0x6032 0x6232 1 Time-outstatus(ReservedinSCCmode) (1) TheseregistersaremappedtoPeripheralFrame1. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 95 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.2.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) The 280x devices include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non- return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full- duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud- selectregister. FeaturesofeachSCImoduleinclude: • Twoexternalpins: – SCITXD:SCItransmit-outputpin – SCIRXD:SCIreceive-inputpin NOTE: BothpinscanbeusedasGPIOifnotusedforSCI. – Baudrateprogrammableto64Kdifferentrates: LSPCLK Baudrate= whenBRR¹0 (BRR+1)*8 LSPCLK Baudrate= whenBRR=0 16 • Data-wordformat – Onestartbit – Data-wordlengthprogrammablefromonetoeightbits – Optionaleven/odd/noparitybit – Oneortwostopbits • Fourerror-detectionflags:parity,overrun,framing,andbreakdetection • Twowake-upmultiprocessormodes:idle-lineandaddressbit • Half-orfull-duplexoperation • Double-bufferedreceiveandtransmitfunctions • Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms withstatusflags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTYflag(transmitter-shiftregisterisempty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (breakconditionoccurred),andRXERRORflag(monitoringfourinterruptconditions) • Separateenablebitsfortransmitterandreceiverinterrupts(exceptBRKDT) 100MHz Maxbitrate= =6.25´106b/s (for100-MHzdevices) • 16 60MHz Maxbitrate= =3.75´106b/s (for60-MHzdevices) 16 • NRZ(non-return-to-zero)format • TenSCImodulecontrolregisterslocatedinthecontrolregisterframebeginningataddress7050h NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When aregister is accessed, theregister data is inthelowerbyte(7–0),andtheupperbyte (15–8)isreadaszeros.Writingtotheupperbytehasnoeffect. 96 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Enhancedfeatures: • Autobaud-detecthardwarelogic • 16-leveltransmit/receiveFIFO TheSCIportoperationisconfiguredandcontrolledbytheregisterslistedinTable6-9andTable6-10. Table6-9.SCI-ARegisters(1) NAME ADDRESS SIZE(x16) DESCRIPTION SCICCRA 0x7050 1 SCI-ACommunicationsControlRegister SCICTL1A 0x7051 1 SCI-AControlRegister1 SCIHBAUDA 0x7052 1 SCI-ABaudRegister,HighBits SCILBAUDA 0x7053 1 SCI-ABaudRegister,LowBits SCICTL2A 0x7054 1 SCI-AControlRegister2 SCIRXSTA 0x7055 1 SCI-AReceiveStatusRegister SCIRXEMUA 0x7056 1 SCI-AReceiveEmulationDataBufferRegister SCIRXBUFA 0x7057 1 SCI-AReceiveDataBufferRegister SCITXBUFA 0x7059 1 SCI-ATransmitDataBufferRegister SCIFFTXA(2) 0x705A 1 SCI-AFIFOTransmitRegister SCIFFRXA(2) 0x705B 1 SCI-AFIFOReceiveRegister SCIFFCTA(2) 0x705C 1 SCI-AFIFOControlRegister SCIPRIA 0x705F 1 SCI-APriorityControlRegister (1) RegistersinthistablearemappedtoPeripheralFrame2space.Thisspaceonlyallows16-bitaccesses.32-bitaccessesproduce undefinedresults. (2) TheseregistersarenewregistersfortheFIFOmode. Table6-10.SCI-BRegisters(1) (2) NAME ADDRESS SIZE(x16) DESCRIPTION SCICCRB 0x7750 1 SCI-BCommunicationsControlRegister SCICTL1B 0x7751 1 SCI-BControlRegister1 SCIHBAUDB 0x7752 1 SCI-BBaudRegister,HighBits SCILBAUDB 0x7753 1 SCI-BBaudRegister,LowBits SCICTL2B 0x7754 1 SCI-BControlRegister2 SCIRXSTB 0x7755 1 SCI-BReceiveStatusRegister SCIRXEMUB 0x7756 1 SCI-BReceiveEmulationDataBufferRegister SCIRXBUFB 0x7757 1 SCI-BReceiveDataBufferRegister SCITXBUFB 0x7759 1 SCI-BTransmitDataBufferRegister SCIFFTXB(2) 0x775A 1 SCI-BFIFOTransmitRegister SCIFFRXB(2) 0x775B 1 SCI-BFIFOReceiveRegister SCIFFCTB(2) 0x775C 1 SCI-BFIFOControlRegister SCIPRIB 0x775F 1 SCI-BPriorityControlRegister (1) Registersinthistablearemappedtoperipheralbus16space.Thisspaceonlyallows16-bitaccesses.32-bitaccessesproduce undefinedresults. (2) TheseregistersarenewregistersfortheFIFOmode. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 97 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Figure6-13showstheSCImoduleblockdiagram. SCICTL1.1 SCITXD Frame Format and Mode TXSHF SCITXD Register TXENA Parity TX EMPTY Even/Odd Enable SCICTL2.6 8 SCICCR.6 SCICCR.5 TXRDY TX INT ENA Transmitter-Data SCICTL2.7 Buffer Register SCICTL2.0 TXWAKE 8 TXINT SCICTL1.3 TX FIFO _0 TX Interrupt Logic TX FIFO _1 TX To CPU 1 - - - - - FIFO Interrupts SCI TX Interrupt Select Logic TX FIFO _15 WUT SCITXBUF.7-0 TX FIFO Registers AutoBaud Detect Logic SCIFFENA SCIHBAUD. 15 - 8 SCIFFTX.14 Baud Rate SCIRXD RXSHF Register SCIRXD MSbyte LSPCLK Register RXWAKE SCIRXST.1 SCILBAUD. 7 - 0 RXENA SCICTL1.0 Baud Rate 8 LSbyte SCICTL2.1 Register Receive-Data RXRDY RX/BK INT ENA Buffer Register SCIRXST.6 SCIRXBUF.7-0 BRKDT 8 SCIRXST.5 RX FIFO _15 - - - - - RX FIFO RX FIFO _1 Interrupts RXINT RX FIFO _0 RX Interrupt Logic SCIRXBUF.7-0 To CPU RX FIFO Registers RXFFOVF SCIRXST.7 SCIRXST.4 - 2 SCIFFRX.15 RX Error FE OE PE RX Error RX ERR INT ENA SCI RX Interrupt Select Logic SCICTL1.6 Figure6-13.SerialCommunicationsInterface(SCI)ModuleBlockDiagram 98 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules (SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communicationsaresupportedbythemaster/slaveoperationoftheSPI. TheSPImodulefeaturesinclude: • Fourexternalpins: – SPISOMI:SPIslave-output/master-inputpin – SPISIMO:SPIslave-input/master-outputpin – SPISTE:SPIslavetransmit-enablepin – SPICLK:SPIserial-clockpin NOTE: AllfourpinscanbeusedasGPIO,iftheSPImoduleisnotused. • Twooperationalmodes:masterandslave Baudrate:125differentprogrammablerates. LSPCLK Baudrate= whenSPIBRR=3to127 (SPIBRR+1) LSPCLK Baudrate= whenSPIBRR=0,1,2 4 • Datawordlength:onetosixteendatabits • Fourclockingschemes(controlledbyclockpolarityandclockphasebits)include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLKsignalandreceivesdataontherisingedgeoftheSPICLKsignal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the fallingedgeoftheSPICLKsignalandreceivesdataonthefallingedgeoftheSPICLKsignal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLKsignalandreceivesdataonthefallingedgeoftheSPICLKsignal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the risingedgeoftheSPICLKsignalandreceivesdataontherisingedgeoftheSPICLKsignal. • Simultaneousreceiveandtransmitoperation(transmitfunctioncanbedisabledinsoftware) • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. • NineSPImodulecontrolregisters:Locatedincontrolregisterframebeginningataddress7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When aregister is accessed, theregister data is inthelowerbyte(7–0),andtheupperbyte (15–8)isreadaszeros.Writingtotheupperbytehasnoeffect. Enhancedfeature: • 16-leveltransmit/receiveFIFO • Delayedtransmitcontrol Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 99 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com The SPI port operation is configured and controlled by the registers listed in Table 6-11 through Table 6- 14. Table6-11.SPI-ARegisters NAME ADDRESS SIZE(x16) DESCRIPTION(1) SPICCR 0x7040 1 SPI-AConfigurationControlRegister SPICTL 0x7041 1 SPI-AOperationControlRegister SPISTS 0x7042 1 SPI-AStatusRegister SPIBRR 0x7044 1 SPI-ABaudRateRegister SPIRXEMU 0x7046 1 SPI-AReceiveEmulationBufferRegister SPIRXBUF 0x7047 1 SPI-ASerialInputBufferRegister SPITXBUF 0x7048 1 SPI-ASerialOutputBufferRegister SPIDAT 0x7049 1 SPI-ASerialDataRegister SPIFFTX 0x704A 1 SPI-AFIFOTransmitRegister SPIFFRX 0x704B 1 SPI-AFIFOReceiveRegister SPIFFCT 0x704C 1 SPI-AFIFOControlRegister SPIPRI 0x704F 1 SPI-APriorityControlRegister (1) RegistersinthistablearemappedtoPeripheralFrame2.Thisspaceonlyallows16-bitaccesses.32-bitaccessesproduceundefined results. Table6-12.SPI-BRegisters NAME ADDRESS SIZE(x16) DESCRIPTION(1) SPICCR 0x7740 1 SPI-BConfigurationControlRegister SPICTL 0x7741 1 SPI-BOperationControlRegister SPISTS 0x7742 1 SPI-BStatusRegister SPIBRR 0x7744 1 SPI-BBaudRateRegister SPIRXEMU 0x7746 1 SPI-BReceiveEmulationBufferRegister SPIRXBUF 0x7747 1 SPI-BSerialInputBufferRegister SPITXBUF 0x7748 1 SPI-BSerialOutputBufferRegister SPIDAT 0x7749 1 SPI-BSerialDataRegister SPIFFTX 0x774A 1 SPI-BFIFOTransmitRegister SPIFFRX 0x774B 1 SPI-BFIFOReceiveRegister SPIFFCT 0x774C 1 SPI-BFIFOControlRegister SPIPRI 0x774F 1 SPI-BPriorityControlRegister (1) RegistersinthistablearemappedtoPeripheralFrame2.Thisspaceonlyallows16-bitaccesses.32-bitaccessesproduceundefined results. 100 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table6-13.SPI-CRegisters NAME ADDRESS SIZE(x16) DESCRIPTION(1) SPICCR 0x7760 1 SPI-CConfigurationControlRegister SPICTL 0x7761 1 SPI-COperationControlRegister SPISTS 0x7762 1 SPI-CStatusRegister SPIBRR 0x7764 1 SPI-CBaudRateRegister SPIRXEMU 0x7766 1 SPI-CReceiveEmulationBufferRegister SPIRXBUF 0x7767 1 SPI-CSerialInputBufferRegister SPITXBUF 0x7768 1 SPI-CSerialOutputBufferRegister SPIDAT 0x7769 1 SPI-CSerialDataRegister SPIFFTX 0x776A 1 SPI-CFIFOTransmitRegister SPIFFRX 0x776B 1 SPI-CFIFOReceiveRegister SPIFFCT 0x776C 1 SPI-CFIFOControlRegister SPIPRI 0x776F 1 SPI-CPriorityControlRegister (1) RegistersinthistablearemappedtoPeripheralFrame2.Thisspaceonlyallows16-bitaccesses.32-bitaccessesproduceundefined results. Table6-14.SPI-DRegisters NAME ADDRESS SIZE(x16) DESCRIPTION(1) SPICCR 0x7780 1 SPI-DConfigurationControlRegister SPICTL 0x7781 1 SPI-DOperationControlRegister SPISTS 0x7782 1 SPI-DStatusRegister SPIBRR 0x7784 1 SPI-DBaudRateRegister SPIRXEMU 0x7786 1 SPI-DReceiveEmulationBufferRegister SPIRXBUF 0x7787 1 SPI-DSerialInputBufferRegister SPITXBUF 0x7788 1 SPI-DSerialOutputBufferRegister SPIDAT 0x7789 1 SPI-DSerialDataRegister SPIFFTX 0x778A 1 SPI-DFIFOTransmitRegister SPIFFRX 0x778B 1 SPI-DFIFOReceiveRegister SPIFFCT 0x778C 1 SPI-DFIFOControlRegister SPIPRI 0x778F 1 SPI-DPriorityControlRegister (1) RegistersinthistablearemappedtoPeripheralFrame2.Thisspaceonlyallows16-bitaccesses.32-bitaccessesproduceundefined results. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 101 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Figure6-14isablockdiagramoftheSPIinslavemode. SPIFFENA SPIFFTX.14 Receiver Overrun RX FIFO Registers Overrun Flag INT ENA SPIRXBUF SPISTS.7 RX FIFO _0 SPICTL.4 RX FIFO _1 RX - - - - - FIFO RX FIFO _15 Interrupt SPIINT/SPIRXINT RX Interrupt Logic 16 SPIFFOVF SPIRXBUF Buffer Register FLAG To CPU SPIFFRX.15 TX TX FIFO Registers FIFO SPITXBUF Interrupt TX Interrupt Logic SPITXINT TX FIFO _15 - - - - - SPI SPI TX FIFO _1 INT FLAG INT ENA 16 TX FIFO _0 SPISTS.6 16 SPICTL.0 SPITXBUF Buffer Register 16 M M S SPIDAT Data Register S SW1 SPISIMO M SPIDAT.15 - 0 M S S SW2 SPISOMI Talk SPICTL.1 (A) SPISTE State Control Master/Slave SPI Char SPICCR.3 - 0 SPICTL.2 S 3 2 1 0 SW3 Clock Clock SPI Bit Rate M S Polarity Phase LSPCLK SPIBRR.6 - 0 SPICCR.6 SPICTL.3 SPICLK M 6 5 4 3 2 1 0 A. SPISTEisdrivenlowbythemasterforaslavedevice. Figure6-14.SPIModuleBlockDiagram(SlaveMode) 102 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.10 Inter-Integrated Circuit (I2C) The 280x device contains one I2C Serial Port. Figure 6-15 shows how the I2C peripheral module interfaceswithinthe280xdevice. TheI2Cmodulehasthefollowingfeatures: • CompliancewiththePhilipsSemiconductorsI2C-busspecification(version2.1): – Supportfor1-bitto8-bitformattransfers – 7-bitand10-bitaddressingmodes – Generalcall – STARTbytemode – Supportformultiplemaster-transmittersandslave-receivers – Supportformultipleslave-transmittersandmaster-receivers – Combinedmastertransmit/receiveandreceive/transmitmode – Datatransferrateoffrom10kbpsupto400kbps(I2CFast-moderate) • One16-wordreceiveFIFOandone16-wordtransmitFIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the followingconditions: – Transmit-dataready – Receive-dataready – Register-accessready – No-acknowledgmentreceived – Arbitrationlost – Stopconditiondetected – Addressedasslave • AnadditionalinterruptthatcanbeusedbytheCPUwheninFIFOmode • Moduleenable/disablecapability • Freedataformatmode Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 103 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com System Control Block C28x CPU I2CAENCLK SYSCLKOUT SYSRS s u B Control al r e h Data[16] rip e P SDAA Data[16] I2C-A GPIO Addr[16] MUX SCLA I2CINT1A PIE Block I2CINT2A A. TheI2CregistersareaccessedattheSYSCLKOUTrate.TheinternaltimingandsignalwaveformsoftheI2Cportare alsoattheSYSCLKOUTrate. B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation.Uponreset,I2CAENCLKisclear,whichindicatestheperipheralinternalclocksareoff. Figure6-15.I2CPeripheralModuleInterfaces TheregistersinTable6-15configureandcontroltheI2Cportoperation. Table6-15.I2C-ARegisters NAME ADDRESS DESCRIPTION I2COAR 0x7900 I2Cownaddressregister I2CIER 0x7901 I2Cinterruptenableregister I2CSTR 0x7902 I2Cstatusregister I2CCLKL 0x7903 I2Cclocklow-timedividerregister I2CCLKH 0x7904 I2Cclockhigh-timedividerregister I2CCNT 0x7905 I2Cdatacountregister I2CDRR 0x7906 I2Cdatareceiveregister I2CSAR 0x7907 I2Cslaveaddressregister I2CDXR 0x7908 I2Cdatatransmitregister I2CMDR 0x7909 I2Cmoderegister I2CISRC 0x790A I2Cinterruptsourceregister I2CPSC 0x790C I2Cprescalerregister I2CFFTX 0x7920 I2CFIFOtransmitregister I2CFFRX 0x7921 I2CFIFOreceiveregister I2CRSR - I2Creceiveshiftregister(notaccessibletotheCPU) I2CXSR - I2Ctransmitshiftregister(notaccessibletotheCPU) 104 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.2.11 GPIO MUX On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in Figure 6-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x280x, 2801x, 2804x DSP system control and interrupts referenceguide fordetails. GPIOXINT1SEL GPIOLMPSEL GPIOXINT2SEL LPMCR0 GPIOXNMISEL Low-Power External Interrupt PIE Modes Block MUX Asynchronous GPxDAT (read) path GPxQSEL1/2 GPxCTRL GPxPUD 00 N/C 01 Peripheral 1 Input Input Internal Qualification Pullup 10 Peripheral 2 Input 11 Peripheral 3 Input Asynchronous path GPxTOGGLE GPIOx pin GPxCLEAR GPxSET 00 GPxDAT (latch) 01 Peripheral 1 Output 10 Peripheral 2 Output 11 Peripheral 3 Output High-Impedance Output Control 00 GPxDIR (latch) 0 = Input, 1 = Output 01 Peripheral 1 Output Enable 10 Peripheral 2 Output Enable XRS 11 Peripheral 3 Output Enable = Default at Reset GPxMUX1/2 A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register dependingontheparticularGPIOpinselected. B. GPxDATlatch/readareaccessedatthesamememorylocation. Figure6-16.GPIOMUXBlockDiagram Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 105 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-16 shows the GPIO registermapping. Table6-16.GPIORegisters NAME ADDRESS SIZE(x16) DESCRIPTION GPIOCONTROLREGISTERS(EALLOWPROTECTED) GPACTRL 0x6F80 2 GPIOAControlRegister(GPIO0to31) GPAQSEL1 0x6F82 2 GPIOAQualifierSelect1Register(GPIO0to15) GPAQSEL2 0x6F84 2 GPIOAQualifierSelect2Register(GPIO16to31) GPAMUX1 0x6F86 2 GPIOAMUX1Register(GPIO0to15) GPAMUX2 0x6F88 2 GPIOAMUX2Register(GPIO16to31) GPADIR 0x6F8A 2 GPIOADirectionRegister(GPIO0to31) GPAPUD 0x6F8C 2 GPIOAPullUpDisableRegister(GPIO0to31) 0x6F8E– Reserved 2 Reserved 0x6F8F GPBCTRL 0x6F90 2 GPIOBControlRegister(GPIO32to35) GPBQSEL1 0x6F92 2 GPIOBQualifierSelect1Register(GPIO32to35) GPBQSEL2 0x6F94 2 Reserved GPBMUX1 0x6F96 2 GPIOBMUX1Register(GPIO32to35) GPBMUX2 0x6F98 2 Reserved GPBDIR 0x6F9A 2 GPIOBDirectionRegister(GPIO32to35) GPBPUD 0x6F9C 2 GPIOBPullUpDisableRegister(GPIO32to35) 0x6F9E– Reserved 2 Reserved 0x6F9F 0x6FA0– Reserved 32 Reserved 0x6FBF GPIODATAREGISTERS(NOTEALLOWPROTECTED) GPADAT 0x6FC0 2 GPIODataRegister(GPIO0to31) GPASET 0x6FC2 2 GPIODataSetRegister(GPIO0to31) GPACLEAR 0x6FC4 2 GPIODataClearRegister(GPIO0to31) GPATOGGLE 0x6FC6 2 GPIODataToggleRegister(GPIO0to31) GPBDAT 0x6FC8 2 GPIODataRegister(GPIO32to35) GPBSET 0x6FCA 2 GPIODataSetRegister(GPIO32to35) GPBCLEAR 0x6FCC 2 GPIODataClearRegister(GPIO32to35) GPBTOGGLE 0x6FCE 2 GPIODataToggleRegister(GPIO32to35) 0x6FD0– Reserved 16 Reserved 0x6FDF GPIOINTERRUPTANDLOWPOWERMODESSELECTREGISTERS(EALLOWPROTECTED) GPIOXINT1SEL 0x6FE0 1 XINT1GPIOInputSelectRegister(GPIO0to31) GPIOXINT2SEL 0x6FE1 1 XINT2GPIOInputSelectRegister(GPIO0to31) GPIOXNMISEL 0x6FE2 1 XNMIGPIOInputSelectRegister(GPIO0to31) 0x6FE3– Reserved 5 Reserved 0x6FE7 GPIOLPMSEL 0x6FE8 2 LPMGPIOSelectRegister(GPIO0to31) 0x6FEA– Reserved 22 Reserved 0x6FFF 106 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table6-17.F2808GPIOMUXTable DEFAULTATRESET GPAMUX1/2(1) PRIMARYI/O PERIPHERAL PERIPHERAL PERIPHERAL REGISTER FUNCTION SELECTION1(2) SELECTION2 SELECTION3 BITS (GPxMUX1/2 (GPxMUX1/2BITS=0,1) (GPxMUX1/2BITS=1,0) (GPxMUX1/2BITS=1,1) BITS=0,0) GPAMUX1 1–0 GPIO0 EPWM1A(O) Reserved(3) Reserved(3) 3–2 GPIO1 EPWM1B(O) SPISIMOD(I/O) Reserved(3) 5–4 GPIO2 EPWM2A(O) Reserved(3) Reserved(3) 7–6 GPIO3 EPWM2B(O) SPISOMID(I/O) Reserved(3) 9–8 GPIO4 EPWM3A(O) Reserved(3) Reserved(3) 11–10 GPIO5 EPWM3B(O) SPICLKD(I/O) ECAP1(I/O) 13–12 GPIO6 EPWM4A(O) EPWMSYNCI(I) EPWMSYNCO(O) 15–14 GPIO7 EPWM4B(O) SPISTED(I/O) ECAP2(I/O) 17–16 GPIO8 EPWM5A(O) CANTXB(O) ADCSOCAO(O) 19–18 GPIO9 EPWM5B(O) SCITXDB(O) ECAP3(I/O) 21–20 GPIO10 EPWM6A(O) CANRXB(I) ADCSOCBO(O) 23–22 GPIO11 EPWM6B(O) SCIRXDB(I) ECAP4(I/O) 25–24 GPIO12 TZ1(I) CANTXB(O) SPISIMOB(I/O) 27–26 GPIO13 TZ2(I) CANRXB(I) SPISOMIB(I/O) 29–28 GPIO14 TZ3(I) SCITXDB(O) SPICLKB(I/O) 31–30 GPIO15 TZ4(I) SCIRXDB(I) SPISTEB(I/O) GPAMUX2 1–0 GPIO16 SPISIMOA(I/O) CANTXB(O) TZ5(I) 3–2 GPIO17 SPISOMIA(I/O) CANRXB(I) TZ6(I) 5–4 GPIO18 SPICLKA(I/O) SCITXDB(O) Reserved(3) 7–6 GPIO19 SPISTEA(I/O) SCIRXDB(I) Reserved(3) 9–8 GPIO20 EQEP1A(I) SPISIMOC(I/O) CANTXB(O) 11–10 GPIO21 EQEP1B(I) SPISOMIC(I/O) CANRXB(I) 13–12 GPIO22 EQEP1S(I/O) SPICLKC(I/O) SCITXDB(O) 15–14 GPIO23 EQEP1I(I/O) SPISTEC(I/O) SCIRXDB(I) 17–16 GPIO24 ECAP1(I/O) EQEP2A(I) SPISIMOB(I/O) 19–18 GPIO25 ECAP2(I/O) EQEP2B(I) SPISOMIB(I/O) 21–20 GPIO26 ECAP3(I/O) EQEP2I(I/O) SPICLKB(I/O) 23–22 GPIO27 ECAP4(I/O) EQEP2S(I/O) SPISTEB(I/O) 25–24 GPIO28 SCIRXDA(I) Reserved(3) TZ5(I) 27–26 GPIO29 SCITXDA(O) Reserved(3) TZ6(I) 29–28 GPIO30 CANRXA(I) Reserved(3) Reserved(3) 31–30 GPIO31 CANTXA(O) Reserved(3) Reserved(3) GPBMUX1 1–0 GPIO32 SDAA(I/OC) EPWMSYNCI(I) ADCSOCAO(O) 3–2 GPIO33 SCLA(I/OC) EPWMSYNCO(O) ADCSOCBO(O) 5–4 GPIO34 Reserved(3) Reserved(3) Reserved(3) (1) GPxMUX1/2referstotheappropriateMUXregisterforthepin;GPAMUX1,GPAMUX2orGPBMUX1. (2) Thistablepertainstothe2808device.Someperipheralsmaynotbeavailableinthe2809,2806,2802,or2801devices.Seethepin descriptionsformoredetail. (3) Theword"Reserved"meansthatthereisnoperipheralassignedtothisGPxMUX1/2registersetting.Shoulditbeselected,thestateof thepinwillbeundefinedandthepinmaybedriven.Thisselectionisareservedconfigurationforfutureexpansion. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 107 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from fourchoices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0,0): This is the default mode of all GPIO pins atresetanditsimplysynchronizestheinputsignaltothesystemclock(SYSCLKOUT). • Qualification Using Sampling Window (GPxQSEL1/2 = 0,1 and 1,0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before theinputisallowedtochange. Time Between Samples GPyCTRLReg Input Signal GPIOx SYNC Qualification Qualified by 3 or 6 Samples GPxQSEL SYSCLKOUT Number of Samples Figure6-17.QualificationUsingSamplingWindow • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samplesarethesame(all0sorall1s)asshowninFigure5-11(for6-samplemode). • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is notrequired(synchronizationisperformedwithintheperipheral). Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected,theinputsignalwilldefaulttoeithera0or1state,dependingontheperipheral. 108 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.3 Memory Maps Block Start Address Data Space Prog Space 0x00 0000 M0 Vector − RAM (32 x 32) (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K (cid:1) 16) 0x00 0400 ÉÉÉÉÉ M1 SARAM (1K (cid:1) 16) 0x00 0800 ÉÉÉÉÉ Peripheral Frame 0 e) ÉÉÉÉÉ K [0000 − FFFF]uivalent data spac 000xxx000000 006DE0000000ÉÉÉ(EÉÉÉPnPeaIrEbip l(VÉÉÉehR2ede5ec r6istaf oe xlE ÉÉÉrr F vN1−re6Pa Rd)mI EAÉÉÉe M= 1 1)ÉÉÉÉÉÉÉÉÉÉÉÉÉReÉÉÉÉÉserveÉÉÉÉÉd ÉÉÉÉÉ Low 64x/240x eq 0x00 7000ÉÉPerip((ppÉhrreoorttaeelcc ÉFtteeraddm))Ée 2 ÉÉÉÉÉÉÉReÉÉÉserveÉÉÉd ÉÉÉ 4 (2 0x00 8000 ÉÉÉÉÉ L0 SARAM (0-wait) (4K (cid:1) 16, Secure Zone, Dual-Mapped) 0x00 9000 L1 SARAM (0-wait) ÉÉ(4ÉK (cid:1) 1É6, SeÉcure ZÉone,É Dual-ÉMappÉed) É 0x00 A000 ÉÉÉÉ(8KH 0(cid:1)É S1A6,R DAÉuMa l(-0MÉ-wapapite)Éd) ÉÉ 0x00 C00É0 ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉResÉervedÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 0x3D 7800ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ OTP (1K (cid:1) 16, Secure Zone) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x3D 7C00 Reserved ÉÉÉÉÉÉÉÉÉÉ 0x3D 8000 ÉÉÉÉÉÉÉÉÉÉ FLASH (128K (cid:1) 16, Secure Zone) e) 0x3F 7FF8 128-bit Password c a 0x3F 8000 F]sp L0 SARAM (0-wait) FFm (4K (cid:1) 16, Secure Zone, Dual-Mapped) K [3F0000 − 3FFuivalent progra 00xx33FF A9000000ÉÉÉÉ(4ÉÉK (cid:1) 1ÉÉ6(8, KHLS 10e(cid:1)ÉÉ c SS1uAA6r,ReR D AAZÉÉuMoMan l((-e00M,-ÉÉ- wDwapuaapiaittel))-ÉÉdM)appÉÉed) ÉÉ High 64240x eq 00xx33FF CF000000ÉÉÉÉBooÉtR ReOsÉMer v(4eKdÉ (cid:1) 16)ÉÉÉ x/ ÉÉÉÉÉÉÉÉÉÉ 4 (2 0x3F FFC0 Vectors (32 (cid:1) 32) (enabled if VMAP = 1, ENPIE = 0) A. Memoryblocksarenottoscale. B. PeripheralFrame0,PeripheralFrame1,andPeripheralFrame2memorymapsarerestrictedtodatamemoryonly. Userprogramcannotaccessthesememorymapsinprogramspace. C. ProtectedmeanstheorderofWritefollowedbyReadoperationsispreservedratherthanthepipelineorder. D. CertainmemoryrangesareEALLOWprotectedagainstspuriouswritesafterconfiguration. Figure6-18.F2809MemoryMap Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 109 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Block Start Address Data Space Prog Space 0x00 0000 M0 Vector − RAM (32 x 32) (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K (cid:1) 16) 0x00 0400 ÉÉÉÉÉ M1 SARAM (1K (cid:1) 16) 0x00 0800 ÉÉÉÉÉ Peripheral Frame 0 e) ÉÉÉÉÉ Low 64K [0000 − FFFF]x/240x equivalent data spac 0000xxxx00000000 0 067DE0000000000ÉÉÉÉ(ÉÉÉÉPPEeenPrraIiiEpb(p(pp ÉÉÉÉ hlh(VRerr2eeooede5rrtct asa6eietflel coc ÉÉÉÉxEFrFttr vee rN1r−eadad6P dmm))R)I EÉÉÉÉeAe M=21 1)ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉRRÉÉÉÉÉÉÉÉeesseerrvvÉÉÉÉÉÉÉÉeedd ÉÉÉÉÉÉÉÉ 4 (2 0x00 8000 ÉÉÉÉÉ L0 SARAM (0-wait) (4K (cid:1) 16, Secure Zone, Dual-Mapped) 0x00 9000 L1 SARAM (0-wait) ÉÉ(É4K (cid:1) 1É6, SeÉcure ZÉone,É Dual-ÉMappÉed) É 0x00 A000 ÉÉÉÉ(8KH 0(cid:1)É S1A6,R DAÉuMa l(-0MÉ-wapapite)Éd) ÉÉ 0x00 C00É0 ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉReseÉrvedÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 0x3D 7800ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ OTP (1K (cid:1) 16, Secure Zone) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x3D 7C00 ÉÉÉÉÉReseÉrvedÉÉÉÉ 0x3E 800É0 ÉÉÉÉÉÉÉÉÉ FLASH (64K (cid:1) 16, Secure Zone) e) 0x3F 7FF8 128-bit Password c a 0x3F 8000 F]sp L0 SARAM (0-wait) FFm (4K (cid:1) 16, Secure Zone, Dual-Mapped) K [3F0000 − 3FFuivalent progra 00xx33FF A9000000ÉÉÉÉ(ÉÉ4K (cid:1) 1ÉÉ6(8, KHLS 10e(cid:1)ÉÉ c SS1uAA6r,ReR D AAZÉÉuMoMan l((-e00M,ÉÉ-- wDwapuaapiaittel))-ÉÉdM)appÉÉed) ÉÉ High 64240x eq 00xx33FF CF000000ÉÉÉÉBoÉoRt ResOeÉMrv (e4dKÉ (cid:1) 16)ÉÉÉ x/ ÉÉÉÉÉÉÉÉÉÉ 4 (2 0x3F FFC0 Vectors (32 (cid:1) 32) (enabled if VMAP = 1, ENPIE = 0) A. Memoryblocksarenottoscale. B. PeripheralFrame0,PeripheralFrame1,andPeripheralFrame2memorymapsarerestrictedtodatamemoryonly. Userprogramcannotaccessthesememorymapsinprogramspace. C. ProtectedmeanstheorderofWritefollowedbyReadoperationsispreservedratherthanthepipelineorder. D. CertainmemoryrangesareEALLOWprotectedagainstspuriouswritesafterconfiguration. Figure6-19.F2808MemoryMap 110 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Block Start Address Data Space Prog Space 0x00 0000 M0 Vector − RAM (32 x 32) (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K (cid:1) 16) 0x00 0400 ÉÉÉÉÉ M1 SARAM (1K (cid:1) 16) 0x00 0800 ÉÉÉÉÉ ce) Peripheral Frame 0 ÉÉÉÉÉ a p 0x00 0D00 K [0000−FFFF]uivalent data s 00xx0000 06E00000ÉÉÉ(ÉÉÉEnPaIEb ÉÉÉl(VeR2ed5ec 6istf oe xÉÉÉErr v N1−e6P dR)I EÉÉÉA M= 1)ÉÉÉÉÉÉÉÉÉÉÉÉÉReÉÉÉÉÉserveÉÉÉÉÉd ÉÉÉÉÉ Low 64240x eq 0x00 7000ÉÉPerip(ÉphreortaelcÉ Fteradm)Ée 1 ÉÉÉÉÉReÉÉserveÉÉd ÉÉ x/ Peripheral Frame 2 ÉÉÉÉÉ 24 (protected) ( 0x00 8000 ÉÉÉÉÉ L0 SARAM (0-wait) ÉÉ(4ÉK (cid:1) 1É6, SeÉcure ZÉÉone, ÉÉDual-ÉÉMappÉÉed) ÉÉ 0x00 9000 L1 SARAM (0-wait) ÉÉ(4ÉK (cid:1) 1É6, SecÉure ZÉone, ÉDual-MÉappÉed) É 0x00 A000ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x3D 7800 OTP ÉÉÉÉÉÉ(ÉÉ1K (cid:1) ÉÉ16, SeÉÉcure ÉÉZoneÉÉ) ÉÉÉÉ 0x3D 7C00 ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ 0x3F 0000 ÉÉÉÉÉFLÉASHÉÉÉÉ (32K (cid:1) 16, Secure Zone) ce) 0x3F 7FF8 128-bit Password a 4K [3F0000 −3FFFF]quivalent program sp 000xxx333FFF A89000000000ÉÉÉÉÉÉ((4ÉÉÉ4KK (cid:1)(cid:1) 11ÉÉÉ66,, LSLS10eeÉÉÉ ccSSRuuAAerreResR eAAZZÉÉÉroMoMvnne ((dee00,,ÉÉÉ-- DwDwuuaaaiaittll))--ÉÉÉMMaappppÉÉÉeedd)) ÉÉÉ h 6x e ÉÉÉÉÉÉÉÉÉÉ g0 Hi24 0x3F F000 4x/ ÉÉÉÉBoÉot ROÉM (4KÉ (cid:1) 16É) ÉÉ 2 ( 0x3F FFC0 Vectors (32 (cid:1) 32) (enabled if VMAP = 1, ENPIE = 0) A. Memoryblocksarenottoscale. B. PeripheralFrame0,PeripheralFrame1,andPeripheralFrame2memorymapsarerestrictedtodatamemoryonly. Userprogramcannotaccessthesememorymapsinprogramspace. C. ProtectedmeanstheorderofWritefollowedbyReadoperationsispreservedratherthanthepipelineorder. D. CertainmemoryrangesareEALLOWprotectedagainstspuriouswritesafterconfiguration. Figure6-20.F2806MemoryMap Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 111 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Block Start Address Data Space Prog Space 0x00 0000 M0 Vector − RAM (32 x 32) (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K (cid:1) 16) ÉÉÉÉÉ 0x00 0400 M1 SARAM (1K (cid:1) 16) ce) 0x00 0800 ÉÉÉÉÉ a p K [0000−FFFF]uivalent data s 00xx0000 00DE0000 ÉÉ(EPnPÉÉeaIrEbip l(Veh2edeÉÉ5c r6itaf o xlE r F N1−ÉÉr6Pa R)mI EAe M= ÉÉ0 1) ÉÉÉÉÉÉÉÉResÉÉÉÉervedÉÉÉÉÉÉÉÉ Low 64x/240x eq 0x00 6000 ÉÉPÉÉerip(phRreÉÉeorstaeelc rFvteÉÉreaddm)e ÉÉ1 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 4 (2 0x00 7000 Peripheral Frame 2 ÉÉResÉervedÉÉ (protected) 0x00 8000 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ L0 SARAM (0-wait) (4K (cid:1) 16, Secure Zone, Dual-Mapped) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x00 9000 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x3D 7800 OTP (F2802 Only)(A) ÉÉÉÉÉÉ(1ÉÉK (cid:1) 1ÉÉ6, SecÉÉure ZÉÉone)ÉÉÉÉÉÉ 0x3D 7C00 ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ 0x3F 0000 ÉÉÉFLASÉH (F2É802) oÉr ROÉM (C2É802)ÉÉ e) (32K (cid:1) 16, Secure Zone) c 0x3F 7FF8 a FF]m sp 0x3F 8000 128-bit Password K [3F0000 −3FFuivalent progra 0x3F 9000 ÉÉÉÉÉÉ(4ÉÉÉK (cid:1) 16ÉÉÉ, SecRÉÉÉuLer0se e (Z0rÉÉÉvo-wendaei,t )DÉÉÉual-MÉÉÉappeÉÉÉd) ÉÉÉ h 64x eq ÉÉÉÉÉÉÉÉÉÉ g0 Hi24 ÉÉÉÉÉÉÉÉÉÉ x/ 4 0x3F F000 (2 ÉÉÉÉBootÉ ROMÉ (4K (cid:1)É 16) ÉÉÉ 0x3F FFC0 Vectors (32 (cid:1) 32) (enabled if VMAP = 1, ENPIE = 0) A. The1Kx16OTPhasbeenreplacedwith1Kx16ROMinC2802. B. Memoryblocksarenottoscale. C. PeripheralFrame0,PeripheralFrame1,andPeripheralFrame2memorymapsarerestrictedtodatamemoryonly. Userprogramcannotaccessthesememorymapsinprogramspace. D. ProtectedmeanstheorderofWritefollowedbyReadoperationsispreservedratherthanthepipelineorder. E. CertainmemoryrangesareEALLOWprotectedagainstspuriouswritesafterconfiguration. F. SomelocationsinROMarereservedforTI.SeeTable6-22formoreinformation. Figure6-21.F2802,C2802MemoryMap 112 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Block Start Address Data Space Prog Space 0x00 0000 M0 Vector − RAM (32 x 32) (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K (cid:1) 16) ÉÉÉÉÉ 0x00 0400 M1 SARAM (1K (cid:1) 16) ce) 0x00 0800 ÉÉÉÉÉ a K [0000−FFFF]uivalent data sp 00xx0000 00DE0000 ÉÉ(EnPÉÉPaIEebr li(Vep2edhÉÉ5c 6eitf ro xaEr l N1 −ÉÉF6P rR)Ia EAm M=eÉÉ 10) ÉÉÉÉÉÉÉÉResÉÉÉÉervedÉÉÉÉÉÉÉÉ Low 64x/240x eq 0x00 6000 ÉÉPÉÉerip(pRhreeÉÉosrtaeelrc vFteeÉÉrdadm)e ÉÉ1 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 4 (2 0x00 7000 Peripheral Frame 2 ÉÉResÉervedÉÉ (protected) 0x00 8000 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ L0 SARAM (0-wait) (4K (cid:1) 16, Secure Zone, Dual-Mapped) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x00 9000 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0x3D 7800 OTP (F2801/F2801x Only)(A) ÉÉÉÉÉÉÉÉ(1K (cid:1)ÉÉ 16, SÉÉecureÉÉ ZoneÉÉ) ÉÉÉÉ 0x3D 7C00 ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ 0x3F 4000 ÉÉÉFLASÉH (F2É801) oÉr ROÉM (C2É801)ÉÉ e) (16K (cid:1) 16, Secure Zone) c 0x3F 7FF8 a FF]m sp 0x3F 8000 128-bit Password K [3F0000 −3FFuivalent progra 0x3F 9000 ÉÉÉÉÉÉ(4ÉÉÉK (cid:1) 16ÉÉÉ, SecÉÉÉRuLer0es e(Z0rÉÉÉo-vwneadei,t )DÉÉÉual-MÉÉÉappeÉÉÉd) ÉÉÉ h 64x eq ÉÉÉÉÉÉÉÉÉÉ g0 Hi24 ÉÉÉÉÉÉÉÉÉÉ x/ 4 0x3F F000 (2 ÉÉÉÉBootÉ ROMÉ (4K (cid:1)É 16) ÉÉÉ 0x3F FFC0 Vectors (32 (cid:1) 32) (enabled if VMAP = 1, ENPIE = 0) A. The1Kx16OTPhasbeenreplacedwith1Kx16ROMinC2801. B. Memoryblocksarenottoscale. C. PeripheralFrame0,PeripheralFrame1,andPeripheralFrame2memorymapsarerestrictedtodatamemoryonly. Userprogramcannotaccessthesememorymapsinprogramspace. D. ProtectedmeanstheorderofWritefollowedbyReadoperationsispreservedratherthanthepipelineorder. E. CertainmemoryrangesareEALLOWprotectedagainstspuriouswritesafterconfiguration. F. SomelocationsinROMarereservedforTI.SeeTable6-22formoreinformation. Figure6-22.F2801,F28015,F28016,C2801MemoryMap Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 113 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table6-18.AddressesofFlashSectorsin F2809 ADDRESSRANGE PROGRAMANDDATASPACE 0x3D8000–0x3DBFFF SectorH(16Kx16) 0x3DC000–0x3DFFFF SectorG(16Kx16) 0x3E0000–0x3E3FFF SectorF(16Kx16) 0x3E4000–0x3E7FFF SectorE(16Kx16) 0x3E8000–0x3EBFFF SectorD(16Kx16) 0x3EC000–0x3EFFFF SectorC(16Kx16) 0x3F0000–0x3F3FFF SectorB(16Kx16) 0x3F4000–0x3F7F7F SectorA(16Kx16) Programto0x0000whenusingthe 0x3F7F80–0x3F7FF5 CodeSecurityModule Boot-to-FlashEntryPoint 0x3F7FF6–0x3F7FF7 (programbranchinstructionhere) SecurityPassword(128-Bit) 0x3F7FF8–0x3F7FFF (Donotprogramtoallzeros) Table6-19.AddressesofFlashSectorsinF2808 ADDRESSRANGE PROGRAMANDDATASPACE 0x3E8000–0x3EBFFF SectorD(16Kx16) 0x3EC000–0x3EFFFF SectorC(16Kx16) 0x3F0000–0x3F3FFF SectorB(16Kx16) 0x3F4000–0x3F7F7F SectorA(16Kx16) Programto0x0000whenusingthe 0x3F7F80–0x3F7FF5 CodeSecurityModule Boot-to-FlashEntryPoint 0x3F7FF6–0x3F7FF7 (programbranchinstructionhere) SecurityPassword(128-Bit) 0x3F7FF8–0x3F7FFF (Donotprogramtoallzeros) Table6-20.AddressesofFlashSectorsinF2806,F2802 ADDRESSRANGE PROGRAMANDDATASPACE 0x3F0000–0x3F1FFF SectorD(8Kx16) 0x3F2000–0x3F3FFF SectorC(8Kx16) 0x3F4000–0x3F5FFF SectorB(8Kx16) 0x3F6000–0x3F7F7F SectorA(8Kx16) Programto0x0000whenusingthe 0x3F7F80–0x3F7FF5 CodeSecurityModule Boot-to-FlashEntryPoint 0x3F7FF6–0x3F7FF7 (programbranchinstructionhere) SecurityPassword(128-Bit) 0x3F7FF8–0x3F7FFF (Donotprogramtoallzeros) 114 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table6-21. AddressesofFlashSectorsinF2801,F28015,F28016 ADDRESSRANGE PROGRAMANDDATASPACE 0x3F4000–0x3F4FFF SectorD(4Kx16) 0x3F5000–0x3F5FFF SectorC(4Kx16) 0x3F6000–0x3F6FFF SectorB(4Kx16) 0x3F7000–0x3F7F7F SectorA(4Kx16) Programto0x0000whenusingthe 0x3F7F80–0x3F7FF5 CodeSecurityModule Boot-to-FlashEntryPoint 0x3F7FF6–0x3F7FF7 (programbranchinstructionhere) SecurityPassword(128-Bit) 0x3F7FF8–0x3F7FFF (Donotprogramtoallzeros) NOTE • When the code-security passwords are programmed, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations must be programmedto0x0000. • If thecodesecurity feature is notused, addresses 0x3F7F80through0x3F7FEF maybe used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and shouldnotcontainprogramcode. • On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF are reserved for TI, irrespective of whether code security has been used or not. User applicationshouldnotusetheselocationsinanyway. Table6-22showshowtohandlethesememorylocations. Table6-22.ImpactofUsingtheCodeSecurityModule FLASH ROM ADDRESS Codesecurityenabled Codesecuritydisabled Codesecurityenabled Codesecuritydisabled 0x3F7F80–0x3F7FEF Applicationcodeanddata Fillwith0x0000 Applicationcodeanddata Fillwith0x0000 0x3F7FF0–0x3F7FF5 Reservedfordataonly ReservedforTI.Donotuse. 0x3D7BFC–0x3D7BFF Applicationcodeanddata Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode isprogrammableandbydefault,itwillprotecttheselectedzones. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 115 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Thewait-statesforthevariousspacesinthememorymapareaarelistedinTable6-23. Table6-23.Wait-states AREA WAIT-STATES COMMENTS M0andM1SARAMs 0-wait Fixed PeripheralFrame0 0-wait Fixed 0-wait(writes) Fixed.TheeCANperipheralcanextendacycleasneeded. PeripheralFrame1 2-wait(reads) Back-to-backwriteswillintroducea1-cycledelay. 0-wait(writes) PeripheralFrame2 Fixed 2-wait(reads) L0andL1SARAMs 0-wait ProgrammedviatheFlashregisters.1-wait-stateoperation Programmable, OTP ispossibleatareducedCPUfrequency.SeeSection6.1.5 1-waitminimum formoreinformation. ProgrammedviatheFlashregisters.0-wait-stateoperation Programmable, ispossibleatreducedCPUfrequency.TheCSMpassword Flash 0-waitminimum locationsarehardwiredfor16wait-states.See Section6.1.5formoreinformation. H0SARAM 0-wait Fixed Boot-ROM 1-wait Fixed 116 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.4 Register Map The280xdevicescontainthreeperipheralregisterspaces.Thespacesarecategorizedasfollows: Peripheral TheseareperipheralsthataremappeddirectlytotheCPUmemorybus. Frame0: SeeTable6-24. Peripheral Theseareperipheralsthataremappedtothe32-bitperipheralbus. Frame1 SeeTable6-25. Peripheral Theseareperipheralsthataremappedtothe16-bitperipheralbus. Frame2: SeeTable6-26. Table6-24.PeripheralFrame0Registers(1) (2) NAME ADDRESSRANGE SIZE(x16) ACCESSTYPE(3) DeviceEmulationRegisters 0x0880–0x09FF 384 EALLOWprotected FLASHRegisters(4) 0x0A80–0x0ADF 96 EALLOWprotected CSMProtected CodeSecurityModuleRegisters 0x0AE0–0x0AEF 16 EALLOWprotected ADCResultRegisters(dual-mapped) 0x0B00–0x0B0F 16 NotEALLOWprotected CPU-TIMER0/1/2Registers 0x0C00–0x0C3F 64 NotEALLOWprotected PIERegisters 0x0CE0–0x0CFF 32 NotEALLOWprotected PIEVectorTable 0x0D00–0x0DFF 256 EALLOWprotected (1) RegistersinFrame0support16-bitand32-bitaccesses. (2) Missingsegmentsofmemoryspacearereservedandshouldnotbeusedinapplications. (3) IfregistersareEALLOWprotected,thenwritescannotbeperformeduntiltheEALLOWinstructionisexecuted.TheEDISinstruction disableswritestopreventstraycodeorpointersfromcorruptingregistercontents. (4) TheFlashRegistersarealsoprotectedbytheCodeSecurityModule(CSM). Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 117 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com Table6-25.PeripheralFrame1Registers(1) (2) NAME ADDRESSRANGE SIZE(x16) ACCESSTYPE SomeeCANcontrolregisters(andselected eCANARegisters 0x6000–0x60FF 256 bitsinothereCANcontrolregisters)are EALLOW-protected. eCANAMailboxRAM 0x6100–0x61FF 256 NotEALLOW-protected SomeeCANcontrolregisters(andselected eCANBRegisters 0x6200–0x62FF 256 bitsinothereCANcontrolregisters)are EALLOW-protected. eCANBMailboxRAM 0x6300–0x63FF 256 NotEALLOW-protected ePWM1Registers 0x6800–0x683F 64 ePWM2Registers 0x6840–0x687F 64 ePWM3Registers 0x6880–0x68BF 64 SomeePWMregistersareEALLOW ePWM4Registers 0x68C0–0x68FF 64 protected.SeeTable6-3. ePWM5Registers 0x6900–0x693F 64 ePWM6Registers 0x6940–0x697F 64 eCAP1Registers 0x6A00–0x6A1F 32 eCAP2Registers 0x6A20–0x6A3F 32 eCAP3Registers 0x6A40–0x6A5F 32 NotEALLOWprotected eCAP4Registers 0x6A60–0x6A7F 32 eQEP1Registers 0x6B00–0x6B3F 64 eQEP2Registers 0x6B40–0x6B7F 64 GPIOControlRegisters 0x6F80–0x6FBF 128 EALLOWprotected GPIODataRegisters 0x6FC0–0x6FDF 32 NotEALLOWprotected GPIOInterruptandLPMSelectRegisters 0x6FE0–0x6FFF 32 EALLOWprotected (1) TheeCANcontrolregistersonlysupport32-bitread/writeoperations.All32-bitaccessesarealignedtoevenaddressboundaries. (2) Missingsegmentsofmemoryspacearereservedandshouldnotbeusedinapplications. Table6-26.PeripheralFrame2Registers(1) (2) NAME ADDRESSRANGE SIZE(x16) ACCESSTYPE SystemControlRegisters 0x7010–0x702F 32 EALLOWProtected SPI-ARegisters 0x7040–0x704F 16 SCI-ARegisters 0x7050–0x705F 16 ExternalInterruptRegisters 0x7070–0x707F 16 ADCRegisters 0x7100–0x711F 32 SPI-BRegisters 0x7740–0x774F 16 NotEALLOWProtected SCI-BRegisters 0x7750–0x775F 16 SPI-CRegisters 0x7760–0x776F 16 SPI-DRegisters 0x7780–0x778F 16 I2CRegisters 0x7900–0x792F 48 (1) PeripheralFrame2onlyallows16-bitaccesses.All32-bitaccessesareignored(invaliddatamaybereturnedorwritten). (2) Missingsegmentsofmemoryspacearereservedandshouldnotbeusedinapplications. 118 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.4.1 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical devicesignals.TheregistersaredefinedinTable6-27. Table6-27.DeviceEmulationRegisters ADDRESS NAME SIZE(x16) DESCRIPTION RANGE 0x0880 DEVICECNF 2 DeviceConfigurationRegister 0x0881 PARTID 0x0882 1 PartIDRegister 0x002C(1)-F2801 0x0024–F2802 0x0034–F2806 0x003C–F2808 0x00FE–F2809 0x0014–F28016 0x001C–F28015 0xFF2C–C2801 0xFF24–C2802 REVID 0x0883 1 RevisionIDRegister 0x0000–SiliconRev.0–TMX 0x0001–SiliconRev.A–TMX 0x0002–SiliconRev.B–TMS 0x0003–SiliconRev.C–TMS RevisionIDRegister 0x0000–Siliconrev.0–TMS(F2809only) 0x0001–Siliconrev.A–TMS(F2809only) PROTSTART 0x0884 1 BlockProtectionStartAddressRegister PROTRANGE 0x0885 1 BlockProtectionRangeAddressRegister (1) Thefirstbyte(00)denotesflashdevices.FFdenotesROMdevices.Othervaluesarereservedforfuturedevices. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 119 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.5 Interrupts Figure6-23showshowthevariousinterruptsourcesaremultiplexedwithinthe280xdevices. Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as showninTable6-28. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP#0shouldnotbeusedwhenthePIEisenabled.Doingsowillresultinundefinedbehavior. WhenthePIEisenabled,TRAP#1throughTRAP#12willtransferprogramcontroltotheinterruptservice routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector fromINT1.1,TRAP#2fetchesthevectorfromINT2.1andsoforth. 120 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Peripherals (SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP,ADC) WDINT WAKEINT Watchdog LPMINT Low-Power Modes XINT1 XINT1 X Interrupt Control U M XINT1CR(15:0) s pt XINT1CTR(15:0) INT1 u INtTo12 PIE nterr 6 I GPIOXINT1SEL(4:0) 9 XINT2SOC ADC XINT2 XINT2 X Interrupt Control U M C28x XINT2CR(15:0) CPU XINT2CTR(15:0) GPIOXINT2SEL(4:0) TINT0 CPU TIMER 0 TINT2 INT14 CPU TIMER 2 (Reserved for SYS/BIOS) TINT1 CPU TIMER 1 X INT13 U M int13_select GPIO0.int nmi_select XNMI_XINT13 X GPIO Interrupt Control U X M MUX NMI U M XNMICR(15:0) GPIO31.int 1 XNMICTR(15:0) GPIOXNMISEL(4:0) Figure6-23.ExternalandPIEInterruptSources Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 121 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com IFR[12:1] IER[12:1] INTM INT1 INT2 1 MUX CPU 0 INT11 INT12 Global (Flag) (Enable) Enable INTx.1 INTx.2 INTx.3 From INTx.4 Peripherals INTx MUX INTx.5 or External INTx.6 Interrupts INTx.7 PIEACKx INTx.8 (Enable) (Flag) (Enable/Flag) PIEIERx[8:1] PIEIFRx[8:1] Figure6-24.MultiplexingofInterruptsUsingthePIEBlock Table6-28.PIEPeripheralInterrupts(1) CPU PIEINTERRUPTS INTERRUPTS INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 WAKEINT TINT0 ADCINT(2) SEQ2INT SEQ1INT INT1 XINT2 XINT1 Reserved (LPM/WD) (TIMER0) (ADC) (ADC) (ADC) EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT INT2 Reserved Reserved (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT INT3 Reserved Reserved (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT INT4 Reserved Reserved Reserved Reserved (eCAP4) (eCAP3) (eCAP2) (eCAP1) EQEP2_INT EQEP1_INT INT5 Reserved Reserved Reserved Reserved Reserved Reserved (eQEP2) (eQEP1) SPITXINTD SPIRXINTD SPITXINTC SPIRXINTC SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA INT6 (SPI-D) (SPI-D) (SPI-C) (SPI-C) (SPI-B) (SPI-B) (SPI-A) (SPI-A) INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A INT8 Reserved Reserved Reserved Reserved Reserved Reserved (I2C-A) (I2C-A) ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA INT9 (CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A) INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (1) Outofthe96possibleinterrupts,43interruptsarecurrentlyused.Theremaininginterruptsarereservedforfuturedevices.These interruptscanbeusedassoftwareinterruptsiftheyareenabledatthePIEIFRxlevel,providednoneoftheinterruptswithinthegroupis beingusedbyaperipheral.Otherwise,interruptscominginfromperipheralsmaybelostbyaccidentallyclearingtheirflagwhile modifyingthePIEIFR.Tosummarize,therearetwosafecaseswhenthereservedinterruptscouldbeusedassoftwareinterrupts: 1)Noperipheralwithinthegroupisassertinginterrupts. 2)Noperipheralinterruptsareassignedtothegroup(examplePIEgroup12). (2) ADCINTissourcedasalogical"OR"ofboththeSEQ1INTandSEQ2INTsignals.Thisistosupportbackwardcompatibilitywiththe implementationfoundontheTMS320F281xseriesofdevices,whereSEQ1INTandSEQ2INTdidnotexist,onlyADCINT.Fornew implementations,TIrecommendsusingSEQ1INTandSEQ2INTandnotenablingADCINTinthePIEIERregister. 122 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 Table6-29.PIEConfigurationandControlRegisters NAME ADDRESS SIZE(x16) DESCRIPTION(1) PIECTRL 0x0CE0 1 PIE,ControlRegister PIEACK 0x0CE1 1 PIE,AcknowledgeRegister PIEIER1 0x0CE2 1 PIE,INT1GroupEnableRegister PIEIFR1 0x0CE3 1 PIE,INT1GroupFlagRegister PIEIER2 0x0CE4 1 PIE,INT2GroupEnableRegister PIEIFR2 0x0CE5 1 PIE,INT2GroupFlagRegister PIEIER3 0x0CE6 1 PIE,INT3GroupEnableRegister PIEIFR3 0x0CE7 1 PIE,INT3GroupFlagRegister PIEIER4 0x0CE8 1 PIE,INT4GroupEnableRegister PIEIFR4 0x0CE9 1 PIE,INT4GroupFlagRegister PIEIER5 0x0CEA 1 PIE,INT5GroupEnableRegister PIEIFR5 0x0CEB 1 PIE,INT5GroupFlagRegister PIEIER6 0x0CEC 1 PIE,INT6GroupEnableRegister PIEIFR6 0x0CED 1 PIE,INT6GroupFlagRegister PIEIER7 0x0CEE 1 PIE,INT7GroupEnableRegister PIEIFR7 0x0CEF 1 PIE,INT7GroupFlagRegister PIEIER8 0x0CF0 1 PIE,INT8GroupEnableRegister PIEIFR8 0x0CF1 1 PIE,INT8GroupFlagRegister PIEIER9 0x0CF2 1 PIE,INT9GroupEnableRegister PIEIFR9 0x0CF3 1 PIE,INT9GroupFlagRegister PIEIER10 0x0CF4 1 PIE,INT10GroupEnableRegister PIEIFR10 0x0CF5 1 PIE,INT10GroupFlagRegister PIEIER11 0x0CF6 1 PIE,INT11GroupEnableRegister PIEIFR11 0x0CF7 1 PIE,INT11GroupFlagRegister PIEIER12 0x0CF8 1 PIE,INT12GroupEnableRegister PIEIFR12 0x0CF9 1 PIE,INT12GroupFlagRegister Reserved 0x0CFA– 6 Reserved 0x0CFF (1) ThePIEconfigurationandcontrolregistersarenotprotectedbyEALLOWmode.ThePIEvectortable isprotected. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 123 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.5.1 External Interrupts Table6-30.ExternalInterruptRegisters NAME ADDRESS SIZE(x16) DESCRIPTION XINT1CR 0x7070 1 XINT1controlregister XINT2CR 0x7071 1 XINT2controlregister Reserved 0x7072–0x7076 5 Reserved XNMICR 0x7077 1 XNMIcontrolregister XINT1CTR 0x7078 1 XINT1counterregister XINT2CTR 0x7079 1 XINT2counterregister Reserved 0x707A–0x707E 5 Reserved XNMICTR 0x707F 1 XNMIcounterregister Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP system control and interruptsreferenceguide. 124 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.6 System Control This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 6-25 shows the various clock and reset domains in the 280x devices that will be discussed. Reset XRS (A) Watchdog SYSCLKOUT Block Peripheral Reset (A) X1 CLKIN 28x PLL OSC X2 CPU Power XCLKIN Peripheral CPU Modes Registers Timers Control System Clock Enables Control Registers Peripheral ePWM 1/2/3/4/5/6 Registers eCAP1/2/3/4 eQEP1/2 I/O us Peripheral eCAN-A/B GPIO al B Registers I2C-A I/O MUX GPIOs r e h p Low-Speed Prescaler eri LSPCLK P Peripheral Low-Speed Peripherals I/O Registers SCI-A/B, SPI-A/B/C/D High-Speed Prescaler HSPCLK ADC 12-BitADC Registers 16ADC Inputs A. CLKINistheclockintotheCPU.ItispassedoutoftheCPUasSYSCLKOUT(thatis,CLKINisthesamefrequency asSYSCLKOUT). Figure6-25.ClockandResetDomains Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 125 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com ThePLL,clocking,watchdogandlow-powermodes,arecontrolledbytheregisterslistedinTable6-31. Table6-31.PLL,Clocking,Watchdog,andLow-PowerModeRegisters(1) NAME ADDRESS SIZE(x16) DESCRIPTION XCLK 0x7010 1 XCLKOUTPinControl,X1andXCLKINStatusRegister PLLSTS 0x7011 1 PLLStatusRegister Reserved 0x7012–0x7019 8 Reserved HISPCP 0x701A 1 High-SpeedPeripheralClockPrescalerRegister(forHSPCLK) LOSPCP 0x701B 1 Low-SpeedPeripheralClockPrescalerRegister(forLSPCLK) PCLKCR0 0x701C 1 PeripheralClockControlRegister0 PCLKCR1 0x701D 1 PeripheralClockControlRegister1 LPMCR0 0x701E 1 Low-PowerModeControlRegister0 Reserved 0x701F–0x7020 1 Reserved PLLCR 0x7021 1 PLLControlRegister SCSR 0x7022 1 SystemControlandStatusRegister WDCNTR 0x7023 1 WatchdogCounterRegister Reserved 0x7024 1 Reserved WDKEY 0x7025 1 WatchdogResetKeyRegister Reserved 0x7026–0x7028 3 Reserved WDCR 0x7029 1 WatchdogControlRegister Reserved 0x702A–0x702F 6 Reserved (1) AlloftheregistersinthistableareEALLOWprotected. 126 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.6.1 OSC and PLL Block Figure6-26showstheOSCandPLLblockonthe280x. OSCCLK OSCCLK OSCCLK XCLKIN XOR 0 or (3.3-V Clock Input) VCOCLK CLKIN PLLSTS[OSCOFF] VCOCLK PLL n n 0 /2 PLLSTS[PLLOFF] PLLSTS[CLKINDIV] X1 On-Chip 4-bit PLLSelect Oscillator (PLLCR) X2 Figure6-26.OSCandPLLBlockDiagram The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the followingconfigurations: 1. A3.3-VexternaloscillatorcanbedirectlyconnectedtotheXCLKINpin.TheX2pinshouldbeleft unconnectedandtheX1pintiedlow.Thelogic-highlevelinthiscaseshouldnotexceedV . DDIO 2. A1.8-VexternaloscillatorcanbedirectlyconnectedtotheX1pin.TheX2pinshouldbeleft unconnectedandtheXCLKINpintiedlow.Thelogic-highlevelinthiscaseshouldnotexceedV . DD Thethreepossibleinput-clockconfigurationsareshowninFigure6-27throughFigure6-29. XCLKIN X1 X2 External Clock Signal NC (Toggling 0-V ) DDIO Figure6-27.Usinga3.3-VExternalOscillator XCLKIN X1 X2 External Clock Signal NC (Toggling 0-V ) DD Figure6-28.Usinga1.8-VExternalOscillator XCLKIN X1 X2 C C L1 L2 Crystal Figure6-29.UsingtheInternalOscillator Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 127 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.6.1.1 ExternalReferenceOscillatorClockOption Thetypicalspecificationsfortheexternalquartzcrystalforafrequencyof20MHzarelistedbelow: • Fundamentalmode,parallelresonant • C (loadcapacitance)=12pF L • C =C =24pF L1 L2 • C =6pF shunt • ESRrange=30to60Ω TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produceproperstartupandstabilityovertheentireoperatingrange. 6.6.1.2 PLL-BasedClockModule The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes131072OSCCLKcycles. Table6-32.PLLCRRegisterBitDefinitions PLLCR[DIV](1) SY(CSLCKLIKNO)(2U)T 0000(PLLbypass) OSCCLK/n 0001 (OSCCLK*1)/n 0010 (OSCCLK*2)/n 0011 (OSCCLK*3)/n 0100 (OSCCLK*4)/n 0101 (OSCCLK*5)/n 0110 (OSCCLK*6)/n 0111 (OSCCLK*7)/n 1000 (OSCCLK*8)/n 1001 (OSCCLK*9)/n 1010 (OSCCLK*10)/n 1011–1111 Reserved (1) ThisregisterisEALLOWprotected. (2) CLKINistheinputclocktotheCPU.SYSCLKOUTistheoutput clockfromtheCPU.ThefrequencyofSYSCLKOUTisthesameas CLKIN.IfCLKINDIV=0,n=2;ifCLKINDIV=1,n=1. NOTE PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed to the core. This bit must be 0 before writing to the PLLCR and must only be set after PLLSTS[PLLLOCKS]=1. 128 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 ThePLL-basedclockmoduleprovidestwomodesofoperation: • Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base tothedevice. • External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocksaregeneratedfromanexternalclocksourceinputontheX1ortheXCLKINpin. Table6-33.PossiblePLLConfigurationModes SYSCLKOUT PLLMODE REMARKS PLLSTS[CLKINDIV] (CLKIN) InvokedbytheusersettingthePLLOFFbitinthePLLSTSregister.ThePLLblock 0 OSCCLK/2 isdisabledinthismode.Thiscanbeusefultoreducesystemnoiseandforlow PLLOff poweroperation.ThePLLCRregistermustfirstbesetto0x0000(PLLBypass) beforeenteringthismode.TheCPUclock(CLKIN)isderiveddirectlyfromthe 1 OSCCLK inputclockoneitherX1/X2,X1orXCLKIN. PLLBypassisthedefaultPLLconfigurationuponpower-uporafteranexternal 0 OSCCLK/2 reset(XRS).ThismodeisselectedwhenthePLLCRregisterissetto0x0000or PLLBypass whilethePLLlockstoanewfrequencyafterthePLLCRregisterhasbeen 1 OSCCLK modified.Inthismode,thePLLitselfisbypassedbutthePLLisnotturnedoff. Achievedbywritinganon-zerovaluenintothePLLCRregister.Uponwritingtothe PLLEnable 0 OSCCLK*n/2 PLLCRthedevicewillswitchtoPLLBypassmodeuntilthePLLlocks. 6.6.1.3 LossofInputClock In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz. Limp mode is not specified to work from power-up, only after input clocks have been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to theCPUiftheinputclockisremovedorabsent. Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions couldbeusedbytheapplicationfirmwaretodetecttheinputclockfailureandinitiatenecessaryshut-down procedureforthesystem. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implementamechanismbywhichtheDSPwillbeheldinreset,shouldtheinputclocksever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detectingfailureoftheflashmemoryandtheV rail. DD3VFL Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 129 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 6.6.2 Watchdog Block The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdogcounter.Figure6-30showsthevariousfunctionalblockswithinthewatchdogmodule. WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR[7:0] OSCCLK WDCLK Watchdog 8-Bit /512 Prescaler Watchdog Counter CLR Clear Counter Internal Pullup WDKEY[7:0] WDRST Generate Watchdog Output Pulse WDINT 55 +AA Good Key (512 OSCCLKs) Key Detector XRS Bad Core-reset WDCHK SCSR (WDENINT) Key WDCR (WDCHK[2:0]) (A) WDRST 1 0 1 A. TheWDRSTsignalisdrivenlowfor512OSCCLKcycles. Figure6-30.WatchdogModule TheWDINTsignalenablesthewatchdogtobeusedasawakeupfromIDLE/STANDBYmode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functionalisthewatchdog.TheWATCHDOGmodulewillrunoffOSCCLK.The WDINTsignalisfedtothe LPM block so that it can wake the device from STANDBY (if enabled). See Section 6.7, Low-Power ModesBlock,formoredetails. InIDLEmode,theWDINTsignalcangenerateaninterrupttotheCPU,viathePIE,totaketheCPUoutof IDLEmode. In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so istheWATCHDOG. 130 DetailedDescription Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 6.7 Low-Power Modes Block The low-power modes on the 280x are similar to the 240x devices. Table 6-34 summarizes the various modes. Table6-34.Low-PowerModes MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1) IDLE 00 On On On(2) XRS,Watchdoginterrupt,anyenabled interrupt,XNMI On XRS,Watchdoginterrupt,GPIOPortA STANDBY 01 (watchdogstillrunning) Off Off signal,debugger(3),XNMI Off XRS,GPIOPortAsignal,XNMI, HALT 1X (oscillatorandPLLturnedoff, Off Off debugger(3) watchdognotfunctional) (1) TheExitcolumnlistswhichsignalsorunderwhatconditionsthelowpowermodewillbeexited.Alowsignal,onanyofthesignals,will exitthelowpowercondition.Thissignalmustbekeptlowlongenoughforaninterrupttoberecognizedbythedevice.Otherwisethe IDLEmodewillnotbeexitedandthedevicewillgobackintotheindicatedlowpowermode. (2) TheIDLEmodeontheC28xbehavesdifferentlythanonthe24x/240x.OntheC28x,theclockoutputfromtheCPU(SYSCLKOUT)is stillfunctionalwhileonthe24x/240xtheclockisturnedoff. (3) OntheC28x,theJTAGportcanstillfunctioneveniftheCPUclock(CLKIN)isturnedoff. Thevariouslow-powermodesoperateasfollows: IDLEMode: ThismodeisexitedbyanyenabledinterruptoranXNMIthatisrecognized bytheprocessor.TheLPMblockperformsnotasksduringthismodeas longastheLPMCR0(LPM)bitsaresetto0,0. STANDBYMode: AnyGPIOportAsignal(GPIO[31:0])canwakethedevicefromSTANDBY mode.Theusermustselectwhichsignal(s)willwakethedeviceinthe GPIOLPMSELregister.Theselectedsignal(s)arealsoqualifiedbythe OSCCLKbeforewakingthedevice.ThenumberofOSCCLKsisspecifiedin theLPMCR0register. HALTMode: OnlytheXRSandanyGPIOportAsignal(GPIO[31:0])canwakethe devicefromHALTmode.TheuserselectsthesignalintheGPIOLPMSEL register. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide for moredetails. Copyright©2003–2019,TexasInstrumentsIncorporated DetailedDescription 131 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 7 Applications, Implementation, and Layout NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 7.1 TI Design or Reference Design TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. SearchanddownloaddesignsatTIDesigns. 132 Applications,Implementation,andLayout Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 8 Device and Documentation Support 8.1 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device. For more detailoneachofthesesteps,seethefollowing: • C2000Real-TimeControlMCUs– Gettingstarted • C2000Real-TimeControlMCUs– Tools& software Step1.Acquiretheappropriatedevelopmenttools The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial development, which,inonepackage,includes: • On-boardJTAGemulationviaUSBorparallelport • Appropriateemulationdriver • CodeComposerStudio™IDEforeZdsp Once you have become familiar with the device and begin developing on your own hardware, purchase Code Composer Studio™ IDE separately for software development and a JTAG emulation tool to get startedonyourproject. Step2.Downloadstartersoftware To simplify programming for C28x devices, it is recommended that users download and use the C/C++ Header Files and Example(s) to begin developing software for the C28x devices and their various peripherals. After downloading the appropriate header file package for your device, refer to the following resources for step-by-step instructions on how to run the peripheral examples and use the header file structure for your ownsoftware • TheQuickStartReadmeinthe/docdirectorytorunyourfirstapplication. • ProgrammingTMS320x28xxand28xxxperipheralsinC/C++applicationreport Step3.Downloadflashprogrammingsoftware Many C28x devices include on-chip flash memory and tools that allow you to program the flash with your softwareIP. • FlashTools:C28xFlashTools • TMS320F281x™flashprogrammingsolutions • RunninganapplicationfrominternalflashmemoryontheTMS320F28xxxDSP Step4.Moveontomoreadvancedtopics For more application software and other advanced topics, visit C2000 real-time control MCUs – Tools & software. Copyright©2003–2019,TexasInstrumentsIncorporated DeviceandDocumentationSupport 133 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 8.2 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (for example, TMS320F2808). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectrical specifications TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthasnot completedqualityandreliabilityverification TMS Fullyqualifiedproductiondevice Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproductthathasnotyetcompletedTexasInstrumentsinternal qualificationtesting TMDS Fullyqualifieddevelopment-supportproduct TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production systembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZ) and temperature range (for example, S). Figure 8-1 provides a legend for readingthecompletedevicenameforanyfamilymember. For device part numbers and further ordering information, see the Package Option Addendum of this document,theTIwebsite(www.ti.com),orcontactyourTIsalesrepresentative. For additional description of the device nomenclature markings on the die, see the TMS320F280x, TMS320C280x,TMS320F2801xDSPssiliconerrata. 134 DeviceandDocumentationSupport Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 TMS 320 F 28015 PZ A -60 PREFIX TMX=experimental device Indicates 60-MHz device. TMP=prototype device Absence of“-60”indicates 100-MHz device. TMS=qualified device TEMPERATURE RANGE DEVICE FAMILY A = −40°C to 85°C 320 = TMS320 DSPFamily S = −40°C to 125°C Q = −40°C to 125°C (Q refers toAEC-Q100 qualification for automotive applications.) TECHNOLOGY F = Flash EEPROM (1.8-V Core/3.3-V I/O) PACKAGE TYPE C = ROM (1.8-V Core/3.3-V I/O) 100-Pin PZ Low-Profile Quad Flatpack (LQFP) 100-Ball GGM Ball GridArray (BGA) 100-BallZGM Lead-Free BGA DEVICE 2809 2808 2806 2802 2801 28015 28016 Figure8-1.ExampleofTMS320x280x/2801xDeviceNomenclature Copyright©2003–2019,TexasInstrumentsIncorporated DeviceandDocumentationSupport 135 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 8.3 Tools and Software TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. To view all available toolsandsoftware,visittheTools & softwarepageforeachdevice,whichcanbefoundinTable8-1. Software C28xIQMathLibrary-AVirtualFloatingPointEngine Texas Instruments TMS320C28x IQmath Library is collection of highly optimized and high precision mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed point code on TMS320C28x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed & high accuracy is critical. By using these routines you can achieve execution speeds considerable faster than equivalent code written in standard ANSI C language. In addition, by providing ready-to-use high precision functions, TI IQmath library can shorten significantly your DSP application development time. (Please find the IQ Math User's Guide in the /docs folderoncethefileisextractedandinstalled). C280x,C2801xC/C++HeaderFilesandPeripheralExamples This utility contains Hardware Abstraction Layer (HAL) for TMS320x280x and TMS320x280xx DSP devices. This HAL facilitates peripheral configuration using "C". It also contains a simple test program for eachperipheraltoexemplifytheusageofHALtocontrol& configuretheon-chipperipheral. DevelopmentTools C2000GangProgrammer The C2000 Gang Programmer is a C2000 device programmer that can program up to eight identical C2000 devices at the same time. The C2000 Gang Programmer connects to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow the user to fully customizetheprocess. CodeComposerStudio™(CCS)IntegratedDevelopmentEnvironment(IDE)forC2000Microcontrollers Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resultinginacompellingfeature-richdevelopmentenvironmentforembeddeddevelopers. UniflashStandaloneFlashTool CCSUniflashisastandalonetoolusedtoprogramon-chipflashmemoryonTIMCUs. Models Various models are available for download from the product Tools & Software pages. These include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all available models, visit the Models section of the Tools & Software page for each device, which canbefoundinTable8-1. 136 DeviceandDocumentationSupport Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 8.4 Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperrightcorner,clickon Alertmetoregisterandreceiveaweeklydigestofanyproductinformationthat haschanged.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. The current documentation that describes the processor, related peripherals, and other technical collateral islistedbelow. Errata TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon errata describes the advisories and usage notesfordifferentversionsofsilicon. CPUUser'sGuides TMS320C28x CPU and instruction set reference guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It alsodescribesemulationfeaturesavailableontheseDSPs. TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide describes the various interruptsandsystemcontrolfeaturesofthe280xdigitalsignalprocessors(DSPs). PeripheralGuides C2000 real-time control peripherals reference guide describes the peripheral reference guides of the 28x digitalsignalprocessors(DSPs). TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) reference guide describes how to configureandusetheon-chipADCmodule,whichisa12-bitpipelinedADC. TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch modepowersupplycontrol,UPS(uninterruptiblepowersupplies),andotherformsofpowerconversion. TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and positioncontrolsystems.Itincludesthemoduledescriptionandregisters. TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module reference guide describes the enhanced capturemodule.Itincludesthemoduledescriptionandregisters. TMS320x280x, 2801x, 2804x High Resolution Pulse Width Modulator (HRPWM) reference guide describestheoperationofthehigh-resolutionextensiontothepulsewidthmodulator(HRPWM). TMS320x280x/2801x Enhanced Controller Area Network (eCAN) reference guide describes the enhanced controllerareanetwork(eCAN)onthex280xandx2801xdevices. TMS320x280x, 2801x, 2804x Serial Communications Interface (SCI) reference guide describes the features and operation of the serial communication interface (SCI) module that is available on the TMS320x280x,2801x,2804xdevices. TMS320x280x, 2801x, 2804x Serial Peripheral Interface reference guide describes how the serial peripheralinterfaceworks. TMS320x280x, 2801x, 2804x Inter-Integrated Circuit (I2C) module reference guide describes the features andoperationoftheinter-integratedcircuit(I2C)module. TMS320x280x, 2801x, 2804x Boot ROM reference guide describes the purpose and features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the device on- chipbootROMandidentifieswherealloftheinformationislocatedwithinthatmemory. Copyright©2003–2019,TexasInstrumentsIncorporated DeviceandDocumentationSupport 137 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com ToolsGuides TMS320C28x Assembly language tools v18.12.0.LTS user's guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, commonobjectfileformat,andsymbolicdebuggingdirectivesfortheTMS320C28xdevice. TMS320C28x optimizing C/C++ compiler v18.12.0.LTS user's guide describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly languagesourcecodefortheTMS320C28xdevice. TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) reference guide describes developmentusingDSP/BIOS. ApplicationReports TMS320x281x to TMS320x2833x or 2823x migration overview describes how to migrate from the 281x devicedesignto2833xor2823xdesigns. TMS320x280x to TMS320x2833x or 2823x migration overview describes how to migrate from a 280x devicedesignto2833xor2823xdesigns. TMS320C28x FPU primer provides an overview of the floating-point unit (FPU) in the C2000™ Delfino microcontrollerdevices. Running an application from internal flash memory on the TMS320F28xxx DSP covers the requirements needed to properly configure application software for execution from on-chip flash memory. Requirements forbothDSP/BIOSandnon-DSP/BIOSprojectsarepresented.Examplecodeprojectsareincluded. Programming TMS320x28xx and 28xxx peripherals in C/C++ explores a hardware abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #definemacrosandtopicsofcodeefficiencyandspecialcaseregistersarealsoaddressed. Using PWM output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller presents a method for using the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x familyofdigitalsignalcontrollersasadigital-to-analogconverter(DAC). TMS320F280x digital signal controller USB connectivity using the TUSB3410 USB-to-UART bridge chip presents hardware connections as well as software preparation and operation of the development system usingasimplecommunicationechoprogram. Using the Enhanced Quadrature Encoder Pulse (eQEP) module in TMS320x280x, 28xxx as a dedicated capture provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to theTMS320x280x,28xxxfamilyofprocessors. Using the ePWM module for 0% - 100% duty cycle control provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors. TMS320x280x and TMS320F2801x ADC calibration describes a method for improving the absolute accuracy of the 12-bit ADC found on the TMS320x280x and TMS320F2801x devices. Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of the ADC to levels better than 0.5%. This application report has an option to downloadanexampleprogramthatexecutesfromRAMontheF2808EzDSP. Online stack overflow detection on the TMS320C28x DSP presents the methodology for online stack overflow detection on the TMS320C28x DSP. C-source code is provided that contains functions for implementingtheoverflowdetectiononbothDSP/BIOSandnon-DSP/BIOSapplications. TMS320x281x to TMS320x280x migration overview describes differences between the Texas Instruments TMS320x281xandtheTMS320x280x/2801x/2804xDSPstoassistinapplicationmigration. Semiconductor packing methodology describes the packing methodologies employed to prepare semiconductordevicesforshipmenttoendusers. 138 DeviceandDocumentationSupport Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 An introduction to IBIS (I/O Buffer Information Specification) modeling discusses various aspects of IBIS including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/outputstructuresandfuturetrends. Calculating useful lifetimes of embedded processors provides a methodology for calculating the useful lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement. Semiconductor and IC package thermal metrics describes traditional and new thermal metrics and puts theirapplicationinperspectivewithrespecttosystem-leveljunctiontemperatureestimation. Calculating FIT for a mission profile explains how use TI’s reliability de-rating tools to calculate a componentlevelFITunderpoweronconditionsforasystemmissionprofile. Serial flash programming of C2000™ microcontrollers discusses using a flash kernel and ROM loaders for serialprogrammingadevice. 8.5 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstoordernow. Table8-1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER ORDERNOW DOCUMENTS SOFTWARE COMMUNITY TMS320F2809 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320F2808 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320F2806 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320F2802 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320F2801 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320C2802 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320C2801 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320F28016 Clickhere Clickhere Clickhere Clickhere Clickhere TMS320F28015 Clickhere Clickhere Clickhere Clickhere Clickhere 8.6 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI's TermsofUse. TIE2E™OnlineCommunity The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, exploreideasandhelpsolveproblemswithfellowengineers. TIEmbeddedProcessorsWiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardwareandsoftwaresurroundingthesedevices. 8.7 Trademarks CodeComposerStudio,MicroStarBGA,Delfino,TMS320C2000,TMS320,E2EaretrademarksofTexas Instruments. eZdspisatrademarkofSpectrumDigital. Allothertrademarksarethepropertyoftheirrespectiveowners. Copyright©2003–2019,TexasInstrumentsIncorporated DeviceandDocumentationSupport 139 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 SPRS230O–OCTOBER2003–REVISEDMARCH2019 www.ti.com 8.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 8.9 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 140 DeviceandDocumentationSupport Copyright©2003–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,TMS320F28016,TMS320F28015 www.ti.com SPRS230O–OCTOBER2003–REVISEDMARCH2019 9 Mechanical, Packaging, and Orderable Information 9.1 Packaging Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2003–2019,TexasInstrumentsIncorporated Mechanical,Packaging,andOrderableInformation 141 SubmitDocumentationFeedback ProductFolderLinks:TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320C2801PZA NRND LQFP PZ 100 TBD Call TI Call TI TMS320C2802PZA NRND LQFP PZ 100 TBD Call TI Call TI TMS320F28015PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F28015PZA & no Sb/Br) TMS TMS320F28015PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F28015PZQ & no Sb/Br) TMS TMS320F28015PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F28015PZS & no Sb/Br) TMS TMS320F28015PZSR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F28015PZS & no Sb/Br) TMS TMS320F28015ZGMA ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 F28015ZGMA MICROSTAR & no Sb/Br) TMS320 TMS320F28016PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F28016PZA & no Sb/Br) TMS TMS320F28016PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F28016PZQ & no Sb/Br) TMS TMS320F28016PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F28016PZS & no Sb/Br) TMS TMS320F2801PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2801PZA & no Sb/Br) TMS TMS320F2801PZA-60 ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2801PZA-60 & no Sb/Br) TMS TMS320F2801PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2801PZQ & no Sb/Br) TMS TMS320F2801PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2801PZS & no Sb/Br) TMS TMS320F2801PZS-60 ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2801PZS-60 & no Sb/Br) TMS TMS320F2801ZGMA ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 F2801ZGMA MICROSTAR & no Sb/Br) TMS320 TMS320F2802PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2802PZA & no Sb/Br) TMS TMS320F2802PZA-60 ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2802PZA-60 & no Sb/Br) TMS Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320F2802PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2802PZQ & no Sb/Br) TMS TMS320F2802PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2802PZS & no Sb/Br) TMS TMS320F2802PZS-60 ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2802PZS-60 & no Sb/Br) TMS TMS320F2802ZGMA LIFEBUY BGA ZGM 100 TBD Call TI Call TI -40 to 85 F2802ZGMA MICROSTAR TMS320 TMS320F2802ZGMS ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 F2802ZGMS MICROSTAR & no Sb/Br) TMS320 TMS320F2806PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2806PZA & no Sb/Br) TMS TMS320F2806PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2806PZQ & no Sb/Br) TMS TMS320F2806PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2806PZS & no Sb/Br) TMS TMS320F2806ZGMA ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 F2806ZGMA MICROSTAR & no Sb/Br) TMS320 TMS320F2806ZGMS ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 F2806ZGMS MICROSTAR & no Sb/Br) TMS320 TMS320F2808GGMA ACTIVE BGA GGM 100 184 TBD SNPB Level-3-220C-168 HR -40 to 85 F2808GGMA MICROSTAR TMS320 TMS320F2808GGMS ACTIVE BGA GGM 100 184 TBD SNPB Level-3-220C-168 HR -40 to 125 F2808GGMS MICROSTAR TMS320 TMS320F2808PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2808PZA & no Sb/Br) TMS TMS320F2808PZAR ACTIVE LQFP PZ 100 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2808PZA & no Sb/Br) TMS TMS320F2808PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2808PZQ & no Sb/Br) TMS TMS320F2808PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2808PZS & no Sb/Br) TMS TMS320F2808ZGMA ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 F2808ZGMA MICROSTAR & no Sb/Br) TMS320 TMS320F2808ZGMS ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 F2808ZGMS MICROSTAR & no Sb/Br) TMS320 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320F2809GGMA ACTIVE BGA GGM 100 184 TBD SNPB Level-3-220C-168 HR -40 to 85 F2809GGMA MICROSTAR TMS320 TMS320F2809GGMS ACTIVE BGA GGM 100 184 TBD SNPB Level-3-220C-168 HR -40 to 125 F2809GGMS MICROSTAR TMS320 TMS320F2809PZA ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 320F2809PZA & no Sb/Br) TMS TMS320F2809PZQ ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2809PZQ & no Sb/Br) TMS TMS320F2809PZS ACTIVE LQFP PZ 100 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 320F2809PZS & no Sb/Br) TMS TMS320F2809ZGMA ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 F2809ZGMA MICROSTAR & no Sb/Br) TMS320 TMS320F2809ZGMS ACTIVE BGA ZGM 100 184 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 F2809ZGMS MICROSTAR & no Sb/Br) TMS320 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

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MECHANICAL DATA MPBG028B FEBRUARY 1997 – REVISED MAY 2002 GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 10,10 SQ 7,20 TYP 9,90 0,80 0,40 K J H 80 0, G F E D 0 4 C 0, B A A1 Corner 1 2 3 4 5 6 7 8 9 10 Bottom View 0,95 0,85 1,40 MAX Seating Plane 0,55 0,08 0,45 0,10 0,45 0,35 4145257–3/C 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGA configuration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 75 51 76 50 100 26 0,13 NOM 1 25 12,00 TYP Gage Plane 14,20 SQ 13,80 0,25 16,20 SQ 0,05 MIN 0°–7° 15,80 1,45 0,75 1,35 0,45 Seating Plane 1,60 MAX 0,08 4040149/B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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