TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 TMS320DM647/TMS320DM648 Digital Media Processor CheckforSamples:TMS320DM647,TMS320DM648 1 Features 1 • High-PerformanceDigitalMediaProcessor • C64x+L1/L2MemoryArchitecture – 720-MHz,800-MHz,900-MHz,1.1-GHz – 256K-bit(32K-byte)L1PProgramRAM/Cache C64x+™ClockRates [DirectMapped] – 1.39ns(-720),1.25ns(-800),1.11ns(-900), – 256K-bit(32K-byte)L1DDataRAM/Cache 0.91ns(-1100)InstructionCycleTime [2-WaySet-Associative] – 5760,6400,7200,8800MIPS – 2M-bit/256K-byte(DM647)or4M-Bit/512K- – Eight32-BitC64x+Instructions/Cycle byte)(DM648)L2UnifiedMapped RAM/Cache[FlexibleAllocation] – FullySoftware-CompatibleWithC64x/Debug – CommercialTemperatureRanges(-720,-900, • SupportsLittleEndianModeOnly and-1100only) • FiveConfigurableVideoPorts – ExtendedTemperatureRanges(-800only) – ProvidingaGluelessI/FtoCommonVideo – IndustrialTemperatureRanges(-720,-900, DecoderandEncoderDevices and-1100only) – SupportsMultipleResolutions/Video • VelociTI.2™ExtensionstoVelociTI™ Standards AdvancedVery-Long-Instruction-Word(VLIW) • VCXOInterpolatedControlPort(VIC) TMS320C64x+™DSPCore – SupportsAudio/VideoSynchronization – EightHighlyIndependentFunctionalUnits • ExternalMemoryInterfaces(EMIFs) WithVelociTI.2Extensions: – 32-BitDDR2SDRAMMemoryControllerWith • SixALUs(32-/40-Bit),EachSupports 512M-ByteAddressSpace(1.8-VI/O) Single32-bit,Dual16-bit,orQuad8-bit – Asynchronous16-BitWideEMIF(EMIFA) ArithmeticperClockCycle • Upto128M-ByteTotalAddressReach • TwoMultipliersSupportFour16x16-bit Multiplies(32-bitResults)perClockCycle • 64M-ByteAddressReachperCESpace orEight8x8-bitMultiplies(16-Bit – GluelessInterfacetoAsynchronous Results)perClockCycle Memories(SRAM,Flash,andEEPROM) – Load-StoreArchitectureWithNon-Aligned – SynchronousMemories(SBSRAMandZBT Support SRAM) – 6432-bitGeneral-PurposeRegisters – SupportsInterfacetoStandardSyncDevices – InstructionPackingReducesCodeSize andCustomLogic(FPGA,CPLD,ASICs, etc.) – AllInstructionsConditional • EnhancedDirect-Memory-Access(EDMA) – AdditionalC64x+™Enhancements Controller(64IndependentChannels) • ProtectedModeOperation • 3-PortGigabitEthernetSwitchSubsystem • ExceptionsSupportforErrorDetection • Four64-BitGeneral-PurposeTimers(Each andProgramRedirection ConfigurableasTwo32-BitTimers) • HardwareSupportforModuloLoopAuto- • OneUART(WithRTSandCTSFlowControl) FocusModuleOperation • One4-wireSerialPortInterface(SPI)WithTwo • C64x+InstructionSetFeatures Chip-Selects – Byte-Addressable(8-/16-/32-/64-bitData) • Master/SlaveInter-IntegratedCircuit(I2C – 8-bitOverflowProtection Bus™) – Bit-FieldExtract,Set,Clear • MultichannelAudioSerialPort(McASP) – Normalization,Saturation,Bit-Counting – TenSerializersandSPDIF(DIT)Mode – VelociTI.2IncreasedOrthogonality • 16/32-BitHost-PortInterface(HPI) – C64x+Extensions • AdvancedEventTriggering(AET)Compatible • Compact16-bitInstructions • 32-Bit33-/66-MHz,3.3-VPeripheralComponent • AdditionalInstructionstoSupport Interconnect(PCI)Master/SlaveInterface ComplexMultiplies ConformstoPCISpecification2.3 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2007–2012,TexasInstrumentsIncorporated specifications per the terms of the Texas Instruments standard warranty. Production processingdoesnotnecessarilyincludetestingofallparameters.

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com • VLYNQ™Interface(FPGAInterface) (MultiplexedWithOtherDeviceFunctions) • On-ChipROMBootloader • Package: • IndividualPower-SavingModes – 529-pinnFBGA(ZUTsuffix) • FlexiblePLLClockGenerators – 19x19mm0.8mmpitchBGA • IEEE-1149.1(JTAG™)Boundary-Scan- – 0.09-μm/6-LevelCuMetalProcess(CMOS) Compatible • 3.3-Vand1.8-VI/O,1.2-VInternal(-720,-800,- • 32General-PurposeI/O(GPIO)Pins 900,-1100) 1.1 Applications • DigitalVideoRecording 1.2 Trademarks TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are trademarksofTexasInstruments. I2CBusisaregisteredtrademarkofKoninklijkePhilipsElectronicsN.V. WindowsisaregisteredtrademarkofMicrosoftCorporationintheUnitedStatesand/orothercountries. Alltrademarksarethepropertyoftheirrespectiveowners. 1.3 Description The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highest- performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647, DM648 devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instruction- word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expandedinstructionsetfrompreviousdevices. AnyreferencetotheC64xDSPorC64xCPUalsoapplies,unlessotherwisenoted,totheC64x+DSPand C64x+CPU,respectively. With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. TheDSPcorecanproducefour16-bitmultiply-accumulates(MACs)percycleforupto4400millionMACs per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature numberSPRU732). The devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M- bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memorycanbeconfiguredasmappedmemory,cache,orcombinationsofthetwo. The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and VP4). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU- BT.656,BT.1120,SMPTE125M,260M,274M,and296M),aVCXOinterpolatedcontrolport(VIC);a1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII 2 Features Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter- integratedcircuit(I2C)businterface;amultichannelaudioserialport(McASP)withtenserializers;four64- bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slowermemories/peripherals,andahigherDDR2SDRAMinterface. The video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120,SMPTE125M,260M,274M,and296M). The video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is splittablebetweenthetwochannels. For more details on the video port peripherals, see the TMS320DM647/DM648 Video Port User's Guide (literaturenumberSPRUEM1). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerateallPHYdevicesinthesystem. The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with hostprocessors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document andtheassociatedperipheralreferenceguides. The devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into sourcecodeexecution. Copyright©2007–2012,TexasInstrumentsIncorporated Features 3 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 1.4 Functional Block Diagram Figure1-1showsthefunctionalblockdiagramofthedevice. Timers (4 64-bit or 8 32-bit) PCI66 PLL or EDMA3.0 UHPI CC JTAG 3-port Ethernet Switch Subsystem TC TC TC TC GPIO x32 SGMII (x2, DM648) VIC (x1, DM647) VLYNQ Switched Central Resource DDR2 EMIFA16-bit Video Ports (5) L2 RAM L1D32KB 256KB McASP (DM647) C64x+ 512KB UART Mega (DM648) SPI L1P32KB L2 ROM I2C 64KB Imaging Coprocessor Figure1-1.FunctionalBlockDiagram 4 Features Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 1 Features ................................................... 1 6.2 RecommendedClockandControlSignalTransition ............................................ .......................................... Behavior 59 1.1 Applications 2 ..................................... .......................................... 6.3 PowerSupplies 59 1.2 Trademarks 2 ..................................... ........................................... 6.4 PLL1Controller 65 1.3 Description 2 ..................................... ........................... 6.5 PLL2Controller 69 1.4 FunctionalBlockDiagram 4 RevisionHistory .............................................. 6 6.6 EnhancedDirectMemoryAccess(EDMA3) ........................................... Controller 71 2 DeviceOverview ........................................ 7 .................................... 6.7 ResetController 84 ............................... 2.1 DeviceCharacteristics 7 ........................................... 6.8 Interrupts 96 ........................ 2.2 CPU(DSPCore)Description 8 ......................... 6.9 DDR2MemoryController 100 ......................................... 2.3 C64x+CPU 11 ............ 6.10 ExternalMemoryInterfaceA(EMIFA) 111 ............................ 2.4 MemoryMapSummary 12 ......................................... 6.11 VideoPort 118 .................................... 2.5 PinAssignments 16 ................. 6.12 VCXOInterpolatedControl(VIC) 126 ................................. 2.6 TerminalFunctions 20 6.13 UniversalAsynchronousReceiver/Transmitter 2.7 DeviceSupport ..................................... 34 (UART) ............................................ 128 3 DeviceConfiguration ................................. 38 6.14 SerialPeripheralInterfacePort(SPI) ............. 130 3.1 SystemModuleRegisters .......................... 38 6.15 Inter-IntegratedCircuit(I2C) ...................... 134 3.2 BootmodeRegisters ................................ 39 6.16 Host-PortInterface(HPI)Peripheral .............. 138 3.3 Pullup/PulldownResistors .......................... 49 6.17 PeripheralComponentInterconnect(PCI) ........ 149 4 SystemInterconnect .................................. 50 6.18 MultichannelAudioSerialPort(McASP).......... 154 4.1 InternalBuses,Bridges,andSwitchFabrics ....... 50 6.19 3-PortEthernetSwitchSubsystem(3PSW)....... 162 4.2 DataSwitchFabricConnections ................... 50 6.20 ManagementDataInput/Output(MDIO) .......... 172 4.3 ConfigurationSwitchFabric ........................ 52 6.21 Timers ............................................. 173 5 DeviceOperatingConditions ....................... 54 6.22 VLYNQPeripheral................................. 175 5.1 AbsoluteMaximumRatings ........................ 54 6.23 General-PurposeInput/Output(GPIO) ............ 178 5.2 RecommendedOperatingConditions .............. 55 6.24 EmulationFeaturesandCapability ............... 180 5.3 ElectricalCharacteristics ........................... 56 6.25 IEEE1149.1JTAG ................................ 181 6 PeripheralInformationandElectrical 7 MechanicalData ...................................... 183 Specifications .......................................... 57 ............................. 7.1 ThermalDataforZUT 183 .............................. 6.1 ParameterInformation 57 ............................ 7.2 PackagingInformation 184 Copyright©2007–2012,TexasInstrumentsIncorporated Contents 5 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. This data manual revision history highlights the technical changes made to the SPRS372G device-specific data manual to make it an SPRS372H revision. Applicable updates to the TMS320DM64x Digital Media Processors device family , specifically relating to the TMS320DM647, TMS320DM648 devices which are nowintheproductiondata(PD)stageofdevelopment,havebeenincorporated. DM647/DM648RevisionHistory SEE ADDITIONS,DELETIONS,MODIFICATIONS ExternalMemoryInterfaces(EMIFs): Section1 • Deletedthefootnotereference(1)from"512M-ByteAddressSpace(1.8-VI/O)"subbullet • Deletedassociatedfootnote[devicesarePD;SR1.0wasTMX] Section1.1 AddedseparateApplicationssection(newformatstructure) TerminalFunctions,PowerPins: Table2-4 • Added"orleftunconnected"totheV (L19)pinDESCRIPTIONcolumn[FortheAdvisory,seethe CCMON Device-SpecificSiliconErrata.] Figure6-5 CorrectedCLKDIRtoVLYNQtoshow0isVLYNQ,external PLL1ControllerDevice-SpecificInformation • Added"[WhenSYSCLK4isusedastheEMIFinputclocksource,theactualclockgoesthrougha Section6.4.1 dividerandthefrequencywouldbeSYSCLK4divide-by-2(seeFigure6-5,PLLInputClock).]"tothe SYSCLK4isusedastheEMIFAAECLKOUTbullet[ClearedDocFeedback] TimingRequirementsforAsynchronousMemoryCyclesforEMIFAModule: Table6-44 • Changed3nsto0nsfort (AOEH-EDV) h Figure6-21 Updatedtoshowtimes3and4arereferredtorisingedgeAAOE/ASOE. Table6-49 Changed5.4nsto4.2nsfort andt . w(VKIH) w(VKIL) Section7.2 DeletedduplicatedOrderableAddendumtable 6 Contents Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the DSP. The tables show significant features of the devices, including thecapacityofon-chipRAM,theperipherals,theCPUfrequency,andthepackagetypewithpincount. Table2-1.CharacteristicsoftheProcessor HARDWAREFEATURES DM647 DM648 DDR2memorycontroller(32-bit 1 1 buswidth)[1.8VI/O] 16-bitbuswidth synchronous/asynchronous 1 1 EMIF[EMIFA] EDMA3(64independent 1 1 channels,8QDMAchannels) 464-bitGeneralPurpose 464-bitGeneralPurpose Timers (eachconfigurableas164-bitor232- (eachconfigurableas164-bitor232-bit) bit) UART (withRTSandCTSflowcontrol) (withRTSandCTSflowcontrol) I2C 1(Master/Slave) 1(Master/Slave) Peripherals Notallperipheral SPI 1(4-wire,2chipselect) 1(4-wire,2chipselect) pinsareavailable McASP 1(10serializers) 1(10serializers) atthesametime (Formoredetail, 3-portEthernetSwitch seeSection3.) Subsystemsupporting 10/100/1000Base-T 1SGMIIportavailable 2SGMIIportsavailable Managementdatainput/output (MDIO) VLYNQ 1 1 General-purposeinput/output Upto32pins Upto32pins port(GPIO) HPI(16/32-bit) 1 1 PCI(32bit)(33MHzor66 1(PCI33orPCI66) 1(PCI33orPCI66) MHz) VIC 1 1 Configurablevideoports 5 5 Size(bytes) 320KBRAM,64KBROM 576KBRAM,64KBROM 32KBL1program(L1P)/cache(upto 32KB) 32KBL1program(L1P)/cache(upto32KB) On-ChipMemory 32KBL1data(L1D)/cache(upto 32KBL1data(L1D)/cache(upto32KB) Organization 32KB) 512KBunifiedmappedRAM/Cache(L2) 256KBunifiedmappedRAM/Cache 64KBBootROM (L2) 64KBBootROM RevisionIDRegister MegaModule (MM_REVID[15:0]) 0x0003 0x0003 RevID (addresslocation0x01812000) CPUID+CPU ControlStatusRegister 0x1000 0x1000 RevID (CSR.[31:16]) JTAGIDregister JTAGBSDL_ID 0x1B77A02F 0x1B77A02F (addresslocation:0x02049018) CPUFrequency MHz 720,900,1100 720,800,900,1100 1.39ns(-720) 1.39ns(-720) 1.25ns(-800) CycleTime ns 1.11ns(-900) 1.11ns(-900) 0.91ns(-1100) 0.91ns(-1100) Core(V) 1.2V(-720,-900,-1100) 1.2V(-720,-800,-900,-1100) Voltage I/O(V) 1.8V,3.3V 1.8V,3.3V Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 7 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-1.CharacteristicsoftheProcessor(continued) HARDWAREFEATURES DM647 DM648 x1(Bypass), x1(Bypass), PLLOptions CLKIN1frequencymultiplier PLLM=15,16,…,31 PLLM=15,16,…,31 (x16,x17,…,x32)(1) (x16,x17,…,x32)(1) BGAPackage 529-PinFlipChipPlasticBGA(ZUT) 529-PinFlipChipPlasticBGA(ZUT) Process 0.09-μm/6-LevelCuMetal 0.09μm 0.09μm Technology Process(CMOS) ProductStatus(2) ProductionData(PD) PD PD (1) ThemaximumCPUfrequencymustnotbeviolated. (2) SeeSection2.7foradescriptionofeachstageofdevelopment. 2.2 CPU (DSP Core) Description The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40- bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the nextupperregister(whichisalwaysanodd-numberedregister). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memorytotheregisterfileandstoreresultsfromtheregisterfileintomemory. TheC64x+CPUextendstheperformanceoftheC64xcorethroughenhancementsandnewfeatures. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high- precisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions. The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were available only on the .L units. On the C64x+ core they are also available on the .S unit, which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Othernewfeaturesinclude: • SPLOOP-AsmallinstructionbufferintheCPUthataidsincreationofsoftwarepipeliningloopswhere multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOPbufferarefullyinterruptible. 8 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 • Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performedbythecodegenerationtools. • Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. • Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detectandrespondtoexceptions,bothfrominternallydetectedsources(suchasillegalopcodes). • Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read,write,andexecutepermissions. • Time-Stamp Counter - Primarily targeted for real-time operating system (RTOS) robustness, a free- runningtime-stampcounterthatisnotsensitivetosystemstallsisimplementedintheCPU. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: • TMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide(literaturenumberSPRU732) • TMS320C64x+DSPMegamoduleReferenceGuide(literaturenumberSPRU871) • TMS320C64xtoTMS320C64x+CPUMigrationGuideApplicationReport(literaturenumberSPRAA84) • TMS320C64x+DSPCacheUser'sGuide(literaturenumberSPRU862) Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Even src1 Odd register register fileA fileA (A0,A2, .L1 src2 (A1,A3, A4...A30) A5...A31) odd dst (D) even dst long src 8 ST1b 32 MSB 32 LSB ST1a 8 long src even dst DatapathA odd dst (D) .S1 src1 src2 32 dst2 (A) dst1 32 (B) .M1 src1 src2 (C) 32 MSB LD1b 32 LSB LD1a dst .D1 src1 DA1 src2 2x 1x Even Odd register DA2 src2 register file B .D2 src1 file B (B0, B2, dst (B1, B3, B4...B30) LD2a 32 LSB B5...B31) LD2b 32 MSB src2 (C) .M2 src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst Datapath B (D) even dst 8 long src 32 MSB ST2a 32 LSB ST2b 8 long src even dst (D) odd dst .L2 src2 src1 ControlRegister A. On.M unit,dst2is 32 MSB. B. On .M unit,dst1is 32 LSB. C. On C64x CPU .M unit,src2is 32 bits; on C64x+ CPU .M unit,src2is 64 bits. D. On .Land .S units,odd dstconnects to odd register files andeven dstconnects to even register files. Figure2-1.TMS320C64x+™CPU(DSPCore)DataPaths 10 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 2.3 C64x+ CPU The C64x+ core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32KB memory space that can be configured as mapped memory or direct mapped cache. The Level 1 data memory/cache (L1D) consists of 32KB that can be configured as mapped memory or 2-way associated cache. The Level 2 memory/cache (L2) consists of a 256KB (DM647)/512 KB (DM648) memoryspacethatissharedbetweenprogramanddataspace.L2memorycanbeconfiguredasmapped memory,cache,oracombinationofboth. Table2-2showsamemorymapoftheC64x+CPUcacheregistersforthedevice. Table2-2.C64x+CacheRegisters HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01840000 L2CFG L2cacheconfigurationregister 0x01840020 L1PCFG L1Psizecacheconfigurationregister 0x01840024 L1PCC L1Pfreezemodecacheconfigurationregister 0x01840040 L1DCFG L1Dsizecacheconfigurationregister 0x01840044 L1DCC L1Dfreezemodecacheconfigurationregister 0x01840048-0x01840FFC - Reserved 0x01841000 - Reserved 0x01841004-0x01841FFC - Reserved 0x01842000 L2ALLOC0 L2allocationregister0 0x01842004 L2ALLOC1 L2allocationregister1 0x01842008 L2ALLOC2 L2allocationregister2 0x0184200C L2ALLOC3 L2allocationregister3 0x01842010-0x01843FFF - Reserved 0x01844000 L2WBAR L2writebackbaseaddressregister 0x01844004 L2WWC L2writebackwordcountregister 0x01844010 L2WIBAR L2writebackinvalidatebaseaddressregister 0x01844014 L2WIWC L2writebackinvalidatewordcountregister 0x01844018 L2IBAR L2invalidatebaseaddressregister 0x0184401C L2IWC L2invalidatewordcountregister 0x01844020 L1PIBAR L1Pinvalidatebaseaddressregister 0x01844024 L1PIWC L1Pinvalidatewordcountregister 0x01844030 L1DWIBAR L1Dwritebackinvalidatebaseaddressregister 0x01844034 L1DWIWC L1Dwritebackinvalidatewordcountregister 0x01844038 - Reserved 0x01844040 L1DWBAR L1Dblockwriteback 0x01844044 L1DWWC L1Dblockwriteback 0x01844048 L1DIBAR L1Dinvalidatebaseaddressregister 0x0184404C L1DIWC L1Dinvalidatewordcountregister 0x01844050-0x01844FFF - Reserved 0x01845000 L2WB L2writebackallregister 0x01845004 L2WBINV L2writebackinvalidateallregister 0x01845008 L2INV L2globalinvalidatewithoutwriteback 0x0184500C-0x01845027 - Reserved 0x01845028 L1PINV L1Pglobalinvalidate 0x0184502C-0x01845039 - Reserved 0x01845040 L1DWB L1Dglobalwriteback 0x01845044 L1DWBINV L1Dglobalwritebackwithinvalidate 0x01845048 L1DINV L1Dglobalinvalidatewithoutwriteback Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-2.C64x+CacheRegisters(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01848000-0x018480FC MAR0-MAR63 Reserved0x00000000-0x3FFFFFFF 0x018480C0-0x018480FC MAR48-MAR63 Reserved0x30000000-0x3FFFFFFF 0x01848100-0x0184813C MAR64-MAR79 MemoryattributeregistersforPCIData0x40000000-0x4FFFFFFF 0x01848140-0x0184827C MAR80-MAR159 Reserved0x50000000-0x9FFFFFFF 0x01848280-0x018482BC MAR160-MAR175 MemoryattributeregistersforEMIFACE20xA0000000-0xA3FFFFFF 0x018482C0-0x018482FC MAR176-MAR191 MemoryattributeregistersforEMIFACE30xB0000000-0xB3FFFFFF 0x01848130-0x0184813C MAR76-MAR79 MemoryAttributeRegistersforVLYNQ0x4C000000-0x4FFFFFFF 0x01848300-0x0184837C MAR192-MAR223 Reserved0xC0000000-0xDFFFFFFF 0x01848380-0x018483BC MAR224-MAR239 MemoryattributeregistersforDDR20xE0000000-0xEFFFFFFF 0x018483C0-0x018483FC MAR240-MAR255 MemoryattributeregistersforDDR20xF0000000-0xFFFFFFFF 2.4 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development, a unified memory map is used where possible to maintain a consistent view of device resources across all busmasters. Table2-3.MemoryMapSummary START END SIZE C64x+ ADDRESS ADDRESS (Bytes) MEMORYMAP 0x00000000 0x000FFFFF 1M Reserved 0x00100000 0x0011FFFF 128K VICP 0x00200000 0x007FFFFF 6M Reserved 0x00800000 0x008BFFFF 768K InternalROM 0x008C0000 0x009FFFFF 2M-768K Reserved 0x00A00000 0x00A3FFFF 256K L2SRAM(forbothDM647andDM648) 0x00A40000 0x00A7FFFF 256K L2SRAM(forDM648only) 0x00A80000 0x00DFFFFF 4M-512K Reserved 0x00E00000 0x00E07FFF 32K L1PSRAM 0x00E08000 0x00EFFFFF 1M–32K Reserved 0x00F00000 0x00F07FFF 32K L1DSRAM 0x00F08000 0x00FFFFFF 1M–32K Reserved 0x01000000 0x017FFFFF 8M Reserved 0x01800000 0x0180FFFF 64K C64x+InterruptController 0x01810000 0x01810FFF 4K C64x+Power-downControl 0x01811000 0x01811FFF 4K C64x+SecurityID 0x01812000 0x01812FFF 4K C64x+RevisionID 0x01813000 0x0181FFFF 52K Reserved 0x01820000 0x0182040F 1040B C64x+EMC 0x01820410 0x0182FFFF 64K–16 Reserved 0x01830000 0x0183FFFF 64K Reserved 0x01840000 0x0184FFFF 64K C64x+Memorycontrol 0x01850000 0x01BBFFFF 3,520K Reserved 0x01BC0000 0x01BCFFFF 64K Emulation 0x01BD0000 0x01BDFFFF 64K Reserved 0x01BE0000 0x01BFFFFF 128K Reserved 0x01BE0000 0x01FFFFFF 4.125M Reserved 0x02000000 0x0200007F 128B HPIControl 0x02000080 0x0203FFFF 256K–128 Reserved 0x02040000 0x02043FFF 16K McASPControl 12 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-3.MemoryMapSummary(continued) START END SIZE C64x+ ADDRESS ADDRESS (Bytes) MEMORYMAP 0x02044000 0x020443FF 1K McASPData 0x02044400 0x020447FF 1K Timer0 0x02044800 0x02044BFF 1K Timer1 0x02044C00 0x02044FFF 1K Timer2 0x02045000 0x020453FF 1K Timer3 0x02045400 0x02045FFF 3K Reserved 0x02046000 0x02046FFF 4K PSC 0x02047000 0x020473FF 1K UART 0x02047400 0x020477FF 1K VICControl 0x02047800 0x02047BFF 1K SPI 0x02047C00 0x02047FFF 1K I2CDataandControl 0x02048000 0x020483FF 1K GPIO 0x02048400 0x020487FF 1K PCIControl 0x02048800 0x02048FFF 2K Reserved 0x02049000 0x02049FFF 4K Chip-LevelRegisters 0x0204A000 0x0207FFFF 216K Reserved 0x02080000 0x0209FFFF 128K VICPConfiguration 0x020A0000 0x020DFFFF 256K Reserved 0x020E0000 0x020E01FF 512 PLLController1 0x020E0200 0x0211FFFF 256K–512 Reserved 0x02120000 0x021201FF 512 PLLController2 0x02120200 0x0215FFFF 256K–512 Reserved 0x02160000 0x029CFFFF 9M-576K Reserved 0x02A00000 0x02A07FFF 32K EDMA3CC 0x02A08000 0x02A1FFFF 96K Reserved 0x02A20000 0x02A27FFF 32K EDMA3TC0 0x02A28000 0x02A2FFFF 32K EDMA3TC1 0x02A30000 0x02A37FFF 32K EDMA3TC2 0x02A38000 0x02A3FFFF 32K EDMA3TC3 0x02A40000 0x02A7FFFF 256K Reserved 0x02A80000 0x02A804FF 1.25K Reserved 0x02A80500 0x02ABFFFF 256K–1.25K Reserved 0x02AC0000 0x02ADFFFF 128K Reserved 0x02AE0000 0x02AFFFFF 128K Reserved 0x02B00000 0x02B000FF 256 Reserved 0x02B00100 0x02B03FFF 16K–256 Reserved 0x02B04000 0x02B0407F 128 Reserved 0x02B04080 0x02B3FFFF 256K–128 Reserved 0x02B40000 0x02B401FF 512 Reserved 0x02B40200 0x02B7FFFF 256K–512 Reserved 0x02B80000 0x02B9FFFF 128K Reserved 0x02BA0000 0x02BBFFFF 128K Reserved 0x02BC0000 0x02BFFFFF 256K Reserved 0x02C00000 0x02C03FFF 16K VP0Control 0x02C04000 0x02C07FFF 16K VP1Control 0x02C08000 0x02C0BFFF 16K VP2Control 0x02C0C000 0x02C0FFFF 16K VP3Control 0x02C10000 0x02C13FFF 16K VP4Control 0x02C14000 0x02C3FFFF 176K Reserved 0x02C40000 0x02C7FFFF 256K Reserved 0x02C80000 0x02CBFFFF 256K Reserved Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-3.MemoryMapSummary(continued) START END SIZE C64x+ ADDRESS ADDRESS (Bytes) MEMORYMAP 0x02CC0000 0x02CFFFFF 256K Reserved 0x02D00000 0x02D01FFF 8K EthernetSubsystemCPPIRAM(1) 0x02D02000 0x02D02FFF 4K EthernetSubsystemControl 0x02D03000 0x02D03FFF 4K EthernetSubsystem3PSW 0x02D04000 0x02D047FF 2K EthernetSubsystemMDIO 0x02D04800 0x02D04BFF 1K EthernetSubsystemSGMII0 0x02D04C00 0x02D04FFF 1K EthernetSubsystemSGMII1(DM648only) 0x02D05000 0x02D057FF 2K Reserved 0x02D05800 0x02DBFFFF 746K Reserved 0x02DC0000 0x02DFFFFF 256K Reserved 0x02E00000 0x02E03FFF 16K Reserved 0x02E04000 0x02FFFFFF 2M–16K Reserved 0x03000000 0x03FFFFFF 16M Reserved 0x04000000 0x0FFFFFFF 192M Reserved 0x10000000 0x1FFFFFFF 256M Reserved 0x20000000 0x2FFFFFFF 256M Reserved 0x30000000 0x300000FF 256 Reserved 0x30000100 0x33FFFFFF 64M–256 Reserved 0x34000000 0x340000FF 256 Reserved 0x34000100 0x37FFFFFF 64M–256 Reserved 0x38000000 0x3BFFFFFF 64M VLYNQ 0x3C000000 0x3CFFFFFF 16M Reserved 0x3D000000 0x3DFFFFFF 16M Reserved 0x3E000000 0x3FFFFFFF 32M Reserved 0x40000000 0x4FFFFFFF 256M PCIData 0x50000000 0x51FFFFFF 32M VP0ChannelAData 0x52000000 0x53FFFFFF 32M VP0ChannelBData 0x54000000 0x55FFFFFF 32M VP1ChannelAData 0x56000000 0x57FFFFFF 32M VP1ChannelBData 0x58000000 0x59FFFFFF 32M VP2ChannelAData 0x5A000000 0x5BFFFFFF 32M VP2ChannelBData 0x5C000000 0x5DFFFFFF 32M Reserved 0x5E000000 0x5FFFFFFF 32M Reserved 0x60000000 0x61FFFFFF 32M VP3ChannelAData 0x62000000 0x63FFFFFF 32M VP3ChannelBData 0x64000000 0x65FFFFFF 32M VP4ChannelAData 0x66000000 0x67FFFFFF 32M VP4ChannelBData 0x68000000 0x6FFFFFFF 128M Reserved 0x70000000 0x77FFFFFF 128M EMIFAConfiguration 0x78000000 0x7FFFFFFF 128M DDR2EMIFConfiguration 0x80000000 0x8FFFFFFF 256M Reserved 0x90000000 0x9FFFFFFF 256M Reserved 0xA0000000 0xA3FFFFFF 64M EMIFACE2(2) 0xA4000000 0xAFFFFFFF 256-64M Reserved 0xB0000000 0xB3FFFFFF 64M EMIFACE3(2) 0xB4000000 0xBFFFFFFF 256-64M Reserved 0xC0000000 0xCFFFFFFF 256M Reserved (1) The8KCPPIDescriptormemoryismappedtoanaddressrange0x02C82000-0x02C83FFF,fromtheperspectiveoftheEthernet subsystem3PSW.Thebufferdescriptors,whenaccessedfromtheC64x+,areaddressedfrom0x02D00000.However,withinthese bufferdescriptors,whenthepointertothenextbufferdescriptorisprogrammed,theEthernetsubsystem3PSWisinterpretingthisvalue. Thus,thisprogrammedvalueshouldbeintheaddressrangestartingfrom0x02C82000. (2) TheEMIFACS0andCS1arenotfunctionallysupported;therefore,theyarenotpinnedout. 14 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-3.MemoryMapSummary(continued) START END SIZE C64x+ ADDRESS ADDRESS (Bytes) MEMORYMAP 0xD0000000 0xDFFFFFFF 256M Reserved 0xE0000000 0xEFFFFFFF 256M DDR2SDRAM 0xF0000000 0xFFFFFFFF 256M DDR2SDRAM Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 2.5 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing,seeSection3.2.6,PINMUXRegister. 2.5.1 Pin Map (Bottom View) Figure 2-2 through Figure 2-5 show the bottom view of the ZUT package pin assignments in four quadrants(A,B,C,andD). 1 2 3 4 5 6 7 8 9 10 11 12 AC VSS DVDD33 AHCLKX AHCLKR DVDD33 ACLKR ACLKX VSS SGMII1RXN VSS REFCLKN VSS AB VP2CLK0 VP2CTL1 AMUTEIN AXR3 VSS AXR0 DVDD33 AVDDT SGMII1RXP AVDDR REFCLKP DVDD33 AA VP2CTL0 VP2D03 VSS AXR6 VADXARC9/ AXR2 AFSX VSS SGMII0RXP SGMII0RXN VSS PGRPE0Q3/ Y VVPS2CCRTULN2/ VP2D06 VP2D04 DVDD33 AXR4 AXR1 SATXCRL8K/ DVDD33 VSS VSS SGMII0TXP RSV21 W VPV2CCLLKK1/ VVPR2XDD102/ VP2D07 VP2D09 VP2D02 AFSR VSS SGMII1TXP SGMII1TXN AVDDA SGMII0TXN RSV22 V VSS DVDD33 V/VPR2XDD113 VVPR2XDD124/ VP2D08 AXR7 AXR5 CVDD VSS RSV17 AVDDA PGINPT0A2/ U VVPR2XDD135/ VVPT2XDD117/ VVPT2XDD106/ VVPT2XDD139/ VVPT2XDD128/ VP2D05 AMUTE MDIO MDCLK DVDDD AVDDT PGRPS0T1/ T VAPE3CCLLKKIN0/ AAVWP3EC/ ATSLW0/E VAPE3DD0035/ VAPE3DD0024/ VAPE3DD0013/ VAPE3DD0002/ VSS DVDD33 VSS DVDDD VSS DVDD33 R VPA3RC/TWL1/ VAPE3DD0182/ VAPE3DD0079/ VAPE3DD0068/ VAPE3DD0057/ VAPE3DD0046/ DVDD33 CVDD CVDDESS VSS CVDDESS VSS P AVEPC3LCKLOKU1/T AVAPO3EC/ ATSL2O/E VAPE3DD1126/ VAPE3DD1115/ VAPE3DD1104/ VAPE3DD0193/ VSS DVDD33 VSS CVDD VSS CVDD N VSS DVDD33 PLLV1 VAPE3DD1137/ VAPE3DD1159/ VAPE3DD1148/ DVDD33 VSS CVDD VSS CVDD VSS M CLKIN1 RSV9 SYSCLK5 VAPB4ED0013/ VAPE4AD1004/ VP4D05 VSS DVDD33 VSS CVDD VSS CVDD Figure2-2.ZUTPinMap[TopLeftQuadrant] 16 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 13 14 15 16 17 18 19 20 21 22 23 AHDD2266/ AHDD2222/ HPHCWLKIL/ VSS PHCDBSE21/ AHDD1144/ DVDD33 PGCPB0E40/ AHDD0022/ AHDD0044/ DVDD33 AC AHDD2277/ AHDD2233/ AHDD1177/ DVDD33 PHIRRDDYY/ AHDD1122/ VSS AHDD0088/ AHDD0055/ AHDD0011/ VSS AB AD28/ PIDSEL/ AD18/ PFRAME/ PTRDY/ AD15/ AD13/ AD09/ AD06/ AD00/ AD03/ AA HD28 GP06 HD18 HINT GP05 HD15 HD13 HD09 HD06 HD00 HD03 AD29/ PCBE3/ AD19/ AD16/ PDEVSEL/ PSTOP/ AD11/ AD10/ AD07/ VP0CTL0 VP0CLK0 Y HD29 GP07 HD19 HD16 HCNTL1 HCNTL0 HD11 HD10 HD07 AHDD3300/ AHDD2244/ AHDD2200/ PHCRB/EW2/ PPHECRSR/ PHSDESR1R/ PHPAASR/ VP0D02 VP0D06 VSS DVDD33 W AD31/ Ad25/ AD21/ VP0D12/ HD31 HD25 HD21 DVDD33 VSS VP0D03 VP0D05 VP0D09 GP12 VP0CTL1 VP0CLK1 V PGGPN0T0/ VSS DVDD33 VSS DVDD33 VP0D04 VP0D08 VP0D16 VP0D18 VP0D17 VP0CTL2 U VSS DVDD33 VSS CVDD VSS VP0D07 VPG0PD1133/ VPG0PD1144/ VPG0PD1155/ VSS DVDD33 T CVDD VSS CVDD VSS DVDD33 VP0D19 VPG1PD1062/ VPG1PD2017/ VPG1PD2006/ VPG1PD1095/ VP1CTL0 R VP1D04/ VP1D03/ VP1D14/ VP1D13/ VSS CVDD VSS DVDD33 VSS GP18 GP17 GP26 GP25 VP1CTL1 VP1CLK0 P VP1D17/ VP1D12/ VP1D09/ VP1D08/ CVDD VSS CVDD VSS DVDD33 GP29 GP24 GP23 GP22 VP1CTL2 VP1CLK1 N VP1D16/ VP1D19/ VP1D15/ VP1D18/ VSS CVDD VSS DVDD33 VSS GP28 GP31 GP27 GP30 VSS DVDD33 M Figure2-3.ZUTPinMap[TopRightQuadrant] Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com L VAPA4CRLDKY0/ VAPB4ED0002/ VPA4CDE026/ VPA4CDE037/ VAPE4AD0008/ VAPE4AD0133/ DVDD33 VSS CVDD VSS CVDD VSS K VP4CLK1 ASVAPD4SC/ TALS2R/E VAPE4AD0019/ VAPE4AD0122/ VAPE4AD0144/ VAPE4AD0199/ VSS DVDD33 VSS CVDD VSS CVDD J VPA4BCAT1L1/ VPA4BCAT0L0/ VAPE4AD0155/ VAPE4AD0166/ VAPE4AD0177/ VAPE4AD0188/ DVDD33 VSS CVDD VSS CVDD VSS H VSS UHPIEN HPAIWEAID1T6H/ AEA23 AEA19 RSAVE_BAO15OT/ RSV7 RSV8 CVDD1 DVDD18 VSS DVDD18 EMIFA AECLKIN BOOT G DVDD33 FA/SATEBAO21OT WIDTH/ SEL/ APECAI6168/ MODE3/ PLLV2 VSS DVDD18 VSS DVDD18 VSS AEA22 AEA17 AEA14 DEVICE BOOT BOOT BOOT F CLKIN2 ENABLE0/ MODE0/ MODE1/ MODE2/ RSV18 VSS DVDD18 DDR_CS DDR_A13 DDR_A06 DDR_A08 AEA20 AEA11 AEA12 AEA13 E RSV12 RSV11 RSV14 RSV13 DVDD18 VSS DDR_D07 DDR_D04 DDR_D00 DDR_RAS DDR_BA[2] DDR_A12 D RSV4 RSV3 RSV6 RSV5 DDQDMR[_1] DDR_D10 DQDGDART_E0 DDR_D05 VSS DDR_CAS DDR_WE VSS C RSV20 RSV19 DVDD18 VSS DDR_D15 DDR_D08 DDR_D06 DDR_D03 DDR_D01 DVDD18 DVRDERF_ DDR_BA[0] B DVDD18 VDD18MON DDR_D12 DDR_D14 DVDD18 DQDGDART_E1 DDR_D09 DDQDMR[_0] DDR_D02 AVDLL1 DDR_CKE DDR_BA[1] A VSS RSV10 DDR_D11 DDR_D13 VSS DDQDSR[_1] DDQDSR[_1] DDQDSR[_0] DDQDSR[_0] RSV15 DDR_CLK DDR_CLK 1 2 3 4 5 6 7 8 9 10 11 12 Figure2-4.ZUTPinMap[BottomLeftQuadrant] 18 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 CVDD VSS CVDD VSS DVDD33 EMU4 VCCMON RSV1 RSV2 TMS TRST L VSS CVDD VSS DVDD33 VSS EMU11 EMU6 EMU3 EMU2 EMU1 EMU0 K CVDD1 VSS CVDD VSS DVDD33 NMI EMU10 EMU8 EMU5 TDI TDO J VSS DVDD18 VSS DVDD33 VSS POR RESETSTAT EMU9 EMU7 DVDD33 TCLK H DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD33 RESET VDD33MON VSS UASRPTIDRIT/S G DDR_A02 DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD33 USAPRITDCOT/S SPICLK USAPRICTSR2X/ F DDR_ODT0 DDR_A03 DDQDMR[_2] DDR_D19 DDR_D23 DQDGDART_E2 DDR_D31 T0GINPP0182/ T1GINPP1102/ DVDD33 VSS E T0OUT12/ SPICS1/ D DDR_A09 DDR_A04 DDR_A00 DDR_D18 DDR_D22 DDR_D25 DDR_D29 VSS GP09 SCL UARTTX T1OUT12/ C DVDD18 DDR_A05 DDR_A01 DDR_D17 DDR_D21 DDR_D24 DDR_D27 DDR_D30 DVDD18 GP11 SDA DDR_ B DDR_A11 DDR_A07 DVDD18 DDR_D16 DDR_D20 DVDD18 DDR_D26 DDR_D28 DQM[3] AVDLL2 DVDD18 DDR_A10 DDR_ODT1 VSS DDQDSR[_2] DDQDSR[_2] VSS DDQDSR[_3] DDQDSR[_3] DQDGDART_E3 RSV16 VSS A 13 14 15 16 17 18 19 20 21 22 23 Figure2-5.ZUTPinMap[BottomRightQuadrant] Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 2.6 Terminal Functions The terminal functions tables (Table 2-4 through Table 2-5) identify the external signal names, the associatedpin(ball)numbersalongwiththemechanicalpackagedesignator,thepintype,whetherthepin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations,seeSection3. All device boot and configuration pins are multiplexed with functional pins. These pins function as device boot and configuration pins only during device reset. When both the reset pin (RESET) and the power-on reset pin (POR) are deasserted, the input states of these multiplexed device boot and configuration pins are sampled and latched into the BOOTCFG register. For proper device operation, these pins must be pulledup/downtothedesiredvalueviaanexternalresistor. Table2-4.TerminalFunctions TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN Clock/PLLConfiguration CLKIN1 M1 I IPD 3.3V ClockInputforPLL1 CLKIN2 F1 I IPD 3.3V ClockInputforPLL2 REFCLKN(2) AC11 I DifferentialReferenceClockinput(negative)forSGMII REFCLKP(2) AB11 I DifferentialReferenceClockinput(positive)forSGMII PLLV1 N3 A 1.8V 1.8-VI/OSupplyVoltageforPLL1 PLLV2 G7 A 1.8V 1.8-VI/OSupplyVoltageforPLL2 SYSCLK5 M3 I/O/Z IPD 3.3V Clockoutofdevicespeed/4 JTAG TCLK H23 I IPU 3.3V JTAGTestPortClock TDI J22 I IPU 3.3V JTAGTestPortDataIn TDO J23 OZ IPU 3.3V JTAGTestPortDataOut TMS L22 I IPU 3.3V JTAGTestPortModeSelect TRST L23 I IPD 3.3V JTAGTestPortReset EMU0 K23 I/O/Z IPU 3.3V JTAGTestPortEmulation0 EMU1 K22 I/O/Z IPU 3.3V JTAGTestPortEmulation1 EMU2 K21 I/O/Z IPU 3.3V JTAGTestPortEmulation2 EMU3 K20 I/O/Z IPU 3.3V JTAGTestPortEmulation3 EMU4 L18 I/O/Z IPU 3.3V JTAGTestPortEmulation4 EMU5 J21 I/O/Z IPU 3.3V JTAGTestPortEmulation5 EMU6 K19 I/O/Z IPU 3.3V JTAGTestPortEmulation6 EMU7 H21 I/O/Z IPU 3.3V JTAGTestPortEmulation7 EMU8 J20 I/O/Z IPU 3.3V JTAGTestPortEmulation8 EMU9 H20 I/O/Z IPU 3.3V JTAGTestPortEmulation9 EMU10 J19 I/O/Z IPU 3.3V JTAGTestPortEmulation10 EMU11 K18 I/O/Z IPU 3.3V JTAGTestPortEmulation11 RESET/INTERRUPTS NMI J18 I IPD 3.3V NonmaskableInterrupt RESETSTAT H19 O 3.3V ResetStatusPin RESET G20 I 3.3V DeviceReset POR H18 I 3.3V PowerOnReset (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) TheclockinputbuffersontheREFCLKP/NpinsarecompatiblewithLVDSandLVPECLclocksources.Theseinputbuffersincludea 100-Ωtermination(PtoN)andacommon-modebiasing.Becausethecommon-modebiasingisincluded,theclocksourcemustbeAC coupled. 20 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN HOST-PORTINTERFACE(HPI)orPERIPHERALCOMPONENTINTERCONNECT(PCI)orGPIO[0:7] AD00/HD00 AA22 I/O/Z 3.3V HostPortdata[15:00]pinorPCIdata-addressbus[15:00] [default] AD01/HD01 AB22 I/O/Z 3.3V AD02/HD02 AC21 I/O/Z 3.3V AD03/HD03 AA23 I/O/Z 3.3V AD04/HD04 AC22 I/O/Z 3.3V AD05/HD05 AB21 I/O/Z 3.3V AD06/HD06 AA21 I/O/Z 3.3V AD07/HD07 Y21 I/O/Z 3.3V AD08/HD08 AB20 I/O/Z 3.3V AD09/HD09 AA20 I/O/Z 3.3V AD10/HD10 Y20 I/O/Z 3.3V AD11/HD11 Y19 I/O/Z 3.3V AD12/HD12 AB18 I/O/Z 3.3V AD13/HD13 AA19 I/O/Z 3.3V AD14/HD14 AC18 I/O/Z 3.3V AD15/HD15 AA18 I/O/Z 3.3V AD16/HD16 Y16 I/O/Z 3.3V HostPortdata[31:16]pinorPCIdata-addressbus[31:16] [default] AD17/HD17 AB15 I/O/Z 3.3V AD18/HD18 AA15 I/O/Z 3.3V AD19/HD19 Y15 I/O/Z 3.3V AD20/HD20 W15 I/O/Z 3.3V AD21/HD21 V15 I/O/Z 3.3V AD22/HD22 AC14 I/O/Z 3.3V AD23/HD23 AB14 I/O/Z 3.3V AD24/HD24 W14 I/O/Z 3.3V AD25/HD25 V14 I/O/Z 3.3V AD26/HD26 AC13 I/O/Z 3.3V AD27/HD27 AB13 I/O/Z 3.3V AD28/HD28 AA13 I/O/Z 3.3V AD29/HD29 Y13 I/O/Z 3.3V AD30/HD30 W13 I/O/Z 3.3V AD31/HD31 V13 I/O/Z 3.3V PPAR/HAS W19 I/O/Z 3.3V HostAddressStrobe(I)orPCIparity[default] PSTOP/HCNTL0 Y18 I/O/Z 3.3V HostControlselectsbetweencontrol,address,ordataregisters(I) orPCIStop[default] PDEVSEL/HCNTL1 Y17 I/O/Z 3.3V HostControlselectsbetweencontrol,address,ordataregisters(I) orPCIDeviceSelect[default] PPERR/HCS W17 I/O/Z 3.3V HostChipSelect(I)orPCIParityError[default] PSERR/HDS1 W18 I/O/Z 3.3V HostDataStrobe1(I)orPCISystemError[default] PCBE0/GP04 AC20 I/O/Z 3.3V PCICommand/ByteEnable0orGP[4][default PCBE1/HDS2 AC17 I 3.3V PCICommand/ByteEnable1orhostdatastrobe2 PCBE2/HR/W W16 I/O/Z 3.3V PCICommand/ByteEnable2orhostreadorwriteselect(I) PCBE3/GP07 Y14 I/O/Z 3.3V PCICommand/ByteEnable3orGPIO[7] PCLK/HHWIL AC15 I/O/Z 3.3V PCIClock(I)[default]orhostHalf-wordSelect-firstorsecond half-word(notnecessarilyhighorloworder)[ForHPI16buswidth selectiononly](I) Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN PFRAME/HINT AA16 I/O/Z 3.3V PCIFrameorhostinterruptfromDSPtohost(O/Z) PIRDY/HRDY AB17 I/O/Z 3.3V PCIInitiatorReady[default]orHostReadyfromDSPtohost(O/Z) PGNT/GP00 U13 I/O/Z 3.3V PCIBusGrant(I)orGPIO[0] PRST/GP01 U12 I/O/Z 3.3V PCIReset(I)orGPIO[1] PINTA/GP02 V12 I/O/Z 3.3V PCIInterruptA(O/Z)orGPIO[2] PREQ/GP03 AA12 I/O/Z 3.3V PCIBusRequest(O/Z)orGPIO[3] PTRDY/GP05 AA17 I/O/Z 3.3V PCITargetReadyorGPIO[5] PIDSEL/GP06 AA14 I/O/Z 3.3V PCIInitializationDeviceSelect(I)orGPIO[6] DDR2MEMORYCONTROLLER DDR_BA[0] C12 I/O/Z 1.8V DDR2MemoryControllerBankAddressControl DDR_BA[1] B12 I/O/Z 1.8V DDR_BA[2] E11 I/O/Z 1.8V DDR_CS F9 I/O/Z 1.8V DDR2MemoryControllerMemorySpaceEnable DDR_A00 D15 I/O/Z 1.8V DDR2MemoryControllerExternalAddress DDR_A01 C15 I/O/Z 1.8V DDR_A02 F13 I/O/Z 1.8V DDR_A03 E14 I/O/Z 1.8V DDR_A04 D14 I/O/Z 1.8V DDR_A05 C14 I/O/Z 1.8V DDR_A06 F11 I/O/Z 1.8V DDR_A07 B14 I/O/Z 1.8V DDR_A08 F12 I/O/Z 1.8V DDR_A09 D13 I/O/Z 1.8V DDR_A10 A13 I/O/Z 1.8V DDR_A11 B13 I/O/Z 1.8V DDR_A12 E12 I/O/Z 1.8V DDR_A13 F10 I/O/Z 1.8V DDR_CLK A12 I/O/Z 1.8V NegativeDDR2MemoryControllerOutputClock(CLKIN2 frequencyx10) DDR_CLK A11 I/O/Z 1.8V DDR2MemoryControllerOutputClock(CLKIN2frequencyx10) DDR_D00 E9 I/O/Z 1.8V DDR2MemoryControllerExternalData DDR_D01 C9 I/O/Z 1.8V DDR_D02 B9 I/O/Z 1.8V DDR_D03 C8 I/O/Z 1.8V DDR_D04 E8 I/O/Z 1.8V DDR_D05 D8 I/O/Z 1.8V DDR_D06 C7 I/O/Z 1.8V DDR_D07 E7 I/O/Z 1.8V DDR_D08 C6 I/O/Z 1.8V DDR_D09 B7 I/O/Z 1.8V DDR_D10 D6 I/O/Z 1.8V DDR_D11 A3 I/O/Z 1.8V DDR_D12 B3 I/O/Z 1.8V DDR_D13 A4 I/O/Z 1.8V DDR_D14 B4 I/O/Z 1.8V DDR_D15 C5 I/O/Z 1.8V 22 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN DDR_D16 B16 I/O/Z 1.8V DDR2MemoryControllerExternalData(continued) DDR_D17 C16 I/O/Z 1.8V DDR_D18 D16 I/O/Z 1.8V DDR_D19 E16 I/O/Z 1.8V DDR_D20 B17 I/O/Z 1.8V DDR_D21 C17 I/O/Z 1.8V DDR_D22 D17 I/O/Z 1.8V DDR_D23 E17 I/O/Z 1.8V DDR_D24 C18 I/O/Z 1.8V DDR_D25 D18 I/O/Z 1.8V DDR_D26 B19 I/O/Z 1.8V DDR_D27 C19 I/O/Z 1.8V DDR_D28 B20 I/O/Z 1.8V DDR_D29 D19 I/O/Z 1.8V DDR_D30 C20 I/O/Z 1.8V DDR_D31 E19 I/O/Z 1.8V DDR_ODT0 E13 I/O/Z 1.8V On-dieterminationsignalstoexternalDDR2SDRAM.Thesepins arereservedforfutureuseandshouldnotbeconnectedtothe DDR_ODT1 A14 I/O/Z 1.8V DDR2SDRAM. Note:Therearenoon-dieterminationresistorsimplementedon theDM647/DM648DSPdie. DDR_CAS D10 I/O/Z 1.8V DDR2MemoryControllerSDRAMcolumnaddressstrobe DDR_CKE B11 I/O/Z 1.8V DDR2MemoryControllerSDRAMclock-enable DDR_DQGATE0 D7 I/O/Z 1.8V DDR2MemoryControllerDataStrobeGate DDR_DQGATE1 B6 I/O/Z 1.8V DDR_DQGATE2 E18 I/O/Z 1.8V DDR_DQGATE3 A21 I/O/Z 1.8V DDR_DQM[0] B8 I/O/Z 1.8V DDR2MemoryControllerByte-enableControls.Decodedfromthe low-orderaddressbits.Thenumberofaddressbitsorbyte DDR_DQM[1] D5 I/O/Z 1.8V enablesuseddependsonthewidthofexternalmemory.Byte-write DDR_DQM[2] E15 I/O/Z 1.8V enablesformosttypesofmemory.Canbedirectlyconnectedto SDRAMreadandwritemasksignal(SDQM). DDR_DQM[3] B21 I/O/Z 1.8V DDR_DQS[0] A9 I/O/Z 1.8V DDR2MemoryControllerDataStrobe[3:0] DDR_DQS[1] A7 I/O/Z 1.8V DDR_DQS[2] A17 I/O/Z 1.8V DDR_DQS[3] A20 I/O/Z 1.8V DDR_DQS[0] A8 I/O/Z 1.8V DDR2MemoryControllerDataStrobe[3:0]Negative DDR_DQS[1] A6 I/O/Z 1.8V DDR_DQS[2] A16 I/O/Z 1.8V DDR_DQS[3] A19 I/O/Z 1.8V DDR_RAS E10 I/O/Z 1.8V DDR2MemoryControllerSDRAMRowAddressStrobe DDR_WE D11 I/O/Z 1.8V DDR2MemoryControllerSDRAMWriteEnable Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN CONFIGURATIONANDEMIFA DEVICEENABLE0/ F2 I/O/Z IPD 3.3V EMIFAExternalAddress20(wordaddress).(O/Z)Forproper AEA20 deviceoperation,thispinmustbeexternallypulledupwitha1-kΩ resistoratdevicereset EMIFAWIDTH/ G3 I/O/Z IPD 3.3V EMIFAExternalAddress22(wordaddress).(O/Z)EMIFAdata AEA22 buswidthselectionpinstatecapturedattherisingedgeof RESET. 0-setsEMIFACS2to8-bitdatabuswidth 1-setsEMIFACS2to16bitdatabuswidth.Fordetails,see Section3. FASTBOOT/ G2 I/O/Z IPD 3.3V EMIFAExternalAddress22(wordaddress).(O/Z)EnablesFAST AEA21 BOOTofthedevice.Fordetails,seeSection3. UHPIEN H2 I IPD 3.3V UHPIEnablePin.Thispincontrolstheselection(enable/disable) oftheHPIandGPIO[0:7]muxedwithPCI.Fordetails,see Section3. HPIWIDTH/ H3 I/O/Z IPD 3.3V EMIFAExternalAddress16(wordaddress)(O/Z)HPIperipheral AEA16 buswidth(HPI_WIDTH)select(AppliesonlywhenHPIisenabled; UHPIENpin=1) RSV_BOOT/ H6 I/O/Z IPU 3.3V EMIFAExternalAddress15(wordaddress)(O/Z)Forproper AEA15 deviceoperation,thispinmustbeexternallypulledupwitha1-kΩ resistoratdevicereset. PCI66/AEA18 G5 I/O/Z IPD 3.3V PCIFrequencySelection(PCI66).ThePCIperipheralmustbe enabled(UHPIEN=0)tousethisfunction.PCI66_AEA18selects thePCIoperatingfrequencyof66MHzor33MHz.PCIoperating frequencyisselectedatresetviathepullup/pulldownresistoron thePCI66pinAEA18: 0-PCIoperatesat33MHz(default) 1-PCIoperatesat66MHz. BOOTMODE0/AEA11 F3 I/O/Z IPD 3.3V TheBOOTMODE[3:0]defineswhatbootcodeisexecutedon BOOTMODE1/AEA12 F4 devicereset.SeeSection3.2.1formoredetails. BOOTMODE2/AEA13 F5 BOOTMODE3/AEA14 G6 INTER-INTEGRATEDCIRCUIT(I2C) SCL D22 I/O/Z 3.3V I2Cclock.WhentheI2Cmoduleisused,useanexternalpullup resistor. SDA C23 I/O/Z 3.3V I2Cdata.WhenI2Cisused,makecertainthereisanexternal pullupresistor. SGMII0/1andMDIO(1)(2) SGMII0RXN AA10 I 1.2V DifferentialSGMIIPort0RXinput(negative) SGMII0RXP AA9 I 1.2V DifferentialSGMIIPort0RXinput(positive) SGMII0TXN W11 O 1.2V DifferentialSGMIIPort0TXoutput(negative) SGMII0TXP Y11 O 1.2V DifferentialSGMIIPort0TXoutput(positive) SGMII1RXN AC9 I 1.2V DifferentialSGMIIPort1RXinput(negative) SGMII1RXP AB9 I 1.2V DifferentialSGMIIPort1RXinput(positive) SGMII1TXN W9 O 1.2V DifferentialSGMIIPort1TXoutput(negative) SGMII1TXP W8 O 1.2V DifferentialSGMIIPort1TXoutput(positive) MDCLK U9 OZ IPD 3.3V MDIOSerialClock(MDCLK) (1) ForDM647:LeavetheSGMII1RXP/NandSGMII1TXP/Npinsdisconnected.DisableENTX/ENRXbitsinCFGTX1/CFGRX1forSGMII1 andstillconfiguretheCFGPLLbecausetheSerDesTXBCLK0isusedastheinternalVBUSclock.ForDM648:ifoneoftheSGMIIpair isnotused,thesameapproachmustbeused. (2) IftheEthernetSubsystemisnotusedatall,theseconnectionsmustbefollowed: • DisconnectAA10,AA9,W11,Y11,AC9,AB9,W9,W8,andU9 • ConnectAC11toCV DD • ConnectAB11toV SS • DirectlyconnectV11(V ),W10(V ),T10(V ),U10(V ),AB8(V ),U11(V ),R9(ESScorepower),R11(ESScore DDA DDA DDD DDD DDT DDT power)toCV DD • DirectlyconnectAB10,(V )toDV DDR DD18 24 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN MDIO U8 I/O/Z IPU 3.3V MDIOSerialData(MDIO) SPIorUART SPICLK F22 I/O/Z IPU 3.3V SPIClockOutput SPICS1/UARTTX D23 I/O/Z IPU 3.3V SPIChipSelect1orUARTTransmit(O/Z) SPICS2/UARTRX F23 I/O/Z IPU 3.3V SPIChipSelect2orUARTReceive SPIDI/UARTRTS G23 I/O/Z IPU 3.3V SPIDatainputorUARTReadytosend(O/Z) SPIDO/UARTCTS F21 I/O/Z IPU 3.3V SPIDataOutputorUARTCleartosend TIMER0/1orGPIO[8:11] T0INP12/GP08 E20 I/O/Z IPD 3.3V Timer0inputpinforlower32-bitcounter(I)orGPIO8 T0OUT12/GP09 D21 I/O/Z IPD 3.3V Timer0outputpinforlower32-bitcounter(O/Z)orGPIO9 T1INPL/GP10 E21 I/O/Z IPD 3.3V Timer1inputpinforlower32-bitcounter(I)orGPIO10 T1OUT12/GP11 C22 I/O/Z IPD 3.3V Timer1outputpinforlower32-bitcounter(O/Z)orGPIO11 McASPORVIDEOPORTORVIC AHCLKR AC4 I/O/Z IPD 3.3V McASPReceivehigh-frequencymasterclock AHCLKX AC3 I/O/Z IPD 3.3V McASPTransmithigh-frequencymasterclock ACLKR AC6 I/O/Z IPD 3.3V McASPReceivemasterclock ACLKX AC7 I/O/Z IPD 3.3V McASPTransmitmasterclock AFSR W6 I/O/Z IPD 3.3V McASPReceiveFramesyncorleft/rightclock(LRCLK) AFSX AA7 I/O/Z IPD 3.3V McASPTransmitFramesyncorleft/rightclock(LRCLK) AXR0 AB6 I/O/Z IPD 3.3V McASPDataPin[0:7] AXR1 Y6 IPD 3.3V AXR2 AA6 IPD 3.3V AXR3 AB4 IPD 3.3V AXR4 Y5 IPD 3.3V AXR5 V7 IPD 3.3V AXR6 AA4 IPD 3.3V AXR7 V6 IPD 3.3V STCLK/AXR8 Y7 I/O/Z IPD 3.3V TheSTCLKsignaldrivesthehardwarecounterforusebythe videoports(I)orMcASPdatapin8. VDAC/AXR9 AA5 I/O/Z IPD 3.3V VCXOInterpolatedControlPort(VIC)single-bitdigital-to-analog converter(VDAC)output(O)orMcASPdatapin9 AMUTEIN AB3 I/O/Z IPD 3.3V McASPMuteInput AMUTE U7 I/O/Z IPD 3.3V McASPMuteOutput VIDEOPORT0ORGPIO[12:15] VP0CLK0 Y23 I IPU 3.3V VideoPort0Clock0(I) VP0CLK1 V23 I/O/Z IPU 3.3V VideoPort0Clock1 VP0CTL0 Y22 I/O/Z IPU 3.3V VideoPort0Control0 VP0CTL1 V22 I/O/Z IPU 3.3V VideoPort0Control1 VP0CTL2 U23 I/O/Z IPU 3.3V VideoPort0Control2 VP0D02 W20 I/O/Z IPD 3.3V VideoPort0Data2 VP0D03 V18 I/O/Z IPD 3.3V VideoPort0Data3 VP0D04 U18 I/O/Z IPD 3.3V VideoPort0Data4 VP0D05 V19 I/O/Z IPD 3.3V VideoPort0Data5 VP0D06 W21 I/O/Z IPD 3.3V VideoPort0Data6 VP0D07 T18 I/O/Z IPD 3.3V VideoPort0Data7 VP0D08 U19 I/O/Z IPD 3.3V VideoPort0Data8 Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN VP0D09 V20 I/O/Z IPD 3.3V VideoPort0Data9 VP0D12/GP12 V21 I/O/Z IPD 3.3V VideoPort0Data12orGPIO12 VP0D13/GP13 T19 I/O/Z IPD 3.3V VideoPort0Data13orGPIO13 VP0D14/GP14 T20 I/O/Z IPD 3.3V VideoPort0Data14orGPIO14 VP0D15/GP15 T21 I/O/Z IPD 3.3V VideoPort0Data15orGPIO15 VP0D16 U20 I/O/Z IPD 3.3V VideoPort0Data16 VP0D17 U22 I/O/Z IPD 3.3V VideoPort0Data17 VP0D18 U21 I/O/Z IPD 3.3V VideoPort0Data18 VP0D19 R18 I/O/Z IPD 3.3V VideoPort0Data19 VIDEOPORT1ORGPIO[16:31] VP1CLK0 P23 I IPU 3.3V VideoPort1Clock0 VP1CLK1 N23 I/O/Z IPU 3.3V VideoPort1Clock1 VP1CTL0 R23 I/O/Z IPU 3.3V VideoPort1Control0 VP1CTL1 P22 I/O/Z IPU 3.3V VideoPort1Control1 VP1CTL2 N22 I/O/Z IPU 3.3V VideoPort1Control2 VP1D02/GP16 R19 I/O/Z IPD 3.3V VideoPort1Data2orGPIO16 VP1D03/GP17 P19 I/O/Z IPD 3.3V VideoPort1Data3orGPIO17 VP1D04/GP18 P18 I/O/Z IPD 3.3V VideoPort1Data4orGPIO18 VP1D05/GP19 R22 I/O/Z IPD 3.3V VideoPort1Data5orGPIO19 VP1D06/GP20 R21 I/O/Z IPD 3.3V VideoPort1Data6orGPIO20 VP1D07/GP21 R20 I/O/Z IPD 3.3V VideoPort1Data7orGPIO21 VP1D08/GP22 N21 I/O/Z IPD 3.3V VideoPort1Data8orGPIO22 VP1D09/GP23 N20 I/O/Z IPD 3.3V VideoPort1Data9orGPIO23 VP1D12/GP24 N19 I/O/Z IPD 3.3V VideoPort1Data12orGPIO24 VP1D13/GP25 P21 I/O/Z IPD 3.3V VideoPort1Data13orGPIO25 VP1D14/GP26 P20 I/O/Z IPD 3.3V VideoPort1Data14orGPIO26 VP1D15/GP27 M20 I/O/Z IPD 3.3V VideoPort1Data15orGPIO27 VP1D16/GP28 M18 I/O/Z IPD 3.3V VideoPort1Data16orGPIO28 VP1D17/GP29 N18 I/O/Z IPD 3.3V VideoPort1Data17orGPIO29 VP1D18/GP30 M21 I/O/Z IPD 3.3V VideoPort1Data18orGPIO30 VP1D19/GP31 M19 I/O/Z IPD 3.3V VideoPort1Data19orGPIO31 VIDEOPORT2ORVLYNQ VP2CLK0 AB1 I IPU 3.3V VideoPort2Clock0(I) VP2CLK1/VCLK W1 I/O/Z IPU 3.3V VideoPort2Clock1orVLYNQClock(I/O) VP2CTL0 AA1 I/O/Z IPU 3.3V VideoPort2Control0 VP2CTL1 AB2 I/O/Z IPU 3.3V VideoPort2Control1 VP2CTL2/VSCRUN Y1 I/O/Z IPU 3.3V VideoPort2Control2orVLYNQserialclockrunrequest(I/O) VP2D02 W5 I/O/Z IPD 3.3V VideoPort2Data2 VP2D03 AA2 I/O/Z IPD 3.3V VideoPort2Data3 VP2D04 Y3 I/O/Z IPD 3.3V VideoPort2Data4 VP2D05 U6 I/O/Z IPD 3.3V VideoPort2Data5 VP2D06 Y2 I/O/Z IPD 3.3V VideoPort2Data6 VP2D07 W3 I/O/Z IPD 3.3V VideoPort2Data7 VP2D08 V5 I/O/Z IPD 3.3V VideoPort2Data8 VP2D09 W4 I/O/Z IPD 3.3V VideoPort2Data9 VP2D12/VRXD0 W2 I/O/Z IPD 3.3V VideoPort2Data12orVLYNQreceivedatapin[0](I) 26 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN VP2D13/VRXD1 V3 I/O/Z IPD 3.3V VideoPort2Data13orVLYNQreceivedatapin[1](I) VP2D14/VRXD2 V4 I/O/Z IPD 3.3V VideoPort2Data14orVLYNQreceivedatapin[2](I) VP2D15/VRXD3 U1 I/O/Z IPD 3.3V VideoPort2Data15orVLYNQreceivedatapin[3](I) VP2D16/VTXD0 U3 I/O/Z IPD 3.3V VideoPort2Data16orVLYNQtransmitdatapin[0](O) VP2D17/VTXD1 U2 I/O/Z IPD 3.3V VideoPort2Data17orVLYNQtransmitdatapin[1](O) VP2D18/VTXD2 U5 I/O/Z IPD 3.3V VideoPort2Data18orVLYNQtransmitdatapin[2](O) VP2D19/VTXD3 U4 I/O/Z IPD 3.3V VideoPort2Data19orVLYNQtransmitdatapin[3](O) VIDEOPORT3OREMIFA VP3CLK0/AECLKIN T1 I IPD 3.3V VideoPort3Clock0(I)orEMIFAexternalinputclock(I) VP3CLK1/ P1 I/O/Z IPD 3.3V VideoPort3Clock1orEMIFAoutputclock(O/Z) AECLKOUT VP3CTL0/ T2 I/O/Z IPU 3.3V VideoPort3Control0orAsynchronousmemorywrite AAWE/ASWE enable/Programmablesynchronousinterfacewrite-enable VP3CTL1/AR/W R1 I/O/Z IPU 3.3V VideoPort3Control1orAsynchronousmemoryread/write(O/Z) VP3CTL2/ P2 I/O/Z IPU 3.3V VideoPort3Control2orAsynchronous/Programmable AAOE/ASOE synchronousmemoryoutput-enable(O/Z) VP3D02/AED00 T6 I/O/Z IPU 3.3V VideoPort3Data2orEMIFAExternalData0 VP3D03/AED01 T5 I/O/Z IPU 3.3V VideoPort3Data3orEMIFAExternalData1 VP3D04/AED02 T4 I/O/Z IPU 3.3V VideoPort3Data4orEMIFAExternalData2 VP3D05/AED03 T3 I/O/Z IPU 3.3V VideoPort3Data5orEMIFAExternalData3 VP3D06/AED04 R6 I/O/Z IPU 3.3V VideoPort3Data6orEMIFAExternalData4 VP3D07/AED05 R5 I/O/Z IPU 3.3V VideoPort3Data7orEMIFAExternalData5 VP3D08/AED06 R4 I/O/Z IPU 3.3V VideoPort3Data8orEMIFAExternalData6 VP3D09/AED07 R3 I/O/Z IPU 3.3V VideoPort3Data9orEMIFAExternalData7 VP3D12/AED08 R2 I/O/Z IPU 3.3V VideoPort3Data12orEMIFAExternalData8 VP3D13/AED09 P6 I/O/Z IPU 3.3V VideoPort3Data13orEMIFAExternalData9 VP3D14/AED10 P5 I/O/Z IPU 3.3V VideoPort3Data14orEMIFAExternalData10 VP3D15/AED11 P4 I/O/Z IPU 3.3V VideoPort3Data15orEMIFAExternalData11 VP3D16/AED12 P3 I/O/Z IPU 3.3V VideoPort3Data16orEMIFAExternalData12 VP3D17/AED13 N4 I/O/Z IPU 3.3V VideoPort3Data17orEMIFAExternalData13 VP3D18/AED14 N6 I/O/Z IPU 3.3V VideoPort3Data18orEMIFAExternalData14 VP3D19/AED15 N5 I/O/Z IPU 3.3V VideoPort3Data19orEMIFAExternalData15 VIDEOPORT4OREMIFA VP4CLK0/AARDY L1 I IPU 3.3V VideoPort4Clock0(I)orAsynchronousmemoryreadyinput(I) VP4CLK1 K1 I/O/Z IPD 3.3V VideoPort4Clock1 VP4CTL0/ABA0 J2 I/O/Z IPD 3.3V VideoPort4Control0orEMIFAbankaddresscontrol(ABA[1:0]) (O/Z).Active-lowbankselectsforthe16-bitEMIFA.When interfacingto16-bitasynchronousdevices,ABA1carriesbit1of thebyteaddress.Foran8-bitasynchronousinterface,ABA[1:0] areusedtocarrybits1and0ofthebyteaddress. VP4CTL1/ABA1 J1 I/O/Z IPD 3.3V VideoPort4Control1orEMIFAbankaddresscontrol(ABA[1:0]) (O/Z).Active-lowbankselectsforthe16-bitEMIFA.WHEN interfacingto16-bitasynchronousdevices,ABA1carriesbit1of thebyteaddress.Foran8-bitasynchronousinterface,ABA[1:0] areusedtocarrybits1and0ofthebyteaddress. Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-4.TerminalFunctions(continued) TERMINALNAME NO TYPE( INTERNAL OPER DESCRIPTION 1) PULLUP/ VOLT PULLDOWN VP4CTL2/ASADS/ K2 I/O/Z IPD 3.3V VideoPort4Control2orProgrammablesynchronousaddress ASRE strobeorread-enable.Forprogrammablesynchronousinterface, ther_enablefieldintheChipSelectxConfigurationRegister selectsbetweenASADSandASRE: –Ifr_enable=0,thentheASADS/ASREsignalfunctionsasthe ASADSsignal. –Ifr_enable=1,thentheASADS/ASREsignalfunctionsasthe ASREsignal. VP4D02/ABE00 L2 I/O/Z IPU 3.3V VideoPort4Data2orEMIFAbyte-enablecontrol0.Decoded fromthelow-orderaddressbits.Thenumberofaddressbitsor byteenablesuseddependsonthewidthofexternalmemory. Byte-writeenablesformosttypesofmemory. VP4D03/ABE01 M4 I/O/Z IPU 3.3V VideoPort4Data3orEMIFAbyte-enablecontrol1.Numberof addressbitsorbyteenablesuseddependsonthewidthof externalmemory.Byte-writeenablesformosttypesofmemory. VP4D04/AEA10 M5 I/O/Z IPU 3.3V VideoPort4Data4orEMIFAExternalAddress10(wordaddress) (O/Z) VP4D05 M6 I/O/Z IPU 3.3V VideoPort4Data5 VP4D06/ACE2 L3 I/O/Z IPU 3.3V VideoPort4Data6orEMIFAmemoryspaceenable2 VP4D07/ACE3 L4 I/O/Z IPU 3.3V VideoPort4Data7orEMIFAmemoryspaceenable3 VP4D08/AEA00 L5 I/O/Z IPD 3.3V VideoPort4Data8orEMIFAExternalAddress0(wordaddress) (O/Z) VP4D09/AEA01 K3 I/O/Z IPD 3.3V VideoPort4Data9orEMIFAExternalAddress1(wordaddress) (O/Z) VP4D12/AEA02 K4 I/O/Z IPD 3.3V VideoPort4Data12orEMIFAExternalAddress2(wordaddress) (O/Z) VP4D13/AEA03 L6 I/O/Z IPD 3.3V VideoPort4Data13orEMIFAExternalAddress3(wordaddress) (O/Z) VP4D14/AEA04 K5 I/O/Z IPD 3.3V VideoPort4Data14orEMIFAExternalAddress4(wordaddress) (O/Z) VP4D15/AEA05 J3 I/O/Z IPD 3.3V VideoPort4Data15orEMIFAExternalAddress5(wordaddress) (O/Z) VP4D16/AEA06 J4 I/O/Z IPD 3.3V VideoPort4Data16orEMIFAExternalAddress6(wordaddress) (O/Z) VP4D17/AEA07 J5 I/O/Z IPD 3.3V VideoPort4Data17orEMIFAExternalAddress7(wordaddress) (O/Z) VP4D18/AEA08 J6 I/O/Z IPD 3.3V VideoPort4Data18orEMIFAExternalAddress8(wordaddress) (O/Z) VP4D19/AEA09 K6 I/O/Z IPD 3.3V VideoPort4Data19orEMIFAExternalAddress9(wordaddress) (O/Z) EMIFA AEA23 H4 OZ IPD 3.3V EMIFAExternalAddress23(wordaddress)(O/Z) AEA19 H5 O/Z IPU 3.3V EMIFAExternalAddress19(wordaddress)(O/Z) AECLKINSEL/AEA17 G4 I/O/Z IPD 3.3V SelectEMIFAexternalclock(I)(TheEMIFAinputclockAECLKIN orSYSCLK4isselectedatresetviathepullup/pulldownresistor onthispin.Note:AECLKINisthedefaultfortheEMIFAinput clock.) orEMIFAexternaladdress17(wordaddress)(O/Z) 28 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-5. TerminalFunctions(GroundandPowerSupply) TERMINAL NO TYPE(1) INTERNAL OPER DESCRIPTION NAME PULLUP/ VOLT PULLDOWN V A1 Ground SS V A5 Ground SS V A15 Ground SS V A18 Ground SS V A23 Ground SS V C4 Ground SS V D9 Ground SS V D12 Ground SS V D20 Ground SS V E6 Ground SS V E23 Ground SS V F7 Ground SS V F15 Ground SS V F17 Ground SS V F19 Ground SS V G8 Ground SS V G10 Ground SS V G12 Ground SS V G14 Ground SS V G16 Ground SS V G18 Ground SS V G22 Ground SS V H1 Ground SS V H11 Ground SS V H13 Ground SS V H15 Ground SS V H17 Ground SS V J8 Ground SS V J10 Ground SS V J12 Ground SS V J14 Ground SS V J16 Ground SS V K7 Ground SS V K9 Ground SS V K11 Ground SS V K13 Ground SS V K15 Ground SS V K17 Ground SS V L8 Ground SS V L10 Ground SS V L12 Ground SS V L14 Ground SS V L16 Ground SS V M7 Ground SS V M9 Ground SS (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-5. TerminalFunctions(GroundandPowerSupply)(continued) TERMINAL NO TYPE(1) INTERNAL OPER DESCRIPTION NAME PULLUP/ VOLT PULLDOWN V M11 Ground SS V M13 Ground SS V M15 Ground SS V M17 Ground SS V M22 Ground SS V N1 Ground SS V N8 Ground SS V N10 Ground SS V N12 Ground SS V N14 Ground SS V N16 Ground SS V P7 Ground SS V P9 Ground SS V P11 Ground SS V P13 Ground SS V P15 Ground SS V P17 Ground SS V R10 Ground SS V R12 Ground SS V R14 Ground SS V R16 Ground SS V T7 Ground SS V T9 Ground SS V T11 Ground SS V T13 Ground SS V T15 Ground SS V T17 Ground SS V T22 Ground SS V U14 Ground SS V U16 Ground SS V V1 Ground SS V V9 Ground SS V V17 Ground SS V W7 Ground SS V W22 Ground SS V Y9 Ground SS V Y10 Ground SS V AA3 Ground SS V AA8 Ground SS V AA11 Ground SS V AB5 Ground SS V AB19 Ground SS V AB23 Ground SS V AC1 Ground SS V AC8 Ground SS V AC10 Ground SS 30 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-5. TerminalFunctions(GroundandPowerSupply)(continued) TERMINAL NO TYPE(1) INTERNAL OPER DESCRIPTION NAME PULLUP/ VOLT PULLDOWN V AC12 Ground SS V AC16 Ground SS POWERPINS CV J9 1.2-VCorePowerSupply DD CV J11 1.2-VCorePowerSupply DD CV J15 1.2-VCorePowerSupply DD CV K10 1.2-VCorePowerSupply DD CV K12 1.2-VCorePowerSupply DD CV K14 1.2-VCorePowerSupply DD CV L9 1.2-VCorePowerSupply DD CV L11 1.2-VCorePowerSupply DD CV L13 1.2-VCorePowerSupply DD CV L15 1.2-VCorePowerSupply DD CV M10 1.2-VCorePowerSupply DD CV M12 1.2-VCorePowerSupply DD CV M14 1.2-VCorePowerSupply DD CV N11 1.2-VCorePowerSupply DD CV N13 1.2-VCorePowerSupply DD CV N15 1.2-VCorePowerSupply DD CV P10 1.2-VCorePowerSupply DD CV P12 1.2-VCorePowerSupply DD CV P14 1.2-VCorePowerSupply DD CV R13 1.2-VCorePowerSupply DD CV N9 1.2-VCorePowerSupply DD CV T16 1.2-VCorePowerSupply DD CV R8 1.2-VCorePowerSupply DD CV R15 1.2-VCorePowerSupply DD CV V8 1.2-VCorePowerSupply DD CV R11 1.2-VCorePowerSupplyforEthernetSubsystem DDESS CV R9 1.2-VCorePowerSupplyforEthernetSubsystem DDESS AV B10 1.8-VI/Osupply DLL1 AV B22 1.8-VI/Osupply DLL2 CV H9 1.2-VPowersupplyforDDR,DDRI/Os,EMIF-DDR DD1 Subsystem CV J13 1.2-VPowersupplyforDDR,DDRI/Os,EMIF-DDR DD1 Subsystem AV V11 1.2-VSerDesAnalogsupply DDA AV W10 1.2-VSerDesAnalogsupply DDA DV T10 1.2-VSerDesDigitalSupply DDD DV U10 1.2-VSerDesDigitalSupply DDD AV AB10 1.8-VSerDesAnalogSupply(Regulator) DDR AV AB8 1.2-VSerDesAnalogSupply DDT AV U11 1.2-VSerDesAnalogSupply DDT DV E22 3.3-VI/Osupplyvoltage DD33 DV F20 3.3-VI/Osupplyvoltage DD33 DV G1 3.3-VI/Osupplyvoltage DD33 Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-5. TerminalFunctions(GroundandPowerSupply)(continued) TERMINAL NO TYPE(1) INTERNAL OPER DESCRIPTION NAME PULLUP/ VOLT PULLDOWN DV G19 3.3-VI/Osupplyvoltage DD33 DV J7 3.3-VI/Osupplyvoltage DD33 DV H16 3.3-VI/Osupplyvoltage DD33 DV H22 3.3-VI/Osupplyvoltage DD33 DV J17 3.3-VI/Osupplyvoltage DD33 DV K8 3.3-VI/Osupplyvoltage DD33 DV K16 3.3-VI/Osupplyvoltage DD33 DV L7 3.3-VI/Osupplyvoltage DD33 DV L17 3.3-VI/Osupplyvoltage DD33 DV M8 3.3-VI/Osupplyvoltage DD33 DV M16 3.3-VI/Osupplyvoltage DD33 DV M23 3.3-VI/Osupplyvoltage DD33 DV N2 3.3-VI/Osupplyvoltage DD33 DV N7 3.3-VI/Osupplyvoltage DD33 DV N17 3.3-VI/Osupplyvoltage DD33 DV P8 3.3-VI/Osupplyvoltage DD33 DV P16 3.3-VI/Osupplyvoltage DD33 DV R7 3.3-VI/Osupplyvoltage DD33 DV R17 3.3-VI/Osupplyvoltage DD33 DV T8 3.3-VI/Osupplyvoltage DD33 DV T12 3.3-VI/Osupplyvoltage DD33 DV T14 3.3-VI/Osupplyvoltage DD33 DV T23 3.3-VI/Osupplyvoltage DD33 DV AB7 3.3-VI/Osupplyvoltage DD33 DV U15 3.3-VI/Osupplyvoltage DD33 DV U17 3.3-VI/Osupplyvoltage DD33 DV V2 3.3-VI/Osupplyvoltage DD33 DV V16 3.3-VI/Osupplyvoltage DD33 DV W23 3.3-VI/Osupplyvoltage DD33 DV Y4 3.3-VI/Osupplyvoltage DD33 DV Y8 3.3-VI/Osupplyvoltage DD33 DV AB16 3.3-VI/Osupplyvoltage DD33 DV AC2 3.3-VI/Osupplyvoltage DD33 DV AC5 3.3-VI/Osupplyvoltage DD33 DV AB12 3.3-VI/Osupplyvoltage DD33 DV AC19 3.3-VI/Osupplyvoltage DD33 DV AC23 3.3-VI/Osupplyvoltage DD33 DV B1 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV B5 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV B15 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV B18 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV B23 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV C3 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV C10 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV C13 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV C21 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 32 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table2-5. TerminalFunctions(GroundandPowerSupply)(continued) TERMINAL NO TYPE(1) INTERNAL OPER DESCRIPTION NAME PULLUP/ VOLT PULLDOWN DV E5 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV F8 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV F14 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV F16 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV F18 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV G9 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV G11 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV G13 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV G15 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV G17 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV H10 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV H12 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DV H14 1.8-VI/Osupplyvoltage(DDR2MemoryController) DD18 DDR_VREF C11 (DV /2)-VreferenceforSSTLbuffer(DDR2Memory DD18 Controller0.Thisinputvoltagecnbegenerateddirectlyfrom DV usingtwo1-KΩresistorstoformaresisterdivider DD18 circuit. V L19 Die-side1.2-Vcoresupplyvoltagemonitorpin.Themonitor CCMON pinsindicatethevoltageonthedie,and,therefore,providethe bestprobepointforvoltagemonitoringpurposes.IftheV CCMON pinisnotused,itshouldbeconnecteddirectlytothe1.2-V coresupplyorleftunconnected. V B2 Die-side1.8-VI/Osupplyvoltagemonitorpin.Themonitorpins DD18MON indicatethevoltageonthedieand,therefore,providethebest probepointforvoltagemonitoringpurposes.IftheV DD18MON pinisnotused,itshouldbeconnecteddirectlytothe1.8-VI/O supply(DV ). DD18 V G21 Die-side3.3-VI/Osupplyvoltagemonitorpin.Themonitorpins DD33MON indicatethevoltageonthedieand,therefore,providethebest probepointforvoltagemonitoringpurposes.IftheV DD33MON pinisnotused,itshouldbeconnecteddirectlytothe3.3-VI/O supply(DV ). DD33 Reserved RSV1 L20 A Reserved.Unconnected RSV2 L21 A Reserved.Unconnected RSV3 D2 O Reserved.Unconnected RSV4 D1 O Reserved.Unconnected RSV5 D4 O Reserved.Unconnected RSV6 D3 O Reserved.Unconnected RSV7 H7 A Reserved.ThesepinsmustbeconnecteddirectlytoV for SS properdeviceoperation. RSV8 H8 A Reserved.ThesepinsmustbeconnecteddirectlytoV for SS properdeviceoperation. RSV9 M2 A Reserved.Unconnected RSV10 A2 A Reserved.Unconnected RSV11 E2 ReservedThispinmustbeconnecteddirectlytoV forproper SS deviceoperation. RSV12 E1 Reserved.Thispinmustbeconnecteddirectlyto1.8-VI/O supply RSV13 E4 ReservedThispinmustbeconnecteddirectlytoV forproper SS deviceoperation. RSV14 E3 Reserved.Thispinmustbeconnecteddirectlyto1.8-VI/O supply Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table2-5. TerminalFunctions(GroundandPowerSupply)(continued) TERMINAL NO TYPE(1) INTERNAL OPER DESCRIPTION NAME PULLUP/ VOLT PULLDOWN RSV15 A10 A Reserved.Unconnected RSV16 A22 A Reserved.Unconnected RSV17 V10 A Reserved.Unconnected RSV18 F6 I Reserved.Thesepinsmustbeconnecteddirectlyto1.8-VI/O supply(DV )forproperdeviceoperation. DD18 RSV19 C2 Reserved.Thispinmustbeconnectedtothe1.8-VI/Osupply (DV )viaa200-Ωresistorforproperdeviceoperation. DD18 NOTE:IftheDDR2MemoryControllerisnotused,the DDR_VREF,RSV19,andRSV20pinscanbedirectly connectedtoground(V )tosavepower.However, SS connectingthesepinsdirectlytogroundwillpreventboundary scanfromfunctioningontheDDR2MemoryControllerpins.To preserveboundary-scanfunctionalityontheDDR2Memory Controllerpins,seeSection6.3.6. RSV20 C1 Reserved.Thispinmustbeconnectedtoground(V )viaa SS 200-Ωresistorforproperdeviceoperation. NOTE:IftheDDR2MemoryControllerisnotused,theRSV19 andRSV20pinscanbedirectlyconnectedtoground(V )to SS savepower.However,connectingthesepinsdirectlytoground willpreventboundaryscanfromfunctioningontheDDR2 MemoryControllerpins.Topreserveboundary-scan functionalityontheDDR2MemoryControllerpins,see Section6.3.6. RSV21 Y12 Reserved.Thispinmustbeconnectedviaa20-Ωresistor directlyto3.3-VI/OSupply(DV )forproperdevice DD33 operation.Theresistorusedshouldhaveaminimalratingof 250mW. RSV22 W12 Reserved.Thispinmustbeconnectedviaa40-Ωresistor directlytoground(V )forproperdeviceoperation.The SS resistorusedshouldhaveaminimalratingof100mW. 2.7 Device Support 2.7.1 Development Support TI offers an extensive line of development tools for the TMS320DM64x DMP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tools support documentation is electronically availablewithintheCodeComposerStudio™IntegratedDevelopmentEnvironment(IDE). ThefollowingproductssupportdevelopmentofTMS320DM64xxDMP-basedapplications: SoftwareDevelopmentTools: CodeComposerStudio™IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCodeGeneration,andDebugplusadditionaldevelopmenttools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target softwareneededtosupportanySoCapplication. HardwareDevelopmentTools: Extended Development System (XDS™) Emulator (supports TMS320DM64x multiprocessor system debug)EVM(EvaluationModule) For a complete listing of development-support tools for the TMS320DM64x platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI fieldsalesofficeorauthorizeddistributor. 34 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 2.7.2 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320DM648ZUTA7). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed qualityandreliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production systembecausetheirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default [720- MHz]). Figure2-6providesalegendforreadingthecompletedevicenameforthedevices. TMS 320 DM648 ZUT ( ) (7) DEVICE SPEED RANGE PREFIX 7= 720 MHz TMX = Experimental device 8= 800 MHZ TMS = Qualified device 9= 900MHZ 1= 1.1 GHz DEVICE FAMILY TEMPERATURE RANGE 320 =TMS320 DSPfamily Blank = 0°C to 90°C, CommercialTemperature (720, 900, 1100) DEVICE A = -40°C to 105°C, ExtendedTemperature (800) C64x+DSP D = -40° C to 90° C, IndustrialTemperature (720, 900, 1100) DM647 DM648 PACKAGE TYPE ZUT=520-pin plastic ball grid array (BGA) Figure2-6.DeviceNomenclature Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 2.7.3 Related Documentation From Texas Instruments The following documents describe the devices. Copies of these documents are available on the Internet at www.ti.com.Tip:Entertheliteraturenumberinthesearchboxprovidedatwww.ti.com. The current documentation that describes the DM64x DMP, related peripherals, and other technical collateral,isavailableintheC6000DSPproductfolderat:www.ti.com/c6000. SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancementoftheC64xDSPwithaddedfunctionalityandanexpandedinstructionset. SPRUEK5 TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2 memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2SDRAMdevicesandstandardMobileDDRSDRAMdevices. SPRUEK6 TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describes the operation of the asynchronous external memory interface (EMIF) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The EMIF supports a glueless interfacetoavarietyofexternaldevices. SPRUEK7 TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide describes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin. SPRUEK8 TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2C peripheral. This document assumes the readerisfamiliarwiththeI2C-busspecification. SPRUEL0 TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the 64- bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can be configuredasageneral-purpose64-bittimerordualgeneral-purpose32-bittimers. SPRUEL1 TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide describes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time- division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponentdigitalaudiointerfacetransmission(DIT). SPRUEL2 TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpointsontheDSP. SPRUEL4 TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guide describes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a 36 DeviceOverview Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, while keeping the EDMA channel resources available for other applications. SPRUEL5 TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the host portinterface(HPI)intheTMS320DM647/DM648DigitalSignalProcessor(DSP).TheHPIis a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memory-mapped peripherals. Connectivity to the CPU memory space is providedthroughtheenhanceddirectmemoryaccess(EDMA)controller. SPRUEL8 TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serialconversionondatareceivedfromtheCPU. SPRUEL9 TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface for connecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial bus where transmit and receive operations occur separately andsimultaneouslywithoutinterference. SPRUEM1 TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User's Guide discusses the video port and VCXO interpolated control (VIC) port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. The VIC port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. When the video port is used in TCI mode, the VIC port is used to control the system clock,VCXO,forMPEGtransportchannel. SPRUEM2 TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communicationbetweenexternalperipheralsorotherDSPs. SPRUEU6 TMS320DM647/DM648 DSP Subsystem User's Guide describes the subsystem in the TMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible for performing digital signal processing for digital media applications. The subsystem acts as the overall system controller, responsible for handling many system functions such as system- level initialization, configuration, user interface, user command execution, connectivity functions,andoverallsystemcontrol. SPRUF57 TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch (DM648 only). It provides the serial gigabit media independent interface (SGMII), the managementdatainputoutput(MDIO)forphysicallayerdevice(PHY)management. Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 3 Device Configuration 3.1 System Module Registers The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System Module registers required for device configurationaredescribedinthefollowingsections. Table3-1.SystemModuleRegisterMemoryMap HEXADDRESSRANGE REGISTERNAME DESCRIPTION 0x02049000 PINMUX Pinmultiplexingcontrol0 0x02049004 Reserved Reserved 0x02049008 DSPBOOTADDR BootAddressofDSP,decodedbybootloadersoftwareforhostboots 0x0204900C BOOTCMPLT BootComplete 0x02049010 Reserved 0x02049014 BOOTCFG Devicebootconfiguration 0x02049018 JTAGID DeviceIDnumber.SeeSection6.25fordetails. 0x0204901C PRI_ALLOC Busmasterprioritycontrol.SeeSection4fordetails 0x02049020-0x02049053 Reserved Reserved 0x02049054 KEY_REG KeyRegistertoprotectagainstaccidentalwrites. 0x02049060-0x020490A7 Reserved Reserved 0x020490A8 CFGPLL CFGPLLinputsforSerDes 0x020490AC Reserved Reserved 0x020490B0 CFGRX0 ConfigureSGMII0RX (1) 0x020490B4 CFGRX1 ConfigureSGMII1RX (1) 0x020490B8 CFGTX0 ConfigureSGMII0TX.(1) 0x020490BC CFGTX1 ConfigureSGMII1TX (1) 0x020490C0 Reserved Reserved 0x020490C4 MAC_ADDR_R0 MACAddressReadOnlyRegister0 0x020490C8 MAC_ADDR_R1 MACAddressReadOnlyRegister1 0x020490CC MAC_ADDR_RW0 MACAddressRead/WriteRegister0 0x020490D0 MAC_ADDR_RW0 MACAddressRead/WriteRegister1 0x020490D4 ESS_LOCK EthernetSubSystemLockRegister (1) SeetheTMS320DM647/DM648DSPEthernetSubsystemUser'sGuideReferenceGuide(literaturenumberSPRUF57)fordetails. 38 DeviceConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 3.2 Bootmode Registers TheBOOTCFGandDSPBOOTADDRregistersaredescribedinthefollowingsections.Atreset,thestatus levelsofvariouspinsrequiredforproperbootarestoredwithintheseregisters. 3.2.1 Boot Configuration (BOOTCFG) Register Configuration pins latched at reset are presented in the BOOTCFG register accessible through the system module. This is a read-only register. The bits show the true latched value of the corresponding input at RESET or POR deassertion. This is desirable since the most important use of this MMR is for the user to debug/viewtheactualvaluedrivenonthepinsduringdevicereset. Figure3-1.BOOTCFGRegister 31 24 Reserved R-0 23 22 21 20 19 18 17 16 AECLKINSEL PC166 HPIWIDTH Reserved FASTBOOT Reserved DUHPIEN EMIFAWIDTH R-L R-L R-L R-L 15 8 Reserved R-0 7 4 3 0 Reserved BOOTMODE R-0 R-L LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-2.BOOTCFGRegisterFieldDescriptions Bit Field Value Description 31:24 Reserved Reserved 23 AECLKINSEL ControlstheclockinputforEMIFA.LatchedfromAECLKINSELatRESETorPORdeassertion 1 EMIFAclockedfrominternalSYSCLK 0 EMIFAclockedfromoutsidefromAECLKIN 22 PCI66 ControlsPCIspeed.PCI.LatchedfromPCI66atRESETorPORdeassertion 0 33MHzPCI 1 66MHz 21 HPIWIDTH ControlsHPIbuswidth.LatchedfromHPIWIDTHatRESETorPORdeassertion 0 16bit 1 32bit 20 Reserved 1 Reserved 19 FASTBOOT FastBoot.LatchedfromFASTBOOTatRESETorPORdeassertion 0 NoFastBoot 1 FastBoot 18 Reserved Reserved 17 DUHPIEN PCIEnableDefault.LatchedfromUHPIENatRESETorPORdeassertion 0 UHPIdisabled 1 UHPIenabled 16 EMIFAWIDTH EMIFACS2BusWidthDefault.LatchedfromEMIFAWIDTHatRESETorPORdeassertion 0 8-bit 1 16-bit 15:4 Reserved Reserved Copyright©2007–2012,TexasInstrumentsIncorporated DeviceConfiguration 39 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table3-2.BOOTCFGRegisterFieldDescriptions(continued) Bit Field Value Description 3:0 BOOTMODE BootMode.LatchedfromBootmodeatRESETorPORdeassertion Table3-3.BootModes DEVICEBOOTAND CONFIGURATIONPINS BOOTDESCRIPTION(1)(2) DM647,DM648 DSPBOOTADDR (MASTER/SLAVE) (DEFAULT) BOOTMODE[3:0] UHPIEN FASTBOOT 0000 0or1 0or1 Noboot(emulationboot) - 0x00800000 0 1 PCIbootnoauto-initialization Slave 0x00800000 0001 1 0or1 HPIboot Slave 0x00800000 0 1 PCIbootwithauto-initialization Slave 0x00800000 0010 1 0or1 HPIboot Slave 0x00800000 0011 0or1 0 UARTbootwithnohardwareflowcontrol Slave 0x00800000 0 EMIFAROMdirectboot(PLLbypassmode) Master 0xA0000000 0100 0or1 1 EMIFAROMAISboot Master 0x00800000 0101 0or1 0or1 I2CBoot(standardmode) Master 0x00800000 0110 0or1 0or1 SPIboot Master 0x00800000 0111 0or1 0or1 Reserved - 0x00800000 1000 0or1 0or1 SGMII0-Bootport,nopacketforwarding Slave 0x00800000 SGMII0-Bootport,SGMII1packet 1001 0or1 0or1 Slave 0x00800000 forwarding(reservedinDM647) SGMII1-Bootport,SGMII0packet 1010 0or1 0or1 Slave 0x00800000 forwarding(reservedinDM647) 1011 0or1 0or1 Reserved - 0x00800000 1100 0or1 0or1 Reserved - 0x00800000 1101 0or1 0or1 Reserved - 0x00800000 UARTBootwithhardwareflowcontrol 1110 0or1 0 Slave 0x00800000 [UART0] 1111 0or1 0or1 Reserved - 0x00800000 (1) InallbootmodesotherthanEMIFAROMDirectBoot(BOOTMODE[3:0]=0100b,UHPIEN=0bor1b,FASTBOOT=0b)allC64x+ cacheisdisabled(L1P,L1D,L2). (2) Fordetailsofthebootprocess,seeUsingtheTMS320DM647BootloaderApplicationReport(literaturenumberSPRAAJ1). 3.2.2 DSPBOOTADDR Register Description The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register format is shown in Figure 3-2 and bit field descriptions are shown in Table 3-4. DSPBOOTADDR is readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the default of the DSPBOOTADDR Register. It can default to the base address of L2 ROM (0x00800000) or thebaseaddressofEMIFACS2(0xA0000000). Figure3-2.DSPBOOTADDRRegister 31 10 9 0 BOOTADDR Reserved R/W-0100001000100000000000 R-0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-4.DSPBOOTADDRRegisterFieldDescriptions Bit Field Value Description 31:10 BOOTADDR Upper22bitsoftheC64x+DSPbootmodeaddress 9:0 Reserved Reserved 40 DeviceConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 3.2.3 Boot Complete (BOOTCMPLT) register The BOOTCMPLT register contains a BC (boot complete) field in bit 0, and a ERR (boot error) field in bits 19:16. The BC field is written by the external host to indicates that it has completed boot. In the bootloader code, theCPUcanpollforthisbit.Oncethisbit=1,theCPUcanbeginexecutingfromDSPBOOTADDR. The ERR field is written by the bootloader software if the software detects a boot error. Coming out of a boot, application software can read this field to determine if boot was accomplished. Actual error code is determinedbysoftware. Figure3-3.BOOTCMPLTRegister3 31 20 19 16 Reserved ERR R-0 R-0 15 1 0 Reserved BC R-0 R-0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-5.BOOTCMPLTRegisterFieldDescriptions Bit Field Value Description 31:20 Reserved Reserved 19:16 ERR Booterror 0000 Noerror 0001–1111 Bootloadersoftwaredetectedbooterror.Fordetailsonbooterrors,seetheUsingthe TMS320DM647/DM648BootloaderApplicationReport(literaturenumberSPRAAJ1). 15:1 Reserved Reserved 0 BC BootCompleteFlagfromhost.Thisisapplicableonlytohostboots. 0 Hosthasnotcompletedbootingthisdevice. 1 HosthascompletedbootingthisdeviceandtheDSPcanbeginexecutingfrom DSPBOOTADDR. Copyright©2007–2012,TexasInstrumentsIncorporated DeviceConfiguration 41 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 3.2.4 Priority Allocation (PRI_ALLOC) Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation Register (PRI_ALLOC), see Figure 3-4. The priority is enforced when several masters in the system are vyingforthesameendpoint.Avalueof000bhasthehighestpriority,while111bhasthelowestpriority. Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the C64x+Megamodule. The Ethernet Subsystem and VLYNQ fields specify the priority of the Ethernet Subsystem and VLYNQ peripherals, respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals. Other master peripherals are not present in the PRI_ALLOC register as they have their own registers to program their priorities. For more information on the default priority values in these peripheral registers, seethedevice-compatibleperipheralreferenceguides. TIrecommendsthatthesepriorityregistersbereprogrammedduringdeviceinitialization. Table3-6.DefaultMasterPriorities MASTER DEFAULTPRIORITY EDMA3TC0 0(EDMACCQUEPRIRegister) EDMA3TC1 0(EDMACCQUEPRIRegister) EDMA3TC2 0(EDMACCQUEPRIRegister) EDMA3TC3 0(EDMACCQUEPRIRegister) 64x+_DMAP 7(C64x+MDMAARBE.PRIRegisterbitfield) 64x+_CFGP 1(C64x+MDMAARBE.PRIRegisterbitfield) EthernetSubsystem 3(PRI_ALLOCregister) VLYNQ 4(PRI_ALLOCregister) UHPI 4(PRI_ALLOCregister) PCI 4(PRI_ALLOCregister) VICP 5(PRI_ALLOCregister) Figure3-4.PriorityAllocationRegister(PRI_ALLOC) 31 16 Reserved R-0000000000001000 15 12 11 9 8 6 5 3 2 0 Reserved VICP VLYNQ HOST EthernetSubsystem R-0000 R/W-101 R/W-100 R/W-100 R/W-011 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset 42 DeviceConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 3.2.5 KEY_REG (write protection) KEY_REGprotectsagainstaccidentalwritestocertainsystemconfigurationregisters.Thecompletesetof registersprotectedbytheKEY_REGis: • PINMUX • BOOTCFG • PRI_ALLOC • CFGPLL • CFGRX0 • CFGTX0 • CFGRX1 • CFGTX1 • MAC_ADDR_RW0 • MAC_ADDR_RW1 Writes to these registers are locked/blocked by default. To enable writes to these registers, write 0xADDDECAF to the KEY_REG. After enabling writes to protected registers by doing the above, the registerwritesshouldoccurwithin10000CPU/6cycles,afterwhichthekeywillbereset. Figure3-5.KEY_REG 31 0 KEY_REG W-0x00000000 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Copyright©2007–2012,TexasInstrumentsIncorporated DeviceConfiguration 43 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 3.2.6 PINMUX Register All pin multiplexing options are controlled by software via PINMUX register (except the ones mentioned in Table 3-8, whose default is selected by configuration pins). This PINMUX register reside within the system module portion of the CFG bus memory map. The format of the registers and a description of the pins theycontrolareinthefollowingsections. The PINMUX Register controls all the software-controlled pin muxing. The register format is shown in Figure3-6.AbriefdescriptionofeachfieldisshowninTable3-7. Figure3-6.PINMUXRegister 31 22 21 20 19 18 17 16 Reserved GPIO_EN Reserved VPI_EN R-0000000000 R/W-00 R-00 R/W-00 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 TIMER VP34_EN SPI_UART_EN Reserved MCASP_EN Reserved VLYNQ_EN Reserved _EN R/W-00 R/W-00 R-00 R/W-00 R-00 R/W-00 R-000 R/W-0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-7.PINMUXRegisterFieldDescriptions Bit Field Value Description 31:22 Reserved Reserved 21:20 GPIO_EN ControlsthepinmuxingbetweenVideoPort0andtheGPIO[12:15] UNMUXED(1) UNMUXED (2) SECONDARYMUXED(3) .VP0D16-19 VP0D02-09/CLK/CTL VP0D12-15 GP12-15 00 3-state 3-state 3-state 01 3-state 3-state 3-state 10 Enable Enable VP0D12-15 11 3-state Enable GP12-15 19:18 Reserved Reserved 17:16 VP1_EN ControlsthepinmuxingbetweenVideoPort1andGPIO[16:31] UNMUXED(4) MUXED (5) VP1CLK0- VP1Data GP[16-31] 1/VP1CTL0-2 (V1D02-09/12-19) 00 3-state 3-state 01 3-state 3-state 10 3-state GP16-31 11 Enable VP1D02-09andVP1D12-19 (1) Thecompletelistofpins:U20,U21,U22,R18. (2) Thecompletelistofpins:Y23,V23,Y22,V22,U23,W20,V18,U18,V19,W21,T18,U19,V20. (3) Thecompletelistofpins:V21,T19,T20,T21. (4) Thecompletelistofpins:P23,N23,R23,P22,N22 (5) Thecompletelistofpins:R19,P19,P18,R22,R21,R20,N21,N20,N19,P21,P20,M20,M18,N18,M21,M19 44 DeviceConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table3-7.PINMUXRegisterFieldDescriptions(continued) Bit Field Value Description 15:14 VP34_EN ControlsthepinmuxingbetweenVideoPort3-4andEMIFA (6) UNMUXED(7) MUXED(8) VP4D05/VP4CLK1 VP3/VP4 EMIFA 00 3-state 3-state 01 3-state 3-state 10 Disable EMIFA 11 Enable VP3/VP4 13:12 SPI_UART_EN ControlsthepinmuxingbetweenSPIandUART UNMUXED (9) MUXED (10) SPICLK SPIorUART 00 3-state 3-state 01 Enable SPI 10 Disable UART 11 Enable SPIDI SPIDO UART_TX UART_RX 11:10 Reserved Reserved (6) ThevalueofVP34_ENdependsontheBOOTMODE[3:0]pinvalueatreset.IftheBOOTMODE[3:0]is0100,theVP3/4andtheEMIFA muxdefaultstoEMIFAenable(thevalueis10b). (7) Thecompletelistofpins:K1,M6. (8) Thecompletelistofpins:T1,P1,T2,R1,P2,T6,T5,T4,T3,R6,R5,R4,R3,R2,P6,P5,P4,P3,N4,N6,N5,L1,J2,J1,K2,L2,M4, M5,L3,L4,L5,K3,K4,L6,K5,J3,J4,J5,J6,K6. (9) Thecompletelistofpin:F22 (10) Thecompletelistofpins:D23,F23,G23,F21 Copyright©2007–2012,TexasInstrumentsIncorporated DeviceConfiguration 45 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table3-7.PINMUXRegisterFieldDescriptions(continued) Bit Field Value Description 9:8 MCASP_EN ControlsthepinmuxingbetweenMcASPandVIC UNMUXED MUXED (11) STCLK,VCTL,orMcASP 00 3-state 01 McASP(allMcASPPins) 10 (McASPwithoutAXR8,AXR9) ACLKR AFSR AXR0 AXR1 AC:LKX AFSX AXR2 AXR3 AHCLKR AMUTEIN AXR4 AXR5 AHCLKX AMUTE AXR6 AXR7 STCLK VCTL 11 Reserved 7:6 Reserved Reserved 5:4 VLYNQ_EN ControlsthepinmuxingbetweenVideoPort2andVLYNQ UNMUXED(12) MUXED(13) VP2#1 VP2#2VLYNQ 00 3-state 3-state 01 3-state 3-state 10 Enable VP2D12-19,VP2CLK1,VP2CTL2 11 Enable VRXD0-3andVTXD0-3,VCLK,VSCRUN 3:1 Reserved Reserved 0 TIMER_EN ControlsthepinmuxingbetweenTIMERandGPIO[8:11] MUXED(14) 0 GPIO[8:11] 1 Timer0/1 (11) Thecompletelistofpins:AC4,AC3,AC6,AC7,W6,AA7,AB6,Y6,AA6,AB4,Y5,V7,AA4,V6,Y7,AA5,AB3,U7 (12) ForthefirsthalfoftheVideoPort2,thecompletelistofpinswithfunction:AB1(VP2CLK0),AA1(VP2CTL0),AB2(VP2CTL1)andW5, AA2,Y3,U6,Y2,W3,V5,W4(VP2D02,VP2D03,VP2D04,VP2D05,VP2D06,VP2D07,VP2D08,VP2D09) (13) ForthesecondhalfoftheVideoPort2,thecompletelistofpinswithfunction:W1(VP2CLK1/VCLK),Y1(VP2CTL2/VSCRUN),W2,V3, V4,U1,U3,U2,U5,U4(VP2D12/VRXD0,VP2D13/VRXD1,VP2D14/VRXD2,VP2D15/VRXD3,VP2D16/VTXD0,VP2D17/VTXD1, VP2D18/VTXD2,VP2D19/VTXD3) (14) Thecompletelistofpins:E20,D21,E21,C22 46 DeviceConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table3-8.PCI/UHPI/GPIOBlock:PCIMUXedWithUHPIandGPIO[0:7] MUXED(1) PCI UHPI/GPIO[0:7] UHPIEN(pin) 1 UHPI/GPIO[0:7] 0 PCI (1) Thecompletelistofpin:AA22,AB22,AC21,AA23,AC22,AB21,AA21,Y21,AB20,AA20,Y20,Y19,AB18,AA19,AC18,AA18,Y16, AB15,AA15,Y15,W15,V15,AC14,AB14,W14,V14,AC13,AB13,AA13,Y13,W13,V13,W19,Y18,Y17,W17,W18,AC20,AC17, W16,Y14,AC15,AA16,AB17,U13,U12,V12,AA12,AA17,AA14. For information on the Ethernet Subsystem registers, see the TMS320DM647/DM648 DSP Subsystem ReferenceGuide(literaturenumberSPRUEU6). 3.2.7 MAC Address Registers • MAC_ADDR_R0 • MAC_ADDR_R1 • MAC_ADDR_RW0 • MAC_ADDR_RW1 Two sets of registers provide default MAC addresses for the device. One set - MAC_ADDR_R0 and MAC_ADDR_R1 - is read only and the other set - MAC_ADDR_RW0 and MAC_ADDR_RW1 - includes readandwriteregisters. Figure3-7.MAC_ADDR_R0Register 31 0 MAC_ID R-MACADDRESS[31:0] LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-9.MAC_ADDR_R0RegisterFieldDescriptions Bit Field Value Description 31:0 MAC_ID Mac Bit0ofMAC_IDisbit0ofMACAddress Address[31:0]of thedevice Figure3-8.MAC_ADDR_R1Register 31 24 23 16 CRC Reserved R-CRCfortheMAC_ID R-00000000 15 0 MAC_ID R-MACADDRESS[47:32] LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-10.MAC_ADDR_R1RegisterFieldDescriptions Bit Field Value Description 31:24 CRC CRCoftheMAC ThisfieldwillholdtheCRCoftheMACaddressofthatparticulardevice. ID 23:16 Reserved 0x00 Reserved Copyright©2007–2012,TexasInstrumentsIncorporated DeviceConfiguration 47 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table3-10.MAC_ADDR_R1RegisterFieldDescriptions(continued) Bit Field Value Description 15:0 MAC_ID Mac Bit0ofMAC_IDisBit32ofMACAddress Address[47:32]of thedevice Figure3-9.MAC_ADDR_RW0Register 31 0 MAC_ADDR_R0 R/W-MACID[31:0] LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-11.MAC_ADDR_RW0RegisterFieldDescriptions Bit Field Value Description 31:0 MAC_ID Mac Bit0ofMAC_IDisbit0ofMACAddress Address[31:0]of thedevice Figure3-10.MAC_ADDR_RW1Register 31 24 23 16 CRC Reserved R/W-CRCfortheMAC_ID R/W-00000000 15 0 MAC_ID R-MACADDRESS[47:32] LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table3-12.MAC_ADDR_RW1RegisterFieldDescriptions Bit Field Value Description 31:24 CRC CRCofthe ThisfieldwillholdtheCRCoftheMACaddressofthatparticulardevice. MACID 23:16 Reserved 0x00 Reserved 15:0 MAC_ID Mac Bit0ofMAC_IDisBit32ofMACAddress Address[47:32] ofthedevice 48 DeviceConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 3.3 Pullup/Pulldown Resistors Proper board design should specify that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldownresistors. Anexternalpullup/pulldownresistormustbeusedinthefollowingsituations: • Boot and Configuration Pins: If the pin is both routed out and in high-impedance mode, an external pullup/pulldownresistormustbeused,eveniftheIPU/IPDmatchesthedesiredvalue/state. • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldownresistortopullthesignaltotheoppositerail. If the boot and configuration pins are both routed out and in high-impedance mode, it is recommended that an external pullup/pulldown resistor be used. Although internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help specify that valid logic levels are latched on these important boot configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debuggingandflexibilityinswitchingoperatingmodes. Tipsforchoosinganexternalpullup/pulldownresistor: • Selectaresistorwiththelargestpossibleresistance • Calculate the worst-case leakage current that flows through this external resistor. Worst-case leakage current can be calculated by adding up all the leakage current at the pin—e.g., the input current (I) I fromthedevice,andleakagecurrentfromtheotherdevice(s)towhichthispinisconnected. • Specify that the voltage at the pin stays well within the low-/high-level input voltages (V or V ) when IL IH worst-caseleakagecurrentisflowingthroughthisexternalresistor. – ToopposeanIPUandpullthesignaltoalogiclow,thevoltageatthepinmuststaywellbelowV . IL – To oppose an IPD and pull the signal to a logic high, the voltage at the pin must stay well above V . IH For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Usersshouldconfirmthisresistorvalueiscorrectfortheirspecificapplication. Formostsystems,a20-kΩ resistorcanbeusedtocomplementtheIPU/IPDonthebootandconfiguration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. Formoredetailedinformationoninputcurrent(I),andthelow-/high-levelinputvoltages(V andV ),see I IL IH Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature. For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functionstable. Copyright©2007–2012,TexasInstrumentsIncorporated DeviceConfiguration 49 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 4 System Interconnect The C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric, the CPU can send data to the video ports without affecting a data transfer between the PCI and the DDR2 memory controller. The switch fabricsalsoallowforseamlessarbitrationbetweenthesystemmasterswhenaccessingsystemslaves. 4.1 Internal Buses, Bridges, and Switch Fabrics Two types of buses exist in the device: data buses and configuration buses. Some device peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer data. For example, data is transferred to the UART or I2C via their configuration bus. Similarly, the data bus can also be used to access the register space of a peripheral. For example, the EMIFA and DDR2 memory controller registers areaccessedthroughtheirdatabusinterface. TheC64x+Megamodule,theEDMA3trafficcontrollers,andthevarioussystemperipheralscanbedivided into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers and PCI. SlavesincludetheMcASP,videoports,andI2C. The device contains two switch fabrics through which masters and slaves communicate. The data switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to move data across the system (for more information, see Section 4.2). The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK1 frequency (SYSCLK1 is generated from PLL1 controller). Peripherals that have a 128-bit data bus interface running at this speed can connect directly to thedataSCR;otherperipheralsrequireabridge. The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3). The configuration SCR connects the C64x+ Megamodule to slaves via 32-bit configuration buses running at a SYSCLK1 frequency (SYSCLK1 is generated from the PLL1 controller). As with the data SCR, some peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also connectstotheconfigurationSCR.Bridgesperformavarietyoffunctions: • Conversionbetweenconfigurationbusanddatabus. • WidthconversionbetweenperipheralbuswidthandSCRbuswidth • FrequencyconversionbetweenperipheralbusfrequencyandSCRbusfrequency Forexample,theEMIFAmemorycontrollerrequireabridgetoconverttheir64-bitdatabusinterfaceintoa 128-bitinterfacesothattheycanconnecttothedataSCR. SomeperipheralscanbeaccessedthroughthedataSCRandalsothroughtheconfigurationSCR. 4.2 Data Switch Fabric Connections Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK1 frequency. SYSCLK1 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3. Some peripherals, like PCI and the C64x+ Megamodule, have both slave and master ports. Each EDMA3 transfer controller has an independentconnectiontothedataSCR. Masters can access the configuration SCR through the data SCR. The configuration SCR is described in Section4.3. 50 SystemInterconnect Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Not all masters on the device may connect to all slaves. Allowed connections are summarized in Table 4- 1. 128 SYSCLK1 S Megamodule M 128 SYSCLK1 S M0 0 EDMA3 M1 128 SYSCLK1 S 128 SYSCLK1 DDR2 1 M S Memory CToranntrsoflelerr M2 128 SYSCLK1 S2 Controller 128 64 M3 128 SYSCLK1 S SYSCLK1 SYSCLK1 3 M Bridge S EMIFA 64 64 128 SYSCLK1 SYSCLK1 SYSCLK1 Megamodule M S S Video Port 0 64 32 SYSCLK3 SYSCLK1 M Bridge S Video Port 1 32 SYSCLK3 64 HPI M SYSCLK1 32 SYSCLK3 128 SYSCLK1 S Video Port 2 PCI M Bridge S 64 64 SYSCLK1 VLYNQ M SYSCLK1 S Video Port 3 32 SYSCLK3 128 SYSCLK1 64 M Bridge SYSCLK1 3-port Gigabit 32 TXBCLK 128 SYSCLK1 Ethernet Switch M Bridge S S Video Port 4 128 SYSCLK1 32 32 SYSCLK3 SYSCLK3 S PCI 32 M Bridge SYSCLK3 S VLYNQ 128 SYSCLK1 32 128 SYSCLK1 SYSCLK1 M Bridge S Config SCR Figure4-1.DataSCR Copyright©2007–2012,TexasInstrumentsIncorporated SystemInterconnect 51 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table4-1.ConnectivityMatrixforDataSCR MEGAMODULE DDR2EMIF EMIFA VIDEO VIDEO PCI VLYNQ Configuration PORT0-2 PORT3-4 SCR TC0 Y Y Y Y Y Y Y Y TC1 Y Y Y Y Y Y Y Y TC2 Y Y Y Y Y Y Y Y TC3 Y Y Y Y Y N N N Megamodule N Y Y N N Y Y N HPI Y Y Y N N Y Y Y PCI Y Y Y N N Y Y Y VLYNQ Y Y Y N N Y Y Y EthernetSubsystem Y Y Y N N N N N 4.3 Configuration Switch Fabric Figure 4-2 shows the connection between the C64x+ megamodule and the configuration SCR, which is mainly used by the C64x+ Megamodule to access peripheral registers. The data SCR also has a connection to the configuration SCR that allows masters to access most peripheral registers. The only registers not accessible by the data SCR through the configuration SCR are the device configuration registers and the PLL1 and PLL2 controller registers; these can be accessed only by the C64x+ Megamodule. The configuration SCR uses 32-bit configuration buses running at SYSCLK1 frequency. SYSCLK1 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency dividedby3. 52 SystemInterconnect Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 32-bit 32-bit SYSCLK1 TXBCLK Ethernet Config SCR M Bridge S SubSystem 32-bit SYSCLK1 32-bit S Video Port 0 SYSCLK1 32-bit SYSCLK1 S Video Port 1 32-bit SYSCLK1 M Bridge S Video Port 2 32-bit SYSCLK1 S Video Port 3 128-bit 32-bit SYSCLK1 SYSCLK1 S Video Port 4 32-bit SYSCLK3 S UART 32-bit SYSCLK3 S I2C 32-bit SYSCLK3 S Timer 0 32-bit SYSCLK3 S Timer 1 32-bit SYSCLK3 S Timer 2 32-bit SYSCLK3 S Timer 3 32-bit SYSCLK1 Megamodule M S 32-bit 32-bit SYSCLK3 S PSC SYSCLK3 32-bit Data SCR M 32-bit SYSCLK1 S SYSCLK3 S PLLControllers M Bridge 32-bit 32-bit 32-bit SYSCLK3 SYSCLK3 SYSCLK1 S PCI VICP M Bridge S 32-bit SYSCLK3 32-bit S McASP SYSCLK1 32-bit SYSCLK3 S SPI 32-bit SYSCLK3 S VIC 32-bit SYSCLK3 S GPIO 32-bit SYSCLK3 S VICPCFG 32-bit SYSCLK3 S HPI 32-bit SYSCLK1 S EDMA3 CC 32-bit 32-bit SYSCLK1 SYSCLK1 S EDMA3TC0 32-bit SYSCLK1 M Bridge S EDMA3TC1 32-bit SYSCLK1 S EDMA3TC2 32-bit 32-bit SYSCLK1 SYSCLK1 S EDMA3TC3 Figure4-2.ConfigurationSCR Copyright©2007–2012,TexasInstrumentsIncorporated SystemInterconnect 53 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 5 Device Operating Conditions 5.1 Absolute Maximum Ratings OverOperatingTemperatureRange(UnlessOtherwiseNoted)(1) Supplyvoltageranges: Core(CV ,CV ,CV ,AV , 1.20-Voperation -0.5Vto1.5V DD DDESS DD1 DDA DV ,AV )(2) DDD DDT I/O,3.3V(DV )(2) -0.5Vto4.2V DD33 I/O,1.8V(DV ,AV ,AV ,AV )(2) -0.5to2.5V DD18 DLL1 DLL2 DDR Inputvoltageranges: V I/O,3.3-Vpins -0.5Vto4.2V I V I/O,1.8V -0.5Vto2.5V I Outputvoltageranges: V I/O,3.3-Vpins -0.5Vto4.2V O V I/O,1.8V -0.5Vto2.5V O Operatingcasetemperature,T Commercial 0°Cto90°C case Extended -40°Cto105°C Industrial -40°Cto90°C Storagetemperaturerange,T (default) -65°Cto150°C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttoV SS. 54 DeviceOperatingConditions Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 5.2 Recommended Operating Conditions MIN NOM MAX UNIT CVDD Supplyvoltage,Core(1) CVDDESS Supplyvoltage,EthernetSubsystemCore(1) CVDD1 Supplyvoltage,DDRCore(1) (-720,-800,-900,- 1.14 1.2 1.26 V AVDDA Supplyvoltage,SerDesAnalog(1) 1100devices) DVDDD Supplyvoltage,SerDesDigital(1) AVDDT Supplyvoltage,SerDesAnalog(1) DVDD33 Supplyvoltage,I/O,3.3V 3.14 3.3 3.46 V DVDD18 Supplyvoltage,DDRI/O,1.8V AVDLL1 Supplyvoltage,I/O,1.8V 1.71 1.8 1.89 V AVDLL2 Supplyvoltage,I/O,1.8V AVDDR Supplyvoltage,1.8-VSerDesAnalogSupply(Regulator) VSS Supplyground(VSS) 0 0 0 V DDR_VREF DDR2referencevoltage(2) 0.49DVDD18 0.5DVDD18 0.51DVDD18 V High-levelinputvoltage,3.3V(exceptPCI-capableandI2Cpins) 2 V High-levelinputvoltage,I2C 0.7DVDD33 V VIH PCI-capablepins 0.5DVDD33 DVDD33+0.5 V DDR_VREF+ DDR2memorycontrollerpins(DC) 0.125 DVDD18+0.3 V Low-levelinputvoltage,3.3V(exceptPCI-capableandI2Cpins) 0.8 V Low-levelinputvoltage,I2C 0 0.3DVDD33 V VIL PCI-capablepins -0.5 0.3DVDD33 V DDR2memorycontrollerpins(DC) -0.3 DDR_VREF-0.125 V Commercial(3) 0 90 Tcase Operatingcasetemperature Extended(4) -40 105 Industrial -40 90 (-1100devices)(3) 33.3 1100 MHz (-900devices) 33.3 900 MHz FSYSCLK1 DSPOperatingFrequency(SYSCLK1) (-720devices) 33.3 720 MHz (-800devices) 33.3 800 MHz (1) FuturevariantsofTISOCdevicesmayoperateatvoltagesrangingfrom0.9Vto1.4Vtoprovidearangeofsystempower/performance options.TIhighlyrecommendsthatusersdesign-inasupplythatcanhandlemultiplevoltageswithinthisrange(i.e.,1.0V,1.05V, 1.1V,1.14V,1.2,1.26Vwith±3%tolerances)byimplementingsimpleboardchangessuchasreferenceresistorvaluesorinputpin configurationmodifications.NotincorporatingaflexiblesupplymaylimitthesystemabilitytoeasilyadapttofutureversionsofTISOC devices. (2) DDR_VREFisexpectedtoequal0.5DV ofthetransmittingdeviceandtotrackvariationsintheDV . DDR2 DD18 (3) Toavoidsignificantdevicedegradationfor1.1GHzdevices,thedevicepower-onhours(POH)mustbelimitedtolessthan87.6K. (4) Toavoidsignificantdevicedegradationforextendedtemperaturedevices(-40°C≤T ≤105°C),thedevicepower-onhours(POH) case mustbelimitedtolessthan50K. Copyright©2007–2012,TexasInstrumentsIncorporated DeviceOperatingConditions 55 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 5.3 Electrical Characteristics OverRecommendedRangesofSupplyVoltageandOperatingTemperature(UnlessOtherwiseNoted) PARAMETER TESTCONDITIONS(1) MIN TYP MAX UNIT 3.3-Vpins(exceptPCI-capable andI2Cpins) DVDD33=MIN,IOH=MAX 0.8DVDD33 V VOHHigh-level outputvoltage PCI-capablepins(2) DVDD33=3.3V,IOH=-0.5mA 0.9DVDD33 DDR2memorycontrollerpins 1.4 3.3-Vpins(exceptPCI-capable andI2Cpins) DVDD33=MIN,IOL=MAX 0.22DVDD33 VOLLow-level PCI-capablepins(2) DVDD33=3.3V,IOL=1.5mA 0.1DVDD33 outputvoltage I2Cpins Pulledupto3.3V,3mAsinkcurrent 0.4 DDR2memorycontrollerpins 0.4 V VI=VSStoDVDD33withoutinternalpullupoe -1 1 μA pulldownresistor 3a.n3d-VI2pCinpsin(es)xceptPCI-capable V(2I)=VSStoDVDD33withinternalpullupresistor 50 100 400 μA IIInputcurrent[dc] VpuIl=ldVowSSntoreDsiVstDoDr33(2)withopposinginternal -400 -100 -50 μA Inputcurrent[dc](I2C) 0.1DVDD33≤VI≤0.9DVDD33 -10 10 μA PCI-capablepins(4) -600 600 μA IOHHigh-level AllperipheralsotherthanDDR2 -8 mA outputcurrent[dc] andPCI DDR2memorycontrollerpins -4 mA PCI-capablepins(2) -0.5 mA IOLLow-level Allperipheralsotherthan 8 mA outputcurrent[dc] DDR2,PCIandI2C I2Cpins 3 mA DDR2memorycontrollerpins 4 mA PCI-capablepins(2) 1.5 mA IOZI/OOff-state 3.3-Vpins -20 20 μA outputcurrent[DC] CVDD=1.2-V,DSPclock=720MHz 2497 mA ICDD Ccuorrreen(Ct(3V)DD,VDDA_1P1V)supply CCVVDDDD==11..22--VV,,DDSSPPcclloocckk==890000MMHHzz 22670451 mmAA CVDD=1.2-V,DSPclock=1100MHz 3013 mA 3cu.3rr-eVnIt/(O3)(DVDD33)supply D90V0DDM=Hz3,.31-1V0,0DMSHPzclock=720MHz,800MHz, 227 mA IDDD 1.8-VI/O(DVDDR2, DDR_VDDDLL,PLLVPRW18, DVDD=1.8-V,DSPclock=720MHz,800MHz, 311 mA VDDA_1P8V,MXVDD)supply 900MHz,1100MHz current(3) CI Inputcapacitance 10 pF Co Outputcapacitance 10 pF (1) FortestconditionsshownasMIN,MAX,orNOM,usetheappropriatevaluespecifiedintherecommendedoperatingconditionstable. (2) Appliesonlytopinswithaninternalpullup(IPU)orpulldown(IPD)resistor. (3) Assumesthefollowingconditions:50%DSPCPUutilization;(peripheralconfigurations,otherhousekeepingactivities)DDR2at50% utilization(266MHz),50%writes,32bits,100%bitswitching,110-MHzVideoPortsat100%utilization,MCASPoperatingat25MHz with100%utilizationwith10serializers,Timer0,1at100%utilization,VICPwith100%utilization,PCIoperatingat66MHzwith50% writesatroomtemp(25°C)usingZUTpackage.(asinthepowerappnote)forthethreeitems. 56 DeviceOperatingConditions Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6 Peripheral Information and Electrical Specifications 6.1 Parameter Information Tester Pin Electronics DataSheetTiming Reference Point 42Ω 3.5 nH Output Transmission Line Under Test Z0 = 50Ω (see Note) Device Pin 4.0 pF 1.85 pF (see Note) NOTE: Thedata sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect.The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure6-1.TestLoadCircuitforACTimingMeasurements The load capacitance value stated is only for characterization and measurement of ac timing signals. This loadcapacitancevaluedoesnotindicatethemaximumloadthedeviceiscapableofdriving. 6.1.1 3.3-V Signal Transition Levels All input and output timing parameters are referenced to V for both 0 and 1 logic levels. For 3.3-V I/O, ref V =1.5V.For1.8-VI/O,V =0.9V. ref ref V ref Figure6-2.InputandOutputVoltageReferenceLevelsforacTimingMeasurements All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, IL IH V MAXandV MINforoutputclocks. OL OH Vref= VIHMIN (or VOHMIN) Vref= VILMAX (or VOLMAX) Figure6-3.RiseandFallTransitionTimeVoltageReferenceLevels 6.1.2 3.3-V Signal Transition Rates Alltimingsaretestedwithaninputedgerateof4voltspernanosecond(4V/ns). Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 57 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.1.3 Timing Parameters and Board Routing Analysis Thetimingparametervaluesspecifiedinthisdatamanualdonotincludedelayscausedbyboardroutings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis Application Report (literature number SPRA839). If needed, external logic hardware such as buffersmaybeusedtocompensateforanytimingdifferences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setuptimemargin,butalsotendstoimprovetheinputholdtimemargins(seeTable6-1andFigure6-4). Figure 6-4 represents a general transfer between the DSP and an external device. The figure also representsboardroutedelaysandhowtheyareperceivedbytheDSPandtheexternaldevice. Table6-1.Board-LevelTimingExample (seeFigure6-4) NO. DESCRIPTION 1 Clockroutedelay 2 MinimumDSPholdtime 3 MinimumDSPsetuptime 4 Externaldeviceholdtimerequirement 5 Externaldevicesetuptimerequirement 6 Controlsignalroutedelay 7 Externaldeviceholdtime 8 Externaldeviceaccesstime 9 DSPholdtimerequirement 10 DSPsetuptimerequirement 11 Dataroutedelay (Output from DSP) 1 (Input to External Device) 2 Control Signals(A) 3 (Output from DSP) 4 5 6 Control Signals (Input to External Device) 7 8 Data Signals(B) (Output from External Device) 9 10 Data Signals(B) 11 (Input to DSP) A. Controlsignalsincludedataforwrites. B. Datasignalsaregeneratedduringreadsfromanexternaldevice. Figure6-4.Board-LevelInput/OutputTimings 58 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between V and V (or between V and V ) in a monotonic IH IL IL IH manner. 6.3 Power Supplies For more information regarding TI's power management products and suggested devices to power TI DSPs,visitwww.ti.com/dsppower. 6.3.1 Power-Supply Sequencing The device includes 1.2-V core supply (CV , CV , CV , AV , DV , AV ), and two I/O DD DDESS DD1 DDA DDD DDT supplies—3.3-V (DV ) and 1.8-V (DV , AV , AV , AV ). To ensure proper device operation, DD33 DD18 DLL1 DLL2 DDR a specific power-up sequence must be followed. Some TI power-supply devices include features that facilitate power sequencing — for example, Auto-Track and Slow-Start/Enable features. For more informationonTIpowersuppliesandtheirfeatures,visitwww.ti.com/dsppower. Followingisasummaryofthepowersequencingrequirements: • The power ramp order must be 3.3-V (DV ) before 1.8-V (DV , AV , AV , AV ), and 1.8- DD33 DD18 DLL1 DLL2 DDR V (DV , AV , AV , AV ) before 1.2-V core supply (CV , CV , CV , AV , DV , DD18 DLL1 DLL2 DDR DD DDESS DD1 DDA DDD AV ) —meaning during power up, the voltage at the 1.8-V rail should never exceed the voltage at DDT the3.3-Vrail.Similarly,thevoltageatthe1.2-VrailshouldneverexceedthevoltageattheDV rail. DDR2 • From the time that power ramp begins, all power supplies (3.3 V, 1.8 V, 1.2 V) must be stable within 200ms.Theterm"stable"meansreachingtherecommendedoperatingcondition(seeSection5.2). 6.3.2 Power-Supply Design Considerations Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the device, the PC board should include separate power planes for core, I/O, and ground; all bypassedwithhigh-qualitylow-ESL/ESRcapacitors. 6.3.3 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum distancetobeeffective.Physicallysmallercapsarebetter,suchas0402,butneedtobeevaluatedfroma yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors; therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 μF) should be furthest away, but still as close as possible. Large caps for eachsupplyshouldbeplacedoutsideoftheBGAfootprint. 6.3.4 Power and Sleep Controller (PSC) The power and sleep controller (PSC) controls power by turning off unused power domains or by gating off clocks to individual peripherals/modules. The device uses the clock-gating feature of the PSC only for powersavings.ThePSCconsistsofaglobalPSC(GPSC)andasetoflocalPSCs(LPSCs). The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The LPSCs are shown in Table 6-2. The PSC register memory map is given in Table 6-3. For more details on the PSC, see the TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literaturenumberSPRUEU6). Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 59 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-2.LPSCAssignments LPSCNUMBER PERIPHERAL/MODULE 0 EDMA3CC 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 DDR2MemoryController 8 UHPI 9 VLYNQ 10 GPIO 11 TIMER0 12 TIMER1 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 SPI 18 I2C 19 PCI 20 VP0 21 VP1 22 VP2 23 VP3 24 VP4 25 EMIFA 26 TIMER2 27 TIMER3 28 VIC 29 McASP 30 UART 31 VICP 32 Reserved 33 C64x+CPU 34 EthernetSubsystem Table6-3.PSCRegisterMemoryMap HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02046000 PID PeripheralRevisionandClassInformationRegister 0x02046004-0x0204600F – Reserved 0x02046010 – Reserved 0x02046014 Reserved 0x02046018 INTEVAL InterruptEvaluationRegister 0x0204601C-0x0204603F – Reserved 0x02046040 – Reserved 0x02046044 MERRPR1 ModuleErrorPending1(mod32-63)Register 0x02046048-0x0204604F – Reserved 60 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-3.PSCRegisterMemoryMap(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02046050 – Reserved 0x02046054 MERRCR1 ModuleErrorClear1(mod32-63)Register 0x02046058-0x0204605F – Reserved 0x02046060 – Reserved 0x02046064-0x02046067 – Reserved 0x02046068 – Reserved 0x0204606C-0x0204611F – Reserved 0x02046120 PTCMD PowerDomainTransitionCommandRegister 0x02046124-0x02046127 – Reserved 0x02046128 PTSTAT PowerDomainTransitionStatusRegister 0x0204612C-0x020461FF – Reserved 0x02046200 PDSTAT0 PowerDomainStatus0Register(AlwaysOn) 0x02046204-0x020462FF – Reserved 0x02046300 PDCTL0 PowerDomainControl0Register(AlwaysOn) 0x02046304-0x1C4150F – Reserved 0x02046510 – Reserved 0x02046514 – Reserved 0x02046518-0x020465FF – Reserved 0x02046600-0x020467FF – Reserved 0x02046800 MDSTAT0 ModuleStatus0Register(EDMACC) 0x02046804 – Reserved 0x02046808 – Reserved 0x0204680C – Reserved 0x02046810 – Reserved 0x02046814 – Reserved 0x02046818 – Reserved 0x0204681C MDSTAT7 ModuleStatus7Register(DDR2) 0x02046820 MDSTAT8 ModuleStatus8Register(HPI) 0x02046824 MDSTAT9 ModuleStatus9Register(VLYNQ) 0x02046828 MDSTAT10 ModuleStatus10Register(GPIO) 0x0204682C MDSTAT11 ModuleStatus11Register(TIMER0) 0x02046830 MDSTAT12 ModuleStatus12Register(TIMER1) 0x02046834 – Reserved 0x02046838 – Reserved 0x0204683C – Reserved 0x02046840 – Reserved 0x02046844 MDSTAT17 ModuleStatus17Register(SPI) 0x02046848 MDSTAT18 ModuleStatus18Register(I2C) 0x0204684C MDSTAT19 ModuleStatus19Register(PCI) 0x02046850 MDSTAT20 ModuleStatus20Register(VideoPort0) 0x02046854 MDSTAT21 ModuleStatus21Register(VideoPort1) 0x02046858 MDSTAT22 ModuleStatus22Register(VideoPort2) 0x0204685C MDSTAT23 ModuleStatus23Register(VideoPort3) 0x02046860 MDSTAT24 ModuleStatus24Register(VideoPort4) 0x02046864 MDSTAT25 ModuleStatus25Register(EMIFA) 0x02046868 MDSTAT26 ModuleStatus26Register(TIMER2) 0x0204686C MDSTAT27 ModuleStatus27Register(TIMER3) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 61 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-3.PSCRegisterMemoryMap(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02046870 MDSTAT28 ModuleStatus28Register(VIC) 0x02046874 MDSTAT29 ModuleStatus29Register(McASP) 0x02046878 MDSTAT30 ModuleStatus30Register(UART) 0x0204687C MDSTAT31 ModuleStatus31Register(VICP) 0x02046880 – Reserved 0x02046884 MDSTAT33 ModuleStatus33Register(C64x+CPU) 0x02046888 MDSTAT34 ModuleStatus34Register(EthernetSubsystem) 0x0204688C-0x020469FF – Reserved 0x02046A00 MDCTL0 ModuleControl0Register(EDMACC) 0x02046A04 – Reserved 0x02046A08 – Reserved 0x02046A0C – Reserved 0x02046A10 – Reserved 0x02046A14 – Reserved 0x02046A18 – Reserved 0x02046A1C MDCTL7 ModuleControl7Register(DDR2) 0x02046A20 MDCTL8 ModuleControl8Register(HPI) 0x02046A24 MDCTL9 ModuleControl9Register(VLYNQ) 0x02046A28 MDCTL10 ModuleControl10Register(GPIO) 0x02046A2C MDCTL11 ModuleControl11Register(TIMER0) 0x02046A30 MDCTL12 ModuleControl12Register(TIMER1) 0x02046A34 – Reserved 0x02046A38 – Reserved 0x02046A3C – Reserved 0x02046A40 – Reserved 0x02046A44 MDCTL17 ModuleControl17Register(SPI) 0x02046A48 MDCTL18 ModuleControl18Register(I2C) 0x02046A4C MDCTL19 ModuleControl19Register(PCI) 0x02046A50 MDCTL20 ModuleControl20Register(VideoPort0) 0x02046A54 MDCTL21 ModuleControl21Register(VideoPort1) 0x02046A58 MDCTL22 ModuleControl22Register(VideoPort2) 0x02046A5C MDCTL23 ModuleControl23Register(VideoPort3) 0x02046A60 MDCTL24 ModuleControl24Register(VideoPort4) 0x02046A64 MDCTL25 ModuleControl25Register(EMIFA) 0x02046A68 MDCTL26 ModuleControl26Register(TIMER2) 0x02046A6C MDCTL27 ModuleControl27Register(TIMER3) 0x02046A70 MDCTL28 ModuleControl28Register(VIC) 0x02046A74 MDCTL29 ModuleControl29Register(McASP) 0x02046A78 MDCTL30 ModuleControl30Register(UART) 0x02046A7C MDCTL31 ModuleControl31Register(VICP) 0x02046A80 – Reserved 0x02046A84 MDCTL33 ModuleControl33Register(C64x+CPU) 0x02046A88 MDCTL34 ModuleControl34Register(EthernetSubsystem) 0x02046A90-0x02046FFF – Reserved 62 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.3.5 Power and Clock Domains The device includes two power domains: the System Domain and the Ethernet Subsystem Domain. Both of these power domains are always on when the chip is on. Both of these domains are powered by the CV pinsofthedevice. DD The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the external memory interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the secondaryPLLcontroller(PLL2controller)usesthedeviceinputclockCLKIN2. Table6-4providesalistingoftheclockdomains. Table6-4.PowerandClockDomains POWERDOMAIN CLOCKDOMAIN PERIPHERAL/MODULE/USAGE SystemDomain CLKDIV1 C64x+CPU SystemDomain CLKDIV3 EDMA/SCR SystemDomain CLKDIV3 DDRSubsystem SystemDomain CLKDIV3 VideoPort0 SystemDomain CLKDIV3 VideoPort1 SystemDomain CLKDIV3 VideoPort2 SystemDomain CLKDIV3 VideoPort3 SystemDomain CLKDIV3 VideoPort4 SystemDomain CLKDIV3 EMIFA SystemDomain CLKDIV6 HPI SystemDomain CLKDIV6 PCI SystemDomain CLKDIV6 VLYNQ SystemDomain CLKDIV6 UART SystemDomain CLKDIV6 I2C SystemDomain CLKDIV6 TIMER0 SystemDomain CLKDIV6 TIMER1 SystemDomain CLKDIV6 TIMER2 SystemDomain CLKDIV6 TIMER3 SystemDomain CLKDIV6 SPI SystemDomain CLKDIV6 McASP SystemDomain CLKDIV6 VIC SystemDomain CLKDIV6 GPIO SystemDomain CLKDIV6 PLLController1 SystemDomain CLKDIV6 PLLController2 SystemDomain CLKDIV6 ConfigSCR SystemDomain CLKDIV40 InternalEMIFAClock SystemDomain CLKDIV41 EmulationandTrace SystemDomain CLKDIV42 VICPcop_clk/2 SystemDomain CLKDIV2 VICPcop_clk EthernetSubsystemDomain SerDesTXBCLK EthernetSubsystem Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 63 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com The device architecture is divided into the power and clock domains shown in Table 6-5, which further showstheclockdomainsandtheirratios. Table6-5.ClockDomainAssignment SUBSYSTEM CLOCKDOMAIN DOMAINCLOCKSOURCE FIXEDRATIOvsSYSREFCLK FREQUENCY DSPSubsystem CLKDIV1 PLLC1.REFSYSCLK - Peripherals(CLKDIV3Domain) CLKDIV3 PLLC1.SYSCLK1 1:3 Emulation/Trace CLKDIV41 PLLC1.SYSCLK2 1:4 Peripherals(CLKDIV6Domain) CLKDIV6 PLLC1.SYSCLK3 1:6 InternalEMIFAClock CLKDIV40 PLLC1.SYSCLK4 1:4(1) VICPcop_clk/2 CLKDIV42 PLLC1.SYSCLK5 1:4 VICPcop_clk CLKDIV2 PLLC1.SYSCLK6 1:2 (1) Thereisa/2dividerinthepathofPLLC1.SYSCLK4sotheeffectiveEMIFAclockisPLLC1.SYSCLK4/2.BydefaulttheinternalEMIFA Clockis1:8. 6.3.6 Preserving Boundary-Scan Functionality on DDR2 Memory Pins Similarly, when the DDR2 Memory Controller is not used, the DDR_VREF, RSV19, and RSV20 pins can be connected directly to ground (V ) to save power. However, this will prevent boundary-scan from SS functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 MemoryControllerpins,DDR_VREF,RSV19,andRSV20shouldbeconnectedasfollows: • DDR_VREF - connect to a voltage of DV /2. The DV /2 voltage can be generated directly from DD18 DD18 theDV supplyusingtwo1-kΩ resistorstoformaresistordividercircuit. DD18 • RSV19-connectthispintothe1.8-VI/Osupply(DV )viaa200-Ω resistor DD18 • RSV20-connectthispintoground(V )viaa200-Ω resistor. SS 64 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.4 PLL1 Controller The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the externalmemoryinterface(EMIFA).Figure6-5showsafunctionalblockdiagramofthePLLInputClock. +1.8 V PLLV1 C1 C2 EMI Filter 560 pF 0.1mF PLL1 Controller F RE PLL1 L L P T PLLEN (PLLCTL.[0]) U DIVIDER PREDIV PLLM O SYSREFCLK CLKIN1 x1, LL (C64x+ MegaModule) /1, /2, /3 x16 to x32 P DIVIDER D1 ENA 1 SYSCLK1 0 /3 PREDEN (PREDIV.[15]) DIVIDER D2 /1, /2, ..., /8 SYSCLK2 D2EN (PLLDIV2.[15]) ENA (Emulation and Trace) DIVIDER D3 /6 SYSCLK3 DIVIDER D4 /4 ... /8 SYSCLK4 /2 D4EN (PLLDIV4.[15]) ENA (Internal DIVIDER D5 EMIF Clock Input) /4 SYSCLK5 VICPcop_clk/2 DIVIDER D6 /2 SYSCLK6 VICPcop_clk AECLKIN (External EMIF Clock Input) VCLK /1, /2, ..., /8 CLKDIV 0 1 AECLKINSEL 0 1 CLKDIR (CTRL.[18:16]) (AEA[17] pin) (CTRL.[15]) EMIFA VLYNQ (EMIF Input Clock) AECLKOUT SYSCLK5 Figure6-5.PLLInputClock Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 65 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com As shown in Figure 6-5, the PLL1 controller features a software-programmable PLL multiplier controller (PLLM) and seven dividers (PREDIV, D1, D2, D3, D4, D5). The PLL1 controller uses the device input clock CLKIN1 to generate a system reference clock (SYSREFCLK) and system clocks (SYSCLK1, SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5). PLL1 power is supplied externally via the PLL1 power- supply pin (PLLV1). An external EMI filter circuit must be added to PLLV1. The 1.8-V supply of the EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DV . TI requires DD18 EMIfiltermanufacturerMurata,partnumberNFM18CC222R1C3. All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). The minimum CLKIN1 rise and fall times should also be observed. For the inputclocktimingrequirements,seeSection6.4.4. 6.4.1 PLL1 Controller Device-Specific Information As shown in Figure 6-5, the PLL1 controller generates several internal clocks including the system reference clock (SYSREFCLK), and the system clocks (SYSCLK1/2/3/4/5/6). The high-frequency clock signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves as a reference clock for the rest of the DSP system. Dividers D1, D2, D3, D4, D5, and D6 divide the high- frequency clock SYSREFCLK to generate SYSCLK1, SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5, and SYSCLK6,respectively. ThesystemclocksareusedtoclockdifferentportionsoftheDSPasfollows: • SYSCLK1 is used for the following modules: 3PDMA, the SCR and the bridges, DDR Subsystem internal logic, Video Port 0, Video Port 1, Video Port 2, Video Port 3, Video Port 4, EMIFA internal logic. • SYSCLK2isusedforEmulationandTrace • SYSCLK3 is used for most of the peripherals. These modules are clocked from SYSCLK3: HPI, PCI, VLYNQ, UART, I2C, TIMER 0, TIMER 1, TIMER 2, TIMER 3, SPI, McASP, VIC, GPIO, PLL Controller 1,PLLController2,ConfigSCR • SYSCLK4isusedastheEMIFAAECLKOUT [When SYSCLK4 is used as the EMIF input clock source, the actual clock goes through a divider and thefrequencywouldbeSYSCLK4divide-by-2(seeFigure6-5,PLLInputClock).] • SYSCLK5isusedastheVICPinternalclock • SYSCLK6isusedastheVICPinternalclock The PLL multiplier controller (PLLM) must be programmed after reset. There is no hardware CLKMODE selection on the device. Since the divider ratio bits for dividers D1, D3, D5, and D6 are fixed, the frequency of SYSCLK1, SYCLK3, SYSCLK5, and SYSCLK6 is tied to the frequency of SYSREFCLK. However, the frequency of SYSCLK2 and SYSCLK4 depends on the configuration of dividers D2 and D4. For example, with PLLM in the PLL1 multiply control register set to 10011b (x20 mode) and a 35-MHz CLKIN1 input, the PLL output PLLOUT is set to 700 MHz and SYSCLK1 and SYSCLK3 run at 233 MHz and 117 MHz, respectively. Divider D4 can be programmed through the PLLDIV4 register to divide SYSREFCLKby8(2*(PLLDIV4.RATIO+1))suchthatSYSCLK4runsat87.5MHz. Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, and SYSCLK4. The PLL1 Controller must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). For the PLL clocks inputandoutputfrequencyranges,seeTable6-6. 66 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-6.PLL1ClockFrequencyRanges CLOCKSIGNAL MIN MAX UNIT CLKIN1 25 66.6 MHz PLLREF(PLLEN=1)(1) 25 66.6 MHz PLLOUT (1) 400 720(-720devices) MHz 400 800(-800devices)(2) MHz 400 900(-900devices) MHz 400 1100(-1100devices) MHz SYSCLK4 1/16P(3) PLLOUT/(2*(PLLDIV4.RATIO+1))(4) MHz (1) OnlyapplieswhenthePLL1ControllerissettoPLLmode(PLLEN=1inthePLLCTLregister).BasedonCLKIN1andPLLOUT,PLL1 multiplierfactorrangesfromx16tox32. (2) OnlyforExtendedTemperatureRangedevice(-800MHz) (3) P=1/CPUclockfrequencyinns (4) PLLDIV4.RATIO=3 6.4.2 PLL1 Controller Operating Modes The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In bypassmode,CLKIN1isfeddirectlytoSYSREFCLK. All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration hascompleted. 6.4.3 PLL1 Stabilization, Lock, and Reset Times The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device power-up. The PLL should not be operated until this stabilization time has finished. ThePLLresettimeistheamountofwaittimeneededwhenresettingthePLL(writingPLLRST=1)forthe PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time value,seeTable6-7. Table6-7.PLL1Stabilization,Lock,andResetTimes MIN TYP MAX UNIT PLLstabilizationtime 150 μs PLLlocktime 2000×C(1) μs PLLresettime 128×C(1) μs (1) C=CLKIN1cycletimeinns.Forexample,whenCLKIN1frequencyis50MHz,useC=20ns. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 67 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.4.4 PLL1 Controller Input and Output Clock Electrical Data/Timing Table6-8.TimingRequirementsforCLKIN1(1)(2)(seeFigure6-6) 720,800,900,1100 NO. PLLMODES(3) UNIT MIN MAX 1 t Cycletime,CLKIN1 15 40 ns c(CLKIN1) 2 t Pulseduration,CLKIN1high 0.4C ns w(CLKIN1H) 3 t Pulseduration,CLKIN1low 0.4C ns w(CLKIN1L) 4 t Transitiontime,CLKIN1 1.2 ns t(CLKIN1) 5 t Periodjitter,(peak-to-peak),CLKIN1 100 ps J(CLKIN1) (1) Thereferencepointsfortheriseandfalltransitionsaremeasuredat3.3-VV MAXandV MIN. IL IH (2) C=CLKIN1cycletimeinns.Forexample,whenCLKIN1frequencyis50MHz,useC=20ns. (3) ThePLL1multiplierfactors(x1[BYPASS],x16tox32)furtherlimittheMINandMAXvaluesfort .SeeSection6.3.5for c(CLKIN1) supportedPLL1multiplierfactors. 5 1 4 2 CLKIN 3 4 Figure6-6.CLKIN1Timing 6.4.5 PLL1 Controller Register Description(s) AsummaryofthePLL1controllerregistersisshowninTable6-9. Table6-9.PLL1andResetControllerRegistersMemoryMap HEXADDRESSRANGE REGISTERNAME DESCRIPTION 0x020E0000 PID PeripheralIdentificationandRevisionInformationRegister 0x020E00E4 RSTYPE ResetTypeRegister 0x020E0100 PLLCTL PLLController1OperationsControlRegister 0x020E0110 PLLM PLLController1MultiplierControlRegister 0x020E0114 PREDIV PLLPre-DividerControlRegister 0x020E011C PLLDIV2 PLLController1Control-Divider2Register(SYSCLK2) 0x020E0138 PLLCMD PLLController1CommandRegister 0x020E013C PLLSTAT PLLController1StatusRegister(ShowsPLLC1Status) 0x020E0140 ALNCTL PLLControllerClockAlignControlRegister 0x020E0144 DCHANGE PLLDIVRatioChangeStatusRegister 0x020E0150 SYSTAT PLLController1SystemClockStatus1Register(IndicatesSYSCLKon/off Status) 0x020E0160 PLLDIV4 PLLController1Control-Divider4Register(SYSCLK4) 68 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.5 PLL2 Controller ThesecondaryPLLcontrollergeneratesinterfaceclocksfortheDDR2memorycontroller. As shown in Figure 6-7, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is fixed to a x20 multiplier rate. PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external PLL filter circuit must be added to PLLV2 as shown in Figure 6-7. The 1.8-V supply for the EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DV . TI requires EMI filter DD18 manufacturerMurata,partnumberNFM18CC222R1C3. +1.8 V PLLV2 C161 C162 SYSCLK1 (From PLLController 1) EMI Filter 560 pF 0.1mF CLKIN2 PLLREF PLLOUT DDR2 Memory Controller PLL2 PLLM x20 Figure6-7.PLLController All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+ DSPdeviceaspossible.Forthebestperformance,TIrequiresthatallthePLLexternalcomponentsbeon a single side of the board without jumpers, switches, or components other than the ones shown. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For theinputclocktimingrequirements,seeSection6.5.3,PLL2ControllerInputClockElectricalData/Timing. 6.5.1 PLL2 Controller Device-Specific Information As shown in Figure 6-7, the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that, internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1 controller. Note that there is a minimum and maximum operating frequency for PLLREF and PLLOUT. The clock generator must not be configured to exceed any of these constraints. For the PLL clocks input and output frequencyranges,seeTable6-10. Table6-10.PLL2ClockFrequencyRanges CLOCKSIGNAL REQUIREDFREQUENCY UNIT PLLREF(CLKIN2) 20-26.6 MHz PLLOUT(DDR2clock) 400-533(1) MHz (1) Thisclockisthe2xoftheDDRclock.TheDDRPHYdividestheclockdown/2. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.5.2 PLL2 Controller Operating Modes Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates in PLL mode. PLL2 is unlocked only during the power-up sequence (see Section 6.7) and is locked by the timetheRESETSTATpingoeshigh.Itdoesnotloselockduringanyoftheotherresets. 6.5.3 PLL2 Controller Input Clock Electrical Data/Timing Table6-11.TimingRequirementsforCLKIN2(1) (2)(seeFigure6-8) 720,800,900,1100 NO. PLLMODEx20 UNIT MIN MAX 1 t Cycletime,CLKIN2 37.5 50 ns c(CLKIN2) 2 t Pulseduration,CLKIN2high 0.4C ns w(CLKIN2H) 3 t Pulseduration,CLKIN2low 0.4C ns w(CLKIN2L) 4 t Transitiontime,CLKIN2 1.2 ns t(CLKIN2) 5 t Periodjitter,(peak-to-peak)CLKIN2 100 ps J(CLKIN2) (1) Thereferencepointsfortheriseandfalltransitionsaremeasuredat3.3-VV MAXandV MIN. IL IH (2) C=CLKIN2cycletimeinns.Forexample,whenCLKIN2frequencyis25MHz,useC=40ns. 5 1 4 2 CLKIN 3 4 Figure6-8.CLKIN2Timing 6.5.4 PLL2 Controller Register Description(s) AsummaryofthePLL2controllerregistersisshowninTable6-12. Table6-12.PLL2andResetControllerRegistersMemoryMap HEXADDRESSRANGE REGISTERNAME DESCRIPTION 0x02120000 PID PeripheralIdentificationandRevisionInformationRegister 0x02120100 PLLCTL PLLController2OperationsControlRegister 0x02120110 PLLM PLLController2MultiplierControlRegister 0x02120138 PLLCMD PLLController2CommandRegister 0x0212013C PLLSTAT PLLController2StatusRegister(ShowsPLLC1Status) 70 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.6 Enhanced Direct Memory Access (EDMA3) Controller The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, user- programmeddatatransfers,andhostaccesses.Thesearesummarizedasfollows: • Transferto/fromon-chipmemories – DSPL1Dmemory – DSPL2memory • Transferto/fromexternalstorage – DDR2SDRAM – Synchronous/AsynchronousEMIF(EMIFA) • Transferto/fromperipherals/hosts – VLYNQ – HPI – McASP – UART – VideoPort0/1/2/3/4 – Timer0/1/2/3 – SPI – I2C 6.6.1 EDMA3 Channel Synchronization Events The EDMA supports up to 64 EDMA channels that service peripheral devices and external memory. Table 6-13 lists the source of EDMA synchronization events associated with each of the programmable EDMA channels. The association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced DMA (EDMA) ControllerUser'sGuide(literaturenumberSPRUEL2). Table6-13.EDMAChannelSynchronizationEvents TPCC DEFAULT BINARY DEFAULTEVENT TPCC DEFAULT BINARY DEFAULTEVENT CHANNEL EVENT# CHANNEL EVENT# 0 0 0000000 HPI/PCI:DSPINT 32 32 0100000 VP2EVTYA 1 1 0000001 TIMER0:TINT0L 33 33 0100001 VP2EVTCbA 2 2 0000010 TIMER0:TINT0H 34 34 0100010 VP2EVTCrA 3 3 0000011 TIMER2:TINT2L 35 35 0100011 VP2EVTYB 4 4 0000100 TIMER2:TINT2H 36 36 0100100 VP2EVTCbB 5 5 0000101 TIMER3:TINT3L 37 37 0100101 VP2EVTCrB 6 6 0000110 TIMER3:TINT3H 38 38 0100110 VP3EVTYA 7 7 0000111 VICP:IMXINT 39 39 0100111 VP3EVTCbA 8 8 0001000 VICP:VLCDINT 40 40 0101000 VP3EVTCrA 9 9 0001001 VICP:DSQINT 41 41 0101001 VP3EVTYB 10 10 0001010 McASP:AXEVTE 42 42 0101010 VP3EVTCbB 11 11 0001011 McASP:AXEVTO 43 43 0101011 VP3EVTCrB 12 12 0001100 McASP:AXEVT 44 44 0101100 ICREVT 13 13 0001101 McASP:AREVTE 45 45 0101101 ICXEVT 14 14 0001110 McASP:AREVTO 46 46 0101110 SPI:SPIXEVT 15 15 0001111 McASP:AREVT 47 47 0101111 SPI:SPIREVT Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-13.EDMAChannelSynchronizationEvents(continued) TPCC DEFAULT BINARY DEFAULTEVENT TPCC DEFAULT BINARY DEFAULTEVENT CHANNEL EVENT# CHANNEL EVENT# 16 16 0010000 TIMER1:TINT1L 48 48 0110000 VP4EVTYA 17 17 0010001 TIMER1:TINT1H 49 49 0110001 VP4EVTCbA 18 18 0010010 UART:URXEVT 50 50 0110010 VP4EVTCrA 19 19 0010011 UART:UTXEVT 51 51 0110011 VP4EVTYB 20 20 0010100 VP0EVTYA 52 52 0110100 VP4EVTCbB 21 21 0010101 VP0EVTCbA 53 53 0110101 VP4EVTCrB 22 22 0010110 VP0EVTCrA 54 54 0110110 GPIO:GPINT6 23 23 0010111 VP0EVTYB 55 55 0110111 GPIO:GPINT7 24 24 0011000 VP0EVTCbB 56 56 0111000 GPIO:GPINT8 25 25 0011001 VP0EVTCrB 57 57 0111001 GPIO:GPINT9 26 26 0011010 VP1EVTYA 58 58 0111010 GPIO:GPINT10 27 27 0011011 VP1EVTCbA 59 59 0111011 GPIO:GPINT11 28 28 0011100 VP1EVTCrA 60 60 0111100 GPIO:GPINT12 29 29 0011101 VP1EVTYB 61 61 0111101 GPIO:GPINT13 30 30 0011110 VP1EVTCbB 62 62 0111110 GPIO:GPINT14 31 31 0011111 VP1EVTCrB 63 63 0111111 GPIO:GPINT15 6.6.2 EDMA Peripheral Register Description(s) Table6-14liststheEDMAregisters,theircorrespondingacronyms,anddevicememorylocations. Table6-14.EDMAChannelControllerRegisters HEXADDRESS ACRONYM REGISTERNAME 0x02A00000 PID PeripheralIDRegister 0x02A00004 CCCFG EDMA3CCConfigurationRegister 0x02A00008-0x02A000FC Reserved 0x02A00100 DCHMAP0 DMAChannel0MappingRegister 0x02A00104 DCHMAP1 DMAChannel1MappingRegister 0x02A00108 DCHMAP2 DMAChannel2MappingRegister 0x02A0010C DCHMAP3 DMAChannel3MappingRegister 0x02A00110 DCHMAP4 DMAChannel4MappingRegister 0x02A00114 DCHMAP5 DMAChannel5MappingRegister 0x02A00118 DCHMAP6 DMAChannel6MappingRegister 0x02A0011C DCHMAP7 DMAChannel7MappingRegister 0x02A00120 DCHMAP8 DMAChannel8MappingRegister 0x02A00124 DCHMAP9 DMAChannel9MappingRegister 0x02A00128 DCHMAP10 DMAChannel10MappingRegister 0x02A0012C DCHMAP11 DMAChannel11MappingRegister 0x02A00130 DCHMAP12 DMAChannel12MappingRegister 0x02A00134 DCHMAP13 DMAChannel13MappingRegister 0x02A00138 DCHMAP14 DMAChannel14MappingRegister 0x02A0013C DCHMAP15 DMAChannel15MappingRegister 0x02A00140 DCHMAP16 DMAChannel16MappingRegister 0x02A00144 DCHMAP17 DMAChannel17MappingRegister 0x02A00148 DCHMAP18 DMAChannel18MappingRegister 0x02A0014C DCHMAP19 DMAChannel19MappingRegister 0x02A00150 DCHMAP20 DMAChannel20MappingRegister 72 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-14.EDMAChannelControllerRegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x02A00154 DCHMAP21 DMAChannel21MappingRegister 0x02A00158 DCHMAP22 DMAChannel22MappingRegister 0x02A0015C DCHMAP23 DMAChannel23MappingRegister 0x02A00160 DCHMAP24 DMAChannel24MappingRegister 0x02A00164 DCHMAP25 DMAChannel25MappingRegister 0x02A00168 DCHMAP26 DMAChannel26MappingRegister 0x02A0016C DCHMAP27 DMAChannel27MappingRegister 0x02A00170 DCHMAP28 DMAChannel28MappingRegister 0x02A00174 DCHMAP29 DMAChannel29MappingRegister 0x02A00178 DCHMAP30 DMAChannel30MappingRegister 0x02A0017C DCHMAP31 DMAChannel31MappingRegister 0x02A00180 DCHMAP32 DMAChannel32MappingRegister 0x02A00184 DCHMAP33 DMAChannel33MappingRegister 0x02A00188 DCHMAP34 DMAChannel34MappingRegister 0x02A0018C DCHMAP35 DMAChannel35MappingRegister 0x02A00190 DCHMAP36 DMAChannel36MappingRegister 0x02A00194 DCHMAP37 DMAChannel37MappingRegister 0x02A00198 DCHMAP38 DMAChannel38MappingRegister 0x02A0019C DCHMAP39 DMAChannel39MappingRegister 0x02A001A0 DCHMAP40 DMAChannel40MappingRegister 0x02A001A4 DCHMAP41 DMAChannel41MappingRegister 0x02A001A8 DCHMAP42 DMAChannel42MappingRegister 0x02A001AC DCHMAP43 DMAChannel43MappingRegister 0x02A001B0 DCHMAP44 DMAChannel44MappingRegister 0x02A001B4 DCHMAP45 DMAChannel45MappingRegister 0x02A001B8 DCHMAP46 DMAChannel46MappingRegister 0x02A001BC DCHMAP47 DMAChannel47MappingRegister 0x02A001C0 DCHMAP48 DMAChannel48MappingRegister 0x02A001C4 DCHMAP49 DMAChannel49MappingRegister 0x02A001C8 DCHMAP50 DMAChannel50MappingRegister 0x02A001CC DCHMAP51 DMAChannel51MappingRegister 0x02A001D0 DCHMAP52 DMAChannel52MappingRegister 0x02A001D4 DCHMAP53 DMAChannel53MappingRegister 0x02A001D8 DCHMAP54 DMAChannel54MappingRegister 0x02A001DC DCHMAP55 DMAChannel55MappingRegister 0x02A001E0 DCHMAP56 DMAChannel56MappingRegister 0x02A001E4 DCHMAP57 DMAChannel57MappingRegister 0x02A001E8 DCHMAP58 DMAChannel58MappingRegister 0x02A001EC DCHMAP59 DMAChannel59MappingRegister 0x02A001F0 DCHMAP60 DMAChannel60MappingRegister 0x02A001F4 DCHMAP61 DMAChannel61MappingRegister 0x02A001F8 DCHMAP62 DMAChannel62MappingRegister 0x02A001FC DCHMAP63 DMAChannel63MappingRegister 0x02A00200 QCHMAP0 QDMAChannel0MappingtoPaRAMRegister 0x02A00204 QCHMAP1 QDMAChannel1MappingtoPaRAMRegister 0x02A00208 QCHMAP2 QDMAChannel2MappingtoPaRAMRegister 0x02A0020C QCHMAP3 QDMAChannel3MappingtoPaRAMRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-14.EDMAChannelControllerRegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x02A00210 QCHMAP4 QDMAChannel4MappingtoPaRAMRegister 0x02A00214 QCHMAP5 QDMAChannel5MappingtoPaRAMRegister 0x02A00218 QCHMAP6 QDMAChannel6MappingtoPaRAMRegister 0x02A0021C QCHMAP7 QDMAChannel7MappingtoPaRAMRegister 0x02A00220-0x02A0021C - Reserved 0x02A00220-0x02A0023C - Reserved 0x02A00240 DMAQNUM0 DMAQueueNumberRegister0(Channels00to07) 0x02A00244 DMAQNUM1 DMAQueueNumberRegister1(Channels08to15) 0x02A00248 DMAQNUM2 DMAQueueNumberRegister2(Channels16to23) 0x02A0024C DMAQNUM3 DMAQueueNumberRegister3(Channels24to31) 0x02A00250 DMAQNUM4 DMAQueueNumberRegister4(Channels32to39) 0x02A00254 DMAQNUM5 DMAQueueNumberRegister5(Channels40to47) 0x02A00258 DMAQNUM6 DMAQueueNumberRegister6(Channels48to55) 0x02A0025C DMAQNUM7 DMAQueueNumberRegister7(Channels56to63) 0x02A00260 QDMAQNUM CCQDMAQueueNumber 0x02A00264-0x02A00280 - Reserved 0x02A00284 QUEPRI QueuePriorityRegister 0x02A00288-0x02A002FC - Reserved 0x02A00300 EMR EventMissedRegister 0x02A00304 EMRH EventMissedRegisterHigh 0x02A00308 EMCR EventMissedClearRegister 0x02A0030C EMCRH EventMissedClearRegisterHigh 0x02A00310 QEMR QDMAEventMissedRegister 0x02A00314 QEMCR QDMAEventMissedClearRegister 0x02A00318 CCERR EDMA3CCErrorRegister 0x02A0031C CCERRCLR EDMA3CCErrorClearRegister 0x02A00320 EEVAL ErrorEvaluateRegister 0x02A00324-0x02A0033C - Reserved 0x02A00340 DRAE0 DMARegionAccessEnableRegisterforRegion0 0x02A00344 DRAEH0 DMARegionAccessEnableRegisterHighforRegion0 0x02A00348 DRAE1 DMARegionAccessEnableRegisterforRegion1 0x02A0034C DRAEH1 DMARegionAccessEnableRegisterHighforRegion1 0x02A00350 DRAE2 DMARegionAccessEnableRegisterforRegion2 0x02A00354 DRAEH2 DMARegionAccessEnableRegisterHighforRegion2 0x02A00358 DRAE3 DMARegionAccessEnableRegisterforRegion3 0x02A0035C DRAEH3 DMARegionAccessEnableRegisterHighforRegion3 0x02A00360 DRAE4 DMARegionAccessEnableRegisterforRegion4 0x02A00364 DRAEH4 DMARegionAccessEnableRegisterHighforRegion4 0x02A00368 DRAE5 DMARegionAccessEnableRegisterforRegion5 0x02A0036C DRAEH5 DMARegionAccessEnableRegisterHighforRegion5 0x02A00370 DRAE6 DMARegionAccessEnableRegisterforRegion6 0x02A00374 DRAEH6 DMARegionAccessEnableRegisterHighforRegion6 0x02A00378 DRAE7 DMARegionAccessEnableRegisterforRegion7 0x02A0037C DRAEH7 DMARegionAccessEnableRegisterHighforRegion7 0x02A00380 QRAE0 QDMARegionAccessEnableRegisterforRegion0 0x02A00384 QRAE1 QDMARegionAccessEnableRegisterforRegion1 0x02A00388 QRAE2 QDMARegionAccessEnableRegisterforRegion2 74 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-14.EDMAChannelControllerRegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x02A0038C QRAE3 QDMARegionAccessEnableRegisterforRegion3 0x02A00390 QRAE4 QDMARegionAccessEnableRegisterforRegion4 0x02A00394 QRAE5 QDMARegionAccessEnableRegisterforRegion5 0x02A00398 QRAE6 QDMARegionAccessEnableRegisterforRegion6 0x02A0039C QRAE7 QDMARegionAccessEnableRegisterforRegion7 0x02A00400 Q0E0 EventQueue0EntryRegister0 0x02A00404 Q0E1 EventQueue0EntryRegister1 0x02A00408 Q0E2 EventQueue0EntryRegister2 0x02A0040C Q0E3 EventQueue0EntryRegister3 0x02A00410 Q0E4 EventQueue0EntryRegister4 0x02A00414 Q0E5 EventQueue0EntryRegister5 0x02A00418 Q0E6 EventQueue0EntryRegister6 0x02A0041C Q0E7 EventQueue0EntryRegister7 0x02A00420 Q0E8 EventQueue0EntryRegister8 0x02A00424 Q0E9 EventQueue0EntryRegister9 0x02A00428 Q0E10 EventQueue0EntryRegister10 0x02A0042C Q0E11 EventQueue0EntryRegister11 0x02A00430 Q0E12 EventQueue0EntryRegister12 0x02A00434 Q0E13 EventQueue0EntryRegister13 0x02A00438 Q0E14 EventQueue0EntryRegister14 0x02A0043C Q0E15 EventQueue0EntryRegister15 0x02A00440 Q1E0 EventQueue1EntryRegister0 0x02A00444 Q1E1 EventQueue1EntryRegister1 0x02A00448 Q1E2 EventQueue1EntryRegister2 0x02A0044C Q1E3 EventQueue1EntryRegister3 0x02A00450 Q1E4 EventQueue1EntryRegister4 0x02A00454 Q1E5 EventQueue1EntryRegister5 0x02A00458 Q1E6 EventQueue1EntryRegister6 0x02A0045C Q1E7 EventQueue1EntryRegister7 0x02A00460 Q1E8 EventQueue1EntryRegister8 0x02A00464 Q1E9 EventQueue1EntryRegister9 0x02A00468 Q1E10 EventQueue1EntryRegister10 0x02A0046C Q1E11 EventQueue1EntryRegister11 0x02A00470 Q1E12 EventQueue1EntryRegister12 0x02A00474 Q1E13 EventQueue1EntryRegister13 0x02A00478 Q1E14 EventQueue1EntryRegister14 0x02A0047C Q1E15 EventQueue1EntryRegister15 0x02A00480 Q2E0 EventQueue2EntryRegister0 0x02A00484 Q2E1 EventQueue2EntryRegister1 0x02A00488 Q2E2 EventQueue2EntryRegister2 0x02A0048C Q2E3 EventQueue2EntryRegister3 0x02A00490 Q2E4 EventQueue2EntryRegister4 0x02A00494 Q2E5 EventQueue2EntryRegister5 0x02A00498 Q2E6 EventQueue2EntryRegister6 0x02A0049C Q2E7 EventQueue2EntryRegister7 0x02A004A0 Q2E8 EventQueue2EntryRegister8 0x02A004A4 Q2E9 EventQueue2EntryRegister9 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-14.EDMAChannelControllerRegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x02A004A8 Q2E10 EventQueue2EntryRegister10 0x02A004AC Q2E11 EventQueue2EntryRegister11 0x02A004B0 Q2E12 EventQueue2EntryRegister12 0x02A004B4 Q2E13 EventQueue2EntryRegister13 0x02A004B8 Q2E14 EventQueue2EntryRegister14 0x02A004BC Q2E15 EventQueue2EntryRegister15 0x02A004C0 Q3E0 EventQueue3EntryRegister0 0x02A004C4 Q3E1 EventQueue3EntryRegister1 0x02A004C8 Q3E2 EventQueue3EntryRegister2 0x02A004CC Q3E3 EventQueue3EntryRegister3 0x02A004D0 Q3E4 EventQueue3EntryRegister4 0x02A004D4 Q3E5 EventQueue3EntryRegister5 0x02A004D8 Q3E6 EventQueue3EntryRegister6 0x02A004DC Q3E7 EventQueue3EntryRegister7 0x02A004E0 Q3E8 EventQueue3EntryRegister8 0x02A004E4 Q3E9 EventQueue3EntryRegister9 0x02A004E8 Q3E10 EventQueue3EntryRegister10 0x02A004EC Q3E11 EventQueue3EntryRegister11 0x02A004F0 Q3E12 EventQueue3EntryRegister12 0x02A004F4 Q3E13 EventQueue3EntryRegister13 0x02A004F8 Q3E14 EventQueue3EntryRegister14 0x02A004FC Q3E15 EventQueue3EntryRegister15 0x02A00500-0x02A0051C - Reserved 0x02A00520-0x02A005FC - Reserved 0x02A00600 QSTAT0 Queue0StatusRegister 0x02A00604 QSTAT1 Queue1StatusRegister 0x02A00608 QSTAT2 QueueStatusRegister2 0x02A0060C QSTAT3 QueueStatusRegister3 0x02A00610-0x02A0061C - Reserved 0x02A00620 QWMTHRA QueueWatermarkThresholdARegisterforQ[3:0] 0x02A00624 - Reserved 0x02A00640 CCSTAT EDMA3CCStatusRegister 0x02A00644-0x02A006FC - Reserved 0x02A00700-0x02A007FC - Reserved 0x02A00800 MPFAR MemoryProtectionFaultAddressRegister 0x02A00804 MPFSR MemoryProtectionFaultStatusRegister 0x02A00808 MPFCR MemoryProtectionFaultCommandRegister 0x02A0080C MPPA0 MemoryProtectionPageAttributeRegister0 0x02A00810 MPPA1 MemoryProtectionPageAttributeRegister1 0x02A00814 MPPA2 MemoryProtectionPageAttributeRegister2 0x02A00818 MPPA3 MemoryProtectionPageAttributeRegister3 0x02A0081C MPPA4 MemoryProtectionPageAttributeRegister4 0x02A00820 MPPA5 MemoryProtectionPageAttributeRegister5 0x02A00824 MPPA6 MemoryProtectionPageAttributeRegister6 0x02A00828 MPPA7 MemoryProtectionPageAttributeRegister7 0x02A0082C-0x02A00FFC - Reserved 0x02A01000 ER EventRegister 76 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-14.EDMAChannelControllerRegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x02A01004 ERH EventRegisterHigh 0x02A01008 ECR EventClearRegister 0x02A0100C ECRH EventClearRegisterHigh 0x02A01010 ESR EventSetRegister 0x02A01014 ESRH EventSetRegisterHigh 0x02A01018 CER ChainedEventRegister 0x02A0101C CERH ChainedEventRegisterHigh 0x02A01020 EER EventEnableRegister 0x02A01024 EERH EventEnableRegisterHigh 0x02A01028 EECR EventEnableClearRegister 0x02A0102C EECRH EventEnableClearRegisterHigh 0x02A01030 EESR EventEnableSetRegister 0x02A01034 EESRH EventEnableSetRegisterHigh 0x02A01038 SER SecondaryEventRegister 0x02A0103C SERH SecondaryEventRegisterHigh 0x02A01040 SECR SecondaryEventClearRegister 0x02A01044 SECRH SecondaryEventClearRegisterHigh 0x02A01048-0x02A0104C Reserved 0x02A01050 IER InterruptEnableRegister 0x02A01054 IERH InterruptEnableRegisterHigh 0x02A01058 IECR InterruptEnableClearRegister 0x02A0105C IECRH InterruptEnableClearRegisterHigh 0x02A01060 IESR InterruptEnableSetRegister 0x02A01064 IESRH InterruptEnableSetRegisterHigh 0x02A01068 IPR InterruptPendingRegister 0x02A0106C IPRH InterruptPendingRegisterHigh 0x02A01070 ICR InterruptClearRegister 0x02A01074 ICRH InterruptClearRegisterHigh 0x02A01078 IEVAL InterruptEvaluateRegister 0x02A0107C - Reserved 0x02A01080 QER QDMAEventRegister 0x02A01084 QEER QDMAEventEnableRegister 0x02A01088 QEECR QDMAEventEnableClearRegister 0x02A0108C QEESR QDMAEventEnableSetRegister 0x02A01090 QSER QDMASecondaryEventRegister 0x02A01094 QSECR QDMASecondaryEventClearRegister 0x02A01098-0x02A01FFF - Reserved 0x02A02000-0x02A02097 - ShadowRegion0ChannelRegisters 0x02A02098-0x02A021FF - Reserved 0x02A02200-0x02A02297 - ShadowRegion1ChannelRegisters 0x02A02298-0x02A023FF - Reserved 0x02A02400-0x02A02497 - ShadowRegion2ChannelRegisters 0x02A02498-0x02A025FF - Reserved 0x02A02600-0x02A02697 - ShadowRegion3ChannelRegisters 0x02A02698-0x02A027FF - Reserved 0x02A02800-0x02A02897 - ShadowRegion4ChannelRegisters 0x02A02898-0x02A029FF - Reserved Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-14.EDMAChannelControllerRegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x02A02A00-0x02A02A97 - ShadowRegion5ChannelRegisters 0x02A02A98-0x02A02BFF - Reserved 0x02A02C00-0x02A02C97 - ShadowRegion6ChannelRegisters 0x02A02C98-0x02A02DFF - Reserved 0x02A02E00-0x02A02E97 - ShadowRegion7ChannelRegisters 0x02A02E98-0x02A02FFF - Reserved Table 6-15 shows an abbreviation of the set of registers that make up the parameter set for each of 128 EDMA events. Each of the parameter register sets consist of eight 32-bit word entries. Table 6-16 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. Table6-15.EDMAParameterSetRAM HEXADDRESSRANGE DESCRIPTION 0x02A04000-0x02A0401F ParametersSet0(832-bitwords) 0x02A04020-0x02A0403F ParametersSet1(832-bitwords) 0x02A04040-0x02A0405F ParametersSet2(832-bitwords) 0x02A04060-0x02A0407F ParametersSet3(832-bitwords) 0x02A04080-0x02A0409F ParametersSet4(832-bitwords) 0x02A040A0-0x02A040BF ParametersSet5(832-bitwords) ... ... 0x02A04FC0-0x02A04FDF ParametersSet126(832-bitwords) 0x02A04FE0-0x02A04FFF ParametersSet127(832-bitwords) ... ... 0x02A05FC0-0x02A05FDF ParametersSet254(832-bitwords) 0x02A05FE0-0x02A05FFF ParametersSet255(832-bitwords) ... ... 0x02A07FC0-0x02A07FDF ParametersSet510(832-bitwords) 0x02A07FE0-0x02A07FFF ParametersSet511(832-bitwords) Table6-16.ParameterSetEntries HEXOFFSETADDRESS ACRONYM PARAMETERENTRY WITHINTHEPARAMETERSET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT ACount,BCount 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceBIndex,DestinationBIndex 0x0014 LINK_BCNTRLD LinkAddress,BCountReload 0x0018 SRC_DST_CIDX SourceCIndex,DestinationCIndex 0x001C CCNT CCount Table6-17.EDMA3TransferController0Registers HEXADDRESSRANGE ACRONYM REGISTERNAME 02A20000 PID PeripheralIdentificationRegister 02A20004 TCCFG EDMA3TCConfigurationRegister 02A20008-02A200FC - Reserved 78 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-17.EDMA3TransferController0Registers(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 02A20100 TCSTAT EDMA3TCChannelStatusRegister 02A20104-02A2011C - Reserved 02A20120 ERRSTAT ErrorRegister 02A20124 ERREN ErrorEnableRegister 02A20128 ERRCLR ErrorClearRegister 02A2012C ERRDET ErrorDetailsRegister 02A20130 ERRCMD ErrorInterruptCommandRegister 02A20134-02A2013C - Reserved 02A20140 RDRATE ReadRateRegister 02A20144-02A2023C - Reserved 02A20240 SAOPT SourceActiveOptionsRegister 02A20244 SASRC SourceActiveSourceAddressRegister 02A20248 SACNT SourceActiveCountRegister 02A2024C SADST SourceActiveDestinationAddressRegister 02A20250 SABIDX SourceActiveSourceB-IndexRegister 02A20254 SAMPPRXY SourceActiveMemoryProtectionProxyRegister 02A20258 SACNTRLD SourceActiveCountReloadRegister 02A2025C SASRCBREF SourceActiveSourceAddressB-ReferenceRegister 02A20260 SADSTBREF SourceActiveDestinationAddressB-ReferenceRegister 02A20264-02A2027C - Reserved 02A20280 DFCNTRLD DestinationFIFOSetCountReload 02A20284 DFSRCBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A20288 DFDSTBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A2028C-02A202FC - Reserved 02A20300 DFOPT0 DestinationFIFOOptionsRegister0 02A20304 DFSRC0 DestinationFIFOSourceAddressRegister0 02A20308 DFCNT0 DestinationFIFOCountRegister0 02A2030C DFDST0 DestinationFIFODestinationAddressRegister0 02A20310 DFBIDX0 DestinationFIFOBIDXRegister0 02A20314 DFMPPRXY0 DestinationFIFOMemoryProtectionProxyRegister0 02A20318-02A2033C - Reserved 02A20340 DFOPT1 DestinationFIFOOptionsRegister1 02A20344 DFSRC1 DestinationFIFOSourceAddressRegister1 02A20348 DFCNT1 DestinationFIFOCountRegister1 02A2034C DFDST1 DestinationFIFODestinationAddressRegister1 02A20350 DFBIDX1 DestinationFIFOBIDXRegister1 02A20354 DFMPPRXY1 DestinationFIFOMemoryProtectionProxyRegister1 02A20358-02A2037C - Reserved 02A20380 DFOPT2 DestinationFIFOOptionsRegister2 02A20384 DFSRC2 DestinationFIFOSourceAddressRegister2 02A20388 DFCNT2 DestinationFIFOCountRegister2 02A2038C DFDST2 DestinationFIFODestinationAddressRegister2 02A20390 DFBIDX2 DestinationFIFOBIDXRegister2 02A20394 DFMPPRXY2 DestinationFIFOMemoryProtectionProxyRegister2 02A20398-02A203BC - Reserved 02A203C0 DFOPT3 DestinationFIFOOptionsRegister3 02A203C4 DFSRC3 DestinationFIFOSourceAddressRegister3 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-17.EDMA3TransferController0Registers(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 02A203C8 DFCNT3 DestinationFIFOCountRegister3 02A203CC DFDST3 DestinationFIFODestinationAddressRegister3 02A203D0 DFBIDX3 DestinationFIFOBIDXRegister3 02A203D4 DFMPPRXY3 DestinationFIFOMemoryProtectionProxyRegister3 02A203D8-02A27FFF - Reserved Table6-18.EDMA3TransferController1Registers HEXADDRESSRANGE ACRONYM REGISTERNAME 02A28000 PID PeripheralIdentificationRegister 02A28004 TCCFG EDMA3TCConfigurationRegister 02A28008-02A280FC - Reserved 02A28100 TCSTAT EDMA3TCChannelStatusRegister 02A28104-02A2811C - Reserved 02A28120 ERRSTAT ErrorRegister 02A28124 ERREN ErrorEnableRegister 02A28128 ERRCLR ErrorClearRegister 02A2812C ERRDET ErrorDetailsRegister 02A28130 ERRCMD ErrorInterruptCommandRegister 02A28134-02A2813C - Reserved 02A28140 RDRATE ReadRateRegister 02A28144-02A2823C - Reserved 02A28240 SAOPT SourceActiveOptionsRegister 02A28244 SASRC SourceActiveSourceAddressRegister 02A28248 SACNT SourceActiveCountRegister 02A2824C SADST SourceActiveDestinationAddressRegister 02A28250 SABIDX SourceActiveSourceB-IndexRegister 02A28254 SAMPPRXY SourceActiveMemoryProtectionProxyRegister 02A28258 SACNTRLD SourceActiveCountReloadRegister 02A2825C SASRCBREF SourceActiveSourceAddressB-ReferenceRegister 02A28260 SADSTBREF SourceActiveDestinationAddressB-ReferenceRegister 02A28264-02A2827C - Reserved 02A28280 DFCNTRLD DestinationFIFOSetCountReload 02A28284 DFSRCBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A28288 DFDSTBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A2828C-02A282FC - Reserved 02A28300 DFOPT0 DestinationFIFOOptionsRegister0 02A28304 DFSRC0 DestinationFIFOSourceAddressRegister0 02A28308 DFCNT0 DestinationFIFOCountRegister0 02A2830C DFDST0 DestinationFIFODestinationAddressRegister0 02A28310 DFBIDX0 DestinationFIFOBIDXRegister0 02A28314 DFMPPRXY0 DestinationFIFOMemoryProtectionProxyRegister0 02A28318-02A2833C - Reserved 02A28340 DFOPT1 DestinationFIFOOptionsRegister1 02A28344 DFSRC1 DestinationFIFOSourceAddressRegister1 02A28348 DFCNT1 DestinationFIFOCountRegister1 02A2834C DFDST1 DestinationFIFODestinationAddressRegister1 02A28350 DFBIDX1 DestinationFIFOBIDXRegister1 80 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-18.EDMA3TransferController1Registers(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 02A28354 DFMPPRXY1 DestinationFIFOMemoryProtectionProxyRegister1 02A28358-02A2837C - Reserved 02A28380 DFOPT2 DestinationFIFOOptionsRegister2 02A28384 DFSRC2 DestinationFIFOSourceAddressRegister2 02A28388 DFCNT2 DestinationFIFOCountRegister2 02A2838C DFDST2 DestinationFIFODestinationAddressRegister2 02A28390 DFBIDX2 DestinationFIFOBIDXRegister2 02A28394 DFMPPRXY2 DestinationFIFOMemoryProtectionProxyRegister2 02A28398-02A283BC - Reserved 02A283C0 DFOPT3 DestinationFIFOOptionsRegister3 02A283C4 DFSRC3 DestinationFIFOSourceAddressRegister3 02A283C8 DFCNT3 DestinationFIFOCountRegister3 02A283CC DFDST3 DestinationFIFODestinationAddressRegister3 02A283D0 DFBIDX3 DestinationFIFOBIDXRegister3 02A283D4 DFMPPRXY3 DestinationFIFOMemoryProtectionProxyRegister3 02A283D8-02A2FFFF - Reserved Table6-19.EDMA3TransferController2Registers HEXADDRESSRANGE ACRONYM REGISTERNAME 02A30000 PID PeripheralIdentificationRegister 02A30004 TCCFG EDMA3TCConfigurationRegister 02A30008-02A300FC - Reserved 02A30100 TCSTAT EDMA3TCChannelStatusRegister 02A30104-02A3011C - Reserved 02A30120 ERRSTAT ErrorRegister 02A30124 ERREN ErrorEnableRegister 02A30128 ERRCLR ErrorClearRegister 02A3012C ERRDET ErrorDetailsRegister 02A30130 ERRCMD ErrorInterruptCommandRegister 02A30134-02A3013C - Reserved 02A30140 RDRATE ReadRateRegister 02A30144-02A3023C - Reserved 02A30240 SAOPT SourceActiveOptionsRegister 02A30244 SASRC SourceActiveSourceAddressRegister 02A30248 SACNT SourceActiveCountRegister 02A3024C SADST SourceActiveDestinationAddressRegister 02A30250 SABIDX SourceActiveSourceB-IndexRegister 02A30254 SAMPPRXY SourceActiveMemoryProtectionProxyRegister 02A30258 SACNTRLD SourceActiveCountReloadRegister 02A3025C SASRCBREF SourceActiveSourceAddressB-ReferenceRegister 02A30260 SADSTBREF SourceActiveDestinationAddressB-ReferenceRegister 02A30264-02A3027C - Reserved 02A30280 DFCNTRLD DestinationFIFOSetCountReload 02A30284 DFSRCBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A30288 DFDSTBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A3028C-02A302FC - Reserved 02A30300 DFOPT0 DestinationFIFOOptionsRegister0 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-19.EDMA3TransferController2Registers(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 02A30304 DFSRC0 DestinationFIFOSourceAddressRegister0 02A30308 DFCNT0 DestinationFIFOCountRegister0 02A3030C DFDST0 DestinationFIFODestinationAddressRegister0 02A30310 DFBIDX0 DestinationFIFOBIDXRegister0 02A30314 DFMPPRXY0 DestinationFIFOMemoryProtectionProxyRegister0 02A30318-02A3033C - Reserved 02A30340 DFOPT1 DestinationFIFOOptionsRegister1 02A30344 DFSRC1 DestinationFIFOSourceAddressRegister1 02A30348 DFCNT1 DestinationFIFOCountRegister1 02A3034C DFDST1 DestinationFIFODestinationAddressRegister1 02A30350 DFBIDX1 DestinationFIFOBIDXRegister1 02A30354 DFMPPRXY1 DestinationFIFOMemoryProtectionProxyRegister1 02A30358-02A3037C - Reserved 02A30380 DFOPT2 DestinationFIFOOptionsRegister2 02A30384 DFSRC2 DestinationFIFOSourceAddressRegister2 02A30388 DFCNT2 DestinationFIFOCountRegister2 02A3038C DFDST2 DestinationFIFODestinationAddressRegister2 02A30390 DFBIDX2 DestinationFIFOBIDXRegister2 02A30394 DFMPPRXY2 DestinationFIFOMemoryProtectionProxyRegister2 02A30398-02A303BC - Reserved 02A303C0 DFOPT3 DestinationFIFOOptionsRegister3 02A303C4 DFSRC3 DestinationFIFOSourceAddressRegister3 02A303C8 DFCNT3 DestinationFIFOCountRegister3 02A303CC DFDST3 DestinationFIFODestinationAddressRegister3 02A303D0 DFBIDX3 DestinationFIFOBIDXRegister3 02A303D4 DFMPPRXY3 DestinationFIFOMemoryProtectionProxyRegister3 02A303D8-02A37FFF - Reserved Table6-20.EDMA3TransferController3Registers HEXADDRESSRANGE ACRONYM REGISTERNAME 02A38000 PID PeripheralIdentificationRegister 02A38004 TCCFG EDMA3TCConfigurationRegister 02A38008-02A380FC - Reserved 02A38100 TCSTAT EDMA3TCChannelStatusRegister 02A38104-02A3811C - Reserved 02A38120 ERRSTAT ErrorRegister 02A38124 ERREN ErrorEnableRegister 02A38128 ERRCLR ErrorClearRegister 02A3812C ERRDET ErrorDetailsRegister 02A38130 ERRCMD ErrorInterruptCommandRegister 02A38134-02A3813C - Reserved 02A38140 RDRATE ReadRateRegister 02A38144-02A3823C - Reserved 02A38240 SAOPT SourceActiveOptionsRegister 02A38244 SASRC SourceActiveSourceAddressRegister 02A38248 SACNT SourceActiveCountRegister 02A3824C SADST SourceActiveDestinationAddressRegister 82 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-20.EDMA3TransferController3Registers(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 02A38250 SABIDX SourceActiveSourceB-IndexRegister 02A38254 SAMPPRXY SourceActiveMemoryProtectionProxyRegister 02A38258 SACNTRLD SourceActiveCountReloadRegister 02A3825C SASRCBREF SourceActiveSourceAddressB-ReferenceRegister 02A38260 SADSTBREF SourceActiveDestinationAddressB-ReferenceRegister 02A38264-02A3827C - Reserved 02A38280 DFCNTRLD DestinationFIFOSetCountReload 02A38284 DFSRCBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A38288 DFDSTBREF DestinationFIFOSetDestinationAddressBReferenceRegister 02A3828C-02A382FC - Reserved 02A38300 DFOPT0 DestinationFIFOOptionsRegister0 02A38304 DFSRC0 DestinationFIFOSourceAddressRegister0 02A38308 DFCNT0 DestinationFIFOCountRegister0 02A3830C DFDST0 DestinationFIFODestinationAddressRegister0 02A38310 DFBIDX0 DestinationFIFOBIDXRegister0 02A38314 DFMPPRXY0 DestinationFIFOMemoryProtectionProxyRegister0 02A38318-02A3833C - Reserved 02A38340 DFOPT1 DestinationFIFOOptionsRegister1 02A38344 DFSRC1 DestinationFIFOSourceAddressRegister1 02A38348 DFCNT1 DestinationFIFOCountRegister1 02A3834C DFDST1 DestinationFIFODestinationAddressRegister1 02A38350 DFBIDX1 DestinationFIFOBIDXRegister1 02A38354 DFMPPRXY1 DestinationFIFOMemoryProtectionProxyRegister1 02A38358-02A3837C - Reserved 02A38380 DFOPT2 DestinationFIFOOptionsRegister2 02A38384 DFSRC2 DestinationFIFOSourceAddressRegister2 02A38388 DFCNT2 DestinationFIFOCountRegister2 02A3838C DFDST2 DestinationFIFODestinationAddressRegister2 02A38390 DFBIDX2 DestinationFIFOBIDXRegister2 02A38394 DFMPPRXY2 DestinationFIFOMemoryProtectionProxyRegister2 02A38398-02A383BC - Reserved 02A383C0 DFOPT3 DestinationFIFOOptionsRegister3 02A383C4 DFSRC3 DestinationFIFOSourceAddressRegister3 02A383C8 DFCNT3 DestinationFIFOCountRegister3 02A383CC DFDST3 DestinationFIFODestinationAddressRegister3 02A383D0 DFBIDX3 DestinationFIFOBIDXRegister3 02A383D4 DFMPPRXY3 DestinationFIFOMemoryProtectionProxyRegister3 02A383D8-02A3FFFF - Reserved Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.7 Reset Controller The reset controller detects the different types of resets supported on the device and manages the distributionofthoseresetsthroughoutthedevice. The device has several types of resets: power-on reset, warm reset, max reset and system reset. Table 6- 21 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. See Section6.7.9formoreinformationontheeffectsofeachresetonthePLLcontrollersandtheirclocks. Table6-21.Device-LevelResetTypes TYPE INITIATOR EFFECT(s) Power-onReset PORpin Resetstheentirechipincludingthetestandemulationlogic Resetseverythingexceptforthetestandemulationlogicandthe WarmReset RESETpin EthernetSubsystem MaxReset Emulator Sameasawarmreset Asystemresetmaintainsmemorycontentsanddoesnotresetthe testandemulationcircuitandtheEthernetSubsystem.Thedevice SystemReset PCIviathePRSTpin configurationpinsarealsonotre-latchedandsystemresetdoesnot affectthestateoftheperipherals(enable/disable). In addition to device-level global resets, the PSC provides the capability to cause local resets to peripheralsand/ortheCPU. 6.7.1 Power-on Reset (POR Pin) Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test and emulation logic. Power-on reset is also referred to as a cold reset since the device usually goes through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplieshavereachedtheirnormaloperatingconditions.Notethatadevicepower-upcycleisnotrequired toinitiateapower-onreset. Thefollowingsequencemustbefollowedduringapower-onreset: 1. WaitforallpowersuppliestoreachnormaloperatingconditionswhilekeepingthePORpinasserted (drivenlow).WhilePORisasserted,allpinswillbeinhigh-impedancemode.AfterthePORpinis deasserted(drivenhigh),allZ-grouppins,low-grouppins,andhigh-grouppinsaresettotheirreset stateandwillremainattheirresetstateuntilconfiguredbytheirrespectiveperipheral.Theclockand resetofeachperipheralisdeterminedbythedefaultsettingsofthepowerandsleepcontroller(PSC). 2. Onceallthepowersuppliesarewithinvalidoperatingconditions,thePORpinmustremainasserted (low)foraminimumnumberof256CLKIN2cycles.ThePLL1controllerinputclock,CLKIN1,andthe PCIinputclock,PCLK,mustbevalidduringthistime.PCLKisneededonlyifthePCImoduleisbeing used.IftheDDR2memorycontrollerandtheEthernetSubsystemarenotneeded,CLKIN2canbetied lowandREFCLKP/REFCLKNcanbeconnectedtoV andCV respectively.Inthiscase,thePOR SS DD pinmustremainasserted(low)foraminimumof256CLKIN1cyclesafterallpowersupplieshave reachedvalidoperatingconditions.WithinthelowperiodofthePORpin,thefollowingoccurs: (a) Theresetsignalsflowtotheentirechip(includingthetestandemulationlogic),resettingmodules thatuseresetasynchronously. (b) ThePLL1controllerclocksarestartedatthefrequencyofthesystemreferenceclock.Theclocks arepropagatedthroughoutthechiptoresetmodulesthatuseresetsynchronously.Bydefault, PLL1isinresetandunlocked. (c) ThePLL2controllerclocksarestartedatthefrequencyofthesystemreferenceclock.PLL2isheld inreset.SincethePLL2controlleralwaysoperatesinPLLmode,thesystemreferenceclockand allthesystemclocksareinvalidatthispoint. (d) TheRESETSTATpinstaysasserted(low),indicatingthedeviceisinreset. 3. ThePORpinmaynowbedeasserted(drivenhigh).WhenthePORpinisdeasserted,the configurationpinvaluesarelatched,andthePLLcontrollerschangetheirsystemclockstotheirdefault divide-downvalues.PLL2istakenoutofresetandautomaticallystartsitslockingsequence.Other 84 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 deviceinitializationisalsostarted. 4. Afterdeviceinitializationiscomplete,theRESETSTATpinisdeasserted(drivenhigh).Bythistime, PLL2hasalreadycompleteditslockingsequenceandisoutputtingavalidclock.Thesystemclocksof bothPLLcontrollersareallowedtofinishtheircurrentcyclesandthenpausedfor10cyclesoftheir respectivesystemreferenceclocks.Afterthepause,thesystemclocksarerestartedattheirdefault divide-bysettings. Thedeviceisnowoutofreset;deviceexecutionbeginsasdictatedbytheselectedbootmode. 6.7.2 Warm Reset (RESET Pin) A warm reset has the same effect as a power-on reset, except that in this case, the test and emulation logicarenotreset. Thefollowingsequencemustbefollowedduringawarmreset: 1. HoldtheRESETpinlowforaminimumof24CLKIN1cycles.WithinthelowperiodoftheRESETpin, thefollowingoccurs: (a) TheZ-grouppins,low-grouppins,andthehigh-grouppinsaresettotheirresetstate (b) Theresetsignalsflowtotheentirechip(excludingthetestandemulationlogic),resettingmodules thatuseresetasynchronously (c) ThePLLControllersarereset.PLL1switchesbacktoPLLbypassmode,resettingalltheir registerstodefaultvalues.BothPLL1andPLL2areplacedinresetandloselock.ThePLL1 controllerclocksstartrunningatthefrequencyofthesystemreferenceclock.Theclocksare propagatedthroughoutthechiptoresetmodulesthatuseresetsynchronously. (d) TheRESETSTATpinbecomesactive(low),indicatingthedeviceisinreset. 2. TheRESETpinmaynowbereleased(driveninactivehigh).WhentheRESETpinisreleased,the configurationpinvaluesarelatchedandthePLLcontrollersimmediatelychangetheirsystemclocksto theirdefaultdivide-downvalues.Otherdeviceinitializationisalsostarted. After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks.Afterthepausethesystemclocksarerestartedattheirdefaultdivide-bysettings. TheclockandresetofeachperipheralisdeterminedbythedefaultsettingsofthePSC. Thedeviceisnowoutofreset,deviceexecutionbeginsasdictatedbytheselectedbootmode. 6.7.3 Maximum Reset A maximum (max) reset is initiated by the emulator. The effects are the same as a warm reset, except the device boot and configuration pins are not re-latched. The emulator initiates a maximum reset via the ICEPICKmodule.ThisICEPICKinitiatedresetisnonmaskable. Themaxresetsequenceisasfollows: 1. Maxresetisinitiatedbytheemulator.Duringthistime,thefollowinghappens: (a) Theresetsignalsflowtotheentirechip,resettingallthemodulesonchipexceptthetestand emulationlogic. (b) ThePLLcontrollersarereset,PLL1switchesbacktoPLLbypassmode,resettingalltheirregisters todefaultvalues.BothPLL1andPLL2areplacedinresetandloselock. (c) TheRESETSTATpinbecomesasserted(low),indicatingthedeviceisinreset. 2. Afterdeviceinitializationiscomplete,thePLLControllerspausethesystemclocksfor10cycles.Atthe endofthese10cycles,theRESETSTATpinisdeasserted(drivenhigh).Atthispoint,thefollowing occurs: (a) TheI/Opinsarecontrolledbythedefaultperipherals(defaultperipheralsaredeterminedby PINMUXregister). (b) Theclockandresetofeachperipheralisdeterminedbythedefaultsettingsofthepowerandsleep controller(PSC). Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com (c) TheC64x+beginsexecutingfromDSPBOOTADDR(determinedbybootmodeselection). Aftertheresetsequence,thebootsequencebegins.Sincethebootandconfigurationpinsarenot latchedwithamaxreset,thepreviousvalues(asshownintheBOOTCFGregister)areusedto selectthebootmode.Formoredetailsonthebootsequence,seetheUsingthe TMS320DM647/DM648BootloaderApplicationReport(literaturenumberSPRAAJ1).Aftertheboot sequence,followthesoftwareinitializationsequence. 6.7.4 System Reset A system reset maintains memory contents and does not reset the clock logic or the test and emulation circuitry. The device configuration pins are also not re-latched and the state of the peripherals (enabled/disabled)isalsonotaffected.AsystemresetisinitiatedbythePRSTpinofPCIperipheral. Duringasystemreset,thefollowinghappens: 1. TheRESETSTATpingoeslowtoindicateaninternalresetisbeinggenerated.Theresetisallowedto propagatethroughthesystem.Internalsystemclocksarenotaffected. 2. Aftertheinternalresetsignalhaspropagated,thePLLcontrollerspauseandrestarttheirsystem clocksforabout10cyclesoftheirsystemreferenceclocks,butretaintheirconfiguration.ThePLLs alsoremainlocked. 3. Thebootsequenceisstartedafterthesystemclocksarerestarted.Sincetheconfigurationpins (includingtheBOOTMODE[3:0]pins)arenotlatchedwithasystemreset,thepreviousvalues,as shownintheBOOTCFGregister,areusedtoselectthebootmode. 6.7.5 Peripheral Local Reset The user can configure the local reset and clock state of a peripheral through programming the PSC. Table 6-2 identifies the LPSC numbers and the peripherals capable of being locally reset by the PSC. For more detailed information on the programming of these peripherals by the PSC, see the TMS320DM647/TMS320DM648DSPSubsystemReferenceGuide(literaturenumberSPRUEU6). 6.7.6 Reset Priority If any of the above reset sources occur simultaneously, the PLLCTRL processes only the highest priority resetrequest.Theresetrequestprioritiesareasfollows(hightolow): • Power-onReset • MaximumReset • WarmReset • SystemReset 86 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.7.7 Reset Controller Register Theresettypestatus(RSTYPE)registeristheonlyregisterfortheresetcontroller. The RSTYPE register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The reset type status register is shown in Figure 6-9 anddescribedinTable6-22. Figure6-9.ResetTypeStatusRegister(RSTYPE) 31 16 Reserved R-0 15 4 3 2 1 0 Reserved SRST MRST WRST POR R-0 R-0 R-0 R-0 R-0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Table6-22.ResetTypeStatusRegister(RSTYPE)FieldDescriptions Bit Field Value Description 31:4 Reserved Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect. 3 SRST Systemreset 0 SystemResetwasnotthelastresettooccur. 1 SystemResetwasthelastresettooccur. 2 MRST Maxreset 0 MaxResetwasnotthelastresettooccur. 1 MaxResetwasthelastresettooccur. 1 WRST Warmreset 0 WarmResetwasnotthelastresettooccur. 1 WarmResetwasthelastresettooccur. 0 POR Power-onreset 0 Power-onResetwasnotthelastresettooccur. 1 Power-onResetwasthelastresettooccur. 6.7.8 Pin Behaviors at Reset During normal operation, devices pins are controlled by the selected peripheral. During device level global reset,thepinbehaviorsareclassifiedintothefollowingResetGroups: • Z Group: These pins are 3-stated when a device-level global reset source (e.g., POR,RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins remain 3-stated until configured otherwisebytheirrespectiveperipheral(aftertheperipheralisenabledbythePSC). • Z/High Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET, orMaxReset)isasserted.Whentheresetsourceisde-asserted,thesepinsdrivealogicHigh. • Z/Low Group: These pins are 3-stated when a device-level global reset source (e.g. POR, RESET, or MaxReset)isasserted.Whentheresetsourceisde-asserted,thesepinsdrivealogicLow. • DDR2 Z/High Group: These pins are 3-stated when a device-level global reset source (e.g. POR, RESET,orMaxReset)isasserted.Whentheresetsourceisde-asserted,thesepinsareDrivenHigh. • DDR2 Low/High Group: These pins are driven Low when a device-level global reset source (e.g. POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven High. • DDR2 High/Low Group: These pins are driven High when a device-level global reset source (e.g. POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven Low. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com • Clock Group: These clock pins are toggling by default. They pause momentarily before RESETSTAT isde-asserted(high). Table6-23liststheResetGroupforeachpin. Table6-23.PinBehaviorsatReset PinName ResetGroup CLKIN1 ZGroup CLKIN2 ZGroup REFCLKN ZGroup REFCLKP ZGroup SYSCLK5 ZGroup TCLK ZGroup TDI ZGroup TDO ZGroup TMS ZGroup TRST ZGroup EMU0 ZGroup EMU1 ZGroup EMU2 ZGroup EMU3 ZGroup EMU4 ZGroup EMU5 ZGroup EMU6 ZGroup EMU7 ZGroup EMU8 ZGroup EMU9 ZGroup EMU10 ZGroup EMU11 ZGroup NMI ZGroup RESET ZGroup POR ZGroup AD00/HD00 ZGroup AD01/HD01 ZGroup AD02/HD02 ZGroup AD03/HD03 ZGroup AD04/HD04 ZGroup AD05/HD05 ZGroup AD06/HD06 ZGroup AD07/HD07 ZGroup AD08/HD08 ZGroup AD09/HD09 ZGroup AD10/HA10 ZGroup AD11/HD11 ZGroup AD12/HD12 ZGroup AD13/HD13 ZGroup AD14/HD14 ZGroup AD15/HD15 ZGroup AD16/HD16 ZGroup AD17/HD17 ZGroup 88 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-23.PinBehaviorsatReset(continued) PinName ResetGroup AD18/HS18 ZGroup AD19/HD19 ZGroup AD20/HD20 ZGroup AD21/HD21 ZGroup AD22/HD22 ZGroup AD23/HD23 ZGroup AD24/HD24 ZGroup AD25/HS25 ZGroup AD26/HD26 ZGroup AD27/AD27 ZGroup AD28/HD28 ZGroup AD29/HD29 ZGroup AD30/HD30 ZGroup AD31/HD31 ZGroup PPAR/HAS ZGroup PSTOP/HCNTL0 ZGroup PDEVSEL/HCNTL1 ZGroup PPERR/HCS ZGroup PSERR/HDS1 ZGroup PCBE0/GP04 ZGroup PCBE2/HR/W ZGroup PCBE3/GP07 ZGroup PCLK/HHWIL ZGroup PGNT/GPO0 ZGroup PRST/GPO1 ZGroup PINTA/GPO2 ZGroup PREQ/GPO3 ZGroup PTRDY/GPO5 ZGroup PIDSEL/GPO6 ZGroup DEVICEENABLE0/AEA20 ZGroup EMIBWIDTH/AEA22 ZGroup FASTBOOT/AEA21 ZGroup UHPIEN ZGroup HPIWIDTH/AEA16 ZGroup RSV_BOOT/AEA15 ZGroup PCI66/AEA18 ZGroup BOOTMODE0/AEA11 ZGroup BOOTMODE1/AEA12 ZGroup BOOTMODE2/AEA13 ZGroup BOOTMODE3/AEA14 ZGroup SCL ZGroup SDA ZGroup SGMII0RXN ZGroup SGMII0RXP ZGroup SGMII1RXN ZGroup SGMII1RXP ZGroup SGMII0TXN ZGroup Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-23.PinBehaviorsatReset(continued) PinName ResetGroup SGMII0TXP ZGroup SGMII1TXN ZGroup SGMII1TXP ZGroup MDIO ZGroup SPICLK ZGroup SPICS1/UARTTX ZGroup SPICS2/UARTRX ZGroup SPIDI/UARTRTS ZGroup SPIDO/UARTCTS ZGroup T0INP12/GP08 ZGroup T0OUT12/GP09 ZGroup T1INPL/GP10 ZGroup T1OUT12/GP11 ZGroup AHCLKR ZGroup ALHCLKX ZGroup ACLKR ZGroup ACLKX ZGroup AFSR ZGroup AFSX ZGroup AXR0 ZGroup AXR1 ZGroup AXR2 ZGroup AXR3 ZGroup AXR4 ZGroup AXR5 ZGroup AXR6 ZGroup AXR7 ZGroup STCLK/AXR8 ZGroup VDAC/AXR9 ZGroup AMUTEIN ZGroup AMUTE ZGroup VP0CLK0 ZGroup VP0CLK1 ZGroup VP0CTL0 ZGroup VP0CTL1 ZGroup VP0CTL2 ZGroup VP0D02 ZGroup VP0D03 ZGroup VP0D04 ZGroup VP0D05 ZGroup VP0D06 ZGroup VP0D07 ZGroup VP0D08 ZGroup VP0D09 ZGroup VP0D12/GP12 ZGroup VP0D13/GP13 ZGroup VP0D14/GP14 ZGroup 90 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-23.PinBehaviorsatReset(continued) PinName ResetGroup VP0D15/GP15 ZGroup VP0D16 ZGroup VP0D17 ZGroup VP0D18 ZGroup VP0D19 ZGroup VP1CLK0 ZGroup VP1CLK1 ZGroup VP1CTL0 ZGroup VP1CTL1 ZGroup VP1CTL2 ZGroup VP1D02/GP16 ZGroup VP1D03/GP17 ZGroup VP1D04/GP18 ZGroup VP1D05/GP19 ZGroup VP1D06/GP20 ZGroup VP1D07/GP21 ZGroup VP1D08/GP22 ZGroup VP1D09/GP23 ZGroup VP1D12/GP24 ZGroup VP1D13/GP25 ZGroup VP1D14/GP26 ZGroup VP1D15/GP27 ZGroup VP1D16/GP28 ZGroup VP1D17/GP29 ZGroup VP1D18/GP30 ZGroup VP1D19/GP31 ZGroup VP2CLK0 ZGroup VP2CLK1/VCLK ZGroup VP2CTL0 ZGroup VP2CTL1 ZGroup VP2CTL2/SCRUN ZGroup VP2D02 ZGroup VP2D03 ZGroup VP2D04 ZGroup VP2D05 ZGroup VP2D06 ZGroup VP2D07 ZGroup VP2D08 ZGroup VP2D09 ZGroup VP2D12/VRXD0 ZGroup VP2D13/VRXD1 ZGroup VP2D14/VRXD2 ZGroup VP2D15/VRXD3 ZGroup VP3CLK1/AECLKOUT ZGroup VP3CTL0/AAWE/ASWE ZGroup VP3CTL1/AR/W ZGroup VP3CTL2/AAOE/ASOE ZGroup Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-23.PinBehaviorsatReset(continued) PinName ResetGroup VP3D02/AED00 ZGroup VP3D03/AED01 ZGroup VP3D04/AED02 ZGroup VP3D05/AED03 ZGroup VP3D06/AED04 ZGroup VP3D07/AED05 ZGroup VP3D08/AED06 ZGroup VP3D09/AED07 ZGroup VP3D12/AED08 ZGroup VP3D13/AED09 ZGroup VP3D14/AED10 ZGroup VP3D15/AED11 ZGroup VP3D16/AED12 ZGroup VP3D17/AED13 ZGroup VP3D18/AED14 ZGroup VP3D19/AED15 ZGroup VP4CLK1 ZGroup VP4CTL0/ABA0 ZGroup VP4CTL1/ABA1 ZGroup VP4CTL2/ASADS/ASRE ZGroup VP4D02/ABE00 ZGroup VP4D03/ABE01 ZGroup VP4D04/AEA10 ZGroup VP4D05 ZGroup VP4D06/ACE2 ZGroup VP4D07/ACE3 ZGroup VP4D08/AEA00 ZGroup VP4D09/AEA01 ZGroup VP4D12/AEA02 ZGroup VP4D13/AEA03 ZGroup VP4D14/AEA04 ZGroup VP4D15/AEA05 ZGroup VP4D16/AEA06 ZGroup VP4D17/AEA07 ZGroup VP4D18/AEA08 ZGroup VP4D19/AEA09 ZGroup AEA23 ZGroup AEA19 ZGroup AEA17 ZGroup MDCLK Z/HighGroup VP4CLK0/AARDY Z/HighGroup PFRAME/HINT Z/HighGroup PIRDY/HRDY Z/LowGroup VP2D16/VTXD0 Z/LowGroup VP2D17/VTXD1 Z/LowGroup VP2D18/VTXD2 Z/LowGroup VP2D19/VTXD3 Z/LowGroup 92 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-23.PinBehaviorsatReset(continued) PinName ResetGroup DDR_D00 DDR2ZGroup DDR_D01 DDR2ZGroup DDR_D02 DDR2ZGroup DDR_D03 DDR2ZGroup DDR_D04 DDR2ZGroup DDR_D05 DDR2ZGroup DDR_D06 DDR2ZGroup DDR_D07 DDR2ZGroup DDR_D08 DDR2ZGroup DDR_D09 DDR2ZGroup DDR_D10 DDR2ZGroup DDR_D11 DDR2ZGroup DDR_D12 DDR2ZGroup DDR_D13 DDR2ZGroup DDR_D14 DDR2ZGroup DDR_D15 DDR2ZGroup DDR_D16 DDR2ZGroup DDR_D17 DDR2ZGroup DDR_D18 DDR2ZGroup DDR_D19 DDR2ZGroup DDR_D20 DDR2ZGroup DDR_D21 DDR2ZGroup DDR_D22 DDR2ZGroup DDR_D23 DDR2ZGroup DDR_D24 DDR2ZGroup DDR_D25 DDR2ZGroup DDR_D26 DDR2ZGroup DDR_D27 DDR2ZGroup DDR_D28 DDR2ZGroup DDR_D29 DDR2ZGroup DDR_D30 DDR2ZGroup DDR_D31 DDR2ZGroup DDR_DQGATE1 DDR2ZGroup DDR_DQGATE3 DDR2ZGroup DDR_DQS[0]P DDR2ZGroup DDR_DQS[1]P DDR2ZGroup DDR_DQS[2]P DDR2ZGroup DDR_DQS[3]P DDR2ZGroup DDR_DQS[0]N DDR2ZGroup DDR_DQS[1]N DDR2ZGroup DDR_DQS[2]N DDR2ZGroup DDR_DQS[3]N DDR2ZGroup DDR_DQM[0] DDR2Z/HighGroup DDR_DQM[1] DDR2Z/HighGroup DDR_DQM[2] DDR2Z/HighGroup DDR_DQM[3] DDR2Z/HighGroup DDR_CAS DDR2HighGroup Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-23.PinBehaviorsatReset(continued) PinName ResetGroup DDR_RAS DDR2HighGroup DDR_WE DDR2HighGroup DDR_A00 DDR2LowGroup DDR_A01 DDR2LowGroup DDR_A02 DDR2LowGroup DDR_A03 DDR2LowGroup DDR_A04 DDR2LowGroup DDR_A05 DDR2LowGroup DDR_A06 DDR2LowGroup DDR_A07 DDR2LowGroup DDR_A08 DDR2LowGroup DDR_A09 DDR2LowGroup DDR_A10 DDR2LowGroup DDR_A11 DDR2LowGroup DDR_A12 DDR2LowGroup DDR_A13 DDR2LowGroup DDR_ODT0 DDR2LowGroup DDR_ODT1 DDR2LowGroup DDR_CKE DDR2LowGroup DDR_DQGATE0 DDR2LowGroup DDR_DQGATE2 DDR2LowGroup DDR_BA[0] DDR2Low/HighGroup DDR_BA[1] DDR2Low/HighGroup DDR_BA[2] DDR2Low/HighGroup DDR_CS DDR2High/LowGroup DDR_CLKP Clock DDR_CLKN Clock VP3CLK0/AECLKIN Clock RESETSTAT ReflectsPORorRESETvalue 6.7.9 Reset Electrical Data/Timing NOTE If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldownresistor. Table6-24.TimingRequirementsforReset(1) (2)(seeFigure6-10) 720,800,900,1100 NO. UNIT MIN MAX 5 t Pulseduration,PORlow(3) 256D ns w(POR) 6 t Pulseduration,RESETlow 24C ns w(RESET) Setuptime,bootmodeandconfigurationpinsvalidbeforePORhighor 7 tsu(boot) RESEThigh (4) 6P ns (1) C=1/CLKIN1clockfrequencyinns (2) D=1/CLKIN2clockfrequencyinns (3) IfCLKIN2isnotused,t mustbemeasuredintermsofCLKIN1cycles;otherwise,usethesloweroftheCLKIN1,CLKIN2cycles. w(POR) (4) P=1/CPUclockfrequencyinnanoseconds 94 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-24.TimingRequirementsforReset(1)(2) (seeFigure6-10)(continued) 720,800,900,1100 NO. UNIT MIN MAX Holdtime,bootmodeandconfigurationpinsvalidafterPORhighorRESET 8 th(boot) high (4) 6P ns Table6-25.SwitchingCharacteristicsOverRecommendedOperatingConditionsDuringReset(1) (seeFigure6-10) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 9 t Delaytime,PORhighANDRESEThightoRESETSTAThigh 1500C ns d(PORH-RSTATH) (1) C=1/CLKIN1clockfrequencyinns. • Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high impedance as soon as their respective power supply has reached normal operating conditions. Pins remaininhighimpedanceuntilconfiguredotherwisebytheirrespectiveperipherals. • Low group consists of pins that become low as soon as their respective power supply has reached normaloperatingconditions.Pinsremainlowuntilconfiguredotherwisebytheirrespectiveperipheral. • High group consists of pins that become high as soon as their respective power supply has reached normaloperatingconditions.Pinsremainhighuntilconfiguredotherwisebytheirrespectiveperipheral. • All peripherals must be enabled through software following a power-on reset; for more details, see Section6.7.1,Power-onReset. • Forpower-supplysequencerequirements,seeSection6.3.1. A. RESETshouldbeusedonlyafterthedevicehasbeenpoweredup.FormoredetailsontheuseoftheRESETpin, seeSection6.7,ResetController. B. A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the RESETpinduringaWarmReset. C. BootandDeviceConfigurationInputs(duringreset)includeAEA[22:11],andUHPIEN. Figure6-10.WarmResetandMaxResetTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.8 Interrupts The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-27 summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP interrupt control, see TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature numberSPRUEU6). Table6-26.DSPInterruptEvents DSP EVENT INTERRUPTSOURCE INTERRUPT EVENTNUMBER 0 EVT0 Outputofeventcombiner0,forevents1–31 1 EVT1 Outputofeventcombiner1,forevents32–63 2 EVT2 Outputofeventcombiner2,forevents64–95 3 EVT33 Outputofeventcombiner3,forevents96–127 4-8 Reserved 9 EMU_DTDMA ECMinterruptfor: • Hostscanaccessevent • DTDMAtransfercompleteevent • AETinterruptevent 10 Reserved Reserved 11 EMU_RTDXRX RTDXreceivecompleteevent 12 EMU_RTDXTX RTDXtransmitcompleteevent 13 IDMA0EMC C64x+EMC0event 14 IDMA1EMC C64x+EMC1event 15 DSPINT Host(PCI/HPI)toDSPinterruptevent 16 I2CINT I2Cinterruptevent 17 Reserved Reserved 18 AEASYNCERRevent EMIFAErrorInterruptevent 19 TINT2L Timerinterruptlowevent 20 TINT2H Timerinterrupthighevent 21 TINT3L Timerinterruptlowevent 22 TINT3H Timerinterrupthighevent 23 PSCINT PSC-ALLINTevent 24 TPCC_GINT EDMA3channelglobalcompletioninterruptevent 25 SPIINT0 SPIInterrupt 26 SPIINT1 SPIInterrupt 27 DSQINT VICP–Sqr(DSPint) 28 IMXINT VICP–IMX 29 VLCDINT VICP-VLCD 30-31 Reserved Reserved 32 RX_PULSE EthernetSubsystemRXpulseinterruptevent 33 RX_THRESH_PULSE EthernetSubsystemRXthresholdinterruptevent 34 TX_PULSE EthernetSubsystemTXpulseinterruptevent 35 MISC_PULSE EthernetSubsystemMISCpulseinterruptevent 36 UART_INT UARTInterrupt 37 VP0_INT VP0Interrupt 38 VP1_INT VP1Interrupt 39 VP2_INT VP2Interrupt 40 VP3_INT VP3Interrupt 96 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-26.DSPInterruptEvents(continued) DSP EVENT INTERRUPTSOURCE INTERRUPT EVENTNUMBER 41 VP4_INT VP4Interrupt 42 GPIO_BNK1_INT (GPIO16:31)GPIOBank1Interruptevent 43 AXINT TXInterruptMcASP 44 ARINT RXInterruptMcASP 45-49 Reserved 50 VINT VLYNQPulseInterruptevent 51 GPINT0 GPIOInterruptevent 52 GPINT1 GPIOInterruptevent 53 GPINT2 GPIOInterruptevent 54 GPINT3 GPIOInterruptevent 55 GPINT4 GPIOInterruptevent 56 GPINT5 GPIOInterruptevent 57 GPINT6 GPIOInterruptevent 58 GPINT7 GPIOInterruptevent 59 GPINT8 GPIOInterruptevent 60 GPINT9 GPIOInterruptevent 61 GPINT10 GPIOInterruptevent 62 GPINT11 GPIOInterruptevent 63 GPINT12 GPIOInterrupt 64 GPINT13 GPIOInterrupt 65 GPINT14 GPIOInterruptevent 66 GPINT15 GPIOInterruptevent 67 TINT0L Timerinterruptlowevent 68 TINT0H Timerinterrupthighevent 69 TINT1L Timerinterruptlowevent 70 TINT1H Timerinterrupthighevent 71 EDMA3CC_INT0 EDMA3CCCompletionInterrupt-Mask0event 72 EDMA3CC_INT1 EDMA3CCCompletionInterrupt–Mask1event 73 EDMA3CC_INT2 EDMA3CCCompletionInterrupt–Mask2event 74 EDMA3CC_INT3 EDMA3CCCompletionInterrupt–Mask3event 75 EDMA3CC_INT4 EDMA3CCCompletionInterrupt–Mask4event 76 EDMA3CC_INT5 EDMA3CCCompletionInterrupt–Mask5event 77 EDMA3CC_INT6 EDMA3CCCompletionInterrupt–Mask6event 78 EDMA3CC_INT7 EDMA3CCCompletionInterrupt–Mask7event 79 EDMA3CC_ERRINT EDMA3CCErrorInterruptevent 80 EDMA3CC_MPINT EDMA3CCMemoryProtectionInterruptevent 81 EDMA3TC0_ERRINT EDMA3TC0ErrorInterruptevent 82 EDMA3TC1_ERRINT EDMA3TC1ErrorInterruptevent 83 EDMA3TC2_ERRINT EDMA3TC2ErrorInterruptevent 84 EDMA3TC3_ERRINT EDMA3TC3ErrorInterruptevent 85 Reserved Reserved 86 Reserved Reserved 87 Reserved Reserved 88 Reserved Reserved 89 Reserved Reserved 90 Reserved Reserved Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 97 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-26.DSPInterruptEvents(continued) DSP EVENT INTERRUPTSOURCE INTERRUPT EVENTNUMBER 91 Reserved Reserved 92 Reserved Reserved 93 Reserved Reserved 94 Reserved Reserved 95 Reserved Reserved 96 INTERR C64x+InterruptControllerDroppedCPUInterruptEvent 97 EMC_IDMAERR C64x+EMCInvalidIDMAParametersevent 98 Reserved Reserved 99 Reserved Reserved 100 EFIINTA EFIInterruptfromsideAevent 101 EFIINTB EFIInterruptfromsideBevent 102-112 Reserved Reserved 113 L1P_ED L1PSinglebiterrordetectedduringDMAreadevent 114-115 Reserved Reserved 116 L2_ED1 L2singlebiterrordetectedevent 117 L2_ED2 L2twobiterrordetectedevent 118 PDC_INT PowerDownsleepinterruptevent 119 Reserved Reserved 120 L1P_CMPA L1PCPUmemoryprotectionfaultevent 121 L1P_DMPA L1PDMAmemoryprotectionfaultevent 122 L1D_CMPA L1DCPUmemoryprotectionfaultevent 123 L1D_DMPA L1DDMAmemoryprotectionfaultevent 124 L2_CMPA L2CPUmemoryprotectionfaultevent 125 L2_DMPA L2DMAmemoryprotectionfaultevent 126 IDMA_CMPA IDMACPUmemoryprotectionfaultevent 127 IDMA_BUSERR IDMAbuserrorinterruptevent 98 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-27.C64x+InterruptControllerRegisters HEXADDRESS ACRONYM REGISTERDESCRIPTION 0x01800000 EVTFLAG0 Eventflagregister0 0x01800004 EVTFLAG1 Eventflagregister1 0x01800008 EVTFLAG2 Eventflagregister2 0x0180000C EVTFLAG3 Eventflagregister3 0x01800020 EVTSET0 Eventsetregister0 0x01800024 EVTSET1 Eventsetregister1 0x01800028 EVTSET2 Eventsetregister2 0x0180002C EVTSET3 Eventsetregister3 0x01800040 EVTCLR0 Eventclearregister0 0x01800044 EVTCLR1 Eventclearregister1 0x01800048 EVTCLR2 Eventclearregister2 0x0180004C EVTCLR3 Eventclearregister3 0x01800080 EVTMASK0 Eventmaskregister0 0x01800084 EVTMASK1 Eventmaskregister1 0x01800088 EVTMASK2 Eventmaskregister2 0x0180008C EVTMASK3 Eventmaskregister3 0x018000A0 MEVTFLAG0 Maskedeventflagregister0 0x018000A4 MEVTFLAG1 Maskedeventflagregister1 0x018000A8 MEVTFLAG2 Maskedeventflagregister2 0x018000AC MEVTFLAG3 Maskedeventflagregister3 0x018000C0 EXPMASK0 Exceptionmaskregister0 0x018000C4 EXPMASK1 Exceptionmaskregister1 0x018000C8 EXPMASK2 Exceptionmaskregister2 0x018000CC EXPMASK3 Exceptionmaskregister3 0x018000E0 MEXPFLAG0 Maskedexceptionflagregister0 0x018000E4 MEXPFLAG1 Maskedexceptionflagregister1 0x018000E8 MEXPFLAG2 Maskedexceptionflagregister2 0x018000EC MEXPFLAG3 Maskedexceptionflagregister3 0x01800104 INTMUX1 Interruptmuxregister1 0x01800108 INTMUX2 Interruptmuxregister2 0x0180010C INTMUX3 Interruptmuxregister3 0x01800140 AEGMUX0 Advancedeventgeneratormuxregister0 0x01800144 AEGMUX1 Advancedeventgeneratormuxregister1 0x01800180 INTXSTAT Interruptexceptionstatus 0x01800184 INTXCLR Interruptexceptionclear 0x01800188 INTDMASK Droppedinterruptmaskregister 0x018001C0 EVTASRT Eventassertregister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.9 DDR2 Memory Controller The 32-bit DDR2 memory controller bus of the device is used to interface to JESD79D-2A standard- compliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM devices; it does not share the bus with any other types of peripherals. The decoupling of DDR2 memories from other devices simplifies board design and provides I/O concurrency from a second external memory interface, EMIFA. The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum throughput of the DDR2 bus. The data rate of the DDR2 bus is equal to the CLKIN2 frequency multiplied by 20. The internal data bus clock frequency of the DDR2 memory controller is fixed at a divide-by-three ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the two bus frequencies. For example, if the internal data bus frequency is 300 MHz (CPU frequency is 900 MHz) and the DDR2 data rate is 533 MHz (266 MHz clock rate as CLKIN2 frequency is 26.6 MHz), the maximum datarateachievablebytheDDR2memorycontrolleris2.13Gbytes/sec. 6.9.1 DDR2 Memory Controller Device-Specific Information The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces such as EMIF and HPI. For these other interfaces, the device timing was specified in terms of data manualspecificationsandI/Obufferinformationspecification(IBIS)models. For the DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the simulationandsystemcharacterizationtobesureallDDR2interfacetimingsinthissolutionaremet. The ODT[1:0] pins of the memory controller must be left unconnected. The ODT pins on the DDR2 memorydevice(s)mustbeconnectedtoground. TheDDR2memorycontrolleronthedevicesupportsthefollowingmemorytopologies: • A32-bitwideconfigurationinterfacingtotwo16-bitwideDDR2SDRAMdevices. • A16-bitwideconfigurationinterfacingtoasingle16-bitwideDDR2SDRAMdevice. A race condition may exist when certain masters write data to the DDR2 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrectmessage. Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have hardwarespecificationofwrite-readordering,itmaybenecessarytospecifydataorderingviasoftware. IfmasterAdoesnotwaitforindicationthatawriteiscomplete,itmustperformthefollowingworkaround: 1. Performtherequiredwrite. 2. PerformadummywritetotheDDR2memorycontrollermoduleIDandrevisionregister. 3. PerformadummyreadtotheDDR2memorycontrollermoduleIDandrevisionregister. 4. IndicatetomasterBthatthedataisreadytobereadaftercompletionofthereadinstep3.The completionofthereadinstep3ensuresthatthepreviouswritewasdone. ThemasterperipheralsthatneedtoimplementthisworkaroundareHPI,PCI,andVLYNQ. 100 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.9.2 DDR2 Memory Controller Peripheral Registers Table6-28.DDR2MemoryControllerRegisters(1) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x78000000 MIDR DDR2MemoryControllerModuleandRevisionRegister 0x78000004 DMCSTAT DDR2MemoryControllerStatusRegister 0x78000008 SDCFG DDR2MemoryControllerSDRAMConfigurationRegister 0x7800000C SDRFC DDR2MemoryControllerSDRAMRefreshControlRegister 0x78000010 SDTIM1 DDR2MemoryControllerSDRAMTiming1Register 0x78000014 SDTIM2 DDR2MemoryControllerSDRAMTiming2Register 0x78000018 - Reserved 0x78000020 BPRIO DDR2MemoryControllerBurstPriorityRegister 0x78000024-0x7800004C - Reserved 0x78000050-0x78000078 - Reserved 0x7800007C-0x780000BC - Reserved 0x780000C0-0x780000E0 - Reserved 0x780000E4 DMCCTL DDR2MemoryControllerControlRegister 0x780000E8-0x780000FC - Reserved 0x78000100-0x7FFFFFFF - Reserved (1) FordetailsabouttheDDR2registersandtheirmodes,seetheTMS320DM647/DM648DSPDDR2MemoryController(DDR2)User's Guide(literaturenumberSPRUEK5). 6.9.3 DDR2 Interface This section provides the timing information for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2 specification,UnderstandingTI'sPCBRoutingRule-BasedDDR2TimingSpecification(SPRAAV0). 6.9.3.1 DDR2InterfaceSchematic Figure6-11showstheDDR2interfaceschematicforax32DDR2memorysystem.Thex16DDR2system schematicshowninFigure6-12isidenticalexceptthatthehighwordDDR2deviceisdeleted. 6.9.3.2 CompatibleJEDECDDR2Devices Table 6-29 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface. Generally,theDDR2interfaceiscompatiblewithx16DDR2-533speedgradeDDR2devices. Table6-29.CompatibleJEDECDDR2Devices NO. PARAMETER MIN MAX UNIT 1 JEDECDDR2DeviceSpeedGrade(1) DDR2-533 2 JEDECDDR2DeviceBitWidth x16 x16 Bits 3 JEDECDDR2DeviceCount(2) 1 2 Devices 4 JEDECDDR2DeviceBallCount(3) 84 92 Balls (1) HigherDDR2speedgradesaresupportedduetoinherentJEDECDDR2backwardscompatibility. (2) OneDDR2deviceisusedfor16-bitDDR2memorysystem.TwoDDR2devicesareusedfor32-bitDDR2memorysystem. (3) 92balldevicesretainedforlegacysupport.Newdesignswillmigrateto84ballDDR2devices.Electrically,the92and84ballDDR2 devicesarethesame. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 101 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com DM647/DM648 DDR2 DDR_ODT0 NC ODT DDR_D00 T BED0 DDR_D7 T BED7 DDR_DQM0 T LDM DDR_DQS0 T LDQS DDR_DQS0 T LDQS DDR_D08 T BED8 DDR_D15 T BED15 DDR_DQM1 T UDM DDR_DQS1 T UDQS DDR_DQS1 T UDQS DDR_DQGATE0 T DDR_DQGATE1 DDR_DQGATE2 T DDR2 DDR_DQGATE3 DDR_ODT1 NC ODT DDR_D16 T BED0 DDR_D23 T BED0 DDR_DQM2 T LDM DDR_DQS2 T LDQS DDR_DQS2 T LDQS DDR_D24 T BED7 DDR_D31 T BED15 DDR_DQM3 T UDM DDR_DQS3 T UDQS DDR_DQS3 T UDQS DDR_BA0 T BA0 BA0 DDR_BA2 T BA2 BA2 DDR_A00 T A0 A0 DDR_A13 T A13 A13 DDR_CS0 T CS CS DDR_CAS T CAS CAS DDR_RAS T RAS RAS Vio 1.8(A) BSDWE T WE WE DDR_CKE T CKE CKE DDR_CLK T CK CK DDR_CLK T CK CK 0.1µF 1 kΩ1% DDR_VREF VREF VREF VREF VREF VREF 0.1µF(B) 0.1µF(B) 0.1µF(B) 0.1µF 1 kΩ1% T Terminator, if desired. See terminator comments. A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. B. V 1.8isthepowersupplyfortheDDR2memoryinterface. io C. OneofthesecapacitorscanbeeliminatedifthedivideranditscapacitorsareplacednearadeviceVREFpin. Figure6-11. 32-BitDDR2High-LevelSchematic 102 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 DM647/DM648 DDR2 DDR_ODT0 NC ODT DDR_D00 T BED0 DDR_D7 T BED7 DDR_DQM0 T LDM DDR_DQS0 T LDQS DDR_DQS0 T LDQS DDR_D08 T BED8 DDR_D15 T BED15 DDR_DQM1 T UDM DDR_DQS1 T UDQS DDR_DQS1 T UDQS DDR_DQGATE0 T DDR_DQGATE1 DDR_DQGATE2 NC 1 kΩ DDR_DQGATE3 DDR_ODT1 NC DDR_D16 NC (A) Vio 1.8 DDR_D23 NC DDR_DQM2 NC 1 kΩ DDR_DQS2 DDR_DQS2 DDR_D24 NC 1 kΩ (A) Vio 1.8 DDR_D31 NC DDR_DQM3 NC 1 kΩ DDR_DQS3 DDR_DQS3 1 kΩ DDR_BA0 T BA0 DDR_BA2 T BA2 DDR_A00 T A0 DDR_A13 T A13 DDR_CS0 T CS DDR_CAS T CAS DDR_RAS T RAS Vio 1.8(A) BSDWE T WE DDR_CKE T CKE DDR_CLK T CK DDR_CLK T CK 0.1µF 1 kΩ1% DDR_VREF VREF VREF VREF 0.1µF(B) 0.1µF(B) 0.1µF 1 kΩ1% T Terminator, if desired. See terminator comments. A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. B. OneofthesecapacitorscanbeeliminatedifthedivideranditscapacitorsareplacednearadeviceVREFpin. C. Vio1.8isthepowersupplyfortheDDR2memoryinterface. Figure6-12. 16-BitDDR2High-LevelSchematic Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 103 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.9.3.3 PCBStackup The minimum stackup required for routing the device is a six-layer stack as shown in Table 6-30. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size ofthePCBfootprint. Table6-30.MinimumPCBStackUp LAYER TYPE DESCRIPTION 1 Signal Toproutingmostlyhorizontal 2 Plane Ground 3 Plane Power 4 Signal Internalrouting 5 Plane Ground 6 Signal Bottomroutingmostlyvertical CompletestackupspecificationsareprovidedinTable6-31. Table6-31.PCBStackUpSpecifications NO. PARAMETER MIN TYP MAX UNIT 1 PCBRouting/PlaneLayers 6 2 SignalRoutingLayers 3 3 FullgroundlayersunderDDR2routingRegion 2 4 NumberofgroundplanecutsallowedwithinDDRroutingregion 0 5 NumberofgroundreferenceplanesrequiredforeachDDR2routinglayer 1 6 NumberoflayersbetweenDDR2routinglayerandreferencegroundplane 0 7 PCBRoutingFeatureSize 4 Mils 8 PCBTraceWidthw 4 Mils 8 PCBBGAescapeviapadsize 18 Mils 9 PCBBGAescapeviaholesize 8 Mils 10 DSPDeviceBGApadsize(1) 11 DDR2DeviceBGApadsize(2) 12 SingleEndedImpedance,Zo 50 75 Ω 13 ImpedanceControl(3) Z-5 Z Z+5 Ω (1) SeetheFlipChipBallGridArrayPackageReferenceGuide(SPRU811)forDSPdeviceBGApadsize. (2) SeetheDDR2devicemanufacturerdocumenationfortheDDR2deviceBGApadsize. (3) ZisthenominalsingledendedimpedanceselectedforthePCBspecifiedbyitem12. 6.9.3.4 Placement Figure 6-13 shows the required placement for the device as well as the DDR2 devices. The dimensions for Figure 6-13 are defined in Table 6-32. The placement does not restrict the side of the PCB where the devices are mounted. The purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 16-bit DDR memory systems, the high word DDR2 device is omitted from the placement. 104 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 X A1 Y OFFSET r e Y DDR2 R2oll Device DDntr o Y C DM648 OFFSET A1 Recommended DDR2 Device Orientation A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. Figure6-13.DDR2DevicePlacement Table6-32.PlacementSpecifications NO. PARAMETER MIN MAX UNIT 1 X(1) (2) 1660 Mils 2 Y(1) (2) 1280 Mils 3 YOffset(1) (2) (3) 650 Mils 4 DDR2KeepoutRegion(4) 5 Clearancefromnon-DDR2signaltoDDR2KeepoutRegion(5) 4 w (1) SeeFigure6-11fordimensiondefintions. (2) MeasurementsfromcenterofDSPdevicetocenterofDDR2device. (3) For16-bitmemorysystems,itisrecommendedthatYOffsetbeassmallaspossible. (4) DDR2KeepoutregiontoencompassentireDDR2routingarea (5) Non-DDR2signalsallowedwithinDDR2keepoutregionprovidedtheyareseparatedfromDDR2routinglayersbyagroundplane. 6.9.3.5 DDR2KeepOutRegion The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep out region is defined for this purpose and is shown in Figure 6-14. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6- 32. A1 er oll DDR2 Device ntr o C 2 R D D A1 Figure6-14.DDR2KeepoutRegion Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 105 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com NOTE The region (see Figure 6-14) should encompass all DDR2 circuitry and varies depending on placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they are routedonlayersseparatedfromDDR2signallayersbyagroundlayer.Nobreaksshouldbe allowed in the reference ground layers in this region. In addition, the 1.8-V power plane shouldcovertheentirekeepoutregion. 6.9.3.6 BulkBypassCapacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 6-33 contains the minimum numbers and capacitance required for the bulk bypass capacitors. This table covers only the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass capacitance maybeneededforothercircuitry. Table6-33.BulkBypassCapacitors NO. PARAMETER MIN MAX UNIT 1 DV BulkBypassCapacitorCount(1) 3 Devices DD18 2 DV BulkBypassTotalCapacitance 30 μF DD18 3 DDR#1BulkBypassCapacitorCount(2) 1 Devices 4 DDR#1BulkBypassTotalCapacitance 10 μF 5 DDR#2BulkBypassCapacitorCount(2) (3) 1 Devices 6 DDR#2BulkBypassTotalCapacitance(3) 10 μF (1) Thesedevicesshouldbeplacednearthedevicetheyarebypassing,butpreferenceshouldbegiventotheplacementofthehigh-speed (HS)bypasscaps. (2) Thesedevicesshouldbeplacednearthedevicetheyarebypassing,butpreferenceshouldbegiventotheplacementofthehigh-speed (HS)bypasscaps. (3) Onlyusedon32-bitwideDDR2memorysystems 6.9.3.7 High-SpeedBypassCapacitors High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and DSP/DDR ground connections. Table 6-34 contains the specification for the HS bypass capacitors as well asforthepowerconnectionsonthePCB. 6.9.3.8 NetClasses Table 6-35 lists the clock net classes for the DDR2 interface. Table 6-36 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the terminationandroutingrulesthatfollow. Table6-34.High-SpeedBypassCapacitors NO. PARAMETER MIN MAX UNIT 1 HSBypassCapacitorPackageSize(1) 0402 10Mils 2 DistancefromHSbypasscapacitortodevicebeingbypassed 250 Mils 3 NumberofconnectionviasforeachHSbypasscapacitor(2) 2 Vias 4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 1 30 Mils 5 NumberofconnectionviasforeachDDR2devicepowerorgroundballs 1 Vias 6 TracelengthfromDDR2devicepowerballtoconnectionvia 35 Mils 7 DV HSBypassCapacitorCount(3) 20 Devices DD18 8 DV HSBypassCapacitorTotalCapacitance 1.2 μF DD18 (1) L×W,10milunits(i.e.,a0402isa40×20milsurfacemountcapacitor) (2) AnadditionalHSbypasscapacitorcansharetheconnectionviasonlyifitismountedontheoppositesideoftheboard. (3) Thesedevicesshouldbeplacedascloseaspossibletothedevicebeingbypassed. 106 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-34.High-SpeedBypassCapacitors(continued) NO. PARAMETER MIN MAX UNIT 9 DDR#1HSBypassCapacitorCount(3) 8 Devices 10 DDR#1HSBypassCapacitorTotalCapacitance 0.4 μF 11 DDR#2HSBypassCapacitorCount(3) (4) 8 Devices 12 DDR#2HSBypassCapacitorTotalCapacitance(4) 0.4 μF (4) Onlyusedon32-bitwideDDR2memorysystems Table6-35.ClockNetClassDefinitions CLOCKNETCLASS DSPPINNAMES CK DDR_CLK/DDR_CLK DQS0 DDR_DQS0/DDR_DQS0 DQS1 DDR_DQS1/DDR_DQS1 DQS2(1) DDR_DQS2/DDR_DQS2 DQS3(1) DDR_DQS3/DDR_DQS3 (1) Onlyusedon32-bitwideDDR2memorysystems. Table6-36.SignalNetClassDefinitions CLOCKNETCLASS ASSOCIATEDCLOCKNETCLASS DSPPINNAMES ADDR_CTRL CK DDR_BA[2:0],DDR_A[13:0],DDR_CS,DDR_CAS,DDR_RAS, DDR_WE,DDR_CKE DQ0 DQS0 DDR_D[7:0],DDR_DQM0 DQ1 DQS1 DDR_D[15:8],DDR_DQM1 DQ2(1) DQS2 DDR_D[23:16],DDR_DQM2 DQ3(1) DQS3 DDR_D[31:24],DDR_DQM3 DQGATEL CK,DQS0,DQS1 DDR_DQGATE0,DDR_DQGATE1 DQGATEH(1) CK,DQS2,DQS3 DDR_DQGATE2,DDR_DQGATE3 (1) Onlyusedon32-bitwideDDR2memorysystems. 6.9.3.9 DDR2SignalTermination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only typepermitted.Table6-37showsthespecificationsfortheseriesterminators. Table6-37.DDR2SignalTerminations NO. PARAMETER MIN TYP MAX UNIT 1 CKNetClass(1) 0 10 Ω 2 ADDR_CTRLNetClass(1) (2) (3) 0 22 Zo Ω 3 DataByteNetClasses(DQS0-DQS3,DQ0-DQ3)(1) (2) (3) (4) 0 22 Zo Ω 4 DQGATENetClasses(DQGATEL,DQGATEH)(1) (2) (3) 0 10 Zo Ω (1) Onlyseriesterminationispermitted,parallelorSSTspecificallydisallowed. (2) TerminatorvalueslargerthantypicalonlyrecommendedtoaddressEMIissues. (3) Terminationvalueshouldbeuniformacrossnetclass. (4) Whennoterminationisusedondatalines(0Ωs),theDDR2devicesmustbeprogrammedtooperatein60%strengthmode. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 107 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.9.3.10 VREFRouting VREF is used as a reference by the input buffers of the DDR2 memories as well as the device’s. VREF is intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 6-11. Other methods of creating VREF are not recommended. Figure 6-15 shows the layoutguidelinesforVREF. VREF Bypass Capacitor DDR2 Device A1 VREF Nominal Minimum Trace Width is 20 Mils DM648 Device A1 Neck down to minimum in BGAescape regions is acceptable. Narrowing to accommodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. Figure6-15.VREFRoutingandTopology 6.9.3.11 DDR2CKandADDR_CTRLRouting Figure 6-16 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A shouldbemaximized. A1 B r A T DDR2ntrolle o C C DM648 A1 A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. Figure6-16.CKandADDR_CTRLRoutingandTopology 108 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-38.CKandADDR_CTRLRoutingSpecification(1) NO PARAMETER MIN TYP MAX UNIT 1 CentertocenterCK-CKspacing 2w 2 CKAtoB/AtoCSkewLengthMismatch(1) 25 Mils 3 CKBtoCSkewLengthMismatch 25 Mils 4 CentertocenterCKtootherDDR2tracespacing(2) 4w 5 CK/ADDR_CTRLnominaltracelength(3) CACLM-50 CACLM CACLM+50 Mils 6 ADDR_CTRLtoCKSkewLengthMismatch 100 Mils 7 ADDR_CTRLtoADDR_CTRLSkewLengthMismatch 100 Mils 8 CentertocenterADDR_CTRLtootherDDR2tracespacing(2) 4w 9 CentertocenterADDR_CTRLtootherADDR_CTRLtracespacing(2) 3w 10 ADDR_CTRLAtoB/AtoCSkewLengthMismatch(1) 100 Mils 11 ADDR_CTRLBtoCSkewLengthMismatch 100 Mils (1) Seriesterminator,ifused,shouldbelocatedclosesttoDSP. (2) Centertocenterspacingisallowedtofalltominimum(w)forupto500milsofroutedlengthtoaccommodateBGAescapeandrouting congestion. (3) CACLMisthelongestManhattandistanceoftheCKandADDR_CTRLnetclasses. Figure6-17showsthetopologyandroutingfortheDQSandDQnetclasses;theroutesarepointtopoint. Skewmatchingacrossbytesisnotneedednorrecommended. T E0 A1 T E1 r e R2oll DDntr o C DM648 T E2 A1 T E3 A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. Figure6-17.DQSandDQRoutingandToplogy Table6-39.DQSandDQRoutingSpecification (1) NO. PARAMETER MIN TYP MAX UNIT 1 CentertocenterDQS-DQSspacing 2w 2 DQSESkewLengthMismatch 25 Mils 3 CentertocenterDQStootherDDR2tracespacing(2) 4w 4 DQS/DQnominaltracelength(1) (3) (4) (5) DQLM-50 DQLM DQLM+50 Mils 5 DQtoDQSSkewLengthMismatch(3) (4) (5) 100 Mils 6 DQtoDQSkewLengthMismatch(3) (4) (5) 100 Mils (1) Seriesterminator,ifused,shouldbelocatedclosesttoDDR. (2) Centertocenterspacingisallowedtofalltominimum(w)forupto500milsofroutedlengthtoaccommodateBGAescapeandrouting congestion. (3) A16-bitDDRmemorysystemhastwosetsofdatanetclasses,onefordatabyte0,andonefordatabyte1,eachwithanassociated DQS(2DQSs). (4) A32-bitDDRmemorysystemwillhavefoursetsofdatanetclasses,oneeachfordatabytes0through3,andeachassociatedwitha DQS(4DQSs). (5) Thereisnoneedanditisnotrecommendedtoskewmatchacrossdatabytes,i.e.,fromDQS0anddatabyte0toDQS1anddatabyte 1. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 109 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-39.DQSandDQRoutingSpecification(1) (continued) NO. PARAMETER MIN TYP MAX UNIT 7 CentertocenterDQtootherDDR2tracespacing(2) (6) 4w 8 CentertoCenterDQtootherDQtracespacing(7) (2) 3w 9 DQ/DQSESkewLengthMismatch(3) (4) (5) 100 Mils (6) DQsfromotherDQSdomainsareconsideredotherDDR2trace. (7) DQLMisthelongestManhattandistanceofeachoftheDQSandDQnetclasses. Figure6-18showstheroutingfortheDQGATEnetclasses.Table6-40containstheroutingspecification. A1 H F T r e R2oll DDntr o C T DM648 A1 L F A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. Figure6-18.DQGATERouting Table6-40.DQGATERoutingSpecification NO. PARAMETER MIN TYP MAX UNIT 1 DQGATELLengthF(1) CKB0B1 2 DQGATEHLengthF(2) (3) CKB2B3 3 CentertocenterDQGATEtoanyothertracespacing 4w 4 DQS/DQnominaltracelength DQLM-50 DQLM DQLM+ Mils 50 5 DQGATELSkew(4) 100 Mils 6 DQGATEHSkew(5) (3) 100 Mils (1) CKB0B1isthesumofthelengthoftheCKnetplustheaveragelengthoftheDQS0andDQS1nets. (2) CKB2B3isthesumofthelengthoftheCKnetplustheaveragelengthoftheDQS2andDQS3nets. (3) Onlyusedon32-bit-wideDDR2memorysystems. (4) SkewfromCKB0B1 (5) SkewfromCKB2B3 110 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.10 External Memory Interface A (EMIFA) TheEMIFAcaninterfacetoavarietyofexternaldevicesorASICs,including: • Pipelinedandflow-throughsynchronous-burstSRAM(SBSRAM) • ZBT(zerobusturnaround)SRAMandlatewriteSRAM • SynchronousFIFOs • Asynchronousmemory,includingSRAM,ROM,andFlash 6.10.1 EMIFA Device-Specific Information Timing analysis must be done to verify all ac timing requirements are met. TI recommends utilizing I/O bufferinformationspecification(IBIS)toanalyzeallactiming. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS ModelsforTimingAnalysisApplicationReport(literaturenumberSPRA839). To maintain signal integrity, serial termination resistors should be inserted into all EMIFA output signal lines. A race condition may exist when certain masters write data to the EMIFA. For example, if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master B attempts to read the software message, then the master B read may bypass themasterAwriteand,thus,masterBmayreadstaledataand,therefore,receiveanincorrectmessage. Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have hardwarespecificationofwrite-readordering,itmaybenecessarytospecifydataorderingviasoftware. IfmasterAdoesnotwaitforindicationthatawriteiscomplete,itmustperformthefollowingworkaround: 1. Performtherequiredwrite. 2. PerformadummywritetotheEMIFAmoduleIDandrevisionregister. 3. PerformadummyreadtotheEMIFAmoduleIDandrevisionregister. 4. IndicatetomasterBthatthedataisreadytobereadaftercompletionofthereadinstep3.The completionofthereadinstep3ensuresthatthepreviouswritewasdone. 6.10.2 EMIFA Peripheral Register Description(s) For more information on the EMIF registers shown in Table 6-41, see TMS320DM647/DM648 DSP ExternalMemoryInterface(EMIF)User'sGuide(literaturenumberSPRUEK6). Table6-41.EMIFARegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x70000000 MIDR ModuleIDandRevisionRegister 0x70000004 STAT StatusRegister 0x70000008 - Reserved 0x7000000C-0x7000001C - Reserved 0x70000020 BPRIO BurstPriorityRegister 0x70000024-0x7000004C - Reserved 0x70000050-0x7000007C - Reserved 0x70000080 CE2CFG EMIFACE2ConfigurationRegister 0x70000084 CE3CFG EMIFACE3ConfigurationRegister 0x70000088 - Reserved 0x7000008C - Reserved 0x70000090-0x7000009C - Reserved 0x700000A0 AWCC EMIFAAsyncWaitCycleConfigurationRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 111 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-41.EMIFARegisters(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x700000A4-0x700000BC - Reserved 0x700000C0 INTRAW EMIFAInterruptRAWRegister 0x700000C4 INTMSK EMIFAInterruptMaskedRegister 0x700000C8 INTMSKSET EMIFAInterruptMaskSetRegister 0x700000CC INTMSKCLR EMIFAInterruptMaskClearRegister 0x700000D0-0x700000DC - Reserved 0x700000E0-0x77FFFFFF - Reserved 6.10.3 EMIFA Electrical Data/Timing Table6-42.TimingRequirementsforAECLKINforEMIFA(1) (2)(seeFigure6-19) 720,800,900,1100 NO. UNIT MIN MAX 1 t Cycletime,AECLKIN 6(3) 16P(4) ns c(EKI) 2 t Pulseduration,AECLKINhigh 2.7 ns w(EKIH) 3 t Pulseduration,AECLKINlow 2.7 ns w(EKIL) 4 t Transitiontime,AECLKIN 2 ns t(EKI) 5 t PeriodJitter,AECLKIN 0.02E(5) ns J(EKI) (1) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. IL IH (2) E=theEMIFinputclock(AECLKINorSYSCLK4/2)periodinnsforEMIFA. (3) MinimumAECLKINcycletimesmustbemet,evenwhenAECLKINisgeneratedbyaninternalclocksource.MinimumAECLKINtimes arebasedoninternallogicspeed;themaximumuseablespeedoftheEMIFmaybelowerduetoACtimingrequirements. (4) PisP=1/CPUclockfrequencyinns. (5) ThistimingappliesonlywhenAECLKINisusedforEMIFA. 5 1 4 2 AECLKIN 3 4 Figure6-19.AECLKINTimingforEMIFA Table6-43.SwitchingCharacteristicsOverRecommendedOperatingConditionsforAECLKOUTforthe EMIFAModule(1) (2) (3)(seeFigure6-20) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 1 t Cycletime,AECLKOUT E-0.7 E+0.7 ns c(EKO) 2 t Pulseduration,AECLKOUThigh EH-0.7 EH+0.7 ns w(EKOH) 3 t Pulseduration,AECLKOUTlow EL-0.7 EL+0.7 ns w(EKOL) 4 t Transitiontime,AECLKOUT 1 ns t(EKO) 5 t Delaytime,AECLKINhightoAECLKOUThigh 1 8 ns d(EKIH-EKOH) 6 t Delaytime,AECLKINlowtoAECLKOUTlow 1 8 ns d(EKIL-EKOL) (1) E=theEMIFinputclock(AECLKINorSYSCLK4/2)periodinnsforEMIFA. (2) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. OL OH (3) EHisthehighperiodofE(EMIFinputclockperiod)innsandEListhelowperiodofE(EMIFinputclockperiod)innsforEMIFA. 112 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 AECLKIN 5 2 4 1 3 3 AECLKOUT A. E=theEMIFinputclock(AECLKINorSYSCLK4/2)periodinnsforEMIFA. B. ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. OL OH C. EHisthehighperiodofE(EMIFinputclockperiod)innsandEListhelowperiodofE(EMIFinputclockperiod)inns forEMIFA. Figure6-20.AECLKOUTTimingfortheEMIFAModule 6.10.3.1 AsynchronousMemoryTiming Table6-44.TimingRequirementsforAsynchronousMemoryCyclesforEMIFAModule(1) (2) (3) (seeFigure6-21andFigure6-22) 720,800,900,1100 NO. UNIT MIN MAX 3 t Setuptime,AEDxvalidbeforeAAOE/ASOEhigh 6.5 ns su(EDV-AOEH) 4 t Holdtime,AEDxvalidafterAAOE/ASOEhigh 0 ns h(AOEH-EDV) 5 t Setuptime,AARDYvalidbeforeAECLKOUTlow 1 ns su(ARDY-EKOH) 6 t Holdtime,AARDYvalidafterAECLKOUTlow 2 ns h(EKOH-ARDY) 7 t Pulsewidth,AARDYassertionanddeassertion 2E+5 ns w(ARDY) Delaytime,fromAARDYsampleddeassertedonAECLKOUTfalling 8 t 4E ns d(ARDY-HOLD) tobeginningofprogrammedholdperiod Setuptime,beforeendofprogrammedstrobeperiodbywhich 9 t AARDYshouldbeassertedinordertoinsertextendedstrobewait 2E ns su(ARDY-HOLD) states. (1) E=AECLKOUTperiodinnsforEMIFA (2) Tospecifydatasetuptime,simplyprogramthestrobewidthwideenough. (3) AARDYisinternallysynchronized.TouseAARDYasanasynchronousinput,thepulsewidthoftheAARDYsignalshouldbeatleast2E tospecifysetupandholdtimeismet. Table6-45.SwitchingCharacteristicsOverRecommendedOperatingConditionsforAsynchronous MemoryCyclesforEMIFAModule(1) (2) (3)(seeFigure6-21andFigure6-22) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 1 t Outputsetuptime,selectsignalsvalidtoAAOE/ASOElow RS×E-1.5 ns osu(SELV-AOEL) 2 t Outputholdtime,AAOE/ASOEhightoselectsignalsinvalid RS×E-1.9 ns oh(AOEH-SELIV) 10 t Delaytime,AECLKOUThightoAAOE/ASOEvalid 1 7.28 ns d(EKOH-AOEV) 11 t Outputsetuptime,selectsignalsvalidtoAAWE/ASWElow WS×E-1.7 ns osu(SELV-AWEL) 12 t Outputholdtime,AAWE/ASWEhightoselectsignalsinvalid WH×E-1.8 ns oh(AWEH-SELIV) 13 t Delaytime,AECLKOUThightoAAWE/ASWEvalid 1.3 7.1 ns d(EKOH-AWEV) (1) E=AECLKOUTperiodinnsforEMIFA (2) RS=Readsetup,RST=Readstrobe,RH=Readhold,WS=Writesetup,WST=Writestrobe,WH=Writehold.Theseparameters areprogrammedviatheEMIFACEConfigurationregisters(CEnCFG). (3) SelectsignalsforEMIFAinclude:ACEx,ABE[1:0],AEA[23:0],ABA[1:0];andforEMIFAwrites,alsoincludeAR/W,AED[15:0]. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 113 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Strobe = 4 Setup = 1 Hold = 1 AECLKOUT 1 2 ACEx 1 2 ABE[1:0] Byte Enables 2 1 AEA[23:0]/ ABA[1:0] Address 3 4 AED[15:0] Read Data 10 10 AAOE/ASOE AAWE/ASWE AR/W AARDY DEASSERTED A. AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE (identified under select signals) and AAWE/ASWE, respectively,duringasynchronousmemoryaccesses. B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register(AWCC). Figure6-21.AsynchronousMemoryReadTimingforEMIFA Strobe = 4 Setup = 1 Hold = 1 AECLKOUT 11 12 ACEx 11 12 ABE[1:0] Byte Enables 11 12 AEA[23:0]/ ABA[1:0] Address 11 12 AED[15:0] Write Data AAOE /ASOE(A) 13 (A) 13 AAWE/ASWE 11 12 AR/W AARDY(B) DEASSERTED A. AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE and AAWE/ASWE (identified under select signals) during asynchronousmemoryaccesses. B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register(AWCC). Figure6-22.AsynchronousMemoryWriteTimingforEMIFA 114 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Strobe Strobe Setup = 2 Extended Strobe Hold = 2 8 9 AECLKOUT 6 5 7 7 AARDY(A) ASSERTED DEASSERTED A. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register(AWCC). Figure6-23.AARDYTiming 6.10.3.2 ProgrammableSynchronousInterfaceTiming Table6-46.TimingRequirementsforProgrammableSynchronousInterfaceCyclesforEMIFAModule (seeFigure6-24) 720,800,900,1100 NO. UNIT MIN MAX 6 t Setuptime,readAEDxvalidbeforeAECLKOUThigh 2 ns su(EDV-EKOH) 7 t Holdtime,readAEDxvalidafterAECLKOUThigh 1.5 ns h(EKOH-EDV) Table6-47.SwitchingCharacteristicsOverRecommendedOperatingConditionsforProgrammable SynchronousInterfaceCyclesforEMIFAModule(1)(seeFigure6-24-Figure6-26) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 1 t Delaytime,AECLKOUThightoACExvalid 1.3 4.9 ns d(EKOH-CEV) 2 t Delaytime,AECLKOUThightoABExvalid 4.9 ns d(EKOH-BEV) 3 t Delaytime,AECLKOUThightoABExinvalid 1.3 ns d(EKOH-BEIV) 4 t Delaytime,AECLKOUThightoAEAxvalid 4.9 ns d(EKOH-EAV) 5 t Delaytime,AECLKOUThightoAEAxinvalid 1.3 ns d(EKOH-EAIV) 8 t Delaytime,AECLKOUThightoASADS/ASREvalid 1.3 4.9 ns d(EKOH-ADSV) 9 t Delaytime,AECLKOUThightoAAOE/ASOEvalid 1.3 4.9 ns d(EKOH-OEV) 10 t Delaytime,AECLKOUThightoAEDxvalid 4.9 ns d(EKOH-EDV) 11 t Delaytime,AECLKOUThightoAEDxinvalid 1.3 ns d(EKOH-EDIV) 12 t Delaytime,AECLKOUThightoAAWE/ASWEvalid 1.3 4.9 ns d(EKOH-WEV) (1) ThefollowingparametersareprogrammableviatheEMIFACEConfigurationregisters(CEnCFG): • Readlatency(R_LTNCY):0-,1-,2-,or3-cyclereadlatency • Writelatency(W_LTNCY):0-,1-,2-,or3-cyclewritelatency • ACExassertionlength(CE_EXT):ForstandardSBSRAMorZBTSRAMinterface,ACExgoesinactiveafterthefinalcommandhas beenissued(CE_EXT=0).ForsynchronousFIFOinterfacewithglue,ACExisactivewhenAAOE/ASOEisactive(CE_EXT=1). • FunctionofASADS/ASRE(R_ENABLE):ForstandardSBSRAMorZBTSRAMinterface,ASADS/ASREhasdeselectcycles (R_ENABLE=0).ForFIFOinterface,ASADS/ASREhasNOdeselectcycles(R_ENABLE=1). Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 115 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com READ latency = 2 AECLKOUT 1 1 ACEx 2 3 ABE[7:0] BBEE11 BBEE22 BBEE33 BBEE44 4 5 AEA[19:0]/ABA[1:0] EA1 EA2 EA3 EA4 6 7 AED[63:0] Q1 Q2 Q3 Q4 8 8 ASADS/ASRE(B) 9 9 AAOE/ASOE(B) AAWE/ASWE(B) Figure6-24.ProgrammableSynchronousInterfaceReadTimingforEMIFA(WithReadLatency=2) NOTE ThisinformationappliestoFigure6-25andFigure6-26. The following parameters are programmable via the EMIF Chip Select n Configuration Register(CESECn): • Readlatency(R_LTNCY):1-,2-,or3-cyclereadlatency • Writelatency(W_LTNCY):0-,1-,2-,or3-cyclewritelatency • ACExassertionlength (CE_EXT): Forstandard SBSRAM orZBTSRAMinterface,ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFOinterface,ACExisactivewhenAAOE/ASOEisactive(CE_EXT=1). • FunctionofASADS/ASRE(R_ENABLE):ForstandardSBSRAMorZBTSRAMinterface, ASADS/ASRE has deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE hasNOdeselectcycles(R_ENABLE=1). AECLKOUT 1 1 ACEx 2 3 ABE[1:0] BE1 BE2 BE3 BE4 5 4 AEA[23:0]/ABA[1:0] EA1 EA2 EA3 EA4 10 10 11 AED[15:0] Q1 Q2 Q3 Q4 8 8 ASADS /ASRE AAOE /ASOE 12 12 AAWE/ ASWE A. Inthisfigure,W_LTNCY=0,CE_EXT=0,R_ENABLE=0,andSSEL=1. Figure6-25.ProgrammableSynchronousInterfaceWriteTimingforEMIFA(WithWriteLatency=0) 116 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Write Latency = 1 AECLKOUT 1 1 ACEx 2 3 ABE[1:0] BE1 BE2 BE3 BE4 4 5 AEA[23:0]/ABA[1:0] EA1 EA2 EA3 EA4 10 10 11 AED[15:0] Q1 Q2 Q3 Q4 8 8 ASADS /ASRE AAOE /ASOE 12 12 AAWE/ ASWE Figure6-26.ProgrammableSynchronousInterfaceWriteTimingforEMIFA(WithWriteLatency=1) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 117 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.11 Video Port Each video port is capable of sending and receiving digital video data. The video ports are also capable of capturing/displaying RAW data. The video port peripherals follow video standards such as BT.656 and SMPTE296. 6.11.1 Video Port Device-Specific Information Thedeviceshavefivevideoportperipherals. The video port peripheral can operate as a video capture port, video display port, or as a transport channelinterface(TCI)captureport. The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the two channels. The entire port (both channels) is always configured for either video capture or display only. Separate data pipelines control the parsing and formatting of video capture or display data for each of the BT.656,Y/C,rawvideo,andTCImodes. For video capture operation, the video port may operate as two 8-bit channels of BT.656 or raw video capture; or as a single channel of 8-bit BT.656, 8-bit raw video, 8-bit Y/C video, 16-bit raw video, or 8-bit TCI. For video display operation, the video port may operate as a single channel of 8-bit BT.656; or as a single channel of 8-bit BT.656, 8-bit raw video, 8-bit Y/C video, or 16-bit raw video. It may also operate in a two channel 8-bit raw mode in which the two channels are locked to the same timing. Channel B is not used duringsinglechanneloperation. For more detailed information on the video port peripherals, see the TMS320DM647/DM648 Video Port User'sGuide(literaturenumberSPRUEM1). 6.11.2 Video Port Peripheral Register Description(s) Table6-48.VideoPort0,1,2,3,and4(VP0,VP1,VP2,VP3,andVP4)ControlRegisters HEXADDRESSRANGE ACRONYM DESCRIPTION VP0 VP1 VP2 VP3 VP4 VideoPortPeripheralIdentification 0x02C00000 0x02C04000 0x02C08000 0x02C0C000 0x02C10000 VPPID Register 0x02C00004 0x02C04004 0x02C08004 0x02C0C004 0x02C10004 PCR VideoPortPeripheralControlRegister 0x02C00008 0x02C04008 0x02C08008 0x02C0C008 0x02C10008 - Reserved 0x02C0000C 0x02C0400C 0x02C0800C 0x02C0C00C 0x02C1000C - Reserved 0x02C00020 0x02C04020 0x02C08020 0x02C0C020 0x02C10020 PFUNC VideoPortPinFunctionRegister 0x02C00024 0x02C04024 0x02C08024 0x02C0C024 0x02C10024 PDIR VideoPortPinDirectionRegister 0x02C00028 0x02C04028 0x02C08028 0x02C0C028 0x02C10028 PDIN VideoPortPinDataInputRegister 0x02C0002C 0x02C0402C 0x02C0802C 0x02C0C02C 0x02C1002C PDOUT VideoPortPinDataOutputRegister 0x02C00030 0x02C04030 0x02C08030 0x02C0C030 0x02C10030 PDSET VideoPortPinDataSetRegister 0x02C00034 0x02C04034 0x02C08034 0x02C0C034 0x02C10034 PDCLR VideoPortPinDataClearRegister 0x02C00038 0x02C04038 0x02C08038 0x02C0C038 0x02C10038 PIEN VideoPortPinInterruptEnableRegister 0x02C0003C 0x02C0403C 0x02C0803C 0x02C0C03C 0x02C1003C PIPOL VideoPortPinInterruptPolarityRegister 0x02C00040 0x02C04040 0x02C08040 0x02C0C040 0x02C10040 PISTAT VideoPortPinInterruptStatusRegister 0x02C00044 0x02C04044 0x02C08044 0x02C0C044 0x02C10044 PICLR VideoPortPinInterruptClearRegister 0x02C000C0 0x02C040C0 0x02C080C0 0x02C0C0C0 0x02C100C0 VPCTL VideoPortControlRegister 0x02C000C4 0x02C040C4 0x02C080C4 0x02C0C0C4 0x02C100C4 VPSTAT VideoPortStatusRegister 0x02C000C8 0x02C040C8 0x02C080C8 0x02C0C0C8 0x02C100C8 VPIE VideoPortInterruptEnableRegister 0x02C000CC 0x02C040CC 0x02C080CC 0x02C0C0CC 0x02C100CC VPIS VideoPortinterruptStatusRegister 0x02C00100 0x02C04100 0x02C08100 0x02C0C100 0x02C10100 VCASTAT VideoCaptureChannelAStatusRegister VideoCaptureChannelAControl 0x02C00104 0x02C04104 0x02C08104 0x02C0C104 0x02C10104 VCACTL Register 118 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-48.VideoPort0,1,2,3,and4(VP0,VP1,VP2,VP3,andVP4)ControlRegisters(continued) HEXADDRESSRANGE ACRONYM DESCRIPTION VP0 VP1 VP2 VP3 VP4 VideoCaptureChannelAField1Start 0x02C00108 0x02C04108 0x02C08108 0x02C0C108 0x02C10108 VCASTRT1 Register VideoCaptureChannelAField1Stop 0x02C0010C 0x02C0410C 0x02C0810C 0x02C0C10C 0x02C1010C VCASTOP1 Register VideoCaptureChannelAField2Start 0x02C00110 0x02C04110 0x02C08110 0x02C0C110 0x02C10110 VCASTRT2 Register VideoCaptureChannelAField2Stop 0x02C00114 0x02C04114 0x02C08114 0x02C0C114 0x02C10114 VCASTOP2 Register VideoCaptureChannelAVertical 0x02C00118 0x02C04118 0x02C08118 0x02C0C118 0x02C10118 VCAVINT InterruptRegister VideoCaptureChannelAThreshold 0x02C0011C 0x02C0411C 0x02C0811C 0x02C0C11C 0x02C1011C VCATHRLD Register VideoCaptureChannelAEventCount 0x02C00120 0x02C04120 0x02C08120 0x02C0C120 0x02C10120 VCAEVTCT Register 0x02C00140 0x02C04140 0x02C08140 0x02C0C140 0x02C10140 VCBSTAT VideoCaptureChannelBStatusRegister VideoCaptureChannelBControl 0x02C00144 0x02C04144 0x02C08144 0x02C0C144 0x02C10144 VCBCTL Register VideoCaptureChannelBField1Start 0x02C00148 0x02C04148 0x02C08148 0x02C0C148 0x02C10148 VCBSTRT1 Register VideoCaptureChannelBField1Stop 0x02C0014C 0x02C0414C 0x02C0814C 0x02C0C14C 0x02C1014C VCBSTOP1 Register VideoCaptureChannelBField2Start 0x02C00150 0x02C04150 0x02C08150 0x02C0C150 0x02C10150 VCBSTRT2 Register VideoCaptureChannelBField2Stop 0x02C00154 0x02C04154 0x02C08154 0x02C0C154 0x02C10154 VCBSTOP2 Register VideoCaptureChannelBVertical 0x02C00158 0x02C04158 0x02C08158 0x02C0C158 0x02C10158 VCBVINT InterruptRegister VideoCaptureChannelBThreshold 0x02C0015C 0x02C0415C 0x02C0815C 0x02C0C15C 0x02C1015C VCBTHRLD Register VideoCaptureChannelBEventCount 0x02C00160 0x02C04160 0x02C08160 0x02C0C160 0x02C10160 VCBEVTCT Register 0x02C00180 0x02C04180 0x02C08180 0x02C0C180 0x02C10180 TCICTL TCICaptureControlRegister 0x02C00184 0x02C04184 0x02C08184 0x02C0C184 0x02C10184 TCICLKINITL TCIClockInitializationLSBRegister 0x02C00188 0x02C04188 0x02C08188 0x02C0C188 0x02C10188 TCICLKINITM TCIClockInitializationMSBRegister 0x02C0018C 0x02C0418C 0x02C0818C 0x02C0C18C 0x02C1018C TCISTCLKL TCISystemTimeClockLSBRegister 0x02C00190 0x02C04190 0x02C08190 0x02C0C190 0x02C10190 TCISTCLKM TCISystemTimeClockMSBRegister TCISystemTimeClockCompareLSB 0x02C00194 0x02C04194 0x02C08194 0x02C0C194 0x02C10194 TCISTCMPL Register TCISystemTimeClockCompareMSB 0x02C00198 0x02C04198 0x02C08198 0x02C0C198 0x02C10198 TCISTCMPM Register TCISystemTimeClockCompareMask 0x02C0019C 0x02C0419C 0x02C0819C 0x02C0C19C 0x02C1019C TCISTMSKL LSBRegister TCISystemTimeClockCompareMask 0x02C001A0 0x02C041A0 0x02C081A0 0x02C0C1A0 0x02C101A0 TCISTMSKM MSBRegister TCISystemTimeClockTicksInterrupt 0x02C001A4 0x02C041A4 0x02C081A4 0x02C0C1A4 0x02C101A4 TCITICKS Register 0x02C00200 0x02C04200 0x02C08200 0x02C0C200 0x02C10200 VDSTAT VideoDisplayStatusRegister 0x02C00204 0x02C04204 0x02C08204 0x02C0C204 0x02C10204 VDCTL VideoDisplayControlRegister 0x02C00208 0x02C04208 0x02C08208 0x02C0C208 0x02C10208 VDFRMSZ VideoDisplayFrameSizeRegister VideoDisplayHorizontalBlanking 0x02C0020C 0x02C0420C 0x02C0820C 0x02C0C20C 0x02C1020C VDHBLNK Register VideoDisplayField1VerticalBlanking 0x02C00210 0x02C04210 0x02C08210 0x02C0C210 0x02C10210 VDVBLKS1 StartRegister VideoDisplayField1VerticalBlanking 0x02C00214 0x02C04214 0x02C08214 0x02C0C214 0x02C10214 VDVBLKE1 EndRegister VideoDisplayField2VerticalBlanking 0x02C00218 0x02C04218 0x02C08218 0x02C0C218 0x02C10218 VDVBLKS2 StartRegister VideoDisplayField2VerticalBlanking 0x02C0021C 0x02C0421C 0x02C0821C 0x02C0C21C 0x02C1021C VDVBLKE2 EndRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 119 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-48.VideoPort0,1,2,3,and4(VP0,VP1,VP2,VP3,andVP4)ControlRegisters(continued) HEXADDRESSRANGE ACRONYM DESCRIPTION VP0 VP1 VP2 VP3 VP4 VideoDisplayField1ImageOffset 0x02C00220 0x02C04220 0x02C08220 0x02C0C220 0x02C10220 VDIMGOFF1 Register VideoDisplayField1ImageSize 0x02C00224 0x02C04224 0x02C08224 0x02C0C224 0x02C10224 VDIMGSZ1 Register VideoDisplayField2ImageOffset 0x02C00228 0x02C04228 0x02C08228 0x02C0C228 0x02C10228 VDIMGOFF2 Register VideoDisplayField2ImageSize 0x02C0022C 0x02C0422C 0x02C0822C 0x02C0C22C 0x02C1022C VDIMGSZ2 Register 0x02C00230 0x02C04230 0x02C08230 0x02C0C230 0x02C10230 VDFLDT1 VideoDisplayField1TimingRegister 0x02C00234 0x02C04234 0x02C08234 0x02C0C234 0x02C10234 VDFLDT2 VideoDisplayField2TimingRegister 0x02C00238 0x02C04238 0x02C08238 0x02C0C238 0x02C10238 VDTHRLD VideoDisplayThresholdRegister VideoDisplayHorizontalSynchronization 0x02C0023C 0x02C0423C 0x02C0823C 0x02C0C23C 0x02C1023C VDHSYNC Register VideoDisplayField1Vertical 0x02C00240 0x02C04240 0x02C08240 0x02C0C240 0x02C10240 VDVSYNS1 SynchronizationStartRegister VideoDisplayField1Vertical 0x02C00244 0x02C04244 0x02C08244 0x02C0C244 0x02C10244 VDVSYNE1 SynchronizationEndRegister VideoDisplayField2Vertical 0x02C00248 0x02C04248 0x02C08248 0x02C0C248 0x02C10248 VDVSYNS2 SynchronizationStartRegister VideoDisplayField2Vertical 0x02C0024C 0x02C0424C 0x02C0824C 0x02C0C24C 0x02C1024C VDVSYNE2 SynchronizationEndRegister 0x02C00250 0x02C04250 0x02C08250 0x02C0C250 0x02C10250 VDRELOAD VideoDisplayCounterReloadRegister 0x02C00254 0x02C04254 0x02C08254 0x02C0C254 0x02C10254 VDDISPEVT VideoDisplayEventRegister 0x02C00258 0x02C04258 0x02C08258 0x02C0C258 0x02C10258 VDCLIP VideoDisplayClippingRegister VideoDisplayDefaultDisplayValue 0x02C0025C 0x02C0425C 0x02C0825C 0x02C0C25C 0x02C1025C VDDEFVAL Register 0x02C00260 0x02C04260 0x02C08260 0x02C0C260 0x02C10260 VDVINT VideoDisplayVerticalInterruptRegister 0x02C00264 0x02C04264 0x02C08264 0x02C0C264 0x02C10264 VDFBIT VideoDisplayFieldBitRegister VideoDisplayField1VerticalBlankingBit 0x02C00268 0x02C04268 0x02C08268 0x02C0C268 0x02C10268 VDVBIT1 Register VideoDisplayField2VerticalBlankingBit 0x02C0026C 0x02C0426C 0x02C0826C 0x02C0C26C 0x02C1026C VDVBIT2 Register 0x50000000 0x54000000 0x58000000 0x60000000 0x64000000 YSRCA YFIFOSourceRegisterA 0x50000020 0x54000020 0x58000020 0x60000020 0x64000020 CBSRCA CBFIFOSourceRegisterA 0x50000040 0x54000040 0x58000040 0x60000040 0x64000040 CRSRCA CRFIFOSourceRegisterA 0x50000080 0x54000080 0x58000080 0x60000080 0x64000080 YDSTA YFIFODestinationRegisterA 0x500000A0 0x540000A0 0x580000A0 0x600000A0 0x640000A0 CBDST CBFIFODestinationRegister 0x500000C0 0x540000C0 0x580000C0 0x600000C0 0x640000C0 CRDST CRFIFODestinationRegister 0x52000000 0x56000000 0x5A000000 0x62000000 0x66000000 YSRCB YFIFOSourceRegisterB 0x52000020 0x56000020 0x5A000020 0x62000020 0x66000020 CBSRCB CBFIFOSourceRegisterB 0x52000040 0x56000040 0x5A000040 0x62000040 0x66000040 CRSRCB CRFIFOSourceRegisterB 0x52000080 0x56000080 0x5A000080 0x62000080 0x66000080 YDSTB YFIFODestinationRegisterB 120 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.11.3 Video Port (VP0, VP1, VP2, VP3, VP4) Electrical Data/Timing 6.11.3.1 VCLKINTiming(VideoCaptureMode) Table6-49.TimingRequirementsforVideoCaptureModeforVPxCLKINx(1) (seeFigure6-27) -720 -800 NO. -900 UNIT -1100 MIN MAX 1 t Cycletime,VPxCLKINx 9.259 ns c(VKI) 2 t Pulseduration,VPxCLKINxhigh 4.2 ns w(VKIH) 3 t Pulseduration,VPxCLKINxlow 4.2 ns w(VKIL) 4 t Transitiontime,VPxCLKINx 3 ns t(VKI) (1) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. IL IH 1 4 2 3 VPxCLKINx 4 Figure6-27.VideoPortCaptureVPxCLKINxTIming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 121 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.11.3.2 VideoDataandControlTiming(VideoCaptureMode) Table6-50.TimingRequirementsinVideoCaptureModeforVideoDataandControlInputs (seeFigure6-28) -720 -800 NO. -900 UNIT -1100 MIN MAX 1 t Setuptime,VPxDxvalidbeforeVPxCLKINxhigh 2.4 ns su(VDATV-VKIH) 2 t Holdtime,VPxDxvalidafterVPxCLKINxhigh 0.5 ns h(VDATV-VKIH) 3 t Setuptime,VPxCTLxvalidbeforeVPxCLKINxhigh 2.4 ns su(VCTLV-VKIH) 4 t Holdtime,VPxCTLxvalidafterVPxCLKINxhigh 0.5 ns h(VCTLV-VKIH) VPxCLKINx 1 2 VPxD[19:0] (Input) 3 4 VPxCTLx (Input) Figure6-28.VideoPortCaptureDataandControlInputTiming 122 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.11.3.3 VCLKINTiming(VideoDisplayMode) Table6-51.TimingRequirementsforVideoDisplayModeforVPxCLKINx(1)(seeFigure6-29) -720 -800 NO. -900 UNIT -1100 MIN MAX 1 t Cycletime,VPxCLKINx 9 ns c(VKI) 2 t Pulseduration,VPxCLKINxhigh 4.1 ns w(VKIH) 3 t Pulseduration,VPxCLKINxlow 4.1 ns w(VKIL) 4 t Transitiontime,VPxCLKINx 3 ns t(VKI) (1) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. IL IH 1 4 2 3 VPxCLKINx 4 Figure6-29.VideoPortDisplayVPxCLKINxTiming 6.11.3.4 VideoControlInput/OutputandVideoDisplayDataOutputTimingWithRespecttoVPxCLKINx andVPxCLKOUTx(VideoDisplayMode) Table6-52.TimingRequirementsinVideoDisplayModeforVideoControlInputShownWithRespectto VPxCLKINxandVPxCLKOUTx(seeFigure6-30) -720 -800 NO. -900 UNIT -1100 MIN MAX 13 t Setuptime,VPxCTLxvalidbeforeVPxCLKINxhigh 2.4 ns su(VCTLV-VKIH) 14 t Holdtime,VPxCTLxvalidafterVPxCLKINxhigh 0.5 ns h(VCTLV-VKIH) 15 t Setuptime,VPxCTLxvalidbeforeVPxCLKOUTxhigh(1) 7.4 ns su(VCTLV-VKOH) 16 t Holdtime,VPxCTLxvalidafterVPxCLKOUTxhigh(1) -0.9 ns h(VCTLV-VKOH) (1) Assumingnon-invertedVPxCLKOUTxsignal. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 123 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-53.SwitchingCharacteristicsOverRecommendedOperatingConditionsinVideoDisplayMode forVideoDataandControlOutputShownWithRespecttoVPxCLKINxandVPxCLKOUTx(1) (2) (seeFigure6-30) -720 -800 NO. PARAMETER -900 UNIT -1100 MIN MAX 1 t Cycletime,VPxCLKOUTx V-0.7 V+0.7 ns c(VKO) 2 t Pulseduration,VPxCLKOUTxhigh VH-0.7 VH+0.7 ns w(VKOH) 3 t Pulseduration,VPxCLKOUTxlow VL-0.7 VL+0.7 ns w(VKOL) 4 t Transitiontime,VPxCLKOUTx 1.8 ns t(VKO) 5 t Delaytime,VPxCLKINxhightoVPxCLKOUTxhigh(3) 5 ns d(VKIH-VKOH) 6 t Delaytime,VPxCLKINxlowtoVPxCLKOUTxlow(3) 5 ns d(VKIL-VKOL) 7 t Delaytime,VPxCLKINxhightoVPxCLKOUTxlow 5 ns d(VKIH-VKOL) 8 t Delaytime,VPxCLKINxlowtoVPxCLKOUTxhigh 5 ns d(VKIL-VKOH) 9 t Delaytime,VPxCLKINxhightoVPxOUTvalid(4) 7 ns d(VKIH-VPOUTV) 10 t Delaytime,VPxCLKINxhightoVPxOUTinvalid(4) 1.7 ns d(VKIH-VPOUTIV) 11 t Delaytime,VPxCLKOUTxhightoVPxOUTvalid(1) (4) 4.7 ns d(VKOH-VPOUTV) 12 t Delaytime,VPxCLKOUTxhightoVPxOUTinvalid(1) (4) 0.7 ns d(VKOH-VPOUTIV) (1) V=thevideoinputclock(VPxCLKINx)periodinns. (2) VHisthehighperiodofV(videoinputclockperiod)innsandVListhelowperiodofV(videoinputclockperiod)inns. (3) Assumingnon-invertedVPxCLKOUTxsignal. (4) VPxOUTconsistsofVPxCTLxandVPxD[19:0] VPxCLKINx 5 2 1 6 VPxCLKOUTx 3 [VCLK2P = 0] 4 7 4 VPxCLKOUTx 8 (Inverted) [VCLK2P = 1] 12 11 VPxCTLx,V 9 10 PxD[19:0] (Outputs) 15 16 14 13 VPxCTLx (Input) Figure6-30.VideoPortDisplayDataOutputTimingandControlInput/OutputTimingWithRespectto VPxCLKINxandVPxCLKOUTx 124 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.11.3.5 VideoDual-DisplaySyncModeTiming(WithRespecttoVPxCLKINx) Table6-54.TimingRequirementsforDual-DisplaySyncModeforVPxCLKINx(seeFigure6-31) -720<br Placement="li ne"/>-800<br NO. Placement="li UNIT ne"/>-900 -1100 MIN MAX 1 t Skewrate,VPxCLKINxbeforeVPyCLKINy ±500 ps skr(VKI) VPxCLKINx 1 VPyCLKINy Figure6-31.VideoPortDual-DisplaySyncTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 125 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.12 VCXO Interpolated Control (VIC) The VIC can be used in conjunction with the video ports (VPs) to maintain synchronization of a video stream.TheVICcanalsobeusedtocontrolaVCXOtoadjustthepixelclockratetoavideoport. 6.12.1 VIC Device-Specific Information The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9- bitstoupto16-bits.TheoutputoftheVICisasinglebitinterpolatedD/Aoutput(VDACpin). Typical D/A converters provide a discrete output level for every value of the digital word that is being converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by choosing a few widely spaced output levels and interpolating values between them. The interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that theaverageoutputrepresentsthevalueofinputcode. In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependentontheresolutionneeded. When the video port is used in transport channel interface (TCI) mode, the VIC port is used to control the systemclock,VCXO,forMPEGtransportstream. TheVICsupportsthefollowingfeatures: • SingleinterpolationforD/Aconversion • Programmableprecisionfrom9-to-16bits • Interfaceforregisteraccesses For more detailed information on the VCXO interpolated control (VIC) peripheral, see the TMS320DM647/DM648VideoPortUser'sGuide(literaturenumberSPRUEM1). 6.12.2 VIC Peripheral Register Description(s) Table6-55.VCXOInterpolatedControl(VIC)PortRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x02047400 VICCTL VICcontrolregister 0x02047404 VICIN VICinputregister 0x02047408 VPDIV VICclockdividerregister 0x0204740C-0x020477FF - Reserved 126 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.12.3 VIC Electrical Data/Timing 6.12.3.1 STCLKTiming Table6-56.TimingRequirementsforSTCLK(1)(seeFigure6-32) -720 -800 NO. -900 UNIT -1100 MIN MAX 1 t Cycletime,STCLK 33.3 ns c(STCLK) 2 t Pulseduration,STCLKhigh 16 ns w(STCLKH) 3 t Pulseduration,STCLKlow 16 ns w(STCLKL) 4 t Transitiontime,STCLK 3 ns t(STCLK) (1) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. IL IH 1 4 2 3 STCLK 4 Figure6-32.STCLKTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 127 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.13 Universal Asynchronous Receiver/Transmitter (UART) ThedevicehasaUARTperipheral.TheUARThasthefollowingfeatures: • 16-bytestoragespaceforboththetransmitterandreceiverFIFOs • 1,4,8,or14byteselectablereceiverFIFOtriggerlevelforautoflowcontrolandDMA • DMAsignalingcapabilityforbothreceivedandtransmitteddata • Programmableauto-rtsandauto-ctsforautoflowcontrol • Frequencypre-scalevaluesfrom1to65,535togenerateappropriatebaudrates • Prioritizedinterrupts • Programmableserialdataformats – 5,6,7,or8-bitcharacters – Even,odd,ornoparitybitgenerationanddetection – 1,1.5,or2stopbitgeneration • Falsestartbitdetection • Linebreakgenerationanddetection • Internaldiagnosticcapabilities – Loopbackcontrolsforcommunicationslinkfaultisolation – Break,parity,overrun,andframingerrorsimulation • Modemcontrolfunctions(CTS,RTS). TheUARTregistersarelistedinTable6-57. 6.13.1 UART Peripheral Register Description(s) Table6-57.UARTRegisterDescriptions HEXADDRESSRANGE ACRONYM REGISTERNAME 0x02047000 RBR UARTReceiverBufferRegister(ReadOnly) 0x02047000 THR UARTTransmitterHoldingRegister(WriteOnly) 0x02047004 IER UARTInterruptEnableRegister 0x02047008 IIR UARTInterruptIdentificationRegister(ReadOnly) 0x02047008 FCR UARTFIFOControlRegister(WriteOnly) 0x0204700C LCR UARTLineControlRegister 0x02047010 MCR UARTModemControlRegister 0x02047014 LSR UARTLineStatusRegister 0x02047018 - Reserved 0x0204701C - Reserved 0x02047020 DLL UARTDivisorLatch(LSB) 0x02047024 DLH UARTDivisorLatch(MSB) 0x02047028 PID PeripheralIdentificationRegister 0x0204702C Reserved 0x02047030 PWREMU_MGMT UARTPowerandEmulationManagementRegister 0x02047034 MDR ModeDefinitionRegister 0x02047038-0x020473FF - Reserved 128 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.13.2 UART Electrical Data/Timing Table6-58.TimingRequirementsforUARTxReceive(1)(seeFigure6-33) 720,800,900,1100 NO. UNIT MIN MAX 4 t Pulseduration,receivedatabit(RXDn)[15/30/100pF] 0.96U 1.05U ns w(URXDB) 5 t Pulseduration,receivestartbit[15/30/100pF] 0.96U 1.05U ns w(URXSB) (1) U=UARTbaudtime=1/programmedbaudrate. Table6-59.SwitchingCharacteristicsOverRecommendedOperatingConditionsforUARTxTransmit(1) (seeFigure6-33) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 1 f Maximumprogrammablebaudrate 5 MHz (baud) 2 t Pulseduration,transmitdatabit(TXDn)[15/30/100pF] U-2 U+2 ns w(UTXDB) 3 t Pulseduration,transmitstartbit[15/30/100pF] U-2 U+2 ns w(UTXSB) (1) U=UARTbaudtime=1/programmedbaudrate. 3 2 Start UART_TXDn Bit Data Bits 5 4 Start UART_RXDn Bit Data Bits Figure6-33.UARTTransmit/ReceiveTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 129 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.14 Serial Peripheral Interface Port (SPI) 6.14.1 SPI Device-Specific Information Figure 6-34 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate only as a master, in which case, it initiates a transfer and drives the SPICLKpin.Fourclockphaseandpolarityoptionsaresupportedaswellasmanydataformattingoptions. SPIDO SPIDI Peripheral Configuration Bus 16-Bit Shift Register State GPIO Machine SPICSx Control Interrupt and 16-Bit Buffer (all pins) Clock SPICLK DMARequests Control 16-Bit Emulation Buffer Figure6-34.BlockDiagramofSPIModule The SPI supports 3- and 4-pin operation with three basic pins (SPICLK, SPIDO, and SPIDI) and two optionalpins(SPICSx). The optional SPICSx (Slave Chip Select) pin is most useful to enable in master mode when there are more than one slave devices on the same SPI port. The device only shifts data and drives the SPIDI pin whenSPICSxisheldlow. Optional−Slave Chip Select SPICSx SPICSx SPICLK SPICLK SPIDI SPIDO SPIDO SPIDI MASTER SPI SLAVE SPI Figure6-35.IllustrationofSPIMaster-to-SPISlaveConnection 130 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.14.2 SPI Peripheral Register Descriptions Table6-60isalistoftheSPIregisters. Table6-60.SPIConfigurationRegisters SPI0 REGISTERNAME DESCRIPTION BYTEADDRESS 0x02047800 SPIGCR0 GlobalControlRegister0 0x02047804 SPIGCR1 GlobalControlRegister1 0x02047808 SPIINT0 InterruptRegister 0x0204780C SPILVL InterruptLevelRegister 0x02047810 SPIFLG FlagRegister 0x02047814 SPIPC0 PinControlRegister0(PinFunction) 0x02047818 SPIPC1 PinControlRegister1(PinDirection) 0x0204781C SPIPC2 PinControlRegister2(PinDataIn) 0x0204783C SPIDAT1 ShiftRegister1(withformatselect) 0x02047840 SPIBUF BufferRegister 0x02047844 SPIEMU EmulationRegister 0x02047848 SPIDELAY DelayRegister 0x0204784C SPIDEF DefaultChipSelectRegister 0x02047850 SPIFMT0 FormatRegister0 0x02047854 SPIFMT1 FormatRegister1 0x02047858 SPIFMT2 FormatRegister2 0x0204785C SPIFMT3 FormatRegister3 0x02047860 TGINTVECT0 InterruptVectorforSPIINT0 0x02047864 TGINTVECT1 InterruptVectorforSPIINT1 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 131 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.14.3 SPI Electrical Data/Timing 6.14.3.1 SerialPeripheralInterface(SPI)Timing Table6-61assumestestingoverrecommendedoperatingconditions(seeFigure6-36). Table6-61.GeneralTimingRequirementsforSPIxMasterModes(1) NO. MIN MAX UNIT greaterof8Por 1 t CycleTime,SPICLK,AllMasterModes 256P ns c(SPC)M 100ns 2 t PulseWidthHigh,SPICLK,AllMasterModes greaterof4Por45ns ns w(SPCH)M 3 t PulseWidthLow,SPICLK,AllMasterModes greaterof4Por45ns ns w(SPCL)M Polarity=0,Phase=0, 4P toSPICLKrising Polarity=0,Phase=1, Delay,initialdatabitvalid toSPICLKrising 0.5tc(SPC)M+4P 4 t onSPIDOtoinitialedgeon ns d(SIMO_SPC)M SPICLK(2) Polarity=1,Phase=0, 4P toSPICLKfalling Polarity=1,Phase=1, 0.5t +4P toSPICLKfalling c(SPC)M Polarity=0,Phase=0, 15 fromSPICLKrising Polarity=0,Phase=1, Delay,subsequentbits fromSPICLKfalling 15 5 t validonSPIDOafter ns d(SPC_SIMO)M transmitedgeofSPICLK Polarity=1,Phase=0, 15 fromSPICLKfalling Polarity=1,Phase=1, 15 fromSPICLKrising Polarity=0,Phase=0, 0.5t -10 fromSPICLKfalling c(SPC)M Outputholdtime,SPIDO Polarity=0,Phase=1, 0.5t -10 validafter fromSPICLKrising c(SPC)M 6 t ns oh(SPC_SIMO)M receiveedgeofSPICLK, Polarity=1,Phase=0, exceptforfinalbit(3) fromSPICLKrising 0.5tc(SPC)M-10 Polarity=1,Phase=1, 0.5t -10 fromSPICLKfalling c(SPC)M Polarity=0,Phase=0, 0.5P+15 toSPICLKfalling Polarity=0,Phase=1, InputSetupTime,SPIDI toSPICLKrising 0.5P+15 7 t validbefore ns su(SOMI_SPC)M receiveedgeofSPICLK Polarity=1,Phase=0, 0.5P+15 toSPICLKrising Polarity=1,Phase=1, 0.5P+15 toSPICLKfalling Polarity=0,Phase=0, 0.5P+5 fromSPICLKfalling Polarity=0,Phase=1, InputHoldTime,SPIDI fromSPICLKrising 0.5P+5 8 t validafter ns ih(SPC_SOMI)M receiveedgeofSPICLK Polarity=1,Phase=0, 0.5P+5 fromSPICLKrising Polarity=1,Phase=1, 0.5P+5 fromSPICLKfalling (1) P=SYSCLK3period (2) FirstbitmaybeMSBorLSBdependinguponSPIconfiguration.MO(0)referstofirstbitandMO(n)referstolastbitoutputonSPIDO. MI(0)referstothefirstbitinputandMI(n)referstothelastbitinputonSPIDI. (3) ThefinaldatabitwillbeheldontheSPIDOpinuntiltheSPIDAT1registeriswrittenwithnewdata. 132 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 1 Master Mode Polarity = 0 Phase = 0 2 3 SPICLK 4 5 6 SPIDO MO(0) MO(1) MO(n−1) MO(n) 7 8 SPIDI MI(0) MI(1) MI(n−1) MI(n) Master Mode Polarity = 0 Phase = 1 4 SPICLK 5 6 SPIDO MO(0) MO(1) MO(n−1) MO(n) 7 8 SPIDI MI(0) MI(1) MI(n−1) MI(n) 4 Master Mode Polarity = 1 Phase = 0 SPICLK 5 6 SPIDO MO(0) MO(1) MO(n−1) MO(n) 7 8 SPIDI MI(0) MI(1) MI(n−1) MI(n) Master Mode Polarity = 1 Phase = 1 SPICLK 4 5 6 SPIDO MO(0) MO(1) MO(n−1) MO(n) 7 8 SPIDI MI(0) MI(1) MI(n−1) MI(n) Figure6-36.SPITimings—MasterMode Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 133 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.15 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between the DM647/DM648 device and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSPthroughtheI2Cmodule.TheI2CportdoesnotsupportCBUS-compatibledevices. TheI2Cportsupports: • CompatiblewithPhilipsI2CSpecificationRevision2.1(January2000) • FastModeupto400Kbps(nofail-safeI/Obuffers) • NoiseFiltertoRemoveNoise50nsorless • Seven-andTen-BitDeviceAddressingModes • Master(Transmit/Receive)andSlave(Transmit/Receive)Functionality • Events:DMA,Interrupt,orPolling • Slew-RateLimitedOpen-DrainOutputBuffers I2C Module Clock Prescale Peripheral Clock (DSP/6) I2CPSC Control Bit Clock Own SCL Generator I2COAR Address Noise I2C Clock Filter I2CCLKH Slave I2CSAR Address I2CCLKL I2CMDR Mode Data Transmit I2CCNT Count Transmit I2CXSR Extended Shift I2CEMDR Mode Transmit I2CDXR Buffer SDA Noise Interrupt/DMA I2C Data Filter Interrupt Receive I2CIMR Mask/Status Receive I2CDRR Buffer I2CSTR ISnttaetrursupt Receive Interrupt I2CRSR Shift I2CIVR Vector Shading denotes control/status registers. Figure6-37.I2CModuleBlockDiagram For more detailed information on the I2C peripheral, see the TMS320DM647/DM648 DSP Inter-Integrated Circuit(I2C)ModuleUser'sGuide(literaturenumberSPRUEK8). 134 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.15.1 I2C Peripheral Register Description(s) Table6-62.I2CRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x02047C00 ICOAR I2COwnAddressRegister 0x02047C04 ICIMR I2CInterruptMaskRegister 0x02047C08 ICSTR I2CInterruptStatusRegister 0x02047C0C ICCLKL I2CClockDividerLowRegister 0x02047C10 ICCLKH I2CClockDividerHighRegister 0x02047C14 ICCNT I2CDataCountRegister 0x02047C18 ICDRR I2CDataReceiveRegister 0x02047C1C ICSAR I2CSlaveAddressRegister 0x02047C20 ICDXR I2CDataTransmitRegister 0x02047C24 ICMDR I2CModeRegister 0x02047C28 ICIVR I2CInterruptVectorRegister 0x02047C2C ICEMDR I2CExtendedModeRegister 0x02047C30 ICPSC I2CPrescalerRegister 0x02047C34 ICDMAC I2CDMAControlRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 135 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.15.2 I2C Electrical Data/Timing 6.15.2.1 Inter-IntegratedCircuits(I2C)Timing Table6-63.TimingRequirementsforI2CTimings(1)(seeFigure6-38) 720,800,900,1100 STANDARD NO. FASTMODE UNIT MODE MIN MAX MIN MAX 1 t Cycletime,SCL 10 2.5 µs c(SCL) Setuptime,SCLhighbeforeSDAlow(forarepeatedSTART 2 t 4.7 0.6 µs su(SCLH-SDAL) condition) Holdtime,SCLlowafterSDAlow(foraSTARTandarepeated 3 t 4 0.6 µs h(SCLL-SDAL) STARTcondition) 4 t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) 5 t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) 6 t Setuptime,SDAvalidbeforeSCLhigh 250 100(2) ns su(SDAV-SCLH) 7 t Holdtime,SDAvalidafterSCLlow 0(3) 0(3) 0.9(4) µs h(SDA-SCLL) 8 t Pulseduration,SDAhighbetweenSTOPandSTARTconditions 4.7 1.3 µs w(SDAH) 9 t Risetime,SDA 1000 20+0.1C (5) 300 ns r(SDA) b 10 t Risetime,SCL 1000 20+0.1C (5) 300 ns r(SCL) b 11 t Falltime,SDA 300 20+0.1C (5) 300 ns f(SDA) b 12 t Falltime,SCL 300 20+0.1C (5) 300 ns f(SCL) b 13 t Setuptime,SCLhighbeforeSDAhigh(forSTOPcondition) 4 0.6 µs su(SCLH-SDAH) 14 t Pulseduration,spike(mustbesuppressed) 0 50 ns w(SP) 15 C (5) Capacitiveloadforeachbusline 400 400 pF b (1) TheI2CpinsSDAandSCLdonotfeaturefail-safeI/Obuffers.Thesepinscouldpotentiallydrawcurrentwhenthedeviceispowered down. (2) AFast-modeI2C-bus™devicecanbeusedinastandard-modeI2C-bussystem,buttherequirementt ≥250nsmustthenbe su(SDA-SCLH) met.ThiswillbethecaseautomaticallyifthedevicedoesnotstretchtheLOWperiodoftheSCLsignal.Ifsuchadevicedoesstretch theLOWperiodoftheSCLsignal,itmustoutputthenextdatabittotheSDAlinet max+t =1000+250=1250ns r su(SDA-SCLH) (accordingtotheStandard-modeI2C-BusSpecification)beforetheSCLlineisreleased. (3) Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignal(referredtotheV oftheSCLsignal)tobridgethe IHmin undefinedregionofthefallingedgeofSCL. (4) Themaximumt hastobemetonlyifthedevicedoesnotstretchthelowperiod[t ]oftheSCLsignal. h(SDA-SCLL) w(SCLL) (5) C =totalcapacitanceofonebuslineinpF.IfmixedwithHS-modedevices,fasterfall-timesareallowed. b 11 9 SDA 8 6 14 4 13 10 5 SCL 1 12 3 7 2 3 Stop Start Repeated Stop Start Figure6-38.I2CReceiveTimings 136 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-64.SwitchingCharacteristicsforI2CTimings(1)(seeFigure6-39) 720,800,900,1100 STANDARD NO. PARAMETER FASTMODE UNIT MODE MIN MAX MIN MAX 16 t Cycletime,SCL 10 2.5 µs c(SCL) Delaytime,SCLhightoSDAlow(forarepeatedSTART 17 t 4.7 0.6 µs d(SCLH-SDAL) condition) Delaytime,SDAlowtoSCLlow(foraSTARTanda 18 t 4 0.6 µs d(SDAL-SCLL) repeatedSTARTcondition) 19 t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) 20 t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) 21 t Delaytime,SDAvalidtoSCLhigh 250 100 ns d(SDAV-SCLH) 22 t Validtime,SDAvalidafterSCLlow 0 0 0.9 µs v(SCLL-SDAV) Pulseduration,SDAhighbetweenSTOPandSTART 23 t 4.7 1.3 µs w(SDAH) conditions 20+0.1C 24 tr(SDA) Risetime,SDA 1000 (2b) 300 ns 20+0.1C 25 tr(SCL) Risetime,SCL 1000 (2b) 300 ns 20+0.1C 26 tf(SDA) Falltime,SDA 300 (2b) 300 ns 20+0.1C 27 tf(SCL) Falltime,SCL 300 (2b) 300 ns 28 t Delaytime,SCLhightoSDAhigh(forSTOPcondition) 4 0.6 µs d(SCLH-SDAH) 29 C CapacitanceforeachI2Cpin 10 10 pF p (1) C =totalcapacitanceofonebuslineinpF.IfmixedwithHS-modedevices,fasterfall-timesareallowed. b (2) C =totalcapacitanceofonebuslineinpF.IfmixedwithHS-modedevices,fasterfall-timesareallowed. b 26 24 SDA 23 21 19 28 25 20 SCL 16 27 18 22 17 18 Stop Start Repeated Stop Start Figure6-39.I2CTransmitTimings Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 137 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.16 Host-Port Interface (HPI) Peripheral 6.16.1 HPI Device-Specific Information The device includes a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32). The AEA14 pin controlstheHPI_WIDTH,allowingtheusertoconfiguretheHPIasa16-bitor32-bitperipheral. SoftwarehandshakingviatheHRDYbitoftheHostPortControlRegister(HPIC)isnotsupported. An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel0. 6.16.2 HPI Peripheral Register Description(s) Table6-65.HPIControlRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS 0x02000000 PID PeripheralIdentificationRegister HPIpowerandemulationmanagement PWREMU_MGMThasbothhost/CPU 0x02000004 PWREMU_MGMT register read/writeaccess. 0x02000008-0x02000024 - Reserved 0x02000028 - Reserved 0x0200002C - Reserved ThehostandtheCPUhaveread/write 0x02000030 HPIC HPIcontrolregister accesstotheHPICregister.(1) HPIA HPIaddressregister 0x02000034 (HPIAW)(2) (Write) Thehosthasread/writeaccesstothe HPIAregisters.TheCPUhasread 0x02000038 (HPHIPAIRA)(2) H(RPeIaadd)dressregister accessonlytotheHPIAregisters. 0x0200003C-0x0200007F - Reserved (1) TheCPUcanwrite1totheHINTbittogenerateaninterrupttothehostanditcanwrite1totheDSPINTbittoclear/acknowledgean interruptfromthehost. (2) Therearetwo32-bitHPIAregisters:HPIARforreadoperationsandHPIAWforwriteoperations.TheHPIcanbeconfiguredsuchthat HPIARandHPIAWactasasingle32-bitHPIA(single-HPIAmode)orastwoseparate32-bitHPIAs(dual-HPIAmode)fromthe perspectiveofthehost.TheCPUcanaccessHPIAWandHPIARindependently.FordetailsabouttheHPIAregistersandtheirmodes, seetheTMS320DM647/DM648DSPHostPortInterface(HPI)User'sGuide(literaturenumberSPRUEL5). 138 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.16.3 HPI Electrical Data/Timing Table6-66.TimingRequirementsforHost-PortInterfaceCycles(1) (2)(seeFigure6-40throughFigure6- 47) 720,800,900,1100 NO. UNIT MIN MAX 9 t Setuptime,HASlowbeforeHSTROBElow 5 ns su(HASL-HSTBL) 10 t Holdtime,HASlowafterHSTROBElow 2 ns h(HSTBL-HASL) 11 t Setuptime,selectsignals(3)validbeforeHASlow 5 ns su(SELV-HASL) 12 t Holdtime,selectsignals(3)validafterHASlow 5 ns h(HASL-SELV) 13 t Pulseduration,HSTROBElow 2M ns w(HSTBL) 14 t Pulseduration,HSTROBEhighbetweenconsecutiveaccesses 2M ns w(HSTBH) 15 t Setuptime,selectsignals(3)validbeforeHSTROBElow 5 ns su(SELV-HSTBL) 16 t Holdtime,selectsignals(3)validafterHSTROBElow 5 ns h(HSTBL-SELV) 17 t Setuptime,hostdatavalidbeforeHSTROBEhigh 5 ns su(HDV-HSTBH) 18 t Holdtime,hostdatavalidafterHSTROBEhigh 1 ns h(HSTBH-HDV) 37 t Setuptime,HCSlowbeforeHSTROBElow 0 ns su(HCSL-HSTBL) Holdtime,HSTROBElowafterHRDYlow.HSTROBEshouldnotbe 38 t inactivateduntilHRDYisactive(low);otherwise,HPIwriteswillnot 1.1 ns h(HRDYL-HSTBL) completeproperly. (1) HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. (2) M=SYSCLK3period=6/CPUclockfrequencyinns. (3) Selectsignalsinclude:HCNTL[1:0]andHR/W.ForHPI16modeonly,selectsignalsalsoincludeHHWIL. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 139 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-67.SwitchingCharacteristicsforHost-PortInterfaceCycles(1) (2) (seeFigure6-40throughFigure6-47) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX Case1.HPICorHPIAread 5 15 Case2.HPIDreadwithnoauto- increment(3) 9×M+20 1 td(HSTBL-HDV) DDeSlPaydtaimtaev,aHliSdTROBElowto Canadsere3a.dHFPIIFDOreinaitdiawllyithemaupttoy-(i3n)crement 9×M+20 ns Case4.HPIDreadwithauto-increment anddatapreviouslyprefetchedintothe 5 15 readFIFO 2 t Disabletime,HDhigh-impedancefromHSTROBEhigh 1 4 ns dis(HSTBH-HDV) 3 t Enabletime,HDdrivenfromHSTROBElow 3 15 ns en(HSTBL-HD) 4 t Delaytime,HSTROBElowtoHRDYhigh 12 ns d(HSTBL-HRDYH) 5 t Delaytime,HSTROBEhightoHRDYhigh 12 ns d(HSTBH-HRDYH) Case1.HPIDreadwithnoauto- Delaytime,HSTROBElowto increment(3) 10×M+20 6 t ns d(HSTBL-HRDYL) HRDYlow Case2.HPIDreadwithauto-increment andreadFIFOinitiallyempty(3) 10×M+20 7 t Delaytime,HDvalidtoHRDYlow 0 ns d(HDV-HRDYL) Case1.HPIAwrite(3) 5×M+20 Delaytime,HSTROBEhighto 34 td(DSH-HRDYL) HRDYlow Cinacsreem2e.nHt(P3)IDwritewithnoauto- 5×M+20 ns Delaytime,HSTROBElowtoHRDYlowforHPIAwriteandFIFOnot 35 td(HSTBL-HRDYL) empty(3) 40×M+20 ns 36 t Delaytime,HASlowtoHRDYhigh 12 ns d(HASL-HRDYH) (1) M=SYSCLK3period=6/CPUclockfrequencyinns. (2) HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. (3) AssumestheHPIisaccessingL2/L1memoryandnoothermasterisaccessingthesamememorylocation. 140 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 HCS HAS HCNTL[1:0] HR/W HHWIL 13 16 16 15 15 37 13 37 14 HSTROBE 3 3 1 2 1 2 HD[15:0] 38 4 7 6 HRDY A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5). Figure6-40.HPI16ReadTiming(HASNotUsed,TiedHigh) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 141 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com HCS HAS 12 12 11 11 HCNTL[1:0] 12 12 11 11 HR/W 12 12 11 11 HHWIL 10 10 9 9 37 13 13 37 14 HSTROBE(A) 1 1 3 2 3 2 HD[15:0] 7 38 36 6 HRDY(B) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5). Figure6-41.HPI16ReadTiming(HASUsed) 142 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 HCS HAS HCNTL[1:0] HR/W HHWIL 16 16 13 15 15 37 13 37 14 HSTROBE(A) 18 18 17 17 HD[15:0] 34 38 4 5 34 35 5 HRDY(B) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5). Figure6-42.HPI16WriteTiming(HASNotUsed,TiedHigh) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com HCS HAS 12 12 11 11 HCNTL[1:0] 12 12 11 11 HR/W 12 12 11 11 HHWIL 10 10 9 9 37 13 13 37 14 HSTROBE(A) 1 1 3 2 3 2 HD[15:0] 7 38 36 6 HRDY(B) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5). Figure6-43.HPI16WriteTiming(HASUsed) 144 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 HAS(input) 16 15 HCNTL[1:0] (input) HR/W(input) 13 HSTROBE(A)(input) 37 HCS(input) 1 2 3 HD[31:0] (output) 38 7 6 4 HRDY(B)(output) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5) Figure6-44.HPI32ReadTiming(HASNotUsed,TiedHigh) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 10 HAS (input) 12 11 HCNTL[1:0] (input) HR/W (input) 9 13 HSTROBE(A)(input) 37 HCS (input) 1 2 3 HD[31:0] (output) 7 38 6 36 HRDY(B)(output) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5) Figure6-45.HPI32ReadTiming(HASUsed) 146 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 HAS(input) 16 15 HCNTL[1:0] (input) HR/W(input) 13 HSTROBE(A) (input) 37 HCS(input) 18 17 HD[31:0] (input) 38 34 35 5 4 HRDY(B)(output) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5) Figure6-46.HPI32WriteTiming(HASNotUsed,TiedHigh) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 10 HAS(input) 12 11 HCNTL[1:0] (input) HR/W(input) 9 13 HSTROBE(A) (input) 37 HCS(input) 18 17 HD[31:0] (input) 35 34 38 36 5 HRDY(B)(output) A. HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. B. Depending on thetypeofwrite orread operation(HPID withoutauto-incrementing; HPIA, HPIC, orHPIDwithauto- incrementing)andthestateoftheFIFO,transitionsonHRDYmayormaynotoccur.Formoredetailedinformationon the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5) Figure6-47.HPI32WriteTiming(HASUsed) 148 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.17 Peripheral Component Interconnect (PCI) The device supports connections to a PCI backplane via the integrated PCI master/slave bus interface. ThePCIportinterfacestoDSPinternalresourcesviathedataswitchedcentralresource.. For more detailed information on the PCI port peripheral module, see the TMS320DM647/DM648 PeripheralComponentInterconnect(PCI)User'sGuide(literaturenumberSPRUEL4). 6.17.1 PCI Device-Specific Information The PCI peripheral conforms to the PCI Local Bus Specification (version 2.3). The PCI peripheral can act bothasaPCIbusmasterandasatarget.ItsupportsPCIbusoperationofspeedsupto66MHzanduses a32-bitdata/addressbus. The pins of the PCI peripheral are multiplexed with the pins of the HPI, and GPIO peripherals. PCI functionality for these pins is controlled (enabled/disabled) by the UHPIEN pin (H2). The maximum speed of the PCI, 33 MHz or 66 MHz, is controlled through the PCI66 pin (G5). For more detailed information on theperipheralcontrol,seeSection3. The device provides an initialization mechanism through which the default values for some of the PCI configuration registers can be read from an I2C EEPROM. Table 6-68 shows the registers which can be initialized through the PCI auto-initialization. Also shown is the default value of these registers when PCI auto-initialization is not used. PCI auto-initialization is enabled by selecting PCI boot with auto- initialization. For more information on this feature, see the TMS320DM647/DM648 Peripheral Component Interconnect (PCI) User's Guide (literature number SPRUEL4) and the Using the TMS320DM647/DM648 BootloaderApplicationReport(literaturenumberSPRAAJ1). Table6-68.DefaultValuesforPCIConfiguration Registers DEFAULT REGISTER VALUE VendorID/DeviceIDRegister(PCIVENDEV) 104CB003h ClassCode/RevisionIDRegister(PCICLREV) 00000001h SubsystemVendorID/SubsystemIDRegister 00000000h (PCISUBID) MaxLatency/MinGrant/InterruptPin/InterruptLine 00000100h Register(PCILGINT) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.17.2 PCI Peripheral Register Description(s) Table6-69.PCIConfigurationRegisters PCIHOSTACCESS ACRONYM PCIHOSTACCESSREGISTERNAME HEXADDRESSOFFSET 0x00 PCIVENDEV VendorID/DeviceID 0x04 PCICSR Command/Status 0x08 PCICLREV ClassCode/RevisionID 0x0C PCICLINE BIST/HeaderType/LatencyTimer/CachelineSize 0x10 PCIBAR0 BaseAddress0 0x14 PCIBAR1 BaseAddress1 0x18 PCIBAR2 BaseAddress2 0x1C PCIBAR3 BaseAddress3 0x20 PCIBAR4 BaseAddress4 0x24 PCIBAR5 BaseAddress5 0x28-0x2B - Reserved 0x2C PCISUBID SubsystemVendorID/SubsystemID 0x30 - Reserved 0x34 PCICPBPTR CapabilitiesPointer 0x38-0x3B - Reserved 0x3C PCILGINT MaxLatency/MinGrant/InterruptPin/InterruptLine 0x40-0x7F - Reserved Table6-70.PCIBackEndConfigurationRegisters DSPACCESS ACRONYM DSPACCESSREGISTERNAME HEXADDRESSRANGE 0x02048400-0x0204840F - Reserved 0x02048410 PCISTATSET PCIStatusSetRegister 0x02048414 PCISTATCLR PCIStatusClearRegister 0x02048418-0x0204841F - Reserved 0x02048420 PCIHINTSET PCIHostInterruptEnableSetRegister 0x02048424 PCIHINTCLR PCIHostInterruptEnableClearRegister 0x02048428-0x0204842F - Reserved 0x02048430 PCIBINTSET PCIBackEndApplicationInterruptEnableSetRegister 0x02048434 PCIBINTCLR PCIBackEndApplicationInterruptEnableClearRegister 0x02048438 PCIBCLKMGT PCIBackEndApplicationClockManagementRegister 0x0204843C-0x020484FF - Reserved 0x02048500 PCIVENDEVMIR PCIVendorID/DeviceIDMirrorRegister 0x02048504 PCICSRMIR PCICommand/StatusMirrorRegister 0x02048508 PCICLREVMIR PCIClassCode/RevisionIDMirrorRegister 0x0204850C PCICLINEMIR PCIBIST/HeaderType/LatencyTimer/CachelineSizeMirrorRegister 0x02048510 PCIBAR0MSK PCIBaseAddressMaskRegister0 0x02048514 PCIBAR1MSK PCIBaseAddressMaskRegister1 0x02048518 PCIBAR2MSK PCIBaseAddressMaskRegister2 0x0204851C PCIBAR3MSK PCIBaseAddressMaskRegister3 0x02048520 PCIBAR4MSK PCIBaseAddressMaskRegister4 0x02048524 PCIBAR5MSK PCIBaseAddressMaskRegister5 0x02048528-0x0204852B - Reserved 0x0204852C PCISUBIDMIR PCISubsystemVendorID/SubsystemIDMirrorRegister 0x02048530 - Reserved 150 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-70.PCIBackEndConfigurationRegisters(continued) DSPACCESS ACRONYM DSPACCESSREGISTERNAME HEXADDRESSRANGE 0x02048534 PCICPBPTRMIR PCICapabilitiesPointerMirrorRegister 0x02048538-0x0204853B - Reserved 0x0204853C PCILGINTMIR PCIMaxLatency/MinGrant/InterruptPin/InterruptLineMirrorRegister 0x02048540-0x0204857F - Reserved 0x02048580 PCISLVCNTL PCISlaveControlRegister 0x02048584-0x020485BF - Reserved 0x020485C0 PCIBAR0TRL PCISlaveBaseAddress0TranslationRegister 0x020485C4 PCIBAR1TRL PCISlaveBaseAddress1TranslationRegister 0x020485C8 PCIBAR2TRL PCISlaveBaseAddress2TranslationRegister 0x020485CC PCIBAR3TRL PCISlaveBaseAddress3TranslationRegister 0x020485D0 PCIBAR4TRL PCISlaveBaseAddress4TranslationRegister 0x020485D4 PCIBAR5TRL PCISlaveBaseAddress5TranslationRegister 0x020485D8-0x020485DF - Reserved 0x020485E0 PCIBAR0MIR PCIBaseAddressRegister0MirrorRegister 0x020485E4 PCIBAR1MIR PCIBaseAddressRegister1MirrorRegister 0x020485E8 PCIBAR2MIR PCIBaseAddressRegister2MirrorRegister 0x020485EC PCIBAR3MIR PCIBaseAddressRegister3MirrorRegister 0x020485F0 PCIBAR4MIR PCIBaseAddressRegister4MirrorRegister 0x020485F4 PCIBAR5MIR PCIBaseAddressRegister5MirrorRegister 0x020485F8-0x020486FF - Reserved 0x02048700 PCIMCFGDAT PCIMasterConfiguration/IOAccessDataRegister 0x02048704 PCIMCFGADR PCIMasterConfiguration/IOAccessAddressRegister 0x02048708 PCIMCFGCMD PCIMasterConfiguration/IOAccessCommandRegister 0x0204870C-0x0204870F - Reserved 0x02048710 PCIMSTCFG PCIMasterConfigurationRegister Table6-71.PCIHookConfigurationRegisters DSPACCESS ACRONYM DSPACCESSREGISTERNAME HEXADDRESSRANGE 0x02048794 PCIVENDEVPRG PCIVendorIDandDeviceIDProgramRegister 0x02048798 PCICMDSTATPRG PCICommandandStatusProgramRegister 0x0204879C PCICLREVPRG PCIClassCodeandRevisionIDProgramRegister 0x020487A0 PCISUBIDPRG PCISubsystemVendorIDandSubsystemIDProgramRegister 0x020487A4 PCIMAXLGPRG PCIMaxLatencyandMinGrantProgramRegister 0x020487A8 PCILRSTREG PCILRESETRegister 0x020487AC PCICFGDONE PCIConfigurationDoneRegister 0x020487B0 PCIBAR0MPRG PCIBaseAddressMaskRegister0ProgramRegister 0x020487B4 PCIBAR1MPRG PCIBaseAddressMaskRegister1ProgramRegister 0x020487B8 PCIBAR2MPRG PCIBaseAddressMaskRegister2ProgramRegister 0x020487BC PCIBAR3MPRG PCIBaseAddressMaskRegister3ProgramRegister 0x020487C0 PCIBAR4MPRG PCIBaseAddressMaskRegister4ProgramRegister 0x020487C4 PCIBAR5MPRG PCIBaseAddressMaskRegister5ProgramRegister 0x020487C8 PCIBAR0PRG PCIBaseAddressRegister0ProgramRegister 0x020487CC PCIBAR1PRG PCIBaseAddressRegister1ProgramRegister 0x020487D0 PCIBAR2PRG PCIBaseAddressRegister2ProgramRegister 0x020487D4 PCIBAR3PRG PCIBaseAddressRegister3ProgramRegister 0x020487D8 PCIBAR4PRG PCIBaseAddressRegister4ProgramRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-71.PCIHookConfigurationRegisters(continued) DSPACCESS ACRONYM DSPACCESSREGISTERNAME HEXADDRESSRANGE 0x020487DC PCIBAR5PRG PCIBaseAddressRegister5ProgramRegister 0x020487E0 PCIBAR0TRLPRG PCIBaseAddressTranslationRegister0ProgramRegister 0x020487E4 PCIBAR1TRLPRG PCIBaseAddressTranslationRegister1ProgramRegister 0x020487E8 PCIBAR2TRLPRG PCIBaseAddressTranslationRegister2ProgramRegister 0x020487EC PCIBAR3TRLPRG PCIBaseAddressTranslationRegister3ProgramRegister 0x020487F0 PCIBAR4TRLPRG PCIBaseAddressTranslationRegister4ProgramRegister 0x020487F4 PCIBAR5TRLPRG PCIBaseAddressTranslationRegister5ProgramRegister 0x020487F8 PCIBASENPRG PCIBaseEnProgRegister 0x020487FC-0x020487FF - Reserved Table6-72.PCIExternalMemorySpace HEXADDRESSOFFSET ACRONYM REGISTERNAME 0x40000000-0x407FFFFF - PCIMasterWindow0 0x40800000-0x40FFFFFF - PCIMasterWindow1 0x41000000-0x417FFFFF - PCIMasterWindow2 0x41800000-0x41FFFFFF - PCIMasterWindow3 0x42000000-0x427FFFFF - PCIMasterWindow4 0x42800000-0x42FFFFFF - PCIMasterWindow5 0x43000000-0x437FFFFF - PCIMasterWindow6 0x43800000-0x43FFFFFF - PCIMasterWindow7 0x44000000-0x447FFFFF - PCIMasterWindow8 0x44800000-0x44FFFFFF - PCIMasterWindow9 0x45000000-0x457FFFFF - PCIMasterWindow10 0x45800000-0x45FFFFFF - PCIMasterWindow11 0x46000000-0x467FFFFF - PCIMasterWindow12 0x46800000-0x46FFFFFF - PCIMasterWindow13 0x47000000-0x477FFFFF - PCIMasterWindow14 0x47800000-0x47FFFFFF - PCIMasterWindow15 0x48000000-0x487FFFFF - PCIMasterWindow16 0x48800000-0x48FFFFFF - PCIMasterWindow17 0x49000000-0x497FFFFF - PCIMasterWindow18 0x49800000-0x49FFFFFF - PCIMasterWindow19 0x4A000000-0x4A7FFFFF - PCIMasterWindow20 0x4A800000-0x4AFFFFFF - PCIMasterWindow21 0x4B000000-0x4B7FFFFF - PCIMasterWindow22 0x4B800000-0x4BFFFFFF - PCIMasterWindow23 0x4C000000-0x4C7FFFFF - PCIMasterWindow24 0x4C800000-0x4CFFFFFF - PCIMasterWindow25 0x4D000000-0x4D7FFFFF - PCIMasterWindow26 0x4D800000-0x4DFFFFFF - PCIMasterWindow27 0x4E000000-0x4E7FFFFF - PCIMasterWindow28 0x4E800000-0x4EFFFFFF - PCIMasterWindow29 0x4F000000-0x4F7FFFFF - PCIMasterWindow30 0x4F800000-0x4FFFFFFF - PCIMasterWindow31 152 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.17.3 PCI Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to be sure that the PCI peripheral meets all ac timing specifications as required by the PCI Local Bus Specification (version 2.3). Theactimingspecificationsarenotreproducedhere.Formoreinformationontheactimingspecifications, see Section 4.2.3, Timing Specification (33 MHz timing), and Section 7.6.4, Timing Specification (66 MHz timing), of the PCI Local Bus Specification (version 2.3). Note that the PCI peripheral only supports 3.3-V signaling. Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.18 Multichannel Audio Serial Port (McASP) The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound(I2S)protocols,andintercomponentdigitalaudiointerfacetransmission(DIT). 6.18.1 McASP Device-Specific Information The device includes one multichannel audio serial port (McASP) interface peripheral. The McASP is a serialportoptimizedfortheneedsofmultichannelaudioapplications. The McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a poolof16shiftregistersthatmaybeconfiguredtooperateaseithertransmitdataorreceivedata. The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronousserialformat. The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the sameformat.However,thetransmitandreceiveformatsneednotbethesame. Both the transmit and receive sections of the McASP also support burst mode which is useful for non- audiodata(forexample,passingcontrolinformationbetweentwoDSPs). The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, aswellaserrormanagement. For more detailed information on and the functionality of the McASP peripheral, see the TMS320DM647/DM648 Multichannel Audio Serial Port (McASP) User's Guide (literature number SPRUEL1). 6.18.1.1 McASPBlockDiagram Figure 6-48 illustrates the major blocks along with external signals of the McASP peripheral; and shows the10serialdata[AXR]pins. 154 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 McASP Transmit DIT Frame Sync AFSX RAM Generator Transmit Clock Check Transmit AHCLKX Clock (High- Generator ACLKX Frequency) Error AMUTE Detect AMUTEIN Receive Receive Clock Check Clock AHCLKR (High- Generator ACLKR Frequency) mit s an Transmit Receive Tr Data Frame Sync AFSR S Formatter Generator M D O PI G X/ R Serializer 0 AXR0[0] X/ E T Serializer 1 AXR0[1] L AB Serializer 2 AXR0[2] M M Serializer 3 AXR0[3] A R G O R P Y Serializer 9 AXR0[9] L L A U D VI DI N ve I ei c Re Receive GPIO A Data Control M Formatter D Figure6-48.McASPConfiguration Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.18.1.2 McASPPeripheralRegisterDescription(s) Table6-73.McASPControlRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x02040000 PID PeripheralIdentificationregister[Registervalue:0x00100101] 0x02040004 PWRDEMU Powerdownandemulationmanagementregister 0x02040008 - Reserved 0x0204000C - Reserved 0x02040010 PFUNC Pinfunctionregister 0x02040014 PDIR Pindirectionregister 0x02040018 PDOUT Pindataoutregister Pindatain/datasetregister 0x0204001C PDIN/PDSET Readreturns:PDIN Writesaffect:PDSET 0x02040020 PDCLR Pindataclearregister 0x02040024-0x02040040 - Reserved 0x02040044 GBLCTL Globalcontrolregister 0x02040048 AMUTE Mutecontrolregister 0x0204004C DLBCTL DigitalLoop-backcontrolregister 0x02040050 DITCTL DITmodecontrolregister 0x02040054-0x0204 - Reserved 005C AliasofGBLCTLcontainingonlyReceiverResetbits,allowstransmittobereset 0x02040060 RGBLCTL independentlyfromreceive. 0x02040064 RMASK ReceiverformatUNITbitmaskregister 0x02040068 RFMT Receivebitstreamformatregister 0x0204006C AFSRCTL Receiveframesynccontrolregister 0x02040070 ACLKRCTL Receiveclockcontrolregister 0x02040074 AHCLKRCTL High-frequencyreceiveclockcontrolregister 0x02040078 RTDM ReceiveTDMslot0-31register 0x0204007C RINTCTL Receiverinterruptcontrolregister 0x02040080 RSTAT Statusregister-Receiver 0x02040084 RSLOT CurrentreceiveTDMslotregister 0x02040088 RCLKCHK Receiverclockcheckcontrolregister 0x0204008C-0x0204 - Reserved 009C AliasofGBLCTLcontainingonlyTransmitterResetbits,allowstransmittobereset 0x020400A0 XGBLCTL independentlyfromreceive. 0x020400A4 XMASK TransmitformatUNITbitmaskregister 0x020400A8 XFMT Transmitbitstreamformatregister 0x020400AC AFSXCTL Transmitframesynccontrolregister 0x020400B0 ACLKXCTL Transmitclockcontrolregister 0x020400B4 AHCLKXCTL High-frequencyTransmitclockcontrolregister 0x020400B8 XTDM TransmitTDMslot0-31register 0x020400BC XINTCTL Transmitinterruptcontrolregister 0x020400C0 XSTAT Statusregister-Transmitter 0x020400C4 XSLOT CurrenttransmitTDMslot 0x020400C8 XCLKCHK Transmitclockcheckcontrolregister 156 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-73.McASPControlRegisters(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x020400CC-0x0204 - Reserved 00FC 0x02040100 DITCSRA0 Left(evenTDMslot)channelstatusregisterfile 0x02040104 DITCSRA1 Left(evenTDMslot)channelstatusregisterfile 0x02040108 DITCSRA2 Left(evenTDMslot)channelstatusregisterfile 0x0204010C DITCSRA3 Left(evenTDMslot)channelstatusregisterfile 0x02040110 DITCSRA4 Left(evenTDMslot)channelstatusregisterfile 0x02040114 DITCSRA5 Left(evenTDMslot)channelstatusregisterfile 0x02040118 DITCSRB0 Right(oddTDMslot)channelstatusregisterfile 0x0204011C DITCSRB1 Right(oddTDMslot)channelstatusregisterfile 0x02040120 DITCSRB2 Right(oddTDMslot)channelstatusregisterfile 0x02040124 DITCSRB3 Right(oddTDMslot)channelstatusregisterfile 0x02040128 DITCSRB4 Right(oddTDMslot)channelstatusregisterfile 0x0204012C DITCSRB5 Right(oddTDMslot)channelstatusregisterfile 0x02040130 DITUDRA0 Left(evenTDMslot)userdataregisterfile 0x02040134 DITUDRA1 Left(evenTDMslot)userdataregisterfile 0x02040138 DITUDRA2 Left(evenTDMslot)userdataregisterfile 0x0204013C DITUDRA3 Left(evenTDMslot)userdataregisterfile 0x02040140 DITUDRA4 Left(evenTDMslot)userdataregisterfile 0x02040144 DITUDRA5 Left(evenTDMslot)userdataregisterfile 0x02040148 DITUDRB0 Right(oddTDMslot)userdataregisterfile 0x0204014C DITUDRB1 Right(oddTDMslot)userdataregisterfile 0x02040150 DITUDRB2 Right(oddTDMslot)userdataregisterfile 0x02040154 DITUDRB3 Right(oddTDMslot)userdataregisterfile 0x02040158 DITUDRB4 Right(oddTDMslot)userdataregisterfile 0x0204015C DITUDRB5 Right(oddTDMslot)userdataregisterfile 0x02040160-0x0204 - Reserved 017C 0x02040180 SRCTL0 Serializer0controlregister 0x02040184 SRCTL1 Serializer1controlregister 0x02040188 SRCTL2 Serializer2controlregister 0x0204018C SRCTL3 Serializer3controlregister 0x02040190 SRCTL4 Serializer4controlregister 0x02040194 SRCTL5 Serializer5controlregister 0x02040198 SRCTL6 Serializer6controlregister 0x0204019C SRCTL7 Serializer7controlregister 0x020401A0 SRCTL8 Serializer8controlregister 0x020401A4 SRCTL9 Serializer9controlregister 0x020401A8-0x0204 - Reserved 01FC 0x02040200 XBUF0 TransmitBufferforSerializer0 0x02040204 XBUF1 TransmitBufferforSerializer1 0x02040208 XBUF2 TransmitBufferforSerializer2 0x0204020C XBUF3 TransmitBufferforSerializer3 0x02040210 XBUF4 TransmitBufferforSerializer4 0x02040214 XBUF5 TransmitBufferforSerializer5 0x02040218 XBUF6 TransmitBufferforSerializer6 0x0204021C XBUF7 TransmitBufferforSerializer7 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 157 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-73.McASPControlRegisters(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x0204021A XBUF8 TransmitBufferforSerializer8 0x02040220 XBUF9 TransmitBufferforSerializer9 0x02040224-0x0204027C - Reserved 0x02040280 RBUF0 ReceiveBufferforSerializer0 0x02040284 RBUF1 ReceiveBufferforSerializer1 0x02040288 RBUF2 ReceiveBufferforSerializer2 0x0204028C RBUF3 ReceiveBufferforSerializer3 0x02040290 RBUF4 ReceiveBufferforSerializer4 0x02040294 RBUF5 ReceiveBufferforSerializer5 0x02040298 RBUF6 ReceiveBufferforSerializer6 0x0204029C RBUF7 ReceiveBufferforSerializer7 0x020402A0 RBUF8 ReceiveBufferforSerializer8 0x020402A4 RBUF9 ReceiveBufferforSerializer9 0x020402A8-0x02043FFF - Reserved Table6-74.McASPDataRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS (UsedwhenRSELorXSELbits=0 McASPreceivebuffersorMcASPtransmit 02044000-020443FF RBUF/XBUF [thesebitsarelocatedintheRFMTor buffersviathePeripheralDataBus. XFMTregisters,respectively].) 6.18.1.3 McASPElectricalData/Timing 6.18.1.3.1 MultichannelAudioSerialPort(McASP)Timing Table6-75.TimingRequirementsforMcASP(seeFigure6-49andFigure6-50)(1) 720,800,900, NO. 1100 UNIT MIN MAX 1 t Cycletime,AHCLKR/X 20 ns c(AHCKRX) 2 t Pulseduration,AHCLKR/Xhighorlow 10 ns w(AHCKRX) 3 t Cycletime,ACLKR/X ACLKR/Xext 33 ns c(CKRX) 4 t Pulseduration,ACLKR/Xhighorlow ACLKR/Xext 16.5 ns w(CKRX) ACLKR/Xint 5 ns 5 t Setuptime,AFSR/XinputvalidbeforeACLKR/Xlatchesdata su(FRX-CKRX) ACLKR/Xext 5 ns ACLKR/Xint 5 ns 6 t Holdtime,AFSR/XinputvalidafterACLKR/Xlatchesdata h(CKRX-FRX) ACLKR/Xext 12.08 ns ACLKR/Xint 5 ns 7 t Setuptime,AXRinputvalidbeforeACLKR/Xlatchesdata su(AXR-CKRX) ACLKR/Xext 5 ns ACLKR/Xint 5 ns 8 t Holdtime,AXRinputvalidafterACLKR/Xlatchesdata h(CKRX-AXR) ACLKR/Xext 7.35 ns (1) ACLKXinternal:ACLKXCTL.CLKXM=1,PDIR.ACLKX=1 ACLKXexternalinput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=0 ACLKXexternaloutput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=1 ACLKRinternal:ACLKRCTL.CLKRM=1,PDIR.ACLKR=1 ACLKRexternalinput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=0 ACLKRexternaloutput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=1 158 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-76.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcASP (seeFigure6-49andFigure6-50)(1) 720,800,900, NO. PARAMETER 1100 UNIT MIN MAX 9 t Cycletime,AHCLKR/X 20 ns c(AHCKRX) 10 t Pulseduration,AHCLKR/Xhighorlow 10 ns w(AHCKRX) 11 t Cycletime,ACLKR/X ACLKR/Xint 33 ns c(CKRX) 12 t Pulseduration,ACLKR/Xhighorlow ACLKR/Xint 16.5 ns w(CKRX) ACLKR/Xint 5 ns 13 t Delaytime,ACLKR/XtransmitedgetoAFSX/Routputvalid d(CKRX-FRX) ACLKR/Xext 14.28 ns ACLKXint 10 ns 14 t Delaytime,ACLKXtransmitedgetoAXRoutputvalid d(CKX-AXRV) ACLKXext 12.5 ns Disabletime,AXRhighimpedancefollowinglastdatabitfrom ACLKR/Xint 10 ns 15 t dis(CKRX-AXRHZ) ACLKR/Xtransmitedge ACLKR/Xext 12.5 ns (1) ACLKXinternal:ACLKXCTL.CLKXM=1,PDIR.ACLKX=1 ACLKXexternalinput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=0 ACLKXexternaloutput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=1 ACLKRinternal:ACLKRCTL.CLKRM=1,PDIR.ACLKR=1 ACLKRexternalinput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=0 ACLKRexternaloutput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=1 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (CLKRP= CLKXP= 0)(A) ACLKR/X (CLKRP= CLKXP= 1)(B) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiverisconfiguredforfallingedge(toshiftdatain). B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiverisconfiguredforrisingedge(toshiftdatain). Figure6-49.McASPInputTiming 160 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (CLKRP= CLKXP= 1)(A) ACLKR/X (CLKRP= CLKXP= 0)(B) 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A1 A30A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiverisconfiguredforrisingedge(toshiftdatain). B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiverisconfiguredforfallingedge(toshiftdatain). Figure6-50.McASPOutputTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.19 3-Port Ethernet Switch Subsystem (3PSW) The Ethernet module controls the flow of packet data between the device and two external Ethernet PHYs (DM648 only) or one external Ethernet PHY (DM647 only), with hardware flow control and quality-of- service (QOS) support. See Figure 6-51 for a block diagram of the Ethernet module. The Ethernet Subsystem contains a 3-port gigabit switch, where one port is internally connected to the C64x+ DSP (via the switched central resource) and the other two ports are brought out externally. Each of the external EthernetportssupportthemodesshowninTable6-77. The Ethernet module controls the flow of packet data between the device and two external Ethernet PHYs , with hardware flow control and quality-of-service (QOS) support. See Figure 6-51 for a block diagram of the Ethernet module. The Ethernet Subsystem contains a 3-port gigabit switch, where one port is internally connected to the C64x+ DSP (via the switched central resource) and the other two ports are broughtoutexternally.EachoftheexternalEthernetportssupportthemodesshowninTable6-77. Table6-77.EthernetOperatingModes DESCRIPTION DATARATE OPERATINGMODE 10Base-T 10Mbits/second(Mbps) half-orfull-duplex 100Base-T 100Mbits/second(Mbps) half-orfull-duplex 1000Base-T 1000Mbits/second(Mbps) full-duplex TheEthernetSubsystemprovidesthesefunctions: • Ethernetcommunication/routingbywayoftwodedicated10/100/1000portswithSGMIIinterfaces – Wire-rateswitching(802.1d),non-blockingswitchfabric – FourprioritylevelsofQoSTXsupport(802.1p)inhardware – ProgrammableinterruptpacingonRX/TXplusinterruptthresholdonRX – Supportsforwardingframesizesof64-2020bytes • AddressLookup – 1024totaladdresslookupengine(ALE)entriesofVLANsand/orMACaddresses – L2addresslockandL2filteringsupport – Multicast/broadcastfilteringandforwardingstatecontrol – Receive-basedordestination-basedmulticastandbroadcastratelimits – MACaddressblocking – Sourceportlocking – OUI(VendorID)hostaccept/denyfeature – Hostcontrolledtime-basedaging – MACauthentication(802.1x) – RemappingofprioritylevelofVLANorports – Multiplespanningtreesupport(spanningtreeperVLAN) 162 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 • VLANsupport – 802.1Qcompliant • AutoaddportVLANforuntaggedframesoningress • AutoVLANremovalonegressandautopadtominimumframesize – Flowcontrol(IEEE802.3x) – Programmable priority escalation to specify delivery of lower priority level packets in the event of over-subscribedTXhighprioritytraffic – HostpassCRCmode(enablesCRCprotectionthroughhost) – Write-protect option for Ethernet module registers (3PGSW, CPPI RAM, MDIO, SGMII0, SGMII1, control) – Ethernetstatistics: • EtherStatsand802.3StatsRMONstatisticsgathering(shared) • Programmablestatisticsinterruptmaskwhenastatisticisaboveonehalfits32-bitvalue – MDIOmoduleforPHYmanagement – SGMII gigabit current mode logic (CML) differential SERializer/DESerializer (SerDes) I/O receiver/transmitters • Adaptive active equalization for superior data dependent jitter tolerance in the presence of a lossychannel • Lossofsignaldetectorwithprogrammablethresholdlevelsinreceivechannels • Integratedreceiverandtransmittertermination • IEEE802.3gigabitEthernetconformant 6.19.1 Ethernet Subsystem Functions Configuration Configuration 2 Bus Registers Gigabit SGMII GMII port 0 SGMII0 MAC0 2 Port 0 3-port Peripheral Host DMA Addr Lookup 2 Gigabit REFCLK Bus Controller Engine Switch Buffer 2 Descriptor Gigabit SGMII Memory GMII port 1 SGMII 1(A) MAC1 2 Port 1 DSP Interrupt Controller MII Configuration MDIO Serial Bus Mgmt A. SGMIIport1isnotavailableonDM647. Figure6-51.EthernetSubsystemBlockDiagram Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by invertingtheframeCRC,sothatthetransmittedframewillbedetectedasanerrorbythenetwork. In networking systems, packet transmission and reception are critical tasks. The communications port programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory thatholdsupto512bufferdescriptors. After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet transmitandreceiveoperations. • Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to processbeforesendingtotheSGMII. • Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the CPPIprotocol. DSP writes may be write-protected to the Ethernet Subsystem configuration registers from addresses 0x02D0 0000 - 0x02D0 4FFF (3PGSW, MDIO, SGMII0, SGMII1, control), and the CPPI RAM. The Ethernet Subsystem setting in the PSC is also write-protected. A specific 32-bit lock code (0x4C6F436B) and a 32-bit unlock code (0x6F50654E) written to ESS_LOCK register will activate or clear this option, respectively.SeeSection3.2.5andSection3.2.7 The3-portgigabitswitchblockcontainsthefollowingfunctions: • 3-portgigabitswitch:performspacketforwardingandroutingfunctions,oneportisinternallyconnected totheC64x+DSPandtwoportsarebroughtoutexternally • CPDMA: performs high-speed DMA transfers with RX and TX CPPI buffers in local memory, including channelsetupandchannelteardown • GMAC(GigabitEthernetMAC): – UsesRxpacketFIFO,andaTXpacketFIFOtoimprovedatatransferefficiency – HandlesprocessingofEthernetpacketdata,frames,andheaders – Includesflowcontrol – Providesstatisticscollectionandreporting • The address lookup engine (ALE) processes all received packets to determine where (that is, which packet location) to forward the packet. The ALE uses the incoming packet received port number, destination address, source address, length/type, and VLAN information to determine how the packet should be forwarded. The ALE outputs the port mask to the switch fabric that indicates to which port(s) thepacketshouldbeforwarded. 6.19.2 Interrupt Controller and Pacing Interrupts The interrupt control block selects the interrupts from the 3-port gigabit switch and MDIO modules for output to the C64x+ DSP. The miscellaneous interrupt is an immediate (non-paced) interrupt selected fromthemiscellaneousinterrupts(hosterrorlevel,statisticslevel,MDIOUser[2],MDIOlink[2]). The eight RX interrupts and eight TX interrupts can be paced. The 8 RX threshold interrupts and the miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very high rate, the performance benefit is significant due to minimizing the overhead associated with servicing each interrupt. Interrupt pacing increases the C64x+ DSP cache hit ratio by minimizing the number of timesthatlargeinterruptserviceroutinesaremovedtoandfromtheDSPinstructioncache. MDIO 164 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 The MDIO module manages the PHY configuration and monitors status. For a list of supported registers and register fields, see Table 6-79. In 10/100 mode, the GMII_MTXD(7:0) data bus uses only the lower nibble. SGMII TheSGMII/SerDesmodulecontains: • Gigabitdifferentialcurrentmodelogic(CML)receiver/transmitters • AnintegratedRX/TXPLLtoprovidetherequiredhigh-quality/high-speedinternalclocks • Phase-interpolator-basedclock/datarecovery • Abandgapreferencefortransmitterswingsettings • Parallel-to-serialconverter • Serial-to-parallelconverter • Integratedreceiverandtransmittertermination • Configurationlogic • 802.3auto-negotiationfunctionality(asdefinedinClause37oftheIEEESpecification802.3) The SGMII receive interface converts the encoded receive signals from the differential receive input terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals. The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as anerrorbyanerrorCRC. NOTE SGMII1ispinnedoutonlyintheDM648device.TheDM647devicehasonlyoneSGMIIport (SGMII0). 6.19.3 Peripheral Register Description(s) Table6-78throughTable6-81listtheregisters. Table6-78.EthernetSwitchRegisters HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D03000 CPSW_ID_VER CPSWIdentificationandVersionRegister 0x02D03004 CPSW_CONTROL CPSWSwitchControlRegister 0x02D03008 CPSW_SOFT_RESET CPSWSoftResetRegister 0x02D0300C CPSW_STAT_PORT_EN CPSWStatisticsPortEnableRegister 0x02D03010 CPSW_PTYPE CPSWTransmitPriorityTypeRegister 0x02D03014 P0_MAX_BLKS CPSWPort0MaximumFIFOblocksRegister 0x02D03018 P0_BLK_CNT CPSWPort0FIFOBlockUsageCountRegister(readonly) 0x02D0301C P0_FLOW_THRESH CPSWPort0FlowControlThresholdRegister 0x02D03020 P0_PORT_VLAN CPSWPort0VLANRegister 0x02D03024 P0_TX_PRI_MAP CPSWPort0TxHeaderPritoSwitchPriMappingRegister 0x02D03028 GMAC0_GAP_THRESH CPSWGMAC0ShortGapThresholdRegister 0x02D0302C GMAC0_SA_LO CPSWGMAC0SourceAddressLowRegister 0x02D03030 GMAC0_SA_HI CPSWGMAC0SourceAddressHighRegister 0x02D03034 P1_MAX_BLKS CPSWPort1MaximumFIFOblocksRegister 0x02D03038 P1_BLK_CNT CPSWPort1FIFOBlockUsageCountRegister(readonly) 0x02D0303C P1_FLOW_THRESH CPSWPort1FlowControlThresholdRegister 0x02D03040 P1_PORT_VLAN CPSWPort1VLANRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 165 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-78.EthernetSwitchRegisters(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D03044 P1_TX_PRI_MAP CPSWPort1TxHeaderPrioritytoSwitchPriMapping Register 0x02D03048 GMAC1_GAP_THRESH CPSWGMAC1ShortGapThresholdRegister 0x02D0304C GMAC1_SA_LO CPSWGMAC1SourceAddressLowRegister 0x02D03050 GMAC1_SA_HI CPSWGMAC1SourceAddressHighRegister 0x02D03054 P2_MAX_BLKS CPSWPort2MaximumFIFOblocksRegister 0x02D03058 P2_BLK_CNT CPSWPort2FIFOBlockUsageCountRegister(readonly) 0x02D0305C P2_FLOW_THRESH CPSWPort2FlowControlThresholdRegister 0x02D03060 P2_PORT_VLAN CPSWPort2VLANRegister 0x02D03064 P2_TX_PRI_MAP CPSWPort2Tx(CPDMARx)HeaderPrioritytoSwitchPri MappingRegister 0x02D03068 CPDMA_TX_PRI_MAP CPSWCPDMATx(Port2Rx)PktPrioritytoHeaderPriority MappingRegister 0x02D0306C CPDMA_RX_CH_MAP CPSWCPDMARx(Port2Tx)SwitchPrioritytoDMA channelMappingRegister 0x02D03070-0x02D0307C reserved 0x02D03080 GMAC0_IDVER GMAC0IdentificationandVersionRegister 0x02D03084 GMAC0_MACCONTROL GMAC0MacControlRegister 0x02D03088 GMAC0_MACSTATUS GMAC0MacStatusRegister 0x02D0308C GMAC0_SOFT_RESET GMAC0SoftResetRegister 0x02D03090 GMAC0_RX_MAXLEN GMAC0RXMaximumLengthRegister 0x02D03094 GMAC0_BOFFTEST GMAC0BackoffTestRegister 0x02D03098 reserved 0x02D0309C reserved 0x02D030A0 GMAC0_EMCONTROL GMAC0EmulationControlRegister 0x02D030A4 GMAC0_RX_PRI_MAP GMAC0RxPktPrioritytoHeaderPriorityMappingRegister 0x02D030A8-0x02D030BC reserved 0x02D030C0 GMAC1_IDVER GMAC1IdentificationandVersionRegister 0x02D030C4 GMAC1_MACCONTROL GMAC1MacControlRegister 0x02D030C8 GMAC1_MACSTATUS GMAC1MacStatusRegister 0x02D030CC GMAC1_SOFT_RESET GMAC1SoftResetRegister 0x02D030D0 GMAC1_RX_MAXLEN GMAC1RXMaximumLengthRegister 0x02D030D4 GMAC1_BOFFTEST GMAC1BackoffTestRegister 0x02D030D8 reserved 0x02D030DC reserved 0x02D030E0 GMAC1_EMCONTROL GMAC1EmulationControlRegister 0x02D030E4 GMAC1_RX_PRI_MAP GMAC1RxPktPrioritytoHeaderPriorityMappingRegister 0x02D030E8-0x02D030FC reserved 0x02D03100 TX_IDVER CPDMATxIdentificationandVersionRegister 0x02D03104 TX_CONTROL CPDMATxControlRegister 0x02D03108 TX_TEARDOWN CPDMATxTeardownRegister 0x02D0310C reserved 0x02D03110 RX_IDVER CPDMARxIdentificationandVersionRegister 0x02D03114 RX_CONTROL CPDMARxControlRegister 0x02D03118 RX_TEARDOWN CPDMARxTeardownRegister 0x02D0311C SOFT_RESET CPDMASoftResetRegister 0x02D03120 DMACONTROL CPDMAControlRegister 0x02D03124 DMASTATUS CPDMAStatusRegister 166 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-78.EthernetSwitchRegisters(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D03128 RX_BUFFER_OFFSET CPDMARxBufferOffsetRegister 0x02D0312C EMCONTROL CPDMAEmulationControlRegister 0x02D03130-0x02D0317C reserved 0x02D03180 TX_INTSTAT_RAW CPDMATxinterruptStatusRegister(rawvalue) 0x02D03184 TX_INTSTAT_MASKED CPDMATxInterruptStatusRegister(maskedvalue) 0x02D03188 TX_INTMASK_SET CPDMATxInterruptMaskSetRegister 0x02D0318C TX_INTMASK_CLEAR CPDMATxInterruptMaskClearRegister 0x02D03190 CPDMA_IN_VECTOR CPDMAInputVectorRegister(readonly) 0x02D03194 CPDMA_EOI_VECTOR CPDMAEndOfInterruptVectorRegister 0x02D03198-0x02D0319C reserved 0x02D031A0 RX_INTSTAT_RAW CPDMARxInterruptStatusRegister(rawvalue) 0x02D031A4 RX_INTSTAT_MASKED CPDMARxInterruptStatusRegister(maskedvalue) 0x02D031A8 RX_INTMASK_SET CPDMARxInterruptMaskSetRegister 0x02D031AC RX_INTMASK_CLEAR CPDMARxInterruptMaskClearRegister 0x02D031B0 DMA_INTSTAT_RAW CPDMADMAInterruptStatusRegister(rawvalue) 0x02D031B4 DMA_INTSTAT_MASKED CPDMADMAInterruptStatusRegister(maskedvalue) 0x02D031B8 DMA_INTMASK_SET CPDMADMAInterruptMaskSetRegister 0x02D031BC DMA_INTMASK_CLEAR CPDMADMAInterruptMaskClearRegister 0x02D031C0 RX0_PENDTHRESH CPDMARxThresholdPendingRegisterChannel0 0x02D031C4 RX1_PENDTHRESH CPDMARxThresholdPendingRegisterChannel1 0x02D031C8 RX2_PENDTHRESH CPDMARxThresholdPendingRegisterChannel2 0x02D031CC RX3_PENDTHRESH CPDMARxThresholdPendingRegisterChannel3 0x02D031D0 RX4_PENDTHRESH CPDMARxThresholdPendingRegisterChannel4 0x02D031D4 RX5_PENDTHRESH CPDMARxThresholdPendingRegisterChannel5 0x02D031D8 RX6_PENDTHRESH CPDMARxThresholdPendingRegisterChannel6 0x02D031DC RX7_PENDTHRESH CPDMARxThresholdPendingRegisterChannel7 0x02D031E0 RX0_FREEBUFFER CPDMARxFreeBufferRegisterChannel0 0x02D031E4 RX1_FREEBUFFER CPDMARxFreeBufferRegisterChannel1 0x02D031E8 RX2_FREEBUFFER CPDMARxFreeBufferRegisterChannel2 0x02D031EC RX3_FREEBUFFER CPDMARxFreeBufferRegisterChannel3 0x02D031F0 RX4_FREEBUFFER CPDMARxFreeBufferRegisterChannel4 0x02D031F4 RX5_FREEBUFFER CPDMARxFreeBufferRegisterChannel5 0x02D031F8 RX6_FREEBUFFER CPDMARxFreeBufferRegisterChannel6 0x02D031FC RX7_FREEBUFFER CPDMARxFreeBufferRegisterChannel7 0x02D03200 TX0_HDP CPDMATxChannel0HeadDescPointer 0x02D03204 TX1_HDP CPDMATxChannel1HeadDescPointer 0x02D03208 TX2_HDP CPDMATxChannel2HeadDescPointer 0x02D0320C TX3_HDP CPDMATxChannel3HeadDescPointer 0x02D03210 TX4_HDP CPDMATxChannel4HeadDescPointer 0x02D03214 TX5_HDP CPDMATxChannel5HeadDescPointer 0x02D03218 TX6_HDP CPDMATxChannel6HeadDescPointer 0x02D0321C TX7_HDP CPDMATxChannel7HeadDescPointer 0x02D03220 RX0_HDP CPDMARx0Channel0HeadDescPointer 0x02D03224 RX1_HDP CPDMARx1Channel1HeadDescPointer 0x02D03228 RX2_HDP CPDMARx2Channel2HeadDescPointer 0x02D0322C RX3_HDP CPDMARx3Channel3HeadDescPointer 0x02D03230 RX4_HDP CPDMARx4Channel4HeadDescPointer Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 167 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-78.EthernetSwitchRegisters(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D03234 RX5_HDP CPDMARx5Channel5HeadDescPointer 0x02D03238 RX6_HDP CPDMARx6Channel6HeadDescPointer 0x02D0323C RX7_HDP CPDMARx7Channel7HeadDescPointer 0x02D03240 TX0_CP CPDMATxChannel0CompletionPointerRegister 0x02D03244 TX1_CP CPDMATxChannel1CompletionPointerRegister 0x02D03248 TX2_CP CPDMATxChannel2CompletionPointerRegister 0x02D0324C TX3_CP CPDMATxChannel3CompletionPointerRegister 0x02D03250 TX4_CP CPDMATxChannel4CompletionPointerRegister 0x02D03254 TX5_CP CPDMATxChannel5CompletionPointerRegister 0x02D03258 TX6_CP CPDMATxChannel6CompletionPointerRegister 0x02D0325C TX7_CP CPDMATxChannel7CompletionPointerRegister 0x02D03260 RX0_CP CPDMARxChannel0CompletionPointerRegister 0x02D03264 RX1_CP CPDMARxChannel1CompletionPointerRegister 0x02D03268 RX2_CP CPDMARxChannel2CompletionPointerRegister 0x02D0326C RX3_CP CPDMARxChannel3CompletionPointerRegister 0x02D03270 RX4_CP CPDMARxChannel4CompletionPointerRegister 0x02D03274 RX5_CP CPDMARxChannel5CompletionPointerRegister 0x02D03278 RX6_CP CPDMARxChannel6CompletionPointerRegister 0x02D0327C RX7_CP CPDMARxChannel7CompletionPointerRegister 0x02D03280-0x02D032BF reserved 0x02D032C0-0x02D032FC reserved 0x02D03300-0x02D0337C reserved 0x02D03380-0x02D033FC reserved 0x02D03400 RXGOODFRAMES CPSW_STATSTotalnumberofgoodframesreceived 0x02D03404 RXBROADCASTFRAMES CPSW_STATSTotalnumberofgoodbroadcastframes received 0x02D03408 RXMULTICASTFRAMES CPSW_STATSTotalnumberofgoodmulticastframes received 0x02D0340C RXPAUSEFRAMES CPSW_STATSPauseRxFrames 0x02D03410 RXCRCERRORS CPSW_STATSTotalnumberofCRCerrorsframesreceived 0x02D03414 RXALIGNCODEERRORS CPSW_STATSTotalnumberofalignment/codeerrors received 0x02D03418 RXOVERSIZEDFRAMES CPSW_STATSTotalnumberofoversizedframesreceived 0x02D0341C RXJABBERFRAMES CPSW_STATSTotalnumberofjabberframesreceived 0x02D03420 RXUNDERSIZEDFRAMES CPSW_STATSTotalnumberofundersizedframesreceived 0x02D03424 RXFRAGMENTS CPSW_STATSRxFragmentsreceived 0x02D03428 reserved 0x02D0342C reserved 0x02D03430 RXOCTETS CPSW_STATSTotalnumberofreceivedbytesingood frames 0x02D03434 TXGOODFRAMES CPSW_STATSGoodTxFrames 0x02D03438 TXBROADCASTFRAMES CPSW_STATSBroadcastTxFrames 0x02D0343C TXMULTICASTFRAMES CPSW_STATSMulticastTxFrames 0x02D03440 TXPAUSEFRAMES CPSW_STATSPauseTxFrames 0x02D03444 TXDEFERREDFRAMES CPSW_STATSDeferredFrames 0x02D03448 TXCOLLISIONFRAMES CPSW_STATSCollisions 0x02D0344C TXSINGLECOLLFRAMES CPSW_STATSSingleCollisionTxFrames 0x02D03450 TXMULTCOLLFRAMES CPSW_STATSMultipleCollisionTxFrames 168 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-78.EthernetSwitchRegisters(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D03454 TXEXCESSIVECOLLISIONS CPSW_STATSExcessiveCollisions 0x02D03458 TXLATECOLLISIONS CPSW_STATSLateCollisions 0x02D0345C TXUNDERRUN CPSW_STATSTransmitUnderrunError 0x02D03460 TXCARRIERSENSEERRORS CPSW_STATSCarrierSenseErrors 0x02D03464 TXOCTETS CPSW_STATSTxOctets 0x02D03468 OCTETFRAMES64 CPSW_STATS64octetFrames 0x02D0346C OCTETFRAMES65T127 CPSW_STATS65-127octetFrames 0x02D03470 OCTETFRAMES128T255 CPSW_STATS128-255octetFrames 0x02D03474 OCTETFRAMES256T511 CPSW_STATS256-511octetFrames 0x02D03478 OCTETFRAMES512T1023 CPSW_STATS512-1023octetFrames 0x02D0347C OCTETFRAMES1024TUP CPSW_STATS1023-1518octetFrames 0x02D03480 NETOCTETS CPSW_STATSNetOctets 0x02D03484 RXSOFOVERRUNS CPSW_STATSReceiveFIFOorDMAStartofFrame Overruns 0x02D03488 RXMOFOVERRUNS CPSW_STATSReceiveFIFOorDMAMidofFrame Overruns 0x02D0348C RXDMAOVERRUNS CPSW_STATSReceiveDMAStartofFrameandMiddleof FrameOverruns 0x02D03490-0x02D034FC reserved 0x02D03500 ALE_IDVER ALEIdentificationandVersionRegister 0x02D03504 reserved 0x02D03508 ALE_CONTROL ALEControlRegister 0x02D0350C reserved 0x02D03510 ALE_PRESCALE ALEPrescaleRegister 0x02D03514 reserved 0x02D03518 ALE_UNKNOWN_VLAN ALEUnknownVLANRegister 0x02D0351C reserved 0x02D03520 ALE_TBLCTL ALETableControlRegister 0x02D03524-0x02D03530 reserved 0x02D03534 ALE_TBLW2 ALETableWord2Register 0x02D03538 ALE_TBLW1 ALETableWord1Register 0x02D0353C ALE_TBLW0 ALETableWord0Register 0x02D03540 ALE_PORTCTL0 ALEPort0ControlRegister 0x02D03544 ALE_PORTCTL1 ALEPort1ControlRegister 0x02D03548 ALE_PORTCTL2 ALEPort2ControlRegister 0x02D0354C-0x02D037FF reserved Table6-79.EthernetSubsystemRegisters HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D02000 IDVER IdentificationandVersionRegister 0x02D02004 SOFT_RESET SoftResetRegister 0x02D02008 EM_CONTROL EmulationControlRegister 0x02D0200C INT_CONTROL InterruptControlRegister 0x02D02010 RX_THRESH_EN ReceiveThresholdInterruptEnableRegister 0x02D02014 RX_EN ReceiveInterruptEnableRegister 0x02D02018 TX_EN TransmitInterruptEnableRegister 0x02D0201C MISC_EN MiscInterruptEnableRegister 0x02D02020 RX_THRESH_STAT ReceiveThresholdMaskedInterruptStatusRegister Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 169 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-79.EthernetSubsystemRegisters(continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D02024 RX_STAT ReceiveInterruptMaskedInterruptStatusRegister 0x02D02028 TX_STAT TransmitInterruptMaskedInterruptStatusRegister 0x02D0202C MISC_STAT MiscInterruptMaskedInterruptStatusRegister 0x02D02030 RX_IMAX ReceiveInterruptsPerMillisecond 0x02D02034 TX_IMAX TransmitInterruptsPerMillisecond Table6-80.SGMII0Registers HEXADDRESSRANGE REGISTERNAME DESCRIPTION 0x02D04800 IDVER IdentificationandVersionRegister 0x02D04804 SOFT_RESET SoftResetRegister 0x02D04808-0x02D0480C Reserved Reserved 0x02D04810 CONTROL ControlRegister 0x02D04814 STATUS StatusRegister(readonly) 0x02D04818 MR_ADV_ABILITY AdvertisedAbilityRegister 0x02D0481C MR_NP_TX TransmitNextPageRegister 0x02D04820 MR_LP_ADV_ABILITY LinkPartnerAdvertisedAbility(readonly) 0x02D04824 MR_NP_RX LinkPartnerReceiveNextPageRegister(readonly) 0x02D04828-0x02D0482C Reserved Reserved 0x02D04830 Reserved Reserved 0x02D04834 Reserved Reserved 0x02D04838 Reserved Reserved 0x02D0483C Reserved Reserved 0x02D04840 DIAG_CLEAR DiagnosticsClearRegister 0x02D04844 DIAG_CONTROL DiagnosticsControlRegister 0x02D04848 DIAG_STATUS DiagnosticsStatusRegister(readonly) 0x02D0484C-0x02D0487F Reserved Reserved Table6-81.SGMII1Registers HEXADDRESSRANGE REGISTERNAME DESCRIPTION 0x02D04C00 IDVER IdentificationandVersionRegister 0x02D04C04 SOFT_RESET SoftResetRegister 0x02D04C08-0x02D04C0C Reserved Reserved 0x02D04C10 CONTROL ControlRegister 0x02D04C14 STATUS StatusRegister(readonly) 0x02D04C18 MR_ADV_ABILITY AdvertisedAbilityRegister 0x02D04C1C MR_NP_TX TransmitNextPageRegister 0x02D04C20 MR_LP_ADV_ABILITY LinkPartnerAdvertisedAbility(readonly) 0x02D04C24 MR_NP_RX LinkPartnerReceiveNextPageRegister(readonly) 0x02D04C28-0x02D04C2C Reserved Reserved 0x02D04C30 Reserved Reserved 0x02D04C34 Reserved Reserved 0x02D04C38 Reserved Reserved 0x02D04C3C Reserved Reserved 0x02D04C40 DIAG_CLEAR DiagnosticsClearRegister 0x02D04C44 DIAG_CONTROL DiagnosticsControlRegister 0x02D04C48 DIAG_STATUS DiagnosticsStatusRegister(readonly) 0x02D04C4C-0x02D04C7F Reserved Reserved 170 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.19.4 Ethernet Subsystem Timing Table6-82.EthernetSubsystemTimingRequirements PARAMETER(1) MIN NOM MAX UNITS t REFCLKP/Nperiod,mode 01 x10mode 8 ns x20mode 16 ns x25mode 20 ns t REFCLKP/Ndutycycle 40 60 % 02 t REFCLKP/Nrise/fall 700 ps 03 t PLLClockPeriod,xnMode t /n ns 04 01 t PLLpowerup 1+200*C μs 05 (1) C=REFCLKP/Nperiodinμs. REFCLKP/NJitterandPLLLoopBandwidth Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impairing system performance. A good quality, low jitter reference clock is necessary to achieve compliancewithmostifnotallphysicallayerstandards(seeTable6-83). Table6-83.REFCLKP/NJitterRequirementsforStandardsCompliance Standard LineRate(Gbps) TotalREFCLKP/NJitter(withinPLLbandwidth) GigabitEthernet 1.25 50pspk-pk Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 171 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.20 Management Data Input/Output (MDIO) The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system. It contains two user access registers to control and monitor up totwoPHYssimultaneously. The MDIO module implements the 802.3 serial management interface to interrogate and control two EthernetPHYssimultaneouslyusingasharedtwo-wirebus. 6.20.1 MII Management Interface Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the Ethernet Switch Subsystem, retrieve the negotiation results, and configure required parameters in the Ethernet Switch Subsystem module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only a maximumoftwoPHYsmaybeconnectedatanygiventime. For more detailed information on the Ethernet Switch Subsystem, see the TMS320DM647/DM648 DSP Ethernet Subsystem User's Guide Reference Guide (literature number SPRUF57). For a list of supported registersandregisterfields,seeTable6-84. 6.20.2 MDIO Register Descriptions Table6-84.MDIORegisters HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x02D04000 MDIOVER Moduleversionregister 0x02D04004 MDIOCONTROL Modulecontrolregister 0x02D04008 MDIOALIVE PHYacknowledgestatusregister 0x02D0400C MDIOLINK PHYlinkstatusregister 0x02D04010 MDIOLINKINTRAW Linkstatuschangeinterruptregister(raw value) 0x02D04014 MDIOLINKINTMASKED Linkstatuschangeinterruptregister(masked value) 0x02D04018-0x02D0401C reserved 0x02D04020 MDIOUSERINTRAW Usercommandcompleteinterruptregister (rawvalue) 0x02D04024 MDIOUSERINTMASKED Usercommandcompleteinterruptregister (maskedvalue) 0x02D04028 MDIOUSERINTMASKSET Userinterruptmasksetregister 0x02D0402C MDIOUSERINTMASKCLR Userinterruptmaskclearregister 0x02D04030-0x02D0407C reserved 0x02D04080 MDIOUSERACCESS0 Useraccessregister0 0x02D04084 MDIOUSERPHYSEL0 UserPHYselectregister0 0x02D04088 MDIOUSERACCESS1 Useraccessregister1 0x02D0408C MDIOUSERPHYSEL1 UserPHYselectregister1 0x02D04090-0x02D040FF reserved 172 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.21 Timers The device has four 64-bit general-purpose timers of which only Timer 0 and Timer 1 have external input/output. The timers can be used to: time events, count events, generate pulses, interrupt the CPU, andsendsynchronizationeventstotheEDMA3channelcontroller. 6.21.1 General-Purpose Timers Each timer can be programmed as a 64-bit timer or as two separate 32-bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connectedtothelowcounter.Thehighcounterdoesnothaveanyexternaldevicepins. For more detailed information, see the TMS320DM647DM648 DSP 64-Bit Timer User's Guide (literature numberSPRUEL0). 6.21.2 Timer Peripheral Register Descriptions Table6-85.Timer0Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x02044400 PID12 PeripheralIdentificationRegister 0x02044404 EMUMGT_CLKSPD Timer0EmulationManagement/ClockSpeedRegister 0x02044410 TIM12 Timer0CounterRegister12 0x02044414 TIM34 Timer0CounterRegister34 0x02044418 PRD12 Timer0PeriodRegister12 0x0204441C PRD34 Timer0PeriodRegister34 0x02044420 TCR Timer0ControlRegister 0x02044424 TGCR Timer0GlobalControlRegister 0x0x02044428-0x020444FF - Reserved Table6-86.Timer1Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x02044800 PID12 PeripheralIdentificationRegister 0x02044804 EMUMGT_CLKSPD Timer1EmulationManagement/ClockSpeedRegister 0x02044810 TIM12 Timer1CounterRegister12 0x02044814 TIM34 Timer1CounterRegister34 0x02044818 PRD12 Timer1PeriodRegister12 0x0204481C PRD34 Timer1PeriodRegister34 0x02044820 TCR Timer1ControlRegister 0x02044824 TGCR Timer1GlobalControlRegister 0x02044828-0x020448FF - Reserved Table6-87.Timer2Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x02044C00 PID12 PeripheralIdentificationRegister 0x02044C04 EMUMGT_CLKSPD Timer2EmulationManagement/ClockSpeedRegister 0x02044C10 TIM12 Timer2CounterRegister12 0x02044C14 TIM34 Timer2CounterRegister34 0x02044C18 PRD12 Timer2PeriodRegister12 0x02044C1C PRD34 Timer2PeriodRegister34 0x02044C20 TCR Timer2ControlRegister 0x02044C24 TGCR Timer2GlobalControlRegister 0x02044C28-0x02044CFF - Reserved Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 173 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-88.Timer3Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x02045000 PID12 PeripheralIdentificationRegister 0x02045004 EMUMGT_CLKSPD Timer3EmulationManagement/ClockSpeedRegister 0x02045010 TIM12 Timer3CounterRegister12 0x02045014 TIM34 Timer3CounterRegister34 0x02045018 PRD12 Timer3PeriodRegister12 0x0204501C PRD34 Timer3PeriodRegister34 0x02045020 TCR Timer3ControlRegister 0x02045024 TGCR Timer3GlobalControlRegister 0x02045028-0x020450FF - Reserved 6.21.3 Timer Electrical Data/Timing Table6-89.TimingRequirementsforTimerInput(1)(seeFigure6-52) 720,800,900, NO. 1100 UNIT MIN MAX 1 t Pulseduration,TIMIxHhigh 12P(1) ns w(TIMIxH) 2 t Pulseduration,TIMIxLlow 12P ns w(TIMIxL) (1) P=1/CPUclockfrequencyinns. Table6-90.SwitchingCharacteristicsforTimerOutput overoperatingfree-airtemperaturerange(unlessotherwisenoted) 720,800,900,1100 NO. PARAMETER UNIT MIN TYP MAX 3 t Pulseduration,TIMOxHhigh 12P(1) w(TIMOxH) 4 t Pulseduration,TIMOxLlow 12P w(TIMOxL) (1) P=1/CPUclockfrequencyinns. 2 1 TINPLx 4 3 TOUTLx Figure6-52.TimerTiming 174 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.22 VLYNQ Peripheral 6.22.1 VLYNQ Device-Specific Information TheVLYNQperipheralconformstotheVLYNQModuleSpecification(revision2.x).Bydefault,theVLYNQ peripheralisinitializedwithadeviceIDof0x22. 6.22.2 VLYNQ Peripheral Register Descriptions Table6-91.VLYNQRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x38000000 - Reserved 0x38000004 CTRL VLYNQLocalControlRegister 0x38000008 STAT VLYNQLocalStatusRegister 0x3800000C INTPRI VLYNQLocalInterruptPriorityVectorStatus/ClearRegister 0x38000010 INTSTATCLR VLYNQLocalInterruptStatus/ClearRegister 0x38000014 INTPENDSET VLYNQLocalInterruptPending/SetRegister 0x38000018 INTPTR VLYNQLocalInterruptPointerRegister 0x3800001C XAM VLYNQLocalTransmitAddressMap 0x38000020 RAMS1 VLYNQLocalReceiveAddressMapSize1 0x38000024 RAMO1 VLYNQLocalReceiveAddressMapOffset1 0x38000028 RAMS2 VLYNQLocalReceiveAddressMapSize2 0x3800002C RAMO2 VLYNQLocalReceiveAddressMapOffset2 0x38000030 RAMS3 VLYNQLocalReceiveAddressMapSize3 0x38000034 RAMO3 VLYNQLocalReceiveAddressMapOffset3 0x38000038 RAMS4 VLYNQLocalReceiveAddressMapSize4 0x3800003C RAMO4 VLYNQLocalReceiveAddressMapOffset4 0x38000040 CHIPVER VLYNQLocalChipVersionRegister 0x38000044 AUTNGO VLYNQLocalAutoNegotiationRegister 0x38000048 MANNGO VLYNQLocalManualNegotiationRegister 0x3800004C NGOSTAT VLYNQLocalNegotiationStatusRegister 0x38000050-0x3800005C - Reserved 0x38000060 INTVEC0 VLYNQLocalInterruptVector3-0 0x38000064 INTVEC1 VLYNQLocalInterruptVector7-4 0x38000068-0x3800007C - Reservedforfutureuse[LocalInterruptVectors8-31] 0x38000080 RREVID VLYNQRemoteRevisionRegister 0x38000084 RCTRL VLYNQRemoteControlRegister 0x38000088 RSTAT VLYNQRemoteStatusRegister 0x3800008C RINTPRI VLYNQRemoteInterruptPriorityVectorStatus/ClearRegister 0x38000090 RINTSTATCLR VLYNQRemoteInterruptStatus/ClearRegister 0x38000094 RINTPENDSET VLYNQRemoteInterruptPending/SetRegister 0x38000098 RINTPTR VLYNQRemoteInterruptPointerRegister 0x3800009C RXAM VLYNQRemoteTransmitAddressMap 0x380000A0 RRAMS1 VLYNQRemoteReceiveAddressMapSize1 0x380000A4 RRAMO1 VLYNQRemoteReceiveAddressMapOffset1 0x380000A8 RRAMS2 VLYNQRemoteReceiveAddressMapSize2 0x380000AC RRAMO2 VLYNQRemoteReceiveAddressMapOffset2 0x380000B0 RRAMS3 VLYNQRemoteReceiveAddressMapSize3 0x380000B4 RRAMO3 VLYNQRemoteReceiveAddressMapOffset3 0x380000B8 RRAMS4 VLYNQRemoteReceiveAddressMapSize4 0x380000BC RRAMO4 VLYNQRemoteReceiveAddressMapOffset4 Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 175 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-91.VLYNQRegisters(continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x380000C0 RCHIPVER VLYNQRemoteChipVersionRegister 0x380000C4 RAUTNGO VLYNQRemoteAutoNegotiationRegister 0x380000C8 RMANNGO VLYNQRemoteManualNegotiationRegister 0x380000CC RNGOSTAT VLYNQRemoteNegotiationStatusRegister 0x380000D0-0x380000DC - Reserved 0x380000E0 RINTVEC0 VLYNQRemoteInterruptVector3-0 0x380000E4 RINTVEC1 VYLNQRemoteInterruptVector7-4 0x380000E8-0x380000FC - Reservedforfutureuse[RemoteInterruptVectors8-31] 6.22.3 VLYNQ Electrical Data/Timing Table6-92.TimingRequirementsforVCLKforVLYNQ(seeFigure6-53) 720,800,900,1100 NO. UNIT MIN MAX 1 t Cycletime,VCLK 8 ns c(VCLK) Pulseduration,VCLKhigh,VCLKInput 2 ns 2 t w(VCLKH) Pulseduration,VCLKhigh,VCLKOutput 3 ns Pulseduration,VCLKlow,VCLKInput 2 ns 3 t w(VCLKL) Pulseduration,VCLKlow,VCLKOutput 3 ns 4 t Transitiontime,VCLK ns t(VCLK) 1 4 2 VCLK 4 3 Figure6-53.VCLKTimingforVLYNQ 176 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 Table6-93.SwitchingCharacteristics OverRecommendedOperatingConditionsforTransmitDatafortheVLYNQModule(seeFigure6-54) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 1 t Delaytime,VCLKhightoVTXD[3:0]invalid[SLOWMode] 2.25 ns d(VCLKH-TXDI) 1 t Delaytime,VCLKhightoVTXD[3:0]invalid[FASTMode] 0.86 ns d(VCLKH-TXDI) 2 t Delaytime,VCLKtoVTXD[3:0]valid 6.85 ns d(VCLKH-TXDV) Table6-94.TimingRequirementsforReceiveDatafortheVLYNQModule(seeFigure6-54) 720,800,900,1100 NO. UNIT MIN MAX RTMdisabled 0.2 ns RTMenabled,RXDFlop=0 1.25 ns RTMenabled,RXDFlop=1 0.91 ns RTMenabled,RXDFlop=2 0.64 ns Setuptime,VRXD[3:0]validbeforeVCLK 3 t RTMenabled,RXDFlop=3 0.36 ns su(RXDV-VCLKH) high RTMenabled,RXDFlop=4 0.09 ns RTMenabled,RXDFlop=5 -0.18 ns RTMenabled,RXDFlop=6 -0.44 ns RTMenabled,RXDFlop=7 -0.69 ns RTMdisabled 2 ns RTMenabled,RXDFlop=0 0.95 ns RTMenabled,RXDFlop=1 1.33 ns RTMenabled,RXDFlop=2 1.72 ns 4 t Holdtime,VRXD[3:0]validafterVCLKhigh RTMenabled,RXDFlop=3 2.15 ns h(VCLKH-RXDV) RTMenabled,RXDFlop=4 2.58 ns RTMenabled,RXDFlop=5 3.03 ns RTMenabled,RXDFlop=6 3.46 ns RTMenabled,RXDFlop=7 3.89 ns 1 VCLK 2 VTXD[3:0] Data 3 4 VRXD[3:0] Data Figure6-54.VLYNQTransmit/ReceiveTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 177 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.23 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. Whenconfiguredasanoutput,awritetoaninternalregistercancontrolthestatedrivenontheoutputpin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. TheGPIOpinsaregroupedintobanksof16pinsperbank(i.e.,bank0consistsofGPIO[0:15]). TheGPIOperipheralsupportsthefollowing: • Upto3.3-VGPIOpins • Interrupts: – Upto16uniqueGPIO[0:15]interruptsfromBank0 – OneGPIObank(aggregated)interruptsignalfromtheGPIOsinBank1 – Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO signal • DMAevents: – Upto10uniqueGPIODMAeventsfromBank0 • Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to antherprocessduringGPIOprogramming). • SeparateInput/Outputregisters • Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can betoggledbydirectwritetotheoutputregister(s). • Output register, when read, reflects output drive status. This, in addition to the input register reflecting pinstatusandopen-drainI/Ocell,allowswiredlogicbeimplemented. ThememorymapfortheGPIOregistersisshowninTable6-95. For more detailed information on GPIOs, see the TMS320DM647/DM648 DSP General-Purpose Input/Output(GPIO)User'sGuide(literaturenumberSPRUEK7). 6.23.1 GPIO Peripheral Register Descriptions Table6-95.GPIORegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x02048000 PID PeripheralIdentificationRegister 0x02048004 - Reserved 0x02048008 BINTEN GPIOinterruptper-bankenable GPIOBanks0and1 0x0204800C - Reserved 0x02048010 DIR GPIOBanks0and1DirectionRegister(GPIO[0:31]) 0x02048014 OUT_DATA GPIOBanks0and1OutputDataRegister(GPIO[0:31]) 0x02048018 SET_DATA GPIOBanks0and1SetDataRegister(GPIO[0:31]) 0x0204801C CLR_DATA GPIOBanks0and1Cleardataforbanks0and1(GPIO[0:31]) 0x02048020 IN_DATA GPIOBanks0and1InputDataRegister(GPIO[0:31]) 0x02048024 SET_RIS_TRIG GPIOBanks0and1SetRisingEdgeInterruptRegister(GPIO[0:31]) 0x02048028 CLR_RIS_TRIG GPIOBanks0and1ClearRisingEdgeInterruptRegister(GPIO[0:31]) 0x0204802C SET_FAL_TRIG GPIOBanks0and1SetFallingEdgeInterruptRegister(GPIO[0:31]) 0x02048030 CLR_FAL_TRIG GPIOBanks0and1ClearFallingEdgeInterruptRegister(GPIO[0:31]) 0x02048034 INSTAT GPIOBanks0and1InterruptStatusRegister(GPIO[0:31]) 178 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.23.2 GPIO Peripheral Input/Output Electrical Data/Timing Table6-96.TimingRequirementsforGPIOInputs(1)(seeFigure6-55) 720,800,900, NO. 1100 UNIT MIN MAX 1 t Pulseduration,GPIxhigh 12P ns w(GPIH) 2 t Pulseduration,GPIxlow 12P ns w(GPIL) (1) ThepulsewidthgivenissufficienttogenerateaCPUinterruptoranEDMAevent.However,ifauserwantstohavethedevice recognizetheGPIxchangesthroughsoftwarepollingoftheGPIOregister,theGPIxdurationmustbeextendedtoallowthedevice enoughtimetoaccesstheGPIOregisterthroughtheinternalbus.P=1/CPUclockfrequencyinns. Table6-97.SwitchingCharacteristicsOverRecommendedOperatingConditionsforGPIOOutputs (seeFigure6-55) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 3 t Pulseduration,GPOxhigh 6P(1) ns w(GPOH) 4 t Pulseduration,GPOxlow 6P(1) ns w(GPOL) (1) Thisparametervalueshouldnotbeusedasamaximumperformancespecification.Actualperformanceofback-to-backaccessesofthe GPIOisdependentuponinternalbusactivity.P=1/CPUclockfrequencyinns. 2 1 GPIx 4 3 GPOx Figure6-55.GPIOPortTiming Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 179 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 6.24 Emulation Features and Capability 6.24.1 Advanced Event Triggering (AET) The device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the followingcapabilities: • HardwareProgramBreakpoints:specifyaddressesoraddressrangesthatcangenerateeventssuch ashaltingtheprocessorortriggeringthetracecapture. • Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate eventssuchashaltingtheprocessorortriggeringthetracecapture. • Counters:counttheoccurrenceofaneventorcyclesforperformancemonitoring. • State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to preciselygenerateeventsforcomplexsequences. FormoreinformationonAET,seethefollowingdocuments: • Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs Application Report (literaturenumberSPRA753) • Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded MicroprocessorSystemsApplicationReport(literaturenumberSPRA387) 6.24.2 Trace The device supports Trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug informationforanalysis.Traceworksinreal-timeanddoesnotimpacttheexecutionofthesystem. For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and TraceHeadersTechnicalReferenceManual(literaturenumberSPRU655). 180 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 6.25 IEEE 1149.1 JTAG TheJTAG (2)interfaceisusedforBSDLtestingandemulationofthedevice. TRST needs to be released only when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK;otherwise,theboundaryscanlogicmaynotrespondasexpectedafterTRSTisasserted. For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to make certain that TRST will always be asserted upon power up and the device's internal emulation logic will always be properlyinitialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllersmaynotdriveTRSThighbutexpecttheuseofapullupresistoronTRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally driveTRSThighbeforeattemptinganyemulationorboundaryscanoperations. 6.25.1 JTAG Peripheral Register Description(s) - JTAG ID Register Table6-98.JTAGIDRegister HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS Read-only.Provides32-bit 0x02049018 JTAGID JTAGIdentificationRegister JTAGIDofthedevice. (2) IEEEStandard1149.1-1990Standard-Test-AccessPortandBoundaryScanArchitecture. TheJTAGIDregisterisaread-onlyregisterthatidentifiestothecustomertheJTAG/DeviceID.TheJTAG ID register resides at address location 0x0204 9018. The register hex value is: 0x0B77 A02F . For the actualregisterbitnamesandtheirassociatedbitfielddescriptions,seeFigure6-56andTable6-99. Figure6-56.JTAGIDRegister(0x02049018) 31-28 27-12 11-1 0 VERSION PARTNUMBER(16-Bit) MANUFACTURER(11-Bit) LSB R-0001 R-1011011101111010 R-00000010111 R-1 LEGEND:R=Read,W=Write,n=valueatreset Table6-99.JTAGIDRegisterSelectionBitDescriptions BIT NAME DESCRIPTION 31:28 VERSION Siliconversionvalue:0001. 27:12 PARTNUMBER PartNumber(16-Bit)value:1011011101111010. 11-1 MANUFACTURER Manufacturer(11-Bit)value:00000010111. 0 LSB LSB.Thisbitisreadasa1. 6.25.2 JTAG Electrical Data/Timing Table6-100.TimingRequirementsforJTAGTestPort(seeFigure6-57) 720,800,900,1100 NO. UNIT MIN MAX 1 t Cycletime,TCK 35 ns c(TCK) 3 t Setuptime,TDI/TMS/TRSTvalidbeforeTCKhigh 2 ns su(TDIV-TCKH) 4 t Holdtime,TDI/TMS/TRSTvalidafterTCKhigh 0 ns h(TCKH-TDIV) Copyright©2007–2012,TexasInstrumentsIncorporated PeripheralInformationandElectricalSpecifications 181 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com Table6-101.SwitchingCharacteristicsOverRecommendedOperatingConditionsforJTAGTestPort (seeFigure6-57) 720,800,900,1100 NO. PARAMETER UNIT MIN MAX 2 t Delaytime,TCKlowtoTDOvalid 0 0.25×t ns d(TCKL-TDOV) c(TCK) 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure6-57.JTAGTest-PortTiming 182 PeripheralInformationandElectricalSpecifications Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 www.ti.com SPRS372H–MAY2007–REVISEDAPRIL2012 7 Mechanical Data Thefollowingtable(s)showthethermalresistancecharacteristicsfortheZUTmechanicalpackage. 7.1 Thermal Data for ZUT Table7-1.ThermalResistanceCharacteristics(PBGAPackage)[ZUT] °C/W(1) AIRFLOW(m/s)(2) RΘ RΘJCJunction-to-case 1.7 N/A JC RΘ RΘJBJunction-to-board 8.6 N/A JB RΘ RΘJAJunction-to-freeair 17.2 0.0 JA 13.7 1.0 12.4 2.0 11.5 3.0 ψ ψJTJunction-to-packagetop 0.6 0.0 JT 0.6 1.0 0.6 2.0 0.7 3.0 ψi ψJBJunction-to-board 8.4 0.0 JB 7.4 1.0 7.0 2.0 6.7 3.0 (1) Thejunction-to-casemeasurementwasconductedinaJEDECdefined1S0Psystem.OthermeasurementswereconductedinaJEDEC defined1S2Psystemandwillchangebasedonenvironmentaswellasapplication. Formoreinformation,seethesethreeEIA/JEDECstandards: • EIA/JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentConditions-NaturalConvection(StillAir) • EIA/JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements (2) m/s=meterspersecond Copyright©2007–2012,TexasInstrumentsIncorporated MechanicalData 183 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

TMS320DM647 TMS320DM648 SPRS372H–MAY2007–REVISEDAPRIL2012 www.ti.com 7.2 Packaging Information The following packaging information and addendum reflects the most current data available for the designateddevice(s).Thisdataissubjecttochangewithoutnoticeandwithoutrevisionofthisdocument. 184 MechanicalData Copyright©2007–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM647TMS320DM648

PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320DM647CUT9 NRND FCBGA CUT 529 Green (RoHS Call TI Level-4-245C-72HR 0 to 0 TMS320DM647CUT & no Sb/Br) @2007 TI 900MHZ TMS320DM647CUTA6 NRND FCBGA CUT 529 TBD Call TI Call TI TMS320DM647CUTA8 NRND FCBGA CUT 529 TBD Call TI Call TI 0 to 0 TMS320DM647CUTD7 NRND FCBGA CUT 529 Green (RoHS Call TI Level-4-245C-72HR 0 to 0 TMS320DM647CUT & no Sb/Br) @2007 TI D720MHZ TMS320DM647CUTD9 NRND FCBGA CUT 529 Green (RoHS Call TI Level-4-245C-72HR -40 to 90 TMS320DM647CUT & no Sb/Br) @2007 TI D900MHZ TMS320DM647ZUT7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM647ZUT Exempt) @2007 TI 720MHZ TMS320DM647ZUT9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM647ZUT Exempt) @2007 TI 900MHZ TMS320DM647ZUTD7 NRND FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM647ZUT Exempt) @2007 TI D720MHZ TMS320DM648CUT7 ACTIVE FCBGA CUT 529 84 Green (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648CUT & no Sb/Br) @2007 TI 720MHZ TMS320DM648CUT9 ACTIVE FCBGA CUT 529 84 Green (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648CUT & no Sb/Br) @2007 TI 900MHZ TMS320DM648CUTA8 ACTIVE FCBGA CUT 529 84 Green (RoHS SNAGCU Level-4-245C-72HR -40 to 105 TMS320DM648CUT & no Sb/Br) @2007 TI A800MHZ TMS320DM648CUTD7 ACTIVE FCBGA CUT 529 84 Green (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648CUT & no Sb/Br) @2007 TI D720MHZ TMS320DM648ZUT1 OBSOLETE FCBGA ZUT 529 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 1.1GHZ Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320DM648ZUT7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TMS320DM648ZUT9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ TMS320DM648ZUT9HK ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ TMS320DM648ZUTA8 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 105 TMS320DM648ZUT Exempt) @2007 TI A800MHZ TMS320DM648ZUTD7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TMS320DM648ZUTD9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D900MHZ TNETV2685FIBZUT11 OBSOLETE FCBGA ZUT 529 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 1.1GHZ TNETV2685FIBZUT5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685FIBZUT7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685FIBZUT9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ TNETV2685FIBZUTA5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685FIBZUTA7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685FIBZUTA9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) D900MHZ TNETV2685FIDZUT11 OBSOLETE FCBGA ZUT 529 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 1.1GHZ TNETV2685FIDZUT5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685FIDZUT7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685FIDZUT9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ TNETV2685FIDZUTA5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685FIDZUTA7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685FIDZUTA9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D900MHZ TNETV2685VIDZUT11 OBSOLETE FCBGA ZUT 529 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 1.1GHZ TNETV2685VIDZUT5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685VIDZUT7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685VIDZUT9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ TNETV2685VIDZUTA5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TNETV2685VIDZUTA7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685VIDZUTA9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D900MHZ TNETV2685ZUT11 OBSOLETE FCBGA ZUT 529 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 1.1GHZ TNETV2685ZUT5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685ZUT7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 720MHZ TNETV2685ZUT9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ TNETV2685ZUTA5 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685ZUTA7 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D720MHZ TNETV2685ZUTA9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR -40 to 90 TMS320DM648ZUT Exempt) @2007 TI D900MHZ VCBUSAM648T9 ACTIVE FCBGA ZUT 529 84 Pb-Free (RoHS SNAGCU Level-4-245C-72HR 0 to 90 TMS320DM648ZUT Exempt) @2007 TI 900MHZ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2019 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5

None

IMPORTANTNOTICEANDDISCLAIMER TIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCE DESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES“ASIS” ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANY IMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRD PARTYINTELLECTUALPROPERTYRIGHTS. TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.Youaresolelyresponsiblefor(1)selectingtheappropriate TIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicable standards,andanyothersafety,security,orotherrequirements.Theseresourcesaresubjecttochangewithoutnotice.TIgrantsyou permissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.Other reproductionanddisplayoftheseresourcesisprohibited.NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythird partyintellectualpropertyright.TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims, damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources. TI’sproductsareprovidedsubjecttoTI’sTermsofSale(www.ti.com/legal/termsofsale.html)orotherapplicabletermsavailableeitheron ti.comorprovidedinconjunctionwithsuchTIproducts.TI’sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI’sapplicable warrantiesorwarrantydisclaimersforTIproducts. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright©2019,TexasInstrumentsIncorporated