TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 1 TMS320DM6435 Digital Media Processor 1.1 Features • High-PerformanceDigitalMediaProcessor – 256K-Bit(32K-Byte)L1PProgram (DM6435) RAM/Cache[FlexibleAllocation] – 2.5-,2.-,1.67-,1.51-,1.43-nsnsInstruction – 640K-Bit(80K-Byte)L1DDataRAM/Cache CycleTime [FlexibleAllocation] – 400-,500-,600-,660-,700-MHzC64x+™ – 1M-Bit(128K-Byte)L2UnifiedMapped ClockRate RAM/Cache[FlexibleAllocation] – Eight32-BitC64x+Instructions/Cycle • SupportsLittleEndianModeOnly – 3200,4000,4800,5280,5600MIPS • VideoProcessingSubsystem(VPSS),VPFE – FullySoftware-CompatibleWithC64x Only – CommercialandAutomotive(QorSsuffix) – FrontEndProvides: Grades • CCDandCMOSImagerInterface – LowPowerDevice(Lsuffix) • BT.601/BT.656DigitalYCbCr4:2:2 • VelociTI.2™ExtensionstoVelociTI™ (8-/16-Bit)Interface AdvancedVery-Long-Instruction-Word(VLIW) • PreviewEngineforReal-TimeImage TMS320C64x+™DSPCore Processing – EightHighlyIndependentFunctionalUnits • GluelessInterfacetoCommonVideo WithVelociTI.2Extensions: Decoders • SixALUs(32-/40-Bit),EachSupports • HistogramModule Single32-Bit,Dual16-Bit,orQuad8-Bit • Auto-Exposure,Auto-WhiteBalanceand ArithmeticperClockCycle Auto-FocusModule • TwoMultipliersSupportFour16x16-Bit • ResizeEngine Multiplies(32-BitResults)perClock – ResizeImagesFrom1/4xto4x CycleorEight8x8-BitMultiplies(16-Bit – SeparateHorizontal/VerticalControl Results)perClockCycle • ExternalMemoryInterfaces(EMIFs) – Load-StoreArchitectureWithNon-Aligned – 32-BitDDR2SDRAMMemoryController Support With256M-ByteAddressSpace(1.8-VI/O) – 6432-BitGeneral-PurposeRegisters • Supportsupto333-MHz(datarate)bus – InstructionPackingReducesCodeSize andinterfacestoDDR2-400SDRAM – AllInstructionsConditional – Asynchronous8-BitWideEMIF(EMIFA) – AdditionalC64x+™Enhancements Withupto64M-ByteAddressReach • ProtectedModeOperation • FlashMemoryInterfaces • ExceptionsSupportforErrorDetection – NOR(8-Bit-WideData) andProgramRedirection – NAND(8-Bit-WideData) • HardwareSupportforModuloLoop • EnhancedDirect-Memory-Access(EDMA) Auto-FocusModuleOperation Controller(64IndependentChannels) • C64x+InstructionSetFeatures • Two64-BitGeneral-PurposeTimers(Each – Byte-Addressable(8-/16-/32-/64-BitData) ConfigurableasTwo32-BitTimers) – 8-BitOverflowProtection • One64-BitWatchDogTimer – Bit-FieldExtract,Set,Clear – Normalization,Saturation,Bit-Counting • TwoUARTs(OnewithRTSandCTSFlow Control) – VelociTI.2IncreasedOrthogonality – C64x+Extensions • Master/SlaveInter-IntegratedCircuit • Compact16-bitInstructions (I2CBus™) • AdditionalInstructionstoSupport • MultichannelBufferedSerialPort(McBSP) ComplexMultiplies – I2SandTDM • C64x+L1/L2MemoryArchitecture – AC97AudioCodecInterface Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdocument. Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com – SPI • IEEE-1149.1(JTAG™) – StandardVoiceCodecInterface(AIC12) Boundary-Scan-Compatible – TelecomInterfaces–ST-Bus,H-100 • Upto111General-PurposeI/O(GPIO)Pins – 128ChannelMode (MultiplexedWithOtherDeviceFunctions) • MultichannelAudioSerialPort(McASP0) • Packages: – FourSerializersandSPDIF(DIT)Mode – 361-PinPb-FreePBGAPackage • 16-BitHost-PortInterface(HPI) (ZWTSuffix),0.8-mmBallPitch • High-EndCANController(HECC) – 376-PinPlasticBGAPackage (ZDUSuffix),1.0-mmBallPitch • 10/100Mb/sEthernetMAC(EMAC) • 0.09-m m/6-LevelCuMetalProcess(CMOS) – IEEE802.3Compliant • 3.3-Vand1.8-VI/O,1.2-VInternal – SupportsMediaIndependentInterface(MII) (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4) – ManagementDataI/O(MDIO)Module • VLYNQ™Interface(FPGAInterface) • 3.3-Vand1.8-VI/O,1.05-VInternal (-7/-6/-5/-4/-L/-Q5) • ThreePulseWidthModulator(PWM)Outputs • Applications: • On-ChipROMBootloader – DigitalMedia • IndividualPower-SavingsModes – NetworkedMediaEncode • FlexiblePLLClockGenerators – VideoImaging 1.2 Description The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction setfrompreviousdevices. AnyreferencetotheC64xDSPorC64xCPUalsoapplies,unlessotherwisenoted,totheC64x+DSP and C64x+CPU,respectively. With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literaturenumberSPRU732). The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space —384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configuredasmappedmemory,cache,orcombinationsofthetwo. 2 TMS320DM6435DigitalMediaProcessor SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slowermemories/peripherals,andahigherspeedsynchronousmemoryinterfaceforDDR2. The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-endinputperipheralusedforvideocapture. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between64and1024. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerateallPHYdevicesinthesystem. The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with hostprocessors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harshenvironmenttocommunicateseriallywithothercontrollers,typicallyinautomotiveapplications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document andtheassociatedperipheralreferenceguides. The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into sourcecodeexecution. SubmitDocumentationFeedback TMS320DM6435DigitalMediaProcessor 3

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 1.3 Functional Block Diagram Figure1-1showsthefunctionalblockdiagramoftheDM6435device. BT.656, Y/C, Raw (Bayer) JTAG Interface 16b System Control DSP Subsystem Video Processing Subsystem (VPSS) Input OSC C64x+(cid:1) DSP CPU Front End Clock(s) PLLs/Clock Generator 128 KB L2 RAM CCD Resizer Power/Sleep Controller 32 KB 80 KB Controller Histogram/ L1 Pgm L1 Data Video 3A Interface Preview Pin Multiplexing Boot ROM Switched Central Resource (SCR) Peripherals Serial Interfaces System McASP McBSP I2C HECC UART GPuernpeorsael- WaTticmhedrog PWM GPIO Timer EDMA Connectivity Program/Data Storage EMAC DDR2 Async EMIF/ VLYNQ With HPI Mem Ctlr NAND/ MDIO (32b) (8b) Figure1-1.TMS320DM6435FunctionalBlockDiagram 4 TMS320DM6435DigitalMediaProcessor SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Contents 1 TMS320DM6435DigitalMediaProcessor........... 1 Temperature(UnlessOtherwiseNoted)........... 127 1.1 Features.............................................. 1 6 PeripheralInformationandElectrical ............................................ Specifications......................................... 129 1.2 Description 2 1.3 FunctionalBlockDiagram............................ 4 6.1 ParameterInformation............................. 129 RevisionHistory............................................... 6 6.2 RecommendedClockandControlSignalTransition ............................................ 2 DeviceOverview......................................... 7 Behavior 130 .................................... ................................ 6.3 PowerSupplies 130 2.1 DeviceCharacteristics 7 6.4 EnhancedDirectMemoryAccess(EDMA3) ......................... 2.2 CPU(DSPCore)Description 8 ........................................... Controller 137 .......................................... 2.3 C64x+CPU 11 ............................................... 6.5 Reset 149 ............................. 2.4 MemoryMapSummary 12 ........ 6.6 ExternalClockInputFromMXI/CLKINPin 158 .................................... 2.5 PinAssignments 16 ......................................... 6.7 ClockPLLs 160 .................................. 2.6 TerminalFunctions 24 ........................................... 6.8 Interrupts 165 ...................................... 2.7 DeviceSupport 58 ................. 6.9 ExternalMemoryInterface(EMIF) 168 2.8 DeviceandDevelopment-SupportTool . ....................................... 6.10 VideoProcessingSub-System(VPSS)Overview 176 Nomenclature 58 6.11 UniversalAsynchronousReceiver/Transmitter ............................. 2.9 DocumentationSupport 60 ............................................. (UART) 187 3 DeviceConfiguration.................................. 61 ....................... 6.12 Inter-IntegratedCircuit(I2C) 190 ........................... 3.1 SystemModuleRegisters 61 ............... 6.13 Host-PortInterface(HPI)Peripheral 194 ............................... 3.2 PowerConsiderations 62 ........ 6.14 MultichannelBufferedSerialPort(McBSP) 199 ................................ 3.3 ClockConsiderations 64 6.15 MultichannelAudioSerialPort(McASP0) 3.4 BootSequence...................................... 67 Peripheral.......................................... 208 3.5 ConfigurationsAtReset............................. 78 6.16 High-EndControllerAreaNetworkController ............................................. .......................... (HECC) 216 3.6 ConfigurationsAfterReset 80 ........ ...................... 6.17 EthernetMediaAccessController(EMAC) 222 3.7 MultiplexedPinConfigurations 84 .......... ........ 6.18 ManagementDataInput/Output(MDIO) 229 3.8 DeviceInitializationSequenceAfterReset 119 .............................................. ......................... 6.19 Timers 230 3.9 DebuggingConsiderations 121 ..................... 4 SystemInterconnect................................. 123 6.20 PulseWidthModulator(PWM) 233 ............................................. ............... 6.21 VLYNQ 235 4.1 SystemInterconnectBlockDiagram 123 ............. 5 DeviceOperatingConditions....................... 125 6.22 General-PurposeInput/Output(GPIO) 239 ................................. 5.1 AbsoluteMaximumRatingsOverOperating 6.23 IEEE1149.1JTAG 243 TemperatureRange(UnlessOtherwiseNoted)... 125 7 MechanicalData....................................... 245 5.2 RecommendedOperatingConditions ............. 126 7.1 ThermalDataforZWT............................. 245 5.3 ElectricalCharacteristicsOverRecommended 7.1.1 ThermalDataforZDU............................. 246 RangesofSupplyVoltageandOperating ............................. 7.1.2 PackagingInformation 246 SubmitDocumentationFeedback Contents 5

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. This data manual revision history highlights the technical changes made to the SPRS344B device-specific datamanualtomakeitanSPRS344Crevision. This data manual revision history highlights the technical changes made to the SPRS344B device-specific datamanualtomakeitanSPRS344Crevision. Scope: Applicable updates to the TMS320DM643x DMP, specifically relating to the TMS320DM6435 device,havebeenincorporated. • Added660-and700-MHzC64x+™devicespeeds. • Addeddesignatorsforlow-power(-L)devices. SEE ADDITIONS/MODIFICATIONS/DELETIONS Global • Updated/Changedsignalnamefrom"C_WE"to"C_WE" • Updated/Changedsignalnamefrom"C_WEN"to"C_WE" Section1.1 Added"5280,5600MIPS"to"High-PerformanceDigitalSignalProcessor(DM6435)"bullet Section1.2 • Infirstparagraph,updated/changedthefollowing: – Firstsentencefrom"Withperformanceupto4800millioninstructionspersecond(MIPS)ataclock rateof600MHz..."to"Withperformanceupto5600millioninstructionspersecond(MIPS)witha clockrateof700MHz..." – Fifthsentencefrom"TheDSPcorecanproduce...foratotalof2400millionMACspersecond...ora totalof4800MMACS."to"TheDSPcorecanproduce...foratotalof2800millionMACsper second...oratotalof5600MMACS." Section2.6 Table2-19,MultichannelAudioSerialPort(McASP0)TerminalFunctions: • Updated/ChangedAFSR0/DR0/GP[100]pindescriptionfrom"...framesynchronizationAFSX0..."to "...framesynchronizationAFSR0..." • Updated/ChangedAFSX0/DX1/GP[107]pindescriptionfrom"...framesynchronizationAFSR0..."to "...framesynchronizationAFSX0..." Section2.8 Updated/ChangedFigure2-10,DeviceNomenclature,toreflectnewdevicespeedsandlow-power designator(-Lsuffix). Section5 AddedfootnotetoSection5.1,AbsoluteMaximumRatingsOverOperatingTemperatureRange(Unless OtherwiseNoted). Section5 Updated/ChangedI andI testconditionsandfootnoteinSection5.3,ElectricalCharacteristicsOver CDD DDD RecommendedRangesofSupplyVoltageandOperatingTemperature(UnlessOtherwiseNoted). Section5.2 Deleted"Futurevariants..."footnotefromtable Section6.7.1 Table6-15,PLLC1ClockFrequencyRanges: • Updated/ChangedPLLOUT1.2V-CV maxvaluefrom"700MHz"to"600MHz"for DD -6/-5/-4/-L/-Q6/-Q5/-Q4devices. • Updated/ChangedSYSCLK11.05V-CV maxvaluefrom"560MHz"to"520MHz"for-7devices. DD Section6.7.1 Updated/Changedsentencefrom"TIrequiresEMIfiltermanufacturerMurata..."to"TIrecommendsEMI filtermanufacturerMurata..." Section6.7.4 Deleted"(-4,-4Q,-4S,-5,-5Q,-5S,-6)"fromTable6-19title,TimingRequirementsforMXI/CLKIN. 6 RevisionHistory SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the TMS320DM6435 DSP. The tables show significant features of the DM6435 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the packagetypewithpincount. Table2-1.CharacteristicsoftheDM6435Processor HARDWAREFEATURES DM6435 DDR2MemoryController (16-/32-bitbuswidth)[1.8VI/O] Asynchronous(8-bitbuswidth), AsynchronousEMIF[EMIFA] RAM,Flash,(8-bitNORor8-bitNAND) EDMA3 1(64independentchannels,8QDMAchannels) 264-bitGeneralPurpose Timers (configurableas264-bitor432-bit) 164-bitWatchDog UARTs 2(onewithRTSandCTSflowcontrol) Peripherals I2C 1(Master/Slave) Notallperipheralspins areavailableatthesame McBSP 1 time(Formoredetail,see McASP 1(4serailizers) theDeviceConfiguration 10/100EthernetMAC(EMAC)with section). 1 ManagementDataInput/Output(MDIO) VLYNQ 1 General-PurposeInput/OutputPort(GPIO) Upto111pins PWM 3outputs HPI(16-bit) 1 ConfigurableVideoPort 1Input(VPFE) HECC 1 Size(Bytes) 240KBRAM,64KBROM 32K-Byte(32KB)L1Program(L1P)RAM/Cache On-ChipMemory (Cacheupto32KB) Organization 80KBL1Data(L1D)RAM/Cache(Cacheupto32KB) 128KBUnifiedMappedRAM/Cache(L2) 64KBBootROM MegaModuleRevID RevisionIDRegister(MM_REVID.[15:0]) SeetheTMS320DM6437/35/33/31DigitalMedia (addresslocation:0x01812000) Processor(DMP)[SiliconRevisions1.1and1.0] CPUID+CPURevID ControlStatusRegister(CSR.[31:16]) SiliconErrata(literaturenumberSPRZ250). JTAGIDregister SeeSection6.23.1,JTAGID(JTAGID)Register JTAGBSDL_ID (addresslocation:0x01C40028) Description(s) 700(-7) 660(-Q6) CPUFrequency(1)(2) MHz 600(-6/-L) 500(-5/-Q5) 400(-4/-Q4) 2.5ns(-4/-Q4) 2ns(-5/-Q5) CycleTime(1)(2) ns 1.67ns(-6/-L) 1.51ns(-Q6) 1.43ns(-7) (1) Performancenumbersassumecorevoltageissetto1.2V. (2) Appliesto"tapeandreel"partnumbercounterpartsaswell.Formoreinformation,seeSection2.8,DeviceandDevelopment-Support ToolNomenclature. SubmitDocumentationFeedback DeviceOverview 7

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-1.CharacteristicsoftheDM6435Processor (continued) HARDWAREFEATURES DM6435 1.2V (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4) Core(V) Voltage(2) 1.05V (-7/-6/-5/-4/-L/-Q5) I/O(V) 1.8V,3.3V MXI/CLKINfrequencymultiplier PLLOptions x1(Bypass),x14tox30 (27MHzreference) 16x16mm,0.8mmpitch 361-PinBGA(ZWT) BGAPackage(s) 23x23mm,1.0mmpitch 376-PinBGA(ZDU) ProcessTechnology µm 0.09µm ProductStatus(3) ProductPreview(PP),AdvanceInformation(AI), PD orProductionData(PD) (3) PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsofTexas Instrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 2.2 CPU (DSP Core) Description The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 3232-bitregistersforatotalof64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32MSBsinthenextupperregister(whichisalwaysanodd-numberedregister). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memorytotheregisterfileandstoreresultsfromtheregisterfileintomemory. TheC64x+CPUextendstheperformanceoftheC64xcorethroughenhancementsandnewfeatures. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions. The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Othernewfeaturesinclude: 8 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 • SPLOOP-Asmallinstructionbufferin the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOPbufferarefullyinterruptible. • Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performedbythecodegenerationtools. • Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. • Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and fromsystemevents(suchasawatchdogtimeexpiration). • Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read,write,andexecutepermissions. • Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-runningtime-stampcounterisimplementedintheCPUwhichisnotsensitivetosystemstalls. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: • TMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide(literaturenumberSPRU732) • TMS320C64x+DSPMegamoduleReferenceGuide(literaturenumberSPRU871) • TMS320C64xtoTMS320C64x+CPUMigrationGuideApplicationReport(literaturenumberSPRAA84) • TMS320C64x+DSPCacheUser'sGuide(literaturenumberSPRU862) SubmitDocumentationFeedback DeviceOverview 9

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com ÁÁÁ ÁÁÁÁ Even src1 Odd register ÁÁÁÁÁÁ register file A file A (A0, A2, .L1 srcÁ2 ÁÁ ÁÁ (A1, A3, A4...A30) A5...A31) odd dsÁt Á ÁÁ (D) even dst long src 8 ÁÁ ST1b 32 MSB 32 LSB ST1a long src 8 Á even dst Á Á Data path A odd dst (D) .S1 src1 ÁÁ Á src2 ÁÁ ÁÁ 32 dst2 ÁÁÁ ÁÁ (A) dst1 32 (B) .M1 src1 ÁÁ ÁÁ src2 ÁÁ Á (C) 32 MSB LD1b 32 LÁSB Á Á LD1a Á dst Á .D1 src1 DA1Á Á src2 2x ÁÁ 1x Even Á Á Odd register DA2Á .D2 ssrrcc12 Á refigleis tBer (Bfi0le, BB2, dst Á (B1, B3, B4...B30) LD2a 32 LSB B5...B31) LD2b 32 MSB Á Á src2 (C) .M2 src1 ÁÁ dst2 32 (B) dst1 32 ÁÁ (A) ÁÁ src2 src1 Á Data path B .S2 odd dst Á (D) even dst 8 long src Á 32 MSB ST2a 32 LSB ST2b Á 8 long src ÁÁ even dst ÁÁ (D) odd dst .L2 ÁÁ src2 src1 Control Register A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure2-1.TMS320C64x+™CPU(DSPCore)DataPaths 10 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 2.3 C64x+ CPU The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P) consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The Level 1 Data memory/cache (L1D) consists of 80 KB—48 KB of which is mapped memory and 32 KB of which can be configured as mapped memory or 2-way set associated cache. The Level 2 memory/cache (L2)consistsofa128KBmemoryspacethatis shared between program and data space. L2 memory can beconfiguredasmappedmemory,cache,oracombinationofboth. Table2-2showsamemorymapoftheC64x+CPUcacheregistersforthedevice. Table2-2.C64x+CacheRegisters HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01840000 L2CFG L2Cacheconfigurationregister 0x01840020 L1PCFG L1PSizeCacheconfigurationregister 0x01840024 L1PCC L1PFreezeModeCacheconfigurationregister 0x01840040 L1DCFG L1DSizeCacheconfigurationregister 0x01840044 L1DCC L1DFreezeModeCacheconfigurationregister 0x01840048-0x01840FFC - Reserved 0x01841000 EDMAWEIGHT L2EDMAaccesscontrolregister 0x01841004-0x01841FFC - Reserved 0x01842000 L2ALLOC0 L2allocationregister0 0x01842004 L2ALLOC1 L2allocationregister1 0x01842008 L2ALLOC2 L2allocationregister2 0x0184200C L2ALLOC3 L2allocationregister3 0x01842010-0x01843FFF - Reserved 0x01844000 L2WBAR L2writebackbaseaddressregister 0x01844004 L2WWC L2writebackwordcountregister 0x01844010 L2WIBAR L2writebackinvalidatebaseaddressregister 0x01844014 L2WIWC L2writebackinvalidatewordcountregister 0x01844018 L2IBAR L2invalidatebaseaddressregister 0x0184401C L2IWC L2invalidatewordcountregister 0x01844020 L1PIBAR L1Pinvalidatebaseaddressregister 0x01844024 L1PIWC L1Pinvalidatewordcountregister 0x01844030 L1DWIBAR L1Dwritebackinvalidatebaseaddressregister 0x01844034 L1DWIWC L1Dwritebackinvalidatewordcountregister 0x01844038 - Reserved 0x01844040 L1DWBAR L1DBlockWriteback 0x01844044 L1DWWC L1DBlockWriteback 0x01844048 L1DIBAR L1Dinvalidatebaseaddressregister 0x0184404C L1DIWC L1Dinvalidatewordcountregister 0x01844050-0x01844FFF - Reserved 0x01845000 L2WB L2writebackallregister 0x01845004 L2WBINV L2writebackinvalidateallregister 0x01845008 L2INV L2GlobalInvalidatewithoutwriteback 0x0184500C-0x01845027 - Reserved 0x01845028 L1PINV L1PGlobalInvalidate 0x0184502C-0x01845039 - Reserved 0x01845040 L1DWB L1DGlobalWriteback 0x01845044 L1DWBINV L1DGlobalWritebackwithInvalidate 0x01845048 L1DINV L1DGlobalInvalidatewithoutwriteback SubmitDocumentationFeedback DeviceOverview 11

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-2.C64x+CacheRegisters (continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01848000-0x018480BC MAR0-MAR47 Reserved(correspondstobyteaddress0x00000000-0x2FFFFFFF) 0x018480C0-0x018480FC MAR48-MAR63 Reserved(correspondstobyteaddress0x30000000-0x3FFFFFFF) 0x01848100-0x01848104 MAR64-MAR65 Reserved(correspondstobyteaddress0x40000000-0x41FFFFFF) MemoryAttributeRegistersforEMIFA 0x01848108-0x01848124 MAR66-MAR73 (correspondstobyteaddress0x42000000-0x49FFFFFF) 0x01848128-0x0184812C MAR74-MAR75 Reserved(correspondstobyteaddress0x4A000000-0x4BFFFFFF) MemoryAttributeRegistersforVLYNQ(correspondstobyteaddress 0x01848130-0x0184813C MAR76-MAR79 0x4C000000-0x4FFFFFFF) 0x01848140-0x018481FC MAR80-MAR127 Reserved(correspondstobyteaddress0x50000000-0x7FFFFFFF) MemoryAttributeRegistersforDDR2 0x01848200-0x0184823C MAR128-MAR143 (correspondstobyteaddress0x80000000-0x8FFFFFFF) 0x01848240-0x018483FC MAR144-MAR255 Reserved(correspondstobyteaddress0x90000000-0xFFFFFFFF) 2.4 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all busmasters. 12 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-3.MemoryMapSummary START END SIZE C64x+ EDMAPERIPHERAL VPSS ADDRESS ADDRESS (Bytes) MEMORYMAP MEMORYMAP MEMORYMAP 0x00000000 0x000FFFFF 1M Reserved 0x00100000 0x0010FFFF 64K BootROM 0x00110000 0x007FFFFF 7M-64K Reserved 0x00800000 0x0081FFFF 128K L2RAM/Cache(1) 0x00820000 0x00E07FFF 6048K Reserved 0x00E08000 0x00E0FFFF 32K L1PRAM/Cache(1) Reserved 0x00E10000 0x00F03FFF 976K Reserved 0x00F04000 0x00F0FFFF 48K L1DRAM 0x00F10000 0x00F17FFF 32K L1DRAM/Cache(1) 0x00F18000 0x017FFFFF 9120K Reserved 0x01800000 0x01BFFFFF 4M CFGSpace 0x01C00000 0x01FFFFFF 4M CFGBusPeripherals CFGBusPeripherals 0x02000000 0x100FFFFF 225M Reserved 0x10100000 0x1010FFFF 64K BootROM Reserved 0x10110000 0x107FFFFF 7M-48K Reserved 0x10800000 0x1081FFFF 128K L2RAM/Cache(1) L2RAM/Cache(1) 0x10820000 0x10E07FFF 6048K Reserved Reserved 0x10E08000 0x10E0FFFF 32K L1PRAM/Cache(1) L1PRAM/Cache(1) 0x10E10000 0x10F03FFF 976K Reserved Reserved Reserved 0x10F04000 0x10F0FFFF 48K L1DRAM L1DRAM 0x10F10000 0x10F17FFF 32K L1DRAM/Cache(1) L1DRAM/Cache(1) 0x10F18000 0x10FFFFFF 1M-96K Reserved Reserved 0x11000000 0x1FFFFFFF 240M Reserved Reserved 0x20000000 0x20007FFF 32K DDR2ControlRegs DDR2ControlRegs 0x20008000 0x2FFFFFFF 256M-32K Reserved Reserved 0x30000000 0x3FFFFFFF 256M Reserved Reserved 0x40000000 0x41FFFFFF 32M Reserved Reserved 0x42000000 0x42FFFFFF 16M EMIFAData(CS2)(2) EMIFAData(CS2)(2) 0x43000000 0x43FFFFFF 16M Reserved Reserved 0x44000000 0x44FFFFFF 16M EMIFAData(CS3)(2) EMIFAData(CS3)(2) 0x45000000 0x45FFFFFF 16M Reserved Reserved 0x46000000 0x46FFFFFF 16M EMIFAData(CS4)(2) EMIFAData(CS4)(2) 0x47000000 0x47FFFFFF 16M Reserved Reserved 0x48000000 0x48FFFFFF 16M EMIFAData(CS5)(2) EMIFAData(CS5)(2) 0x49000000 0x49FFFFFF 16M Reserved Reserved 0x4A000000 0x4BFFFFFF 32M Reserved Reserved 0x4C000000 0x4FFFFFFF 64M VLYNQ(RemoteData) VLYNQ(RemoteData) 0x50000000 0x7FFFFFFF 768M Reserved Reserved 0x80000000 0x8FFFFFFF 256M DDR2MemoryController DDR2MemoryController DDR2MemoryController 0x90000000 0xFFFFFFFF 1792M Reserved Reserved Reserved (1) ForallbootmodesthatdefaulttoDSPBOOTADDR=0x00100000(i.e.,allbootmodesexcepttheEMIFAROMDirectBoot, BOOTMODE[3:0]=0100,FASTBOOT=0),thebootloadercodedisablesallC64x+cache(L2,L1P,andL1D)sothatuponexitfromthe bootloadercode,allC64x+memoriesareconfiguredasallRAM(L2CFG.L2MODE=0h,L1PCFG.L1PMODE=0h,and L1DCFG.L1DMODE=0h).Ifcacheuseisrequired,theapplicationcodemustexplicitlyenablethecache.Formoreinformationonboot modes,seeSection3.4.1,BootModes.Formoreinformationonthebootloader,seetheUsingtheTMS320DM643xBootloader ApplicationReport(literaturenumberSPRAAG0).FortheEMIFAROMDirectBoot(BOOTMODE[3:0]=0100,FASTBOOT=0),the bootloaderisnotexecuted—thatis,L2RAM/CachedefaultstoallRAM(L2CFG.L2MODE=0h);L1PRAM/Cachedefaultstoallcache (L1PCFG.L1PMODE=7h);andL1DRAM/Cachedefaultstoallcache(L1DCFG.L1DMODE=7h). (2) TheEMIFACS0andCS1arenotfunctionallysupportedontheDM6435device,andtherefore,arenotpinnedout. SubmitDocumentationFeedback DeviceOverview 13

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-4.ConfigurationMemoryMapSummary START END SIZE C64x+ ADDRESS ADDRESS (Bytes) 0x01800000 0x0180FFFF 64K C64x+InterruptController 0x01810000 0x01810FFF 4K C64x+PowerdownController 0x01811000 0x01811FFF 4K C64x+SecurityID 0x01812000 0x01812FFF 4K C64x+RevisionID 0x01820000 0x0182FFFF 64K C64x+EMC 0x01830000 0x0183FFFF 64K Reserved 0x01840000 0x0184FFFF 64K C64x+MemorySystem 0x01850000 0x0187FFFF 192K Reserved 0x01880000 0x01BBFFFF 3328K Reserved 0x01BC0000 0x01BC00FF 256 Reserved 0x01BC0100 0x01BC01FF 256 PinManagerandTrace 0x01BC0400 0x01BFFFFF 255K Reserved 0x01C00000 0x01C0FFFF 64K EDMACC 0x01C10000 0x01C103FF 1K EDMATC0 0x01C10400 0x01C107FF 1K EDMATC1 0x01C10800 0x01C10BFF 1K EDMATC2 0x01C10C00 0x01C1FFFF 29K Reserved 0x01C20000 0x01C203FF 1K UART0 0x01C20400 0x01C207FF 1K UART1 0x01C20800 0x01C20FFF 2K Reserved 0x01C21000 0x01C213FF 1K I2C 0x01C21400 0x01C217FF 1K Timer0 0x01C21800 0x01C21BFF 1K Timer1 0x01C21C00 0x01C21FFF 1K Timer2(Watchdog) 0x01C22000 0x01C223FF 1K PWM0 0x01C22400 0x01C227FF 1K PWM1 0x01C22800 0x01C22BFF 1K PWM2 0x01C22C00 0x01C22FFF 1K Reserved 0x01C23000 0x01C23FFF 4K HECCControl(1) 0x01C24000 0x01C253FF 5K HECCRAM 0x01C25400 0x01C3FFFF 107K Reserved 0x01C40000 0x01C407FF 2K SystemModule 0x01C40800 0x01C40BFF 1K PLLController1 0x01C40C00 0x01C40FFF 1K PLLController2 0x01C41000 0x01C41FFF 4K PowerandSleepController 0x01C42000 0x01C66FFF 148K Reserved 0x01C67000 0x01C677FF 2K GPIO 0x01C67800 0x01C67FFF 2K HPI 0x01C68000 0x01C6FFFF 32K Reserved 0x01C70000 0x01C73FFF 16K VPSSRegisters 0x01C74000 0x01C7FFFF 48K Reserved 0x01C80000 0x01C80FFF 4K EMACControlRegisters 0x01C81000 0x01C81FFF 4K EMACControlModuleRegisters 0x01C82000 0x01C83FFF 8K EMACControlModuleRAM 0x01C84000 0x01C847FF 2K MDIOControlRegisters (1) Softwaremustnotaccess"Reserved"locationsoftheHECC.AccesstoHECC"Reserved"locationsmayhangthedevice. 14 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-4.ConfigurationMemoryMapSummary (continued) START END SIZE C64x+ ADDRESS ADDRESS (Bytes) 0x01C84800 0x01CFFFFF 494K Reserved 0x01D00000 0x01D007FF 2K McBSP0 0x01D00800 0x01D00FFF 2K Reserved 0x01D01000 0x01D013FF 1K McASP0Control 0x01D01400 0x01D017FF 1K McASP0Data 0x01D01800 0x01DFFFFF 1018K Reserved 0x01E00000 0x01E00FFF 4K EMIFAControl 0x01E01000 0x01E01FFF 4K VLYNQControlRegisters 0x01E02000 0x0FFFFFFF 226M-8K Reserved SubmitDocumentationFeedback DeviceOverview 15

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 2.5 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing,seeSection3.7,MultiplexedPinConfigurationsofthisdocument. 2.5.1 Pin Map (Bottom View) Figure 2-2 through Figure 2-5 show the bottom view of the ZWT package pin assignments in four quadrants (A, B, C, and D). Figure 2-6 through Figure 2-9 show the bottom view of the ZDU package pin assignmentsinfourquadrants(A,B,C,andD). 1 2 3 4 5 6 7 8 9 10 W VSS VSS DDR_D[7] DDR_D[9] DDR_D[12] DDR_D[14] DDR_CLK DDR_CLK DDR_A[12] DDR_A[11] W V DVDDR2 DDR_D[4] DDR_D[6] DDR_D[8] DDR_D[11] DDR_D[13] DDR_D[15] DDR_CKE DDR_BA[1] DDDDRR__AA[[88]] V U DDR_D[2] DDR_D[3] DDR_D[5] DDR_DQS[0] DDR_D[10] DDR_DQS[1] DDR_RAS DDR_BA[0] DDR_BA[2] DDR_A[10] U T DDR_D[0] DDR_D[1] RSV16 DDR_DQM[0] DVDDR2 DDR_DQM[1] DDR_CAS DDR_WE DDR_CS DDR_ZN T R VSS TRST TMS DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 R P DVDD33 EMU0 TDO TDI DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS P N TCK EMU1 RESETOUT POR VSS DVDD33 VSS CVDD VSS CVDD N CLKOUT0/ M PWM2/ SCL SDA RESET DVDD33 VSS CVDD VSS CVDD VSS M GP[84] HECC_RX/ URTS0/ L UGCPT[8S70] UGRPX[8D50]/ PGWP[M880]/ TUIRNXPD11L// RSV3 DVDD33 VSS CVDD VSS CVDD L GP[56] HECC_TX/ K VSS TGINPP[908L]/ UGTPX[8D60]/ TUOTUXTD11L// RSV2 VSS CVDD VSS CVDD VSS K GP[55] 1 2 3 4 5 6 7 8 9 10 Figure2-2.ZWTPinMap[QuadrantA] 16 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 11 12 13 14 15 16 17 18 19 W DDR_A[6] DDR_A[5] DDR_A[0] DDR_D[16] DDR_D[18] DDR_D[21] DDR_D[27] DVDDR2 DVDDR2 W V DDR_A[7] DDR_A[4] DDR_A[2] DDR_D[17] DDR_D[19] DDR_D[22] DDR_D[24] DDR_D[29] VSS V U DDR_A[9] DDR_A[3] DDR_A[1] DDR_DQS[2] DDR_D[20] DDR_DQS[3] DDR_D[25] DDR_D[28] DDR_D[30] U T DDR_ZP DDR_VDDDLL DDR_VSSDLL DDR_DQM[2] DDR_VREF DDR_DQM[3] DDR_D[23] DDR_D[26] DDR_D[31] T R VSS DVDDR2 RSV5 DVDDR2 VSS DVDDR2 VSS VSS VSS R P DVDDR2 VSS DVDDR2 VSS RSV14 RSV11 RSV12 RSV8 RSV7 P N VSS CVDD VSS VSS RSV13 RSV15 RSV10 RSV9 RSV6 N M CVDD VSS CVDD VSS DVDD33 VSS VSS VSS VSS M L VSS CVDD VSS DVDDR2 RSV4 PLLPWR18 VSS MXVDD VSS L MXI/ K CVDD VSS CVDD VSS DVDD33 VSS DVDD33 MXVSS CLKIN K 11 12 13 14 15 16 17 18 19 Figure2-3.ZWTPinMap[QuadrantB] SubmitDocumentationFeedback DeviceOverview 17

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 11 12 13 14 15 16 17 18 19 J VSS CVDD VSS DVDD33 VSS DVDD33 VSS VSS MXO J H CVDD VSS CVDD VSS GP[29] GP[28] GP[27] DVDD33 VSS H GP[24]/ GP[25]/ GP[26]/ G VSS DVDD33 VSS DVDD33 (BOOTMODE2)(BOOTMODE3) (FASTBOOT) VSS GP[30] G F DVDD33 VSS DVDD33 VSS (BOOGTPM[2O3]D/E1) EGMP_[D2[06]]/ EGMP_[D2[17]]/ (BOOGTPM[2O2]D/E0) EGMP_[C3S3]5/ F EM_WAIT/ EM_D[3]/ EM_D[5]/ EM_D[4]/ EM_CS4/ E RSV18 RSV19 VSS EM_WE (RDY/BSY) GP[17] GP[19] GP[18] GP[32] E CI2(CCD10)/ C_FIELD/ C_WE/ EM_A[18]/ YI4(CCD4)/ EM_D[0]/ EM_D[2]/ EM_D[1]/ D EM_A[21]/ EM_R/W/ EM_OE GP[31] D EM_D[5]/ GP[40] GP[14] GP[16] GP[15] GP[34] GP[35] GP[46] CI4(CCD12)/ CI0(CCD8)/ EM_BA[1]/ EM_BA[0]/ EM_A[16]/ EM_A[20]/ YI5(CCD5)/ YI2(CCD2)/ YI0(CCD0)/ EM_CS3/ EM_CS2/ C GP[5]/ GP[6]/ C EM_D[3]/ EM_D[7]/ GP[41] GP[38] GP[36] GP[13] GP[12] (AEM0) (AEM1) GP[48] GP[44] CI5(CCD13)/ CI1(CCD9)/ EM_A[2]/ EM_A[0]/ LCD_FIELD/ B EEMM__AD[1[25]]// EEMM__AD[1[69]]// YI6G(PC[C4D2]6)/ YI3G(PC[C3D9]3)/ YI1G(PC[C3D7]1)/ (C(LAEE)A/GWP0[8/]/ GP[7]/ EM_A[3]/ VSS B GP[49] GP[45] PLLMS0) (AEM2) GP[11] CI3(CCD11)/ EM_A[1]/ EM_A[4]/ A EEMM__AD[1[47]]// YI7G(PC[C4D3]7)/ GVPD[5/3] GPCP[L5K4/] GHPD[5/2] (A(LAEE)A/GWP1[9/]/ (AGEPA[1W0]2// DVDD33 VSS A GP[47] PLLMS1) PLLMS2) 11 12 13 14 15 16 17 18 19 Figure2-4.ZWTPinMap[QuadrantC] 18 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 1 2 3 4 5 6 7 8 9 10 AHCLKR0/ AXR0[1]/ CLKS0/ J DVDD33 CLKR0/ DX0/ TOUT0L/ VSS DVDD33 VSS CVDD VSS CVDD J GP[101] GP[104] GP[97] ACLKR0/ AFSR0/ H CLKX0/ AGXPR[100[05]]/ AGXPR[100[23]]/ DR0/ DVDD33 VSS CVDD VSS CVDD VSS H GP[99] GP[100] G AGHPC[L1K0X8]0/ GAPFS[1X007/] AGMPU[1T1E00]/ AGXPR[100[32]]/ VSS DVDD33 VSS DVDD33 VSS DVDD33 G F AGCPL[K10X60]/ AMGUPT[1E0I9N]0/ PGWP[M4]1/ VSS DVDD33 VSS DVDD33 VSS DVDD33 VSS F E GP[0] GP[1] GP[2] GP[3] RSV1 DVDD33 VSS DVDD33 VSS RSV17 E HAS/ HRDY/ HCNTL1/ HD14/ HD12/ HD6/ HD1/ EM_A[6]/ EM_A[9]/ EM_A[12]/ D MDIO/ MRXD2/ MTXEN/ MTXD0/ MTXD2/ VLYNQ_TXD1/ VLYNQ_RXD0/ D GP[95] GP[92] GP[89] GP[83] GP[80] GP[75] GP[72] GP[70] GP[64] GP[59] HD0/ HCS/ HINT/ HDS2/ HHWIL/ HD11/ HD9/ HD4/ VLYNQ_ EM_A[7]/ EM_A[11]/ C MDCLK/ MRXD3/ MRXD0/ MRXDV/ MTXD3/ MCOL/ VLYNQ_RXD3/ C SCRUN/ GP[94] GP[90] GP[81] GP[82] GP[78] GP[74] GP[69] GP[67] GP[62] GP[58] CI7(CCD15)/ HDS1/ HCNTL0/ HD13/ HD10/ HD7/ HD3/ B VSS MGRPX[7D91]/ MGRPX[7E6R]/ MGTPX[7D11]/ MGCP[R6S8]/ VLYGNQP[_6T5X]D2/ VLYNGQP[_6R1X]D2/ EGMP_[A9[65]]/ EGMP_[A9[38]]/ EEMM__AD[1[03]]// B GP[51] CI6(CCD14)/ HR/W/ HD15/ HD8/ HD5/ VLYNQ_ HD2/ A DVDD33 DVDD33 MRXCLK/ MTXCLK/ VLYNQ_TXD3/ VLYNQ_TXD0/ CLOCK/ VLYNQ_RXD1/ EMG_PA[9[110]]/ EEMM__AD[1[14]]// A GP[77] GP[73] GP[66] GP[63] GP[57] GP[60] GP[50] 1 2 3 4 5 6 7 8 9 10 Figure2-5.ZWTPinMap[QuadrantD] SubmitDocumentationFeedback DeviceOverview 19

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 1 2 3 4 5 6 7 8 9 10 11 VSS VSS DDR_D[6] DDR_D[8] DDR_D[12] DDR_D[15] DDR_CLK0 DDR_CLK0 DDR_BS[1] DDR_BS[2] DDR_A[10] AB AB AA DVDDR2 DDR_D[3] DDR_D[4] DDR_DQS[0] DDR_D[10] DDR_D[13] DDR_DQS[1] DDR_CKE DDR_BS[0] DDR_A[12] DDR_A[11] AA DDR_D[0] DDR_D[1] DDR_D[5] DDR_DQM[0] DDR_D[11] DDR_D[14] DDR_DQM[1] DDR_RAS DDR_CAS DDR_WE DDR_CS Y Y W VSS DDR_D[2] RSV17 DDR_D[7] DDR_D[9] VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 W V DVDDR2 TRST TMS DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS V 6 7 8 9 10 11 U TCK TDO TDI VSS DVDDR2 U T EMU0 EMU1 RESETOUT DVDD33 VSS T CLKOUT0/ R PGWP[M842]/ POR RESET VSS DVDD33 R HECC_RX/ UCTS0/ TINP1L/ P GP[87] SDA URXD1/ DVDD33 VSS P VSS CVDD CVDD P GP[56] HECC_TX/ UTXD0/ TOUT1L/ N GP[86] SCL UTXD1/ VSS DVDD33 N CVDD VSS VSS N GP[55] URTS0/ URXD0/ M VSS GP[85] PWM0/ RSV3 VSS M CVDD CVDD VSS M GP[88] 1 2 3 4 5 9 10 11 Figure2-6.ZDUPinMap[QuadrantA] 20 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 12 13 14 15 16 17 18 19 20 21 22 AB DDR_A[7] DDR_A[4] DDR_A[1] DDR_A[0] DDR_D[18] DDR_D[21] DDR_D[22] DDR_D[25] DDR_D[28] DVDDR2 DVDDR2 AB AA DDR_A[9] DDR_A[6] DDR_A[3] DDR_DQS[2] DDR_D[16] DDR_D[19] DDR_DQS[3] DDR_D[23] DDR_D[26] DDR_D[30] VSS AA Y DDR_A[8] DDR_A[5] DDR_A[2] DDR_DQM[2] DDR_D[17] DDR_D[20] DDR_DQM[3] DDR_D[24] DDR_D[27] DDR_D[29] DDR_D[31] Y W DDR_ZN DDR_ZP DDR_VDDDLL DDR_VSSDLL RSV5 DVDDR2 DDR_VREF DVDDR2 VSS VSS VSS W V DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS DVDDR2 VSS RSV12 RSV7 RSV6 V 12 13 14 15 16 17 U VSS VSS RSV11 RSV15 RSV8 U T VSS RSV14 RSV13 RSV9 RSV10 T R VSS VSS VSS VSS VSS R P CVDD CVDD VSS P DVDD33 RSV4 DVDD33 VSS DVDD33 P MXI/ N VSS VSS CVDD N VSS DVDD33 PLLPWR18 MXVDD CLKIN N M VSS VSS CVDD M DVDD33 VSS DVDD33 MXVSS MXO M 12 13 14 18 19 20 21 22 Figure2-7.ZDUPinMap[QuadrantB] SubmitDocumentationFeedback DeviceOverview 21

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 12 13 14 18 19 20 21 22 GP[24]/ L VSS CVDD CVDD L VSS GP[27] (BOOTMODE2) DVDD33 VSS L K VSS VSS CVDD K DVDD33 (FAGSPT[B2O6]O/T) (BOGOPTM[2O3D]/E1) GP[29] GP[30] K J CVDD CVDD VSS J VSS DVDD33 (BOGOPTM[2O2D]/E0) GP[28] EGMP_[C3S3]5/ J EM_D[7]/ GP[25]/ EM_CS4/ H DVDD33 VSS GP[21] (BOOTMODE3) GP[32] H EM_D[1]/ EM_D[4]/ G VSS DVDD33 GP[15] GP[18] GP[31] G EM_D[3]/ EM_D[6]/ EM_D[5]/ F DVDD33 VSS GP[17] GP[20] GP[19] F 12 13 14 15 16 17 EM_BA[0]/ E VSS DVDD33 VSS DVDD33 VSS DVDD33 VSS DVDD33 GP[6]/ EGMP_[D1[40]]/ EGMP_[D1[62]]/ E (AEM1) LCD_FIELD/ EM_WAIT/ EM_CS3/ D RSV17 RSV18 RSV19 VSS DVDD33 VSS DVDD33 EM_OE (RDY/BSY) EM_A[3]/ GP[13] D GP[11] CI5(CCD13)/ CI1(CCD9)/ CI0(CCD8)/ EM_A[15]/ C_FIELD/ C_WE/ EM_BA[1]/ EM_A[0]/ C EM_A[11]/ EM_D[2]/ EM_A[19]/ EM_A[20]/ EM_A[21]/ EM_R/W/ YI4(CCD4)/ EM_WE GP[5[/ GP[7]/ EM_CS2/ C GP[90] GP[49] EM_D[6]/ EM_D[7]/ GP[34] GP[35] GP[40] (AEM0) (AEM2) GP[12] GP[45] GP[44] CI4(CCD12)/ CI3(CCD11)/ EM_A[1]/ EM_A[4]/ EM_A[12]/ EM_A[16]/ EM_A[17]/ YI6(CCD6)/ YI5(CCD5)/ YI2(CCD2) YI1(CCD1)/ YI0(CCD0)/ (ALE)/GP[9]/ GP[10]/ B GP[89] EM_D[3]/ EM_D[4]/ GP[42] GP[41] GP[38] GP[37] GP[36] (AEAW1/ (AEAW2/ VSS B GP[48] GP[47] PLLMS1) PLLMS2) CI7(CCD15)/ CI6(CCD14)/ CI2(CCD10)/ EM_A[2]/ EM_A[13]/ EM_A[14]/ EM_A[18]/ YI7(CCD7)/ YI3(CCD3)/ VD/ PCLK/ HD/ (CLE)/GP[8]/ A EM_D[0]/ EM_D[1]/ EM_D[5]/ GP[43] GP[39] GP[53] GP[54] GP[52] (AEAW0/ DVDD33 VSS A GP[51] GP[50] GP[46] PLLMS0) 12 13 14 15 16 17 18 19 20 21 22 Figure2-8.ZDUPinMap[QuadrantC] 22 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 1 2 3 4 5 9 10 11 CLKS0/ TINP0L/ L DVDD33 GP[98] TOUT0L/ RSV2 DVDD33 L CVDD VSS VSS L GP[97] AHCLKR0/ AXR0[1]/ AFSR0/ K CLKR0/ DX0/ DR0/ DVDD33 VSS K CVDD VSS VSS K GP[101] GP[104] GP[100] ACLKR0/ AXR0[2]/ AXR0[3]/ J CLKX0/ FSX0/ FSR0/ VSS DVDD33 J VSS CVDD CVDD J GP[99] GP[103] GP[102] AHCLKX0/ AXR0[0]/ AMUTE0/ H GP[108] GP[105] GP[110] DVDD33 VSS H G AGCPL[K10X60]/ GAPFS[1X007/] AMGUPT[1E0I9N]0/ VSS DVDD33 G F GP[2] GP[3] PGWP[M4]1/ DVDD33 VSS F 6 7 8 9 10 11 E GP[0] GP[1] DVDD33 VSS DVDD33 VSS DVDD33 VSS DVDD33 VSS DVDD33 E HCS/ HINT/ HHWIL/ D MDCLK/ MRXD3/ MRXDV/ RSV1 VSS DVDD33 VSS DVDD33 VSS DVDD33 VSS D GP[81] GP[82] GP[74] HAS/ HDS2/ HRDY/ HCNTL1/ HD12/ HD9/ HD6/ HD4/ HD1/ C MDIO/ MRXD0/ MRXD2/ MTXEN/ MTXD2/ MCOL/ VLYNQ_TXD1/ VLYNQ_RXD3/ VLYNQ_RXD0/ EM_A[7]/ EM_A[9]/ C GP[94] GP[92] GP[83] GP[78] GP[80] GP[75] GP[70] GP[67] GP[64] GP[62] GP[59] HD0/ HCNTL0/ HDS1/ HD13/ HD14/ HD10/ HD7/ HD3/ EM_A[6]/ VLYNQ_ EM_A[10]/ B DVDD33 MRXER/ MRXD1/ MTXD1/ MTXD0/ MCRS/ VLYNQ_TXD2/ VLYNQ_RXD2/ SCRUN/ AD20/ GP[91] B GP[76] GP[79] GP[71] GP[72] GP[68] GP[65] GP[61] GP[95] GP[58] HR/W/ HD15/ HD11/ HD8/ HD5/ VLYNQ_ HD2/ EM_A[5]/ EM_A[8]/ A VSS DVDD33 MRXCLK/ MTXCLK/ MTXD3/ VLYNQ_TXD3/ VLYNQ_TXD0 CLOCK/ VLYNQ_RXD1/ GP[96] GP[93] A GP[77] GP[73] GP[69] GP[66] GP[63] GP[57] GP[60] 1 2 3 4 5 6 7 8 9 10 11 Figure2-9.ZDUPinMap[QuadrantD] SubmitDocumentationFeedback DeviceOverview 23

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 2.6 Terminal Functions The terminal functions tables (Table 2-5 through Table 2-28) identify the external signal names, the associatedpin(ball)numbersalongwith the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations,seetheDeviceConfigurationssectionofthisdatamanual. All device boot and configuration pins are multiplexed configuration pins— meaning they are multiplexed with functional pins. These pins function as device boot and configuration pins only during device reset. The input states of these pins are sampled and latched into the BOOTCFG register when device reset is deasserted (see Note below). After device reset is deasserted, the values on these multiplexed pins no longerhavetoholdtheconfiguration. For proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. Section 3.9.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldownresistorsarerequired. Note: Internal to the chip, the two device reset pins RESET and POR are logically AND’d together for the purpose of latching device boot and configuration pins. The values on all device boot and configuration pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from low-to-high. Table2-5.BOOTTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. BOOT GP[25]/ (BOOTMODE3) G16 H21 Bootmodeconfigurationbits.Thesebootmodefunctionsalong GP[24]/ withtheFASTBOOTfunctiondeterminewhatdevicebootmode (BOOTMODE2) G15 L20 IPD configurationisselected. I/O/Z GP[23]/ F15 K20 DVDD33 TheDM6435devicesupportsseveraltypesofbootmodesalong (BOOTMODE1) withaFASTBOOToption;formoredetailsonthetypes/options, F18 J20 seeSection3.4.1,BootModes. GP[22]/ (BOOTMODE0) FastBoot GP[26]/ IPD G17 K19 I/O/Z 0=NotFastBoot (FASTBOOT) DV DD33 1=FastBoot EM_A[4]/GP[10]/ IPD EMIFAAddressBusWidth(AEAW)andFastBootPLLMultiplier A17 B21 I/O/Z (AEAW2/PLLMS2) DV Select(PLLMS). DD33 Theseconfigurationpinsservetwopurposeswhicharebased EM_A[1]/(ALE)/ IPD A16 B20 I/O/Z onAEM[2:0]settings. GP[9]/(AEAW1/PLLMS1) DV DD33 ForAEM[2:0]=001[8-bitEMIFA(Async)PinoutMode1],the AEAW/PLLMSpinsserveastheAEAWfunctiontoselect EMIFAAddressBusWidth. EM_A[2]/(CLE)/ IPD ForallotherAEMmodes,theAEAW/PLLMSpinsselectthePLL B16 A20 I/O/Z GP[8]/(AEAW0/PLLMS0) DVDD33 multiplierforfastboot. Formoredetails,seeSection3.5.1.2,EMIFAAddressWidth Select(AEAW)andFastBootPLLMultiplerSelect(PLLMS). (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 24 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-5.BOOTTerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. EM_A[0]/GP[7]/ IPD SelectsEMIFAPinoutMode B17 C21 I/O/Z (AEM2) DV DD33 TheDM6435supportsthefollowingEMIFAPinoutModes: EM_BA[0]/GP[6]/ IPD C17 E20 I/O/Z (AEM1) DV AEM[2:0]=000,NoEMIFA DD33 AEM[2:0]=001,8-bitEMIFA(Async)PinoutMode1 AEM[2:0]=101,8-bitEMIFA(NAND)PinoutMode5 EM_BA[1]/GP[5]/ IPD C16 C20 I/O/Z (AEM0) DVDD33 Thissignaldoesn'tactuallyaffecttheEMIFAmodule.Itonly affectshowtheEMIFAispinnedout. ForproperDM6435deviceoperation,ifthispinisbothrouted and3-stated(notdriven)duringdevicereset,itmustbepulled IPD GP[28] H16 J21 I/O/Z downviaanexternalresistor.Formoredetailedinformationon DV DD33 pullup/pulldownresistors,seeSection3.9.1,Pullup/Pulldown Resistors. ForproperDM6435deviceoperation,ifthispinisbothrouted and3-stated(notdriven)duringdevicereset,itmustbepulled IPU GP[27] H17 L19 I/O/Z upviaanexternalresistor.Formoredetailedinformationon DV DD33 pullup/pulldownresistors,seeSection3.9.1,Pullup/Pulldown Resistors. SubmitDocumentationFeedback DeviceOverview 25

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-6.Oscillator/PLLTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2) DESCRIPTION NAME NO. NO. OSCILLATOR,PLL CrystalinputMXIforMXoscillator(systemoscillator,typically27MHz). MXI/ K19 N22 I MXV Iftheinternaloscillatorisbypassed,thisistheexternaloscillatorclock CLKIN DD input.(3) MXO J19 M22 O MXV CrystaloutputforMXoscillator DD MXV L18 N21 S (4) 1.8VpowersupplyforMXoscillator.Ontheboard,thispincanbe DD connectedtothesame1.8VpowersupplyasDV . DDR2 MXV K18 M21 GND (4) GroundforMXoscillator SS PLL L16 N20 S (4) 1.8VpowersupplyforPLLs PWR18 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeachsignal (3) Formoreinformationonexternalboardconnections,seeSection6.6,ExternalClockInputFromMXI/CLKINPin. (4) Formoreinformation,seetheRecommendedOperatingConditionstable Table2-7.ClockGeneratorTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. CLOCKGENERATOR ThispinismultiplexedbetweentheSystemClockgenerator(PLL1),PWM2, andGPIO. CLKOUT0/ IPD M1 R1 I/O/Z FortheSystemClockgenerator(PLL1),itisclockoutputCLKOUT0.Thisis PWM2/GP[84] DV DD33 configurablefor27MHzorother27MHz-divided-down(/1to/32)clock outputs. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 26 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-8.RESETandJTAGTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. RESET IPU RESET M4 R3 I Devicereset DV DD33 – Resetoutputstatuspin.TheRESETOUTpinindicateswhenthe RESETOUT N3 T3 O/Z DV deviceisinreset. DD33 IPU POR N4 R2 I Power-onreset. DV DD33 JTAG IPU JTAGtest-portmodeselectinput. TMS R3 V3 I DV Forproperdeviceoperation,donotopposetheIPUonthispin. DD33 – TDO P3 U2 O/Z JTAGtest-portdataoutput DV DD33 IPU TDI P4 U3 I JTAGtest-portdatainput DV DD33 IPU TCK N1 U1 I JTAGtest-portclockinput DV DD33 JTAGtest-portreset.ForIEEE1149.1JTAGcompatibility,see IPD TRST R2 V2 I theIEEE1149.1JTAGcompatibilitystatementportionofthisdata DV DD33 sheet IPU EMU1 N2 T2 I/O/Z Emulationpin1 DV DD33 IPU EMU0 P2 T1 I/O/Z Emulationpin0 DV DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 27

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-9.EMIFATerminalFunctions(BootConfiguration) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. EMIFA:BOOTCONFIGURATION EM_A[4]/GP[10]/ IPD ThesepinsaremultiplexedbetweentheEMIFAandGPIO.When A17 B21 I/O/Z (AEAW2/PLLMS2) DV RESETorPORisasserted,thesepinsfunctionasEMIFA DD33 configurationpins.AtresetifAEM[2:0]=001(EMIFAin8-bitAsync EM_A[1]/(ALE)/GP[9]/ IPD A16 B20 I/O/Z mode),thentheinputstatesofAEAW[2:0]aresampledtosetthe (AEAW1/PLLMS1) DV DD33 EMIFAAddressBusWidth.Afterreset,thesepinsfunctionasEMIFA orGPIOpinfunctionsbasedonpinmuxselection. EM_A[2]/(CLE)/GP[8]/ IPD FormoredetailsontheAEAW/PLLMSfunctions,seeSection3.5.1.2, B16 A20 I/O/Z (AEAW0/PLLMS0) DVDD33 EMIFAAddressWidthSelect(AEAW)andFastBootPLLMultipler Select(PLLMS). EM_BA[1]/GP[5]/ IPD ThesepinsaremultiplexedbetweentheEMIFAandGPIO.When C16 C20 I/O/Z (AEM0) DV RESETorPORisasserted,thesepinsfunctionasEMIFA DD33 configurationpins.Atreset,theinputstatesofAEM[2:0]aresampled EM_BA[0]/GP[6]/ IPD C17 E20 I/O/Z tosettheEMIFAPinoutMode. (AEM1) DV DD33 Formoredetails,seeSection3.5.1,ConfigurationsatReset.After reset,thesepinsfunctionasEMIFAorGPIOpinfunctionsbasedon EM_A[0]/GP[7]/ IPD pinmuxselection. B17 C21 I/O/Z (AEM2) DVDD33 FormoredetailsontheAEMfunctions,seeSection3.5.1.1,EMIFA PinoutMode(AEM[2:0]). (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 28 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-10.EMIFATerminalFunctions(EMIFAPinoutMode1,AEM[2:0]=001) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. EMIFAFUNCTIONALPINS:8-BitASYNC/NOR(EMIFAPinoutMode1,AEM[2:0]=001) ActualpinfunctionsaredeterminedbythePINMUX0andPINMUX1registerbitsettings(e.g.,AEAW[2:0],AEM[2:0],etc.).Formoredetails, seeSection3.7,MultiplexedPinConfigurations. ThispinismultiplexedbetweenEMIFAandGPIO. ForEMIFA,thispinisChipSelect2outputEM_CS2forusewith asynchronousmemories(i.e.,NORflash). EM_CS2/ IPD ThisisthechipselectforthedefaultbootandROMbootmodes. C19 C22 I/O/Z GP[12] DV DD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFAandGPIO. ForEMIFA,thispinisChipSelect3outputEM_CS3forusewith asynchronousmemories(i.e.,NORflash). EM_CS3/ IPD C18 D22 I/O/Z GP[13] DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFAandGPIO. ForEMIFA,itisChipSelect4outputEM_CS4forusewith asynchronousmemories(i.e.,NORflash). EM_CS4/ IPD E19 H22 I/O/Z GP[32] DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFAandGPIO. ForEMIFA,itisChipSelect5outputEM_CS5forusewith asynchronousmemories(i.e.,NORflash). EM_CS5/ IPD F19 J22 I/O/Z GP[33] DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. C_WE/EM_R/W/ IPD ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. D13 C17 I/O/Z GP[35] DVDD33 ForEMIFA,itisread/writeoutputEM_R/W. EM_WAIT/ IPU ForEMIFA(ASYNC/NOR),thispiniswaitstateextensioninput E15 D20 I/O/Z (RDY/BSY) DV EM_WAIT. DD33 IPU EM_OE D15 D19 I/O/Z ForEMIFA,itisoutputenableoutputEM_OE. DV DD33 IPU EM_WE E14 C19 I/O/Z ForEMIFA,itiswriteenableoutputEM_WE. DV DD33 ThispinismultiplexedbetweenEMIFAandGPIO. EM_BA[0]/GP[6]/ C17 E20 I/O/Z IPD ForEMIFA,thisistheBankAddress0output(EM_BA[0]).When (AEM1) DVDD33 connectedtoan8-bitasynchronousmemory,thispinisthelowest orderbitofthebyteaddress. ThispinismultiplexedbetweenEMIFAandGPIO. EM_BA[1]/GP[5]/ C16 C20 I/O/Z IPD ForEMIFA,thisistheBankAddress1outputEM_BA[1].When (AEM0) DVDD33 connectedtoan8-bitasynchronousmemory,thispinisthe2ndbitof theaddress. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 29

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-10.EMIFATerminalFunctions(EMIFAPinoutMode1,AEM[2:0]=001) (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. C_FIELD/ IPD ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. D12 C16 I/O/Z EM_A[21]/GP[34] DVDD33 ForEMIFA,itisaddressbit21outputEM_A[21]. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI0(CCD8)/ IPD EM_A[20]/GP[44] C12 C15 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit20output DD33 EM_A[20]ifAEAW[2:0]=100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI1(CCD9)/ IPD EM_A[19]/GP[45] B12 C14 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit19output DD33 EM_A[19]ifAEAW[2:0]=100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI2(CCD10)/ IPD EM_A[18]/GP[46] D11 A14 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit18output DD33 EM_A[18]ifAEAW[2:0]=011/100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI3(CCD11)/ IPD EM_A[17]/GP[47] A11 B14 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit17output DD33 EM_A[17]ifAEAW[2:0]=011/100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI4(CCD12)/ IPD EM_A[16]/GP[48] C11 B13 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit16output DD33 EM_A[16]ifAEAW[2:0]=010/011/100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI5(CCD13)/ IPD EM_A[15]/GP[49] B11 C13 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit15output DD33 EM_A[15]ifAEAW[2:0]=010/011/100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI6(CCD14)/ IPD EM_A[14]/GP[50] A10 A13 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit14output DD33 EM_A[14]ifAEAW[2:0]=001/010/011/100b. ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. CI7(CCD15)/ IPD EM_A[13]/GP[51] B10 A12 I/O/Z DV ForEMIFA(AEM[2:0]=001),thispinisaddressbit13output DD33 EM_A[13]ifAEAW[2:0]=001/010/011/100b. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[12]/GP[89] D10 B12 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit12outputEM_A[12]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[11]/GP[90] C10 C12 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit11outputEM_A[11]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[10]/GP[91] A9 B11 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit10outputEM_A[10]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[9]/GP[92] D9 C11 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit9outputEM_A[9]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[8]/GP[93] B9 A11 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit8outputEM_A[8]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[7]/GP[94] C9 C10 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit7outputEM_A[7]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[6]/GP[95] D8 B10 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit6outputEM_A[6]. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[5]/GP[96] B8 A10 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit5outputEM_A[5]. EM_A[4]/GP[10]/ IPD ThispinismultiplexedbetweenEMIFAandGPIO. A17 B21 I/O/Z (AEAW2/PLLMS2) DVDD33 ForEMIFA,thispinisaddressbit4outputEM_A[4]. 30 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-10.EMIFATerminalFunctions(EMIFAPinoutMode1,AEM[2:0]=001) (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. IPD ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[3]/GP[11] B18 D21 I/O/Z DVDD33 ForEMIFA,thispinisaddressbit3outputEM_A[3]. EM_A[2]/(CLE)/GP[8]/ IPD ThispinismultiplexedbetweenEMIFAandGPIO. B16 A20 I/O/Z (AEAW0/PLLMS0) DVDD33 ForEMIFA,thispinisaddressbit2outputEM_A[2]. EM_A[1]/(ALE)/GP[9]/ IPD ThispinismultiplexedbetweenEMIFAandGPIO. A16 B20 I/O/Z (AEAW1/PLLMS1) DVDD33 ForEMIFA,thispinisaddressoutputEM_A[1]. ThispinismultiplexedbetweenEMIFAandGPIO. EM_A[0]/GP[7]/ IPD ForEMIFA,thispinisAddressoutputEM_A[0],whichistheleast (AEM2) B17 C21 I/O/Z DV significantbitona32-bitwordaddress. DD33 Foran8-bitasynchronousmemory,thispinisthe3rdbitofthe address. IPD EM_D0/GP[14] D16 E21 I/O/Z DV DD33 IPD EM_D1/GP[15] D18 G20 I/O/Z DV DD33 IPD EM_D2/GP[16] D17 E22 I/O/Z DV DD33 IPD EM_D3/GP[17] E16 F20 I/O/Z ThesepinsaremultiplexedbetweenEMIFAandGPIO. DV DD33 ForEMIFA(AEM[2:0]=001),thesepinsarethe8-bitbi-directional IPD EM_D4/GP[18] E18 G21 I/O/Z databus(EM_D[7:0]). DV DD33 IPD EM_D5/GP[19] E17 F22 I/O/Z DV DD33 IPD EM_D6/GP[20] F16 F21 I/O/Z DV DD33 IPD EM_D7/GP[21] F17 H20 I/O/Z DV DD33 EMIFAFUNCTIONALPINS:8-BitNAND(EMIFAPinoutMode1,AEM[2:0]=001) ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. EM_A[1]/(ALE)/GP[9]/ IPD (AEAW1/PLLMS1) A16 B20 I/O/Z DV WhenusedforEMIFA(NAND),thispinistheAddressLatchEnable DD33 output(ALE). ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. EM_A[2]/(CLE)/GP[8]/ IPD (AEAW0/PLLMS0) B16 A20 I/O/Z DV WhenusedforEMIFA(NAND),thispinistheCommandLatch DD33 Enableoutput(CLE). EM_WAIT/ IPU E15 D20 I/O/Z WhenusedforEMIFA(NAND),itisready/busyinput(RDY/BSY). (RDY/BSY) DV DD33 IPU EM_OE D15 D19 I/O/Z WhenusedforEMIFA(NAND),thispinisreadenableoutput(RE). DV DD33 IPU EM_WE E14 C19 I/O/Z WhenusedforEMIFA(NAND),thispiniswriteenableoutput(WE). DV DD33 ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA(NAND),thispinisChipSelect2outputEM_CS2foruse withNANDflash. EM_CS2/ IPD ThisisthechipselectforthedefaultbootandROMbootmodes. C19 C22 I/O/Z GP[12] DV DD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. SubmitDocumentationFeedback DeviceOverview 31

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-10.EMIFATerminalFunctions(EMIFAPinoutMode1,AEM[2:0]=001) (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA(NAND),thispinisChipSelect3outputEM_CS3foruse withNANDflash. EM_CS3/ IPD C18 D22 I/O/Z GP[13] DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA(NAND),itisChipSelect4outputEM_CS4forusewith NANDflash. EM_CS4/ IPD E19 H22 I/O/Z GP[32] DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA(NAND),itisChipSelect5outputEM_CS5forusewith NANDflash. EM_CS5/ IPD F19 J22 I/O/Z GP[33] DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. IPD EM_D0/GP[14] D16 E21 I/O/Z DV DD33 IPD EM_D1/GP[15] D18 G20 I/O/Z DV DD33 IPD EM_D2/GP[16] D17 E22 I/O/Z DV DD33 IPD EM_D3/GP[17] E16 F20 I/O/Z ThesepinsaremultiplexedbetweenEMIFA(NAND)andGPIO. DV DD33 ForEMIFA(NAND)AEM[2:0]=001,thesearethe8-bitbi-directional IPD EM_D4/GP[18] E18 G21 I/O/Z databus(EM_D[7:0]). DV DD33 IPD EM_D5/GP[19] E17 F22 I/O/Z DV DD33 IPD EM_D6/GP[20] F16 F21 I/O/Z DV DD33 IPD EM_D7/GP[21] F17 H20 I/O/Z DV DD33 32 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-11.EMIFATerminalFunctions(EMIFAPinoutMode5,AEM[2:0]=101) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. EMIFAFUNCTIONALPINS:8-BitNAND(EMIFAPinoutMode5,AEM[2:0]=101) ActualpinfunctionsaredeterminedbythePINMUX0andPINMUX1registerbitsettings(e.g.,AEAW[2:0],AEM[2:0],etc.).Formoredetails, seeSection3.7,MultiplexedPinConfigurations. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. EM_A[1]/(ALE)/GP[9]/ IPD (AEAW1/PLLMS1) A16 B20 I/O/Z DV WhenusedforEMIFA(NAND),thispinistheAddressLatchEnable DD33 output(ALE). ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. EM_A[2]/(CLE)/GP[8]/ IPD (AEAW0/PLLMS0) B16 A20 I/O/Z DV WhenusedforEMIFA(NAND),thispinistheCommandLatch DD33 Enableoutput(CLE). EM_WAIT/ IPU E15 D20 I/O/Z WhenusedforEMIFA(NAND),itisready/busyinput(RDY/BSY). (RDY/BSY) DV DD33 IPU EM_OE D15 D19 I/O/Z WhenusedforEMIFA(NAND),thispinisreadenableoutput(RE). DV DD33 IPU EM_WE E14 C19 I/O/Z WhenusedforEMIFA(NAND),thispiniswriteenableoutput(WE). DV DD33 ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA,thispinisChipSelect2outputEM_CS2forusewith NANDflash. IPD ThisisthechipselectforthedefaultbootandROMbootmodes. EM_CS2/GP[12] C19 C22 I/O/Z DV DD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA,thispinisChipSelect3outputEM_CS3forusewith NANDflash. IPD EM_CS3/GP[13] C18 D22 I/O/Z DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA,itisChipSelect4outputEM_CS4forusewithNAND flash. IPD EM_CS4/GP[32] E19 H22 I/O/Z DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. ThispinismultiplexedbetweenEMIFA(NAND)andGPIO. ForEMIFA,itisChipSelect5outputEM_CS5forusewithNAND flash. IPD EM_CS5/GP[33] F19 J22 I/O/Z DVDD33 Note:Thispinfeaturesaninternalpulldown(IPD).Ifthispinis connectedandusedasanEMIFAchipselectsignal,forproper deviceoperation,anexternalpullupresistormustbeusedtoensure theEM_CSxfunctiondefaultstoaninactive(high)state. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 33

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-11.EMIFATerminalFunctions(EMIFAPinoutMode5,AEM[2:0]=101) (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. IPD EM_D0/GP[14] D16 E21 I/O/Z DV DD33 IPD EM_D1/GP[15] D18 G20 I/O/Z DV DD33 IPD EM_D2/GP[16] D17 E22 I/O/Z DV DD33 IPD EM_D3/GP[17] E16 F20 I/O/Z ThesepinsaremultiplexedbetweenEMIFA(NAND)andGPIO. DV DD33 ForEMIFAAEM[2:0]=101(NAND),thesearethe8-bitbi-directional IPD EM_D4/GP[18] E18 G21 I/O/Z databus(EM_D[7:0]). DV DD33 IPD EM_D5/GP[19] E17 F22 I/O/Z DV DD33 IPD EM_D6/GP[20] F16 F21 I/O/Z DV DD33 IPD EM_D7/GP[21] F17 H20 I/O/Z DV DD33 34 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-12.DDR2MemoryControllerTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. DDR2MemoryController DDR_CLK W7 AB7 I/O/Z DV DDR2ClockOutput DDR2 DDR_CLK W8 AB8 I/O/Z DV DDR2DifferentialClockOutput DDR2 DDR_CKE V8 AA8 I/O/Z DV DDR2ClockEnableOutput DDR2 DDR_CS T9 Y11 I/O/Z DV DDR2ActiveLowChipSelectOutput DDR2 DDR_WE T8 Y10 I/O/Z DV DDR2ActiveLowWriteEnableOutput DDR2 DDR_DQM[3] T16 Y18 I/O/Z DVDDR2 DDR2DataMaskOutputs DDR_DQM[2] T14 Y15 I/O/Z DV DQM3:ForupperbytedatabusDDR_D[31:24] DDR2 DQM2:ForDDR_D[23:16] DDR_DQM[1] T6 Y7 I/O/Z DVDDR2 DQM1:ForDDR_D[15:8] DDR_DQM[0] T4 Y4 I/O/Z DV DQM0:ForlowerbyteDDR_D[7:0] DDR2 DDR_RAS U7 Y8 I/O/Z DV DDR2RowAccessSignalOutput DDR2 DDR_CAS T7 Y9 I/O/Z DV DDR2ColumnAccessSignalOutput DDR2 DDR_DQS[0] U4 AA4 I/O/Z DV DataStrobeInput/Outputsforeachbyteofthe32-bitdatabus.They DDR2 areoutputstotheDDR2memorywhenwritingandinputswhen DDR_DQS[1] U6 AA7 I/O/Z DV DDR2 reading.Theyareusedtosynchronizethedatatransfers. DDR_DQS[2] U14 AA15 I/O/Z DVDDR2 DQS3:ForupperbyteDDR_D[31:24] DQS2:ForDDR_D[23:16] DDR_DQS[3] U16 AA18 I/O/Z DV DQS1:ForDDR_D[15:8] DDR2 DQS0:ForbottombyteDDR_D[7:0] DDR_BA[0] U8 AA9 BankSelectOutputs(BA[2:0]).Twoarerequiredtosupport1GbDDR2 DDR_BA[1] V9 AB9 I/O/Z DV DDR2 memories. DDR_BA[2] U9 AB10 DDR_A[12] W9 AA10 DDR_A[11] W10 AA11 DDR_A[10] U10 AB11 DDR_A[9] U11 AA12 DDR_A[8] V10 Y12 DDR_A[7] V11 AB12 DDR_A[6] W11 AA13 I/O/Z DV DDR2AddressBusOutput DDR2 DDR_A[5] W12 Y13 DDR_A[4] V12 AB13 DDR_A[3] U12 AA14 DDR_A[2] V13 Y14 DDR_A[1] U13 AB14 DDR_A[0] W13 AB15 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) Foremoreinformation,seetheRecommendedOperatingConditionstable SubmitDocumentationFeedback DeviceOverview 35

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-12.DDR2MemoryControllerTerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. DDR_D[31] T19 Y22 DDR_D[30] U19 AA21 DDR_D[29] V18 Y21 DDR_D[28] U18 AB20 DDR_D[27] W17 Y20 DDR_D[26] T18 AA20 DDR_D[25] U17 AB19 DDR_D[24] V17 Y19 DDR_D[23] T17 AA19 DDR_D[22] V16 AB18 DDR_D[21] W16 AB17 DDR_D[20] U15 Y17 DDR_D[19] V15 AA17 DDR_D[18] W15 AB16 DDR_D[17] V14 Y16 DDR_D[16] W14 AA16 DDR2bi-directionaldatabuscanbeconfiguredas32-bitswideor I/O/Z DV DDR_D[15] V7 AB6 DDR2 16-bitswide. DDR_D[14] W6 Y6 DDR_D[13] V6 AA6 DDR_D[12] W5 AB5 DDR_D[11] V5 Y5 DDR_D[10] U5 AA5 DDR_D[9] W4 W5 DDR_D[8] V4 AB4 DDR_D[7] W3 W4 DDR_D[6] V3 AB3 DDR_D[5] U3 Y3 DDR_D[4] V2 AA3 DDR_D[3] U2 AA2 DDR_D[2] U1 W2 DDR_D[1] T2 Y2 DDR_D[0] T1 Y1 DDR_VREF T15 W18 I (3) ReferencevoltageinputfortheSSTL_18I/Obuffers DDR_VSSDLL T13 W15 GND (3) GroundfortheDDR2DLL DDR_VDDDLL T12 W14 S (3) Power(1.8Volts)fortheDDR2DigitalLockedLoop DDR_ZN T10 W12 (3) I2m0p0e-WdarnecseistcoornttoroDlVforDD.R2outputs.Thismustbeconnectedviaa DDR2 DDR_ZP T11 W13 (3) I2m0p0e-WdarnecseistcoornttoroVlfor.DDR2outputs.Thismustbeconnectedviaa SS 36 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-13.EMACandMDIOTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. EMAC ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HCNTL1/MTXEN/ IPD D3 C4 I/O/Z GPIO. GP[75] DV DD33 InEthernetMACmode,itisTransmitEnableoutputMTXEN. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD15/MTXCLK/ IPD A4 A4 I/O/Z GPIO. GP[73] DV DD33 InEthernetMACmode,itisTransmitClockinputMTXCLK. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD9/MCOL/ IPD C6 C6 I/O/Z GPIO. GP[67] DV DD33 InEthernetMACmode,itisCollisionDetectinputMCOL. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD11/MTXD3/ IPD C5 A5 I/O/Z GPIO. GP[69] DV DD33 InEthernetMACmode,itisTransmitData3outputMTXD3. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD12/MTXD2/ IPD D5 C5 I/O/Z GPIO. GP[70] DV DD33 InEthernetMACmode,itisTransmitData2outputMTXD2. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD13/MTXD1/ IPD B4 B4 I/O/Z GPIO. GP[71] DV DD33 InEthernetMACmode,itisTransmitData1outputMTXD1. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD14/MTXD0/ IPD D4 B5 I/O/Z GPIO. GP[72] DV DD33 InEthernetMACmode,itisTransmitData0outputMTXD0. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HR/W/MRXCLK/ IPD A3 A3 I/O/Z GPIO. GP[77] DV DD33 InEthernetMACmode,itisReceiveClockinputMRXCLK. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HHWIL/MRXDV/ IPD C4 D3 I/O/Z GPIO. GP[74] DV DD33 InEthernetMACmode,itisReceiveDataValidinputMRXDV. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HCNTL0/MRXER/ IPD B3 B2 I/O/Z GPIO. GP[76] DV DD33 InEthernetMACmode,itisReceiveErrorinputMRXER. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HD10/MCRS/ IPD B5 B6 I/O/Z GPIO. GP[68] DV DD33 InEthernetMACmode,itisCarrierSenseinputMCRS. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HINT/MRXD3/ IPU C2 D2 I/O/Z GPIO. GP[82] DV DD33 InEthernetMACmode,itisReceiveData3inputMRXD3. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HRDY/MRXD2/ IPU D2 C3 I/O/Z GPIO. GP[80] DV DD33 InEthernetMACmode,itisReceiveData2inputMRXD2. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HDS1/MRXD1/ IPU B2 B3 I/O/Z GPIO. GP[79] DV DD33 InEthernetMACmode,itisReceivedata1inputMRXD1. ThispinismultiplexedbetweenHPI,EthernetMAC(EMAC),and HDS2/MRXD0/ IPU C3 C2 I/O/Z GPIO. GP[78] DV DD33 InEthernetMACmode,itisReceiveData0inputMRXD0. MDIO ThispinismultiplexedbetweenHPI,MDIO,andGPIO. HCS/MDCLK/ IPU C1 D1 I/O/Z InEthernetMACmode,itisManagementDataClockoutput GP[81] DV DD33 MDCLK. HAS/MDIO/ IPU ThispinismultiplexedbetweenHPI,MDIO,andGPIO. D1 C1 I/O/Z GP[83] DV InEthernetMACmode,itisManagementDataIOMDIO(I/O/Z). DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 37

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-14.VLYNQTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. VLYNQ VLYNQ_CLOCK/ IPU ThispinismultiplexedbetweenVLYNQ,andGPIO. A7 A8 I/O/Z GP[57] DV ForVLYNQ,itistheclockVLYNQ_CLOCK(I/O/Z). DD33 ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. HD0/VLYNQ_SCRUN/ IPU C8 B9 I/O/Z ForVLYNQ,itistheSerialClockrunrequestVLYNQ_SCRUN GP[58] DV DD33 (I/O/Z). HD8/VLYNQ_TXD3/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. A5 A6 I/O/Z GP[66] DV ForVLYNQ,itistransmitbusbit3outputVLYNQ_TXD3. DD33 HD7/VLYNQ_TXD2/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. B6 B7 I/O/Z GP[65] DV ForVLYNQ,itistransmitbusbit2outputVLYNQ_TXD2. DD33 HD6/VLYNQ_TXD1/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. D6 C7 I/O/Z GP[64] DV ForVLYNQ,itistransmitbusbit1outputVLYNQ_TXD1. DD33 HD5/VLYNQ_TXD0/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. A6 A7 I/O/Z GP[63] DV ForVLYNQ,itistransmitbusbit0output(VLYNQ_TXD0). DD33 HD4/VLYNQ_RXD3/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. C7 C8 I/O/Z GP[62] DV ForVLYNQ,itisreceivebusbit3inputVLYNQ_RXD3. DD33 HD3/VLYNQ_RXD2/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. B7 B8 I/O/Z GP[61] DV ForVLYNQ,itisreceivebusbit2inputVLYNQ_RXD2. DD33 HD2/VLYNQ_RXD1/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. A8 A9 I/O/Z GP[60] DV ForVLYNQ,itisreceivebusbit1inputVLYNQ_RXD1. DD33 HD1/VLYNQ_RXD0/ IPD ThispinismultiplexedbetweenHPI,VLYNQ,andGPIO. D7 C9 I/O/Z GP[59] DV ForVLYNQ,itisreceivebusbit0inputVLYNQ_RXD0. DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 38 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-15.Host-PortInterfaceTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. Host-PortInterface(HPI) HD0/VLYNQ_SCRUN/ IPU C8 B9 GP[58] DV DD33 HD1/VLYNQ_RXD0/ D7 C9 GP[59] HD2/VLYNQ_RXD1/ A8 A9 GP[60] HD3/VLYNQ_RXD2/ B7 B8 GP[61] HD4/VLYNQ_RXD3/ C7 C8 GP[62] HD5/VLYNQ_TXD0/ A6 A7 GP[63] HD6/VLYNQ_TXD1/ D6 C7 GP[64] HD7/VLYNQ_TXD2/ ThispinismultiplexedbetweenHPI,VLYNQorEMAC,and GP[65] B6 B7 GPIO. I/O/Z InHPImode,thesepinsarehost-portdatapinsHD[15:0] HD8/VLYNQ_TXD3/ A5 A6 IPD (I/O/Z)andaremultiplexedinternallywiththeHPIaddress GP[66] DVDD33 lines. HD9/MCOL/ C6 C6 GP[67] HD10/MCRS/ B5 B6 GP[68] HD11/MTXD3/ C5 A5 GP[69] HD12/MTXD2/ D5 C5 GP[70] HD13/MTXD1/ B4 B4 GP[71] HD14/MTXD0/ D4 B5 GP[72] HD15/MTXCLK/ A4 A4 GP[73] ThispinismultiplexedbetweenHPI,EMAC,andGPIO. HHWIL/MRXDV/ IPD C4 D3 I/O/Z InHPImode,thispinishalf-wordidentificationinputHHWIL GP[74] DV DD33 (I). ThispinismultiplexedbetweenHPI,EMAC,andGPIO. InHPImode,thispiniscontrolinput1HCNTL1(I).Thestate HCNTL1/MTXEN/ IPD D3 C4 I/O/Z ofHCNTL1andHCNTL0determinesifaddress,data,or GP[75] DV DD33 controlinformationisbeingtransmittedbetweenanexternal hostandtheDM6435. ThispinismultiplexedbetweenHPI,EMAC,andGPIO. InHPImode,thispiniscontrolinput0HCNTL0(I).Thestate HCNTL0/MRXER/ IPD B3 B2 I/O/Z ofHCNTL1andHCNTL0determinesifaddress,data,or GP[76] DV DD33 controlinformationisbeingtransmittedbetweenanexternal hostandtheDM6435. HR/W/MRXCLK/ IPD ThispinismultiplexedbetweenHPI,EMAC,andGPIO. A3 A3 I/O/Z GP[77] DV InHPImode,thispinishostreadorwriteselectHR/W(I). DD33 HDS2/MRXD0/ IPU ThispinismultiplexedbetweenHPI,EMAC,andGPIO. C3 C2 I/O/Z GP[78] DV InHPImode,thispinishostdatastrobeinput2HDS2(I). DD33 HDS1/MRXD1/ IPU ThispinismultiplexedbetweenHPI,EMAC,andGPIO. B2 B3 I/O/Z GP[79] DV InHPImode,thispinishostdatastrobeinput1HDS1(I). DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 39

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-15.Host-PortInterfaceTerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. ThispinismultiplexedbetweenHPI,EMAC,andGPIO. HRDY/MRXD2/ IPU D2 C3 I/O/Z InHPImode,thispinishostreadyoutputfromDSPtohost GP[80] DV DD33 (O/Z). ThispinismultiplexedbetweenHPI,MDIO,andGPIO. HCS/MDCLK/ IPU C1 D1 I/O/Z InHPImode,thispinisHPIactivelowchipselectinputHCS GP[81] DV DD33 (I). HINT/RXD3/ IPU ThispinismultiplexedbetweenHPI,EMAC,andGPIO. C2 D2 I/O/Z GP[82] DV InHPImode,thispinishostinterruptoutputHINT(O/Z). DD33 ThispinismultiplexedbetweenHPI,MDIO,andGPIO. HAS/MDIO/ IPU InHPImode,thispinishostaddressstrobeHAS(I). D1 C1 I/O/Z GP[83] DV ForproperHPIoperation,ifthispinisroutedout,itmustbe DD33 pulledupviaanexternalresistor. 40 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-16.VPFETerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. VIDEO/IMAGEIN(VPFE) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. IPD InVPFEmode,thispinisthepixelclockinput(PCLK)usedtoload PCLK/GP[54] A14 A18 I/O/Z DV imagedataintotheCCDController(CCDC)onpinsCI[7:0]and DD33 YI[7:0]. ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. IPD InVPFEmode,thispinistheverticalsynchronizationsignal(VD)that VD/GP[53] A13 A17 I/O/Z DV canbeeitheraninput(slavemode)oranoutput(mastermode), DD33 whichsignalsthestartofanewframetotheCCDC. ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. IPD InVPFEmode,thispinisthehorizontalsynchronizationsignal(HD) HD/GP[52] A15 A19 I/O/Z DV thatcanbeeitheraninput(slavemode)oranoutput(mastermode), DD33 whichsignalsthestartofanewlinetotheCCDC. ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. WhenusedbytheCCDCasinputCI7,itsupportsseveralmodes: CI7(CCD15)/ B10 A12 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD15. EM_A[13]/GP[51] DVDD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB7,andCR7 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY7,CB7,and CR7oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. WhenusedbytheCCDCasinputCI6,itsupportsseveralmodes: CI6(CCD14)/ A10 A13 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD14. EM_A[14]/GP[50] DVDD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB6,andCR6 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY6,CB6,and CR6oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. WhenusedbytheCCDCasinputCI5,itsupportsseveralmodes: CI5(CCD13)/ B11 C13 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD13. EM_A[15]/GP[49] DVDD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB5andCR5 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY5,CB5,and CR5oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. WhenusedbytheCCDCasinputCI4,itsupportsseveralmodes: CI4(CCD12)/ IPD EM_A[16]/GP[48] C11 B13 I/O/Z DV In16-bitCCDRawmode,itisinputCCD12. DD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB4andCR4 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY4,CB4,and CR4oftheupper8-bitchannel.(4) (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal (4) Inadditiontothesedefaultfunctions,inYCbCrmode,theVPFECCDConfigurationregisterCCDCFG.YCINSWPbitfieldallowsthe usertoswapthefunctionoftheYI[7:0]andCI[7:0]pins. SubmitDocumentationFeedback DeviceOverview 41

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-16.VPFETerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. WhenusedbytheCCDCasinputCI3,itsupportsseveralmodes: CI3(CCD11)/ IPD EM_A[17]/GP[47] A11 B14 I/O/Z DV In16-bitCCDRawmode,itisinputCCD11. DD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB3andCR3 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY3,CB3,and CR3oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. ThispinisCCDCinputCI2anditsupportsseveralmodes: CI2(CCD10)/ IPD EM_A[18]/GP[46] D11 A14 I/O/Z DV In16-bitCCDRawmode,itisinputCCD10. DD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB2andCR2 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY2,CB2,and CR2oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. ThispinisCCDCinputCI1anditsupportsseveralmodes: CI1(CCD9)/ IPD EM_A[19]/GP[45] B12 C14 I/O/Z DV In16-bitCCDRawmode,itisinputCCD9. DD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB1andCR1 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY1,CB1,and CR1oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC),EMIFA,and GPIO. ThispinisCCDCinputCI0anditsupportsseveralmodes: CI0(CCD8)/ IPD EM_A[20]/GP[44] C12 C15 I/O/Z DV In16-bitCCDRawmode,itisinputCCD8. DD33 In16-bitYCbCrmode,itistimemultiplexedbetweenCB0andCR0 inputs.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY0,CB0,and CR0oftheupper8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. hispinisCCDCinputYI7anditsupportsseveralmodes: YI7(CCD7)/ IPD GP[43] A12 A15 I/O/Z DV In16-bitCCDRawmode,itisinputCCD7. DD33 In16-bitYCbCrmode,itisinputY7.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY7,CB7,and CR7ofthelower8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI6anditsupportsseveralmodes: YI6(CCD6)/ IPD GP[42] B13 B15 I/O/Z DV In16-bitCCDRawmode,itisinputCCD6. DD33 In16-bitYCbCrmode,itisinputY6.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY6,CB6,and CR6ofthelower8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI5anditsupportsseveralmodes: YI5(CCD5)/ IPD GP[41] C13 B16 I/O/Z DV In16-bitCCDRawmode,itisinputCCD5. DD33 In16-bitYCbCrmode,itisinputY5.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY5,CB5,and CR5ofthelower8-bitchannel.(4) 42 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-16.VPFETerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI4anditsupportsseveralmodes: YI4(CCD4)/ D14 C18 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD4. GP[40] DVDD33 In16-bitYCbCrmode,itisinputY4.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY4,CB4,and CR4ofthelower8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI3anditsupportsseveralmodes: YI3(CCD3)/ B14 A16 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD3. GP[39] DVDD33 In16-bitYCbCrmode,itisinputY3.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY3,CB3,and CR3ofthelower8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI2anditsupportsseveralmodes: YI2(CCD2)/ C14 B17 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD2. GP[38] DVDD33 In16-bitYCbCrmode,itisinputY2.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY2,CB2,and CR2ofthelower8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI1anditsupportsseveralmodes: YI1(CCD1)/ B15 B18 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD1. GP[37] DVDD33 In16-bitYCbCrmode,itisinputY1.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY1,CB1,and CR1ofthelower8-bitchannel.(4) ThispinismultiplexedbetweentheVPFE(CCDC)andGPIO. ThispinisCCDCinputYI0anditsupportsseveralmodes: YI0(CCD0)/ C15 B19 I/O/Z IPD In16-bitCCDRawmode,itisinputCCD0. GP[36] DVDD3 In16-bitYCbCrmode,itisinputY0.(4) In8-bitYCbCrmode,itistimemultiplexedbetweenY0,CB0,and CR0ofthelower8-bitchannel.(4) C_WE/EM_R/W/ IPD ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. D13 C17 I/O/Z GP[35] DV InVPFEmode,itistheCCDControllerwriteenableinputC_WE. DD33 ThispinismultiplexedbetweenVPFE(CCDC),EMIFA,andGPIO. C_FIELD/EM_A[21]/ IPD D12 C16 I/O/Z InVPFEmode,itisCCDCfieldidentificationbidirectionalsignal GP[34] DV DD33 C_FIELD. SubmitDocumentationFeedback DeviceOverview 43

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-17.I2CTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. I2C ForI2C,thispinisI2Cclock.InI2Cmastermode,thispinisan output.InI2Cslavemode,thispinisaninput. SCL M2 N2 I/O/Z DV DD33 WhentheI2Cmoduleisused,forproperdeviceoperation,thispin mustbepulledupviaanexternalresistor. ForI2C,thispinistheI2Cbi-directionaldatasignal. SDA M3 P2 I/O/Z DV WhentheI2Cmoduleisused,forproperdeviceoperation,thispin DD33 mustbepulledupviaanexternalresistor. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 44 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-18.MultichannelBufferedSerialPort0(McBSP0)TerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. MultichannelBufferedSerialPort0(McBSP0) Formoredetailsonpinmultiplexing,seeSection3.7,MultiplexedPinConfigurations. CLKS0/TOUT0L/ IPD ThispinismultiplexedbetweenMcBSP0,Timer0,andGPIO. J4 L3 I/O/Z GP[97] DV ForMcBSP0,itisMcBSP0externalclocksource(I). DD33 ACLKR0/CLKX0/ IPD ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. H1 J1 I/O/Z GP[99] DV ForMcBSP0,itisMcBSP0transmitclockCLKX0(I/O/Z). DD33 AHCLKR0/CLKR0/ IPD ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. J2 K1 I/O/Z GP[101] DV ForMcBSP0,itisMcBSP0receiveclockCLKR0(I/O/Z). DD33 ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AXR0[2]/FSX0/ IPD H3 J2 I/O/Z ForMcBSP0,itisMcBSP0transmitframesynchronizationFSX0 GP[103] DV DD33 (I/O/Z). ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AXR0[3]/FSR0/ IPD G4 J3 I/O/Z ForMcBSP0,itisMcBSP0receiveframesynchronizationFSR0 GP[102] DV DD33 (I/O/Z). AXR0[1]/DX0/ IPD ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. J3 K2 I/O/Z GP[104] DV ForMcBSP0,itisMcBSP0datatransmitoutputDX0(O/Z). DD33 AFSR0/DR0/ IPD ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. H4 K3 I/O/Z GP[100] DV ForMcBSP0,itisMcBSP0datareceiveinputDR0(I). DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 45

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-19.MultichannelAudioSerialPort(McASP0)TerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. McASP0 AMUTEIN0/ IPD ThispinismultiplexedbetweenMcASP0andGPIO. F2 G3 I/O/Z GP[109] DV ForMcASP0,itisMcASP0muteinputAMUTEIN0(I). DD33 IPD ThispinismultiplexedbetweenMcASP0andGPIO. AMUTE0/GP[110] G3 H3 I/O/Z DV ForMcASP0,itisMcASP0muteoutputAMUTE0(O/Z). DD33 ACLKR0/CLKX0/ IPD ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. H1 J1 I/O/Z GP[99] DV ForMcASP0,itisMcASP0receivebitclockACLKR0(I/O/Z). DD33 ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AHCLKR0/CLKR0/ IPD J2 K1 I/O/Z ForMcASP0,itisMcASP0receivehigh-frequencymasterclock GP[101] DV DD33 AHCLKR0(I/O/Z). IPD ThispinismultiplexedbetweenMcASP0andGPIO. ACLKX0/GP[106] F1 G1 I/O/Z DV ForMcASP0,itisMcASP0transmitbitclockACLKX0(I/O/Z). DD33 ThispinismultiplexedbetweenMcASP0andGPIO. IPD AHCLKX0/GP[108] G1 H1 I/O/Z ForMcASP0,itisMcASP0transmithigh-frequencymasterclock DV DD33 AHCLKX0(I/O/Z). ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AFSR0/DR0/ IPD H4 K3 I/O/Z ForMcASP0,itisMcASP0receiveframesynchronizationAFSR0 GP[100] DV DD33 (I/O/Z). ThispinismultiplexedbetweenMcASP0andGPIO. IPD AFSX0/GP[107] G2 G2 I/O/Z ForMcASP0,itisMcASP0transmitframesynchronizationAFSX0 DV DD33 (I/O/Z). ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AXR0[3]/FSR0/ IPD G4 J3 I/O/Z ForMcASP0,itisMcASP0transmit/receive(TX/RX)datapin3 GP[102] DV DD33 AXR0[3](I/O/Z). ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AXR0[2]/FSX0/ IPD H3 J2 I/O/Z ForMcASP0,itisMcASP0transmit/receive(TX/RX)datapin2 GP[103] DV DD33 AXR0[2](I/O/Z). ThispinismultiplexedbetweenMcASP0,McBSP0,andGPIO. AXR0[1]/DX0/ IPD J3 K2 I/O/Z ForMcASP0,itisMcASP0transmit/receive(TX/RX)datapin1 GP[104] DV DD33 AXR0[1](I/O/Z). ThispinismultiplexedbetweenMcASP0andGPIO. IPD AXR0[0]/GP[105] H2 H2 I/O/Z ForMcASP0,itisMcASP0transmit/receive(TX/RX)datapin0 DV DD33 AXR0[0](I/O/Z). (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 46 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-20.High-EndControllerAreaNetwork(HECC) SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. HECC HECC_RX/ TINP1L/ IPU ThispinismultiplexedbetweenHECC,Timer1,UART1,andGPIO. L4 P3 I/O/Z URXD1/ DV ForHECC,thispinisHECCreceiveserialdataHECC_RX(I). DD33 GP[56] HECC_TX/ TOUT1L/ IPU ThispinismultiplexedbetweenHECC,Timer1,UART1,andGPIO. K4 N3 I/O/Z UTXD1/ DV ForHECC,thispinisHECCtransmitserialdataHECC_TX(O/Z). DD33 GP[55] (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 47

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-21.UART0andUART1TerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. UART1 HECC_RX/ ThispinismultiplexedbetweentheHECC,Timer1,UART1(Data), TINP1L/ IPU L4 P3 I/O/Z andGPIO. URXD1/ DV DD33 FoUART1thispinisthereceivedatainputURXD1. GP[56] HECC_TX/ ThispinismultiplexedbetweentheHECC,Timer1,UART1(Data), TOUT1L/ IPU K4 N3 I/O/Z andGPIO. UTXD1/ DV DD33 FoUART1thispinisthetransmitdataoutputUTXD1. GP[55] UART0 URXD0/ IPU ThispinismultiplexedbetweenUART0(Data)andGPIO. L2 M2 I/O/Z GP[85] DV WhenusedbyUART0thispinisthereceivedatainputURXD0. DD33 UTXD0/ IPU ThispinismultiplexedbetweenUART0(Data)andGPIO. K3 N1 I/O/Z GP[86] DV InUART0mode,thispinisthetransmitdataoutputUTXD0. DD33 UCTS0 IPU ThispinismultiplexedbetweentheUART0(FlowControl)andGPIO. L1 P1 I/O/Z GP[87] DV InUART0mode,thispinisthecleartosendinputUCTS0. DD33 URTS0 ThispinismultiplexedbetweentheUART0(FlowControl),PWM0, IPU PWM0 L3 M3 I/O/Z andGPIO. DV GP[88] DD33 InUART0mode,thispinisthereadytosendoutputURTS0. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 48 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-22.PWM0,PWM1,andPWM2TerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. PWM2 ThispinismultiplexedbetweentheSystemClockgenerator(PLL1), CLKOUT0/PWM2/ IPD M1 R1 I/O/Z PWM2,andGPIO. GP[84] DV DD33 ForPWM2,thispinisoutputPWM2. PWM1 IPD ThispinismultiplexedbetweenGPIOandPWM1. GP[4]/PWM1 F3 F3 I/O/Z DV ForPWM1,thispinisoutputPWM1. DD33 PWM0 ThispinismultiplexedbetweentheUART0(FlowControl),PWM0, URTS0/PWM0/ IPU L3 M3 I/O/Z andGPIO. GP[88] DV DD33 ForPWM0,thispinisoutputPWM0. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 49

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-23.Timer0,Timer1,andTimer2TerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. Timer2 Noexternalpins.TheTimer2(watchdog)peripheralpinsarenotpinnedoutasexternalpins. Timer1 HECC_RX/ ThispinismultiplexedbetweentheHECC,Timer1,UART1(Data), TINP1L/ IPU andGPIO. L4 P3 I/O/Z URXD1/ DV ForTimer1,thispinisthetimer1inputpinforthelower32-bit DD33 GP[56] counter HECC_TX/ ThispinismultiplexedbetweentheHECC,Timer1,UART1,and TOUT1L/ IPU GPIO. K4 N3 I/O/Z UTXD1/ DV ForTimer1,thispinisthetimer1outputpinforthelower32-bit DD33 GP[55] counter Timer0 ThispinismultiplexedbetweentheTimer0andGPIO. TINP0L/ IPD K2 L2 I/O/Z ForTimer0,thispinisthetimer0inputpinforthelower32-bit GP[98] DV DD33 counter CLKS0/ ThispinismultiplexedbetweentheMcBSP0,Timer0,andGPIO. IPD TOUT0L/ J4 L3 I/O/Z ForTimer0,thispinisthetimer0outputpinforthelower32-bit DV GP[97] DD33 counter (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 50 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-24.GPIOTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. GPIO 97outof111GPIOpinsontheDM6435devicearemultiplexedwithotherperipheralspinfunctions(e.g.,VPFE,HPI,VLYNQ, EMAC/MDIO,McASP0,McBSP0,Timer0,Timer1,UART0,UART1,PWM0,PWM1,PWM2,EMIFA,andtheCLKOUT0pin),seethe peripheral-specificTerminalFunctionstablesfortheGPIOmultiplexing. (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 51

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-25.StandaloneGPIO3.3VTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. StandaloneGPIO3.3V IPD GP[0] E1 E1 I/O/Z ThispinfunctionsasstandaloneGPIOpin0. DV DD33 IPD GP[1] E2 E2 I/O/Z ThispinfunctionsasstandaloneGPIOpin1. DV DD33 IPD GP[2] E3 F1 I/O/Z ThispinfunctionsasstandaloneGPIOpin2. DV DD33 IPD GP[3] E4 F2 I/O/Z ThispinfunctionsasstandaloneGPIOpin3. DV DD33 GP[22]/ IPD F18 J20 I/O/Z (BOOTMODE0) DV DD33 GP[23]/ IPD F15 K20 I/O/Z (BOOTMODE1) DV DD33 GP[24]/ IPD Thesepinsfunctionasbootconfigurationpinsduringdevicereset. G15 L20 I/O/Z (BOOTMODE2) DV Afterdevicereset,thesepinsfunctionasstandaloneGPIO. DD33 GP[25]/ IPD G16 H21 I/O/Z (BOOTMODE3) DV DD33 GP[26]/ IPD G17 K19 I/O/Z (FASTBOOT) DV DD33 ForproperDM6435deviceoperation,thispinmustbepulledupvia IPU GP[27] H17 L19 I/O/Z anexternalresistor. DV DD33 Afterdevicereset,thispinfunctionsasstandaloneGPIOpin27. ForproperDM6435deviceoperation,thispinmustbepulleddown IPD GP[28] H16 J21 I/O/Z viaanexternalresistor. DV DD33 Afterdevicereset,thispinfunctionsasstandaloneGPIOpin28. IPD GP[29] H15 K21 I/O/Z ThispinfunctionsasstandaloneGPIOpin29. DV DD33 IPD GP[30] G19 K22 I/O/Z ThispinfunctionsasstandaloneGPIOpin30. DV DD33 IPD GP[31] D19 G22 I/O/Z ThispinfunctionsasstandaloneGPIOpin31. DV DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal 52 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-26.ReservedTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER(2)(3) DESCRIPTION NAME NO. NO. RESERVED RSV1 E5 D4 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV2 K5 L4 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV3 L5 M4 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV4 L15 P19 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV5 R13 W16 Reserved.(Leaveunconnected,donotconnecttopowerorground) Reserved.ThispinmustbetieddirectlytoV fornormaldevice RSV6 N19 V22 SS operation. RSV7 P19 V21 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV8 P18 U22 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV9 N18 T21 Reserved.(Leaveunconnected,donotconnecttopowerorground) RSV10 N17 T22 Reserved.(Leaveunconnected,donotconnecttopowerorground) Reserved.ThispinmustbetieddirectlytoV fornormaldevice RSV11 P16 U20 SS operation. Reserved.ThispinmustbetieddirectlytoV fornormaldevice RSV12 P17 V20 SS operation. Reserved.ThispinmustbetieddirectlytoV fornormaldevice RSV13 N15 T20 SS operation. Reserved.ThispinmustbetieddirectlytoV fornormaldevice RSV14 P15 T19 SS operation. Reserved.ThispinmustbetieddirectlytoV fornormaldevice RSV15 N16 U21 SS operation. IPD Reserved.ForproperDM6435deviceoperation,thispinmustbe RSV16 T3 W3 I DV pulleddownviaanexternalresistorandtiedtoV . DD33 SS IPD RSV17 E10 D12 I/O/Z Reserved.(Leaveunconnected,donotconnecttopowerorground) DV DD33 IPD RSV18 E11 D13 I/O/Z Reserved.(Leaveunconnected,donotconnecttopowerorground) DV DD33 IPD RSV19 E12 D14 I/O/Z Reserved.(Leaveunconnected,donotconnecttopowerorground) DV DD33 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal (2) IPD=Internalpulldown,IPU=Internalpullup.Formoredetailedinformationonpullup/pulldownresistorsandsituationswhereexternal pullup/pulldownresistorsarerequired,seeSection3.9.1,Pullup/PulldownResistors. (3) SpecifiestheoperatingI/Osupplyvoltageforeachsignal SubmitDocumentationFeedback DeviceOverview 53

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-27.SupplyTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER DESCRIPTION NAME NO. NO. SUPPLYVOLTAGEPINS A1 A2 A2 A21 A18 B1 E6 D6 E8 D8 F5 D10 F7 D16 F9 D18 F11 E3 F13 E5 G6 E7 G8 E9 G10 E11 G12 E13 G14 E15 H5 E17 H18 E19 J1 F4 J6 F18 J14 G5 3.3VI/Osupplyvoltage DV S DD33 J16 G19 (seethePower-SupplyDecouplingsectionofthisdatamanual) K15 H4 K17 H18 L6 J5 M5 J19 M15 K4 N6 K18 P1 L1 L5 L21 M18 M20 N5 N19 P4 P18 P20 P22 R5 T4 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal 54 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-27.SupplyTerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER DESCRIPTION NAME NO. NO. L14 U5 P5 V1 P7 V4 P9 V6 P11 V8 P13 V10 R4 V12 R6 V14 R8 V16 1.8VDDR2I/Osupplyvoltage DV S DDR2 R10 V18 (seethePower-SupplyDecouplingsectionofthisdatamanual) R12 W7 R14 W9 R16 W11 T5 W17 V1 W19 W18 AA1 W19 AB21 AB22 H7 J10 H9 J11 H11 J12 H13 J13 J8 K9 J10 K14 J12 L9 K7 L13 K9 L14 K11 M9 1.20Vsupplyvoltage(-7/-6/-5/-4/-L/-Q6/-Q5/-Q4devices) CV K13 M10 S 1.05Vcoresupplyvoltage(-7/-6/-5/-4/-L/-Q5devices) DD (seethePower-SupplyDecouplingsectionofthisdatamanual) L8 M14 L10 N9 L12 N14 M7 P10 M9 P11 M11 P12 M13 P13 N8 N10 N12 SubmitDocumentationFeedback DeviceOverview 55

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table2-28.GroundTerminalFunctions SIGNAL ZWT ZDU TYPE(1) OTHER DESCRIPTION NAME NO. NO. GROUNDPINS A19 A1 B1 A22 B19 B22 E7 D5 E9 D7 E13 D9 F4 D11 F6 D15 F8 D17 F10 E4 F12 E6 F14 E8 G5 E10 G7 E12 G9 E14 G11 E16 G13 E18 G18 F5 H6 F19 V H8 G4 GND Groundpins SS H10 G18 H12 H5 H14 H19 H19 J4 J5 J9 J7 J14 J9 J18 J11 K5 J13 K10 J15 K11 J17 K12 J18 K13 K1 L10 K6 L11 K8 L12 K10 L18 K12 L22 K14 M1 K16 M5 (1) I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal 56 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table2-28.GroundTerminalFunctions (continued) SIGNAL ZWT ZDU TYPE(1) OTHER DESCRIPTION NAME NO. NO. L7 M11 L9 M12 L11 M13 L13 M19 L17 N4 L19 N10 M6 N11 M8 N12 M10 N13 M12 N18 M14 P5 M16 P9 M17 P14 M18 P21 M19 R4 N5 R18 N7 R19 N9 R20 N11 R21 N13 R22 N14 T5 V P6 T18 GND Groundpins SS P8 U4 P10 U18 P12 U19 P14 V5 R1 V7 R5 V9 R7 V11 R9 V13 R11 V15 R15 V17 R17 V19 R18 W1 R19 W6 V19 W8 W1 W10 W2 W20 W21 W22 AA22 AB1 AB2 SubmitDocumentationFeedback DeviceOverview 57

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 2.7 Device Support 2.7.1 Development Support TI offers an extensive line of development tools for the TMS320DM643x DMP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically availablewithintheCodeComposerStudio™IntegratedDevelopmentEnvironment(IDE). ThefollowingproductssupportdevelopmentofTMS320DM643xDMP-basedapplications: SoftwareDevelopmentTools: CodeComposerStudio™IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCodeGeneration,andDebugplusadditionaldevelopmenttools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target softwareneededtosupportanySoCapplication. HardwareDevelopmentTools: Extended Development System (XDS™) Emulator (supports TMS320DM643x DMP multiprocessor systemdebug)EVM(EvaluationModule) For a complete listing of development-support tools for the TMS320DM643x DMP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 2.8 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320DM6435ZWT400). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed qualityandreliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. 58 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production systembecausetheirexpectedend-usefailureratestill is undefined. Only qualified production devices are tobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperaturerange),andthedevicespeedrangeinmegahertz(forexample,"6"indicates[600-MHz]). Figure 2-10 provides a legend for reading the complete device name for any TMS320DM643x DMP platformmember. TMS 320 DM6435 ( ) ZWT ( ) ( ) DEVICE SPEED RANGE PREFIX 4 = 400 MHz TMX = Experimental device 5 = 500 MHz TMS = Qualified device 6 = 600 MHz(D) 7 = 700 MHz L= Low Power Device DEVICE FAMILY TEMPERATURE RANGE (JUNCTION) 320 =TMS320™DSPFamily Blank = 0° C to 90° C, Commercial Grade Q = -40°C to 125°C,Automotive Grade DEVICE R =0° C to 90° C, Commercial Grade (Tape and Reel) C64x+™DSP: S = -40°C to 125°C,Automotive Grade (Tape and Reel) DM6437 PACKAGETYPE(A) DM6435 ZWT = 361-pin plastic BGA, with Pb-Free soldered balls DM6433 ZDU = 376-pin plastic BGA, with Pb-Free soldered balls [Green] DM6431 SILICON REVISION: Blank = Revision 1.3 A. BGA= Ball GridArray B. For“TMX”initial devices, the device number is DM6437. C. Not all combinations are available. For more information, see theOrderable Devicestable in the Packing Information section. D. The maximum CPU frequency for the -Q6 device is 660 MHz. See thePLL1 and PLL2section for maximum operating frequencies of the PLL1 controller. E. The device speed range symbolization indicates the maximum CPU frequency when the core voltage (CV ) is set to 1.2 V. DD To determine the maximum CPU frequency the core voltage is set to 1.05 V, refer to thePLL1 and PLL2section. Figure2-10.DeviceNomenclature SubmitDocumentationFeedback DeviceOverview 59

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 2.9 Documentation Support 2.9.1 Related Documentation From Texas Instruments The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box providedatwww.ti.com. The current documentation that describes the DM643x DMP, related peripherals, and other technical collateral,isavailableintheC6000DSPproductfolderat:www.ti.com/c6000. SPRU978 TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signal processor(DSP)subsystemintheTMS320DM643xDigitalMediaProcessor(DMP). SPRU983 TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP). SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in thedevicesthatisidenticalisnotincluded. SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancementoftheC64xDSPwithaddedfunctionalityandanexpandedinstructionset. SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,bandwidthmanagement,andthememoryandcache. 60 DeviceOverview SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3 Device Configuration 3.1 System Module Registers The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. System Module registers required for device configurationsarediscussedinthefollowingsections. Table3-1.SystemModuleRegisterMemoryMap HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C40000 PINMUX0 PinMultiplexingControl0(seeSection3.7.2.1,PINMUX0Register Description). 0x01C40004 PINMUX1 PinMultiplexingControl1(seeSection3.7.2.2,PINMUX1Register Description). 0x01C40008 DSPBOOTADDR DSPBootAddress(seeSection3.4.2.3,DSPBOOTADDRRegister). 0x01C4000C BOOTCOMPLT BootComplete(seeSection3.4.2.2,BOOTCMPLTRegister). 0x01C40010 – Reserved 0x01C40014 BOOTCFG DeviceBootConfiguration(seeSection3.4.2.1,BOOTCFGRegister). 0x01C40018-0x01C40027 – Reserved 0x01C40028 JTAGID JTAGID(seeSection6.23.1,JTAGID(JTAGID)Register Description(s)). 0x01C4002C – Reserved 0x01C40030 HPICTL HPIControl(seeSection3.6.2.1,HPIControlRegister). 0x01C40034 – Reserved 0x01C40038 – Reserved 0x01C4003C MSTPRI0 BusMasterPriorityControl0(seeSection3.6.1,SwitchCentral Resource(SCR)BusPriorities). 0x01C40040 MSTPRI1 BusMasterPriorityControl1(seeSection3.6.1,SwitchCentral Resource(SCR)BusPriorities). 0x01C40044 VPSS_CLKCTL VPSSClockControl(seeSection3.3.2,VPSSClocks). 0x01C40048 VDD3P3V_PWDN V 3.3-VI/OPowerdownControl(seeSection3.2,Power DD Considerations). 0x01C4004C DDRVTPER DDR2VTPEnableRegister(seeSection6.9.4,DDR2Memory Controller). 0x01C40050-0x01C40080 – Reserved 0x01C40084 TIMERCTL TimerControl(seeSection3.6.2.2,TimerControlRegister). 0x01C40088 EDMATCCFG EDMATransferControllerDefaultBurstSizeConfiguration(see Section3.6.2.3,EDMATCConfigurationRegister). 0x01C4008C – Reserved SubmitDocumentationFeedback DeviceConfiguration 61

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.2 Power Considerations TheDM6435providesseveralmeansofmanagingpowerconsumption. As described in the Section 6.3.4, DM6435 Power and Clock Domains, the DM6435 has one single power domain—the “Always On” power domain. Within this power domain, the DM6435 utilizes local clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320DM643x DMP DSP Subsystem ReferenceGuide(literaturenumberSPRU978). Some of the DM6435 peripherals support additional power saving features. For more details on power saving features supported, see the TMS320DM643x DMP Peripherals Overview Reference Guide (literaturenumberSPRU983). Most DM6435 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN register in the System Module (see Figure 3-1) is used to selectively power down unused 3.3-V I/O pins. For independent control, the 3.3-V I/Os are separated into functional groups—most of which are named accordingtothepinmultiplexinggroups(seeTable3-2).FortheseI/Ogroups,onlytheI/Obuffersneeded for Host/EMIFA Boot or Power-Up Operations are powered up by default (CLKOUT Block, EMIFA/VPSS Block,HostBlock,andGPIOBlock). Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user mustprogramtheVDD3P3V_PWDNregistertopowerupthecorrespondingI/Obuffers. For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see Section3.7.3.1,MultiplexedPinsonDM6435. 31 16 RESERVED R-0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RSV EMBK3 UR0FC UR0DAT TIMER1 TIMER0 SP PWM1 GPIO HOST EMBK2 EMBK1 EMBK0 CLKOUT R-00 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset Figure3-1.VDD3P3V_PWDNRegister Table3-2.VDD3P3V_PWDNRegisterBitDescriptions(1) BIT NAME DESCRIPTION 31:14 RESERVED Reserved.Read-only,writeshavenoeffect. Reserved.Thisbitshouldbeprogrammedto1duringdeviceinitialization(seeSection3.8, 13 RSV DeviceInitializationSequenceAfterReset). EMIFA/VPSSSub-Block3I/OPowerDownControl. Controlsthepowerofthe8I/OpinsintheEMIFA/VPSSSub-Block3. 12 EMBK3 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). UART0FlowControlBlockI/OPowerDownControl. Controlsthepowerofthe2I/OpinsintheUART0FlowControlBlock. 11 UR0FC 0=I/Opinspoweredup. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z)[default]. (1) FormoredetailsonI/Opinsbelongingtoeachpinmuxblock,seeSection3.7,MultiplexedPinConfigurations. 62 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-2.VDD3P3V_PWDNRegisterBitDescriptions (continued) BIT NAME DESCRIPTION UART0DataBlockI/OPowerDownControl. Controlsthepowerofthe2I/OpinsintheUART0DataBlock. 10 UR0DAT 0=I/Opinspoweredup. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z)[default]. Timer1BlockI/OPowerDownControl. Controlsthepowerofthe2I/OpinsintheTimer1Block. 9 TIMER1 0=I/Opinspoweredup. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z)[default]. Timer0BlockI/OPowerDownControl. Controlsthepowerofthe2I/OpinsintheTimer0Block. 8 TIMER0 0=I/Opinspoweredup. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z)[default]. SerialPortBlockI/OPowerDownControl. Controlsthepowerofthe12I/OpinsintheSerialPortBlock(SerialPortSub-Block0and SerialPortSub-Block1). 7 SP 0=I/Opinspoweredup. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z)[default]. PWM1BlockI/OPowerDownControl. Controsthelpowerofthe1I/OpininthePWM1Block. 6 PWM1 0=I/Opinspoweredup. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z)[default]. GPIOBlockI/OPowerDownControl. Controlsthepowerofthe4I/OpinsintheGPIOBlock(GP[3:0]). Note:TheGPIOBlockcontainsstandaloneGPIOpinsandisnotapinmuxgroup. 5 GPIO 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). HostBlockI/OPowerDownControl. Controlsthepowerofthe27I/OpinsintheHostBlock. 4 HOST 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). EMIFA/VPSSSub-Block2I/OPowerDownControl. Controlsthepowerofthe3I/OpinsintheEMIFA/VPSSSub-Block2. 3 EMBK2 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). EMIFA/VPSSSub-Block1I/OPowerDownControl. Controlsthepowerofthe29I/OpinsintheEMIFA/VPSSSub-Block1. 2 EMBK1 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). EMIFA/VPSSSub-Block0I/OPowerDownControl. Controlsthepowerofthe21I/OpinsintheEMIFA/VPSSSub-Block0. 1 EMBK0 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). CLKOUTBlockI/OPowerDownControl. Controlsthepowerofthe1I/OpinintheCLKOUTBlock. 0 CLKOUT 0=I/Opinspoweredup[default]. 1=I/Opinspowereddownandnotoperational.Outputsare3-stated(Hi-Z). SubmitDocumentationFeedback DeviceConfiguration 63

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.3 Clock Considerations Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and thePowerandSleepController (PSC). In addition, the System Module VPSS_CLKCTL register configures theclocksourcetotheVideoProcessingSubsystem(VPSS). 3.3.1 Clock Configurations after Device Reset After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the desiredperipheralclockstate(clockgatingornot). For additional power savings, some of the DM6435 peripherals support clock gating within the peripheral boundary. For more details on clock gating and power saving features supported by a specific peripheral, see the peripheral-specific reference guides [listed/linked in the TMS320DM643x DMP Peripherals OverviewReferenceGuide(literaturenumberSPRU983)]. 3.3.1.1 DeviceClockFrequency The DM6435 defaults to PLL bypass mode. To bring the device up to the desired clock frequency, the usershouldprogramPLLC1andPLLC2afterdevicereset. DM6435 supports a FASTBOOT option, where upon exit from device reset the internal bootloader code automatically programs the PLLC1 into PLL mode with a specific PLL multiplier and divider to speed up device boot. While the FASTBOOT option is beneficial for faster boot, the PLL multiplier and divider selected for boot may not be the exact frequency desired for the run-time application. It is the user's responsibility to reconfigure PLLC1 after fastboot to bring the device into the desired clock frequency. Section3.4.1,BootModesdiscussesthedifferentfastbootmodesinmoredetail. TheusermustadheretothevariousclockrequirementswhenprogrammingthePLLC1andPLLC2: • Fixed frequency ratio requirements between CLKDIV1, CLKDIV3, and CLKDIV6 clock domains. For more details on the frequency ratio requirements, see Section 6.3.4, DM6435 Power and Clock Domains. • PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see Section6.7.1,PLL1andPLL2. 3.3.1.2 ModuleClockState The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC). Table 3-3 shows the default state of each module after a device-level global reset. The DM6435 device has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on thedefinitionsofthe module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978). 64 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-3.DM6435DefaultModuleStates DEFAULTMODULESTATE LPSC# MODULENAME [PSCRegisterMDSTATn.STATE] 0 VPSS(Master) SwRstDisable 1 VPSS(Slave) SwRstDisable 2 EDMACC SwRstDisable 3 EDMATC0 SwRstDisable 4 EDMATC1 SwRstDisable 5 EDMATC2 SwRstDisable 6 EMACMemoryController SwRstDisable 7 MDIO SwRstDisable 8 EMAC SwRstDisable 9 McASP0 SwRstDisable 11 VLYNQ SwRstDisable 12 HPI SwRstDisable 13 DDR2MemoryContoller SwRstDisable SwRstDisable,ifconfigurationpinsAEM[2:0]=000b 14 EMIFA Enable,ifconfigurationpinsAEM[2:0]=Others[001band101b] 16 McBSP0 SwRstDisable 18 I2C SwRstDisable 19 UART0 SwRstDisable 20 UART1 SwRstDisable 22 HECC SwRstDisable 23 PWM0 SwRstDisable 24 PWM1 SwRstDisable 25 PWM2 SwRstDisable 26 GPIO SwRstDisable 27 TIMER0 SwRstDisable 28 TIMER1 SwRstDisable 39 C64x+CPU Enable SubmitDocumentationFeedback DeviceConfiguration 65

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.3.2 VPSS Clocks The Video Processing SubSystem (VPSS) clocks are controlled via the VPSS_CLKCTL register. The VPSS_CLKCTLregisterformatisshowninFigure3-2andthebitfielddescriptionsaregiveninTable3-4. 31 16 RESERVED R-0000000000000000 15 5 4 3 2 1 0 PCLK RESERVED RESERVED RESERVED INV R-00000000000 R/W-00 R/W-0 R/W-00 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-2.VPSS_CLKCTLRegister Table3-4.VPSS_CLKCTLRegisterBitDescription BIT NAME DESCRIPTION 31:5 RESERVED Reserved.Read-only,writeshavenoeffect. Reserved.Forproperdeviceoperation,theusermustonlywrite"0"tothese 4:3 RESERVED bits. PCLKpolarity 2 PCLKINV 0=VPSSreceivesnormalPCLK[default]. 1=VPSSreceivesinvertedPCLK. Reserved.Forproperdeviceoperation,theusermustonlywrite"0"tothese 1:0 RESERVED bits. 66 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.4 Boot Sequence The boot sequence is a process by which the device's memory is loaded with program and data sections, andbywhichsomeofthedevice'sinternal registers are programmed with predetermined values. The boot sequence is started automatically after each device-level global reset. For more details on device-level globalresets,seeSection6.5,Reset. There are several methods by which the memory and register initialization can take place. Each of these methods is referred to as a boot mode. The boot mode to be used is selected at reset. For more informationonthebootmodeselections,seeSection3.4.1,BootModes. The device is booted through multiple means—primary bootloaders within internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and registerconfigurationsrequiredforbootingthedevice,aredescribedinthefollowingsubsections. 3.4.1 Boot Modes The DM6435 boot modes are determined by these device boot and configuration pins. For information on howthesepinsaresampledatdevicereset,seeSection6.5.1.2,LatchingBootandConfigurationPins. • BOOTMODE[3:0] • FASTBOOT • AEM[2:0] • PLLMS[2:0] Note: the PLLMS[2:0] configuration pins are actually multiplexed with the AEAW[2:0] configuration pins. For more details on the multiplexed AEAW[2:0]/PLLMS[2:0] configuration pins and control, see Section 3.5.1.2, EMIFA Address Width Selects (AEAW[2:0]) and FASTBOOT PLL Multiplier Selects (PLLMS[2:0]). BOOTMODE[3:0]determinesthetypeofboot(e.g.,I2CBoot,EMIFABoot,or HPI Boot, etc.). FASTBOOT determinesifthePLLisenabledduringboottospeedupthebootprocess. The combination of AEM[2:0] and PLLMS[2:0] is used by bootloader code to determine the PLL multiplier usedduringfastbootmodes(FASTBOOT=1). The DM6435 boot modes are grouped into three categories—Non-Fastboot Modes, Fixed-Multiplier FastbootModes,andUser-SelectMultiplierFastbootModes. • Non-Fastboot Modes (FASTBOOT = 0): The device operates in default PLL bypass mode during boot.TheNon-FastbootbootmodesavailableontheDM6435areshowninTable3-5. • Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b): The bootloader code speeds up the device during boot according to the fixed PLL multipliers. The Fixed-Multiplier Fastboot bootmodesavailableontheDM6435areshowninTable3-6. Note: The PLLMS[2:0] configurations have no effect on the Fixed-Multiplier Fastboot Modes, as these pinsfunctionasAEAW[2:0]toselecttheEMIFAaddresswidthwhenAEM[2:0]=001b. • User-Select Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 000b and 101b): The bootloader code speeds up the device during boot. The PLL multiplier is selected by the user via the PLLMS[2:0] pins. The User-Select Multiplier Fastboot bootmodes available on the DM6435 are shown inTable3-7. Allothermodesnotshowninthesetablesarereservedandinvalidsettings. For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching Boot andConfigurationPins. SubmitDocumentationFeedback DeviceConfiguration 67

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-5.Non-FastbootModes(FASTBOOT=0) DEVICEBOOTAND CONFIGURATION PLLC1CLOCKSETTINGATBOOT PINS BOOTDESCRIPTION(1) (DMMas6t4e3r5/SDlaMvPe) DEVICE DS(DPEBFOAOUTLATD)(D1)R PLL CLKDIV1DOMAIN BOOTMODE[3:0] MODE(2) (SYSCLK1DIVIDER) FREQUENCY (SYSCLK1) 0000 NoBoot(EmulationBoot) Master Bypass /1 CLKIN 0x00100000 0001 Reserved – – – – – 0010 HPIBoot Slave Bypass /1 CLKIN 0x00100000 0011 Reserved – – – – – EMIFAROMDirectBoot 0100 Master Bypass /1 CLKIN 0x4200000 [PLLBypassMode] I2CBoot 0101 [STANDARDMODE](3) Master Bypass /1 CLKIN 0x00100000 0110 16-bitSPIBoot[McBSP0] Master Bypass /1 CLKIN 0x00100000 0111 NANDFlashBoot Master Bypass /1 CLKIN 0x00100000 UARTBootwithout 1000 HardwareFlowControl Master Bypass /1 CLKIN 0x00100000 [UART0] 1001 Reserved – – – – – 1010 VLYNQBoot Slave Bypass /1 CLKIN 0x00100000 1011 Reserved – – – – – 1100 Reserved – – – – – 1101 Reserved – – – – – UARTBootwithHardware 1110 Master Bypass /1 CLKIN 0x00100000 FlowControl[UART0] 24-bitSPIBoot(McBSP0+ 1111 Master Bypass /1 CLKIN 0x00100000 GP[97]) (1) ForallbootmodesthatdefaulttoDSPBOOTADDR=0x00100000(i.e.,allbootmodesexcepttheEMIFAROMDirectBoot, BOOTMODE[3:0]=0100,FASTBOOT=0),thebootloadercodedisablesallC64x+cache(L2,L1P,andL1D)sothatuponexitfromthe bootloadercode,allC64x+memoriesareconfiguredasallRAM.Ifcacheuseisrequired,theapplicationcodemustexplicitlyenablethe cache.Formoreinformationonthebootloader,seetheUsingtheTMS320DM643xBootloaderApplicationReport(literaturenumber SPRAAG0). (2) ThePLLMODEforNon-FastbootModesisfixedasshowninthistable;therefore,thePLLMS[2:0]configurationpinshavenoeffecton thePLLMODE. (3) I2CBoot(BOOTMODE[3:0]=0101b)isonlyavailableiftheMXI/CLKINfrequencyisbetween21MHzto30MHz.I2CBootisnot availableforMXI/CLKINfrequencieslessthan21MHz. 68 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-6.Fixed-MultiplierFastbootModes(FASTBOOT=1,AEM[2:0]=001b) DEVICEBOOTAND CONFIGURATION PLLC1CLOCKSETTINGATBOOT PINS BOOTDESCRIPTION(1) (DMMas6t4e3r5/SDlaMvPe) DEVICE DS(DPEBFOAOUTLATD)(D1)R PLL CLKDIV1DOMAIN BOOTMODE[3:0] MODE(2) (SYSCLK1DIVIDER) FREQUENCY (SYSCLK1) 0000 NoBoot(EmulationBoot) Master Bypass /1 CLKIN 0x00100000 HPIBootwithPLL 0001 Slave x27 /2 CLKINx27/2 0x00100000 Multiplierx27atboot HPIBootwithPLL 0010 Slave x20 /2 CLKINx20/2 0x00100000 Multiplierx20atboot HPIBootwithPLL 0011 Slave x15 /2 CLKINx15/2 0x00100000 Multiplierx15atboot EMIFAROMFASTBOOT 0100 withApplicationImage Master x20 /2 CLKINx20/2 0x0010000 Script(AIS) I2CBoot 0101 [FASTMODE](3) Master x20 /2 CLKINx20/2 0x00100000 0110 16-bitSPIBoot[McBSP0] Master x20 /2 CLKINx20/2 0x00100000 0111 NANDFlashBoot Master x20 /2 CLKINx20/2 0x00100000 UARTBootwithout 1000 HardwareFlowControl Master x20 /2 CLKINx20/2 0x00100000 [UART0] EMIFAROMFASTBOOT 1001 Master x20 /2 CLKINx20/2 0x00100000 withoutAIS 1010 VLYNQBoot Slave x20 /2 CLKINx20/2 0x00100000 1011 Reserved – – – – – 1100 Reserved – – – – – 1101 Reserved – – – – – UARTBootwithHardware 1110 Master x20 /2 CLKINx20/2 0x00100000 FlowControl[UART0] 24-bitSPIBoot(McBSP0+ 1111 Master x20 /2 CLKINx20/2 0x00100000 GP[97]) (1) ForallbootmodesthatdefaulttoDSPBOOTADDR=0x00100000,thebootloadercodedisablesallC64x+cache(L2,L1P,andL1D) sothatuponexitfromthebootloadercode,allC64x+memoriesareconfiguredasallRAM.Ifcacheuseisrequired,theapplication codemustexplicitlyenablethecache.Formoreinformationonthebootloader,seetheUsingtheTMS320DM643xBootloader ApplicationReport(literaturenumberSPRAAG0). (2) ThePLLMODEforFixed-MultiplierFastbootModesisfixedasshowninthistable;therefore,thePLLMS[2:0]configurationpinshaveno effectonthePLLMODE. (3) I2CBoot(BOOTMODE[3:0]=0101b)isonlyavailableiftheMXI/CLKINfrequencyisbetween21MHzto30MHz.I2CBootisnot availableforMXI/CLKINfrequencieslessthan21MHz. SubmitDocumentationFeedback DeviceConfiguration 69

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-7.User-SelectMultiplierFastbootModes(FASTBOOT=1,AEM[2:0]=000bor101b) DEVICEBOOTAND CONFIGURATION PLLC1CLOCKSETTINGATBOOT PINS BOOTDESCRIPTION(1) (DMMas6t4e3r5/SDlaMvPe) DEVICE DS(DPEBFOAOUTLATD)(D1)R PLL CLKDIV1DOMAIN BOOTMODE[3:0] MODE(2) (SYSCLK1DIVIDER) FREQUENCY (SYSCLK1) 0000 NoBoot(EmulationBoot) Master Bypass /1 CLKIN 0x00100000 0001 Reserved – – – – – 0010 HPIBoot Slave Table3-8 /2 Table3-8 0x00100000 0011 Reserved – – – – – EMIFAROMFASTBOOT 0100 Master Table3-8 /2 Table3-8 0x00100000 withAIS I2CBoot 0101 [FASTMODE](3) Master Table3-8 /2 Table3-8 0x00100000 0110 16-bitSPIBoot[McBSP0] Master Table3-8 /2 Table3-8 0x00100000 0111 NANDFlashBoot Master Table3-8 /2 Table3-8 0x00100000 UARTBootwithout 1000 HardwareFlowControl Master Table3-8 /2 Table3-8 0x00100000 [UART0] EMIFAROMFASTBOOT 1001 Master Table3-8 /2 Table3-8 – withoutAIS 1010 Reserved – – – – – 1011 Reserved – – – – – 1100 Reserved – – – – – 1101 Reserved – – – – – UARTBootwithHardware 1110 Master Table3-8 /2 Table3-8 0x00100000 FlowControl[UART0] 1111 Reserved – – – – – (1) ForallbootmodesthatdefaulttoDSPBOOTADDR=0x00100000,thebootloadercodedisablesallC64x+cache(L2,L1P,andL1D) sothatuponexitfromthebootloadercode,allC64x+memoriesareconfiguredasallRAM.Ifcacheuseisrequired,theapplication codemustexplicitlyenablethecache.Formoreinformationonthebootloader,seetheUsingtheTMS320DM643xBootloader ApplicationReport(literaturenumberSPRAAG0). (2) AnysupportedPLLMODEisavailable.[SeeTable3-8forsupportedDM6435PLLMODEoptions]. (3) I2CBoot(BOOTMODE[3:0]=0101b)isonlyavailableiftheMXI/CLKINfrequencyisbetween21MHzto30MHz.I2CBootisnot availableforMXI/CLKINfrequencieslessthan21MHz. Table3-8.PLLMultiplierSelection(PLLMS[2:0])inUser-SelectMultiplierFastbootModes (FASTBOOT=1;AEM[2:0]=000bor101b) DEVICEBOOTAND PLLC1CLOCKSETTINGATBOOT CONFIGURATIONPINS CLKDIV1DOMAIN PLLMS[2:0] PLLMODE DEVICEFREQUENCY(SYSCLK1) (SYSCLK1DIVIDER) 000 x20 /2 CLKINx20/2 001 x15 /2 CLKINx15/2 010 x16 /2 CLKINx16/2 011 x18 /2 CLKINx18/2 100 x22 /2 CLKINx22/2 101 x25 /2 CLKINx25/2 110 x27 /2 CLKINx27/2 111 x30 /2 CLKINx30/2 As shown in Table 3-5, Table 3-6, and Table 3-7, at device reset the Boot Controller defaults the DSPBOOTADDR to one of two values based on the boot mode selected. In all boot modes, the C64x+ is immediately released from reset and begins executing from address location indicated in DSPBOOTADDR. 70 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 • Internal Bootloader ROM (0x0010 0000): For most boot modes, the DSPBOOTADDR defaults to the internal Bootloader ROM so that the DSP can immediately execute the bootloader code in the internal ROM. The bootloader code decodes the captured BOOTMODE, FASTBOOT, default AEM (DAEM), andPLLMSinformation(intheBOOTCFGregister)todeterminetheproperbootoperation. Note: For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application code must explicitly enable the cache. For more information on boot modes, see Section 3.4.1, Boot Modes. For more information on the bootloader, see the Using the TMS320DM643x Bootloader Application Report (literaturenumberSPRAAG0). • EMIFA Chip Select Space 2 (0x4200 0000): The EMIFA ROM Direct Boot in PLL Bypass Mode (BOOTCFG settings BOOTMODE[3:0] = 0100b, FASTBOOT = 0) is the only exception where the DSPBOOTADDR defaults to the EMIFA Chip Select Space 2. The DSP begins execution directly from theexternalROMatthisEMIFAspace. For more information how the bootloader code handles each boot mode, see Using the TMS320DM643x BootloaderApplicationReport(literaturenumberSPRAAG0). 3.4.1.1 FASTBOOT When DM6435 exits pin reset (RESET or POR released), the PLL Controllers (PLLC1 and PLLC2) default to PLL Bypass Mode. This means the PLLs are disabled, and the MXI/CLKIN clock input is driving the chip. All the clock domain divider ratios discussed in Section 6.3.4, DM6435 Power and Clock Domains, still apply. For example, assume an MXI/CLKIN frequency of 27 MHz—meaning the internal clock source for EMIFA is at CLKDIV3 domain = 27 MHz/3 = 9 MHz, a very slow clock. In addition, the EMIFA registers areresettotheslowestconfigurationwhichtranslatestoveryslowperipheraloperation/boot. To optimize boot time, the user should reprogram clock settings via the PLLC as early as possible during the boot process. The FASTBOOT pin facilitates this operation by allowing the device to boot at a faster clockrate. Except for the EMIFA ROM Direct Boot in PLL Bypass Mode (BOOTCFG settings BOOTMODE[3:0] = 0100b, FASTBOOT = 0), all other boot modes default to executing from the Internal Bootloader ROM. The first action that the bootloader code takes is to decode the boot mode. If the FASTBOOT option is selected (BOOTCFG.FASTBOOT = 1), the bootloader software begins by programming the PLLC1 (System PLLC) to PLL Mode to give the device a slightly faster operation before fetching code from external devices. The exact PLL multiplier that the bootloader uses is determined by the AEM[2:0] and PLLMS[2:0]settings,asshowninTable3-6andTable3-7. Some boot modes must be accompanied with FASTBOOT = 1 so that the corresponding peripheral can runatareasonableratetocommunicatetotheexternaldevice(s). Note:PLLC2stillstaysinPLLBypassMode,thebootloaderdoesnotreconfigureit. SubmitDocumentationFeedback DeviceConfiguration 71

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.4.1.2 SelectingFASTBOOTPLLMultiplier Table 3-6, Table 3-7, and Table 3-8 show the PLL multipliers used by the bootloader code during fastboot (FASTBOOT = 1) and the resulting device frequency. The user is responsible for selecting the bootmode with the appropriate PLL multiplier for their MXI/CLKIN clock source so that the device speed and PLL frequency range requirements are met. For the PLLC1 Clock Frequency Ranges, see Table 6-15, PLLC1 ClockFrequencyRangesinSection6.7.1,PLL1andPLL2. ThefollowingareguidelinesforPLLoutputfrequencyanddevicespeed(frequency): • PLL Output Frequency: (PLLOUT = CLKIN frequency * boot PLL Multiplier) must stay within the PLLOUTfrequencyrangeinTable6-15,PLLC1ClockFrequencyRanges. • Device Frequency: (SYSCLK1) calculated from Table 3-6 and Table 3-7 must not exceed the SYSCLK1maximumfrequencyinTable6-15,PLLC1ClockFrequencyRanges. For example, for a 600-MHz device with a CLKIN = 27 MHz, in order to stay within the PLLOUT frequency range and SYSCLK1 maximum frequency from Table 6-15, PLLC1 Clock Frequency Ranges,theusermustselectabootmodewithaPLL1multiplierbetweenx15andx22. 3.4.1.3 EMIFABootModes As shown in Table 3-5, Table 3-6, and Table 3-7, there are different types of EMIFA Boot Modes. This subsection summarizes these types of EMIFA boot modes. For further detailed information, see the Using theTMS320DM643xBootloaderApplicationReport(literaturenumberSPRAAG0). • EMIFAROMDirectBootinPLLBypassMode(FASTBOOT=0,BOOTMODE[3:0]=0100b) – TheC64x+fetchesthecodedirectlyfromEMIFAChipSelect2Space[EM_CS2](address 0x42000000) – ThePLLisinBypassMode – EMIFAisconfiguredasAsynchronousEMIF.Theuserisresponsibleforensuringthedesirable AsynchronousEMIFpinsareavailablethroughconfigurationpinsAEM[2:0]andAEAW[2:0]. AEM[2:0]mustbeconfiguredto001b[8-bitEMIFA(Async)PinoutMode1]. • EMIFAROMFastbootwithAIS(FASTBOOT=1,BOOTMODE[3:0]=0100b) – TheC64x+beginsexecutionfromtheinternalbootloaderROMataddress0x00100000. – ThebootloadercodeprogramsPLLC1toPLLModetospeedupthebootprocess.ThePLL multipliervalueisdeterminedbytheAEM[2:0]andPLLMS[2:0]configurationsasshownin Table3-6andTable3-7. – ThebootloadercodereadscodefromtheEMIFAEM_CS2spaceusingtheapplicationimagescript (AIS)format. – EMIFAisconfiguredasAsynchronousEMIF.Theuserisresponsibleforensuringthedesirable AsynchronousEMIFpinsareavailablethroughconfigurationpinsAEM[2:0]andAEAW[2:0]. AEM[2:0]mustbeconfiguredto001b[8-bitEMIFA(Async)PinoutMode1]. • EMIFAROMFastbootwithoutAIS:(FASTBOOT=1,BOOTMODE[3:0]=1001b) – TheC64x+beginsexecutionfromtheinternalbootloaderROMataddress0x00100000. – ThebootloadercodeprogramsPLLC1toPLLModetospeedupthebootprocess.ThePLL multipliervalueisdeterminedbytheAEM[2:0]andPLLMS[2:0]configurationsasshownin Table3-6andTable3-7. – ThebootloadercodethenjumpstotheEMIFAEM_CS2space,atwhichpointtheC64x+fetches thecodedirectlyfromaddress0x42000000. – EMIFAisconfiguredasAsynchronousEMIF.Theuserisresponsibleforensuringthedesirable AsynchronousEMIFpinsareavailablethroughconfigurationpinsAEM[2:0]andAEAW[2:0]. AEM[2:0]mustbeconfiguredto001b[8-bitEMIFA(Async)PinoutMode1]. 72 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 • NANDFlashBoot:(FASTBOOT=0or1,BOOTMODE[3:0]=0111b) – TheC64x+beginsexecutionfromtheinternalbootloaderROMataddress0x00100000. – DependingontheFASTBOOT,AEM[2:0],andPLLMS[2:0]settings,thebootloadercodemay programthePLLC1toPLLModetospeedupthebootprocess.SeeTable3-5,Table3-6,and Table3-7. – ThebootloadercodereadsthecodefromEMIFA(NAND)EM_CS2(address0x42000000)using AISformat. – EMIFAisconfiguredinNANDmode.Theuserisresponsibleforensuringthedesirable AsynchronousEMIFpinsareavailablethroughconfigurationpinsAEM[2:0]andAEAW[2:0]. AEM[2:0]canbeconfiguredto001b[8-bitEMIFA(Async)PinoutMode1]or101b[8-bitEMIFA (NAND)PinoutMode5]. 3.4.1.4 SerialBootModes(I2C,UART[UART0],SPI[McBSP0]) Thissubsectiondiscusseshowthebootloaderconfigurestheclockdividersfortheserialboot modes—I2C boot,UARTboot,andSPIboot. 3.4.1.4.1 I2CBoot If FASTBOOT = 0, then I2C Boot (BOOTMODE = 0101) is performed in Standard-Mode (up-to 100 kbps). If FASTBOOT = 1, then I2C Boot is performed in Fast-Mode (up-to 400 kbps). The actual I2C data transferrateisdependentontheMXI/CLKINfrequency. ThisishowthebootloaderprogramstheI2C: • I2CBootinFast-Mode(BOOTMODE[3:0]=0101b,FASTBOOT=1) – I2Cregistersettings:ICPSC.IPSC=2 ,ICCLKL.ICCL=8 ,ICCKH.ICCH=8 10 10 10 – ResultinginthefollowingI2Cprescaledmoduleclockfrequency(internalI2Cclock): • (CLKINfrequencyinMHz)/3 – ResultinginthefollowingI2Cserialclock(SCL): • SCLfrequency(inkHz)=(CLKINfrequencyinMHz)/78*1000 • SCLlowpulseduration(inm s)=39/(CLKINfrequencyinMHz) • SCLhighpulseduration(inm s)=39/(CLKINfrequencyinMHz) • I2CBootinStandard-Mode(BOOTMODE[3:0]=0101b,FASTBOOT=0) – I2Cregistersettings:ICPSC.IPSC=2 ,ICCLKL.ICCL=45 ,ICCKH.ICCH=45 10 10 10 – ResultinginthefollowingI2Cprescaledmoduleclockfrequency(internalI2Cclock): • (CLKINfrequencyinMHz)/3 – ResultinginthefollowingI2Cserialclock(SCL): • SCLfrequency(inkHz)=(CLKINfrequencyinMHz)/300*1000 • SCLlowpulseduration(inm s)=150/(CLKINfrequencyinMHz) • SCLhighpulseduration(inm s)=150/(CLKINfrequencyinMHz) Note: The I2C peripheral requires that the prescaled module clock frequency must be between 7 MHz and 12 MHz. Therefore, the I2C boot is only available for MXI/CLKIN frequency between 21 MHz and 30MHz. For more details on the I2C periperhal configurations and clock requirements, see the TMS320DM643x DMPInter-IntegratedCircuit(I2C)PeripheralUser’sGuide(literaturenumberSPRU991). SubmitDocumentationFeedback DeviceConfiguration 73

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.4.1.4.2 UARTBoot For UART Boot (BOOTMODE[3:0] = 1000b or 1110b), the bootloader programs the UART0 peripheral as follows: • UART0divisorissetto15 10 • ResultinginthisUART0baudrateinkilobitpersecond(kbps): – (CLKINfrequencyinMHz)*1000/(15*16) The user is responsible for ensuring the resulting baud rate is appropriate for the system. The UART0 divisor (/15) is optimized for CLKIN frequency between 27 to 29 MHz to stay within 5% of the 115200-bps baudrate. For more details on the UART peripheral configurations and clock generation, see the TMS320DM643x DMPUniversalAsynchronousReceiver/Transmitter(UART)User'sGuide(literaturenumberSPRU997). 3.4.1.4.3 SPIBoot Both 16-bit address SPI Boot (BOOTMODE = 0110) and 24-bit address SPI boot are performed through theMcBSP0peripheral.ThebootloaderprogramstheMcBSP0peripheralasfollows: • McBSP0registersettings:SRGR.CLKGDV=2 10 • ResultinginthisSPIserialclockfrequency: – (SYSCLK3frequencyinMHz)/3 SYSCLK3 frequency = SYSCLK1 frequency / 6. SYSCLK1 frequency during boot can be found in Table3-5,Table3-6,Table3-7,and/orTable3-8basedonthebootmodeselection. For example, if BOOTMODE[3:0] = 0110b, FASTBOOT = 1, the MXI/CLKIN frequency = 27 MHz, AEM[2:0] = 000b, PLLMS[2:0] = 100b, the combination of Table 3-7 and Table 3-8 indicates that the device frequency (SYSCLK1) is CLKIN x 22 / 2 = 297 MHz. This means SYSCLK3 frequency is 297/6=49.5MHz,resultinginSPIserialclockfrequencyof49.5/3=16.5MHz. 3.4.1.5 HostBootModes TheDM6435supportsHPIBoot. TheHPIBootisavailableinfastbootandnon-fastboot,asshowninTable3-5,Table3-6,andTable3-7. Note: the HPI HSTROBE inactive pulse duration timing requirement [t ] is dependent on the HPI w(HSTBH) internal clock source (SYSCLK3) frequency (see Section 6.13.3, HPI Electrical Data/Timing). The external host must be aware of the SYSCLK3 frequency during boot to ensure the HSTROBE pulse duration timingrequirementismet. 3.4.2 Bootmode Registers 3.4.2.1 BOOTCFGRegister The Device Bootmode (see Section 3.4.1, Boot Modes) and Configuration pins (see Section 3.5.1, Device and Peripheral Configurations at Device Reset) latched at reset are captured in the Device Boot Configuration (BOOTCFG) register which is accessible through the System Module. This is a read-only register. The bits show the values latched from the corresponding configuration pins sampled at device reset. For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching Boot and Configuration Pins. For the corresponding device boot and configuration pins, see Table 2-5, BOOTTerminalFunctions. 74 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 31 20 19 18 17 16 RESERVED FASTBOOT RESERVED R-000000000001 R-L R-000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSV PLLMS RSV DAEM RESERVED BOOTMODE R-0 R-LLL R-0 R-LLL R-0000 R-LLLL LEGEND:R=Readonly;L=pinstatelatchedatresetrisingedge;-n=valueafterreset Figure3-3.BOOTCFGRegister—0x01C40014 Table3-9.BOOTCFGRegisterDescription Bit FieldName Description 31:20 RESERVED Reserved.Writeshavenoeffect. Fastboot(seeSection3.4.1.1,FASTBOOT) ThisfieldisusedbythedevicebootloadercodetodetermineifitneedstospeedupthedevicetoPLLmode beforebooting. 19 FASTBOOT 0=NoFastboot 1=Fastboot ThedefaultvalueislatchedfromFASTBOOTconfigurationpin. 18:15 RSV Reserved.Writeshavenoeffect. PINMUX0.AEAWdefault[AEAW]andFastbootPLLMultiplierSelect[PLLMS](seeSection3.5.1.2,EMIFA AddressWidthSelect[AEAW]andFastBootPLLMultiplierSelect[PLLMS]) TheAEAW[2:0]/PLLMSconfigurationpinsservetwopurposes: AEAW[2:0]:8-bitEMIFA(Async)PinoutMode1AddressWidth IfAEM=001,thisfieldservesasAEAWanditindicatesthe8-bitEMIFA(Async)PinoutMode1Address Width.Inthiscase,thisfieldaffectspinmuxcontrolonlybysettingthedefaultofPinMuxControlRegister 14:12 PLLMS PINMUX0.AEAW[2:0].ThisfielddoesnotaffectEMIFAregistersettings. FormoredetailsontheAEAWsettings,seeSection3.7.2.1,PINMUX0RegisterDescription. PLLMS:FastbootPLLMultiplierSelect IfFASTBOOT=1andAEM[2:0]=000bor101b,thisfieldselectstheFASTBOOTPLLMultiplier.Inthiscase, thisfielddoesnotaffectthepinmuxcontrolortheEMIFAregistersettings.Thebootloadercodeusesthisfield todeterminethePLLmultiplierusedforFastboot. 11 RSV Reserved.Writeshavenoeffect. PINMUX0.AEMdefault[DAEM](seeSection3.5.1.1,EMIFAPinoutMode(AEM[2:0])) FormoredetailsontheAEMsettings,seeSection3.7.2.1,PINMUX0RegisterDescription. 10:8 DAEM This field affects pin mux control by setting the default of PINMUX0.AEM. This field does not affect EMIFA Registersettings. ThedefaultvalueislatchedfromtheAEM[2:0]configurationpins. 7:4 RESERVED Reserved.Writeshavenoeffect. BootMode(seeSection3.4.1,BootModes) 3:0 BOOTMODE ThisfieldisusedinconjunctionwithFASTBOOT,AEM,andPLLMStodeterminethedevicebootmode. ThedefaultvalueislatchedfromtheBOOTMODE[3:0]configurationpins. SubmitDocumentationFeedback DeviceConfiguration 75

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.4.2.2 BOOTCMPLTRegister If the bootloader code detects an error during boot, it records the error status in the Boot Complete (BOOTCMPLT)register. In addition, the BOOTCMPLT register is used for communication between the external host and the bootloader code during a Host Boot (HPI Boot). Once the external host has completed boot, it must performthefollowingcommunicationwiththebootloadercode: • Write the desired 32-bit CPU starting address in the DSPBOOTADDR register (see Section 3.4.2.3, DSPBOOTADDRRegister). • Write a ‘1’ to the Boot Complete (BC) bit field in the BOOTCMPLT register to indicate that the host has completedbootingthisdevice. Once the bootloader code detects BC = 1, it directs the CPU to begin executing from the DSPBOOTADDRregister. The BOOTCMPLT register is reset by any device-level global reset. For the list of device-level global resets,seeSection6.5,Reset. 31 20 19 16 RESERVED ERR R/W-000000000000 R/W-0000 15 1 0 RESERVED BC R/W-000000000000000 R/W-0 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-4.BOOTCMPLTRegister—0x01C4000C Table3-10.BOOTCMPLTRegisterDescription Bit FieldName Description 31:20 RESERVED Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothesebits. BootError 0000=NoError(default). 19:16 ERR 0001-1111=bootloadersoftwaredetectedabooterrorandabortedtheboot.Fortheerrorcodes,seethe UsingtheTMS320DM643xDMPBootloaderApplicationReport(literaturenumberSPRAAG0). 15:1 RESERVED Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothesebits. BootCompleteFlagfromHost ThisfieldisonlyapplicabletoHostBoots. 0 BC 0=Hosthasnotcompletedbootingthisdevice(default). 1=Hosthascompletedbootingthisdevice.DSPcanbeginexecutingfromtheDSPBOOTADDRregister value. 76 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.4.2.3 DSPBOOTADDRRegister The DSP Boot Address (DSPBOOTADDR) register contains the starting address for the C64x+ CPU. Whenever the C64x+ is released from reset, it begins executing from the location pointed to by DSPBOOTADDR register. For Host boots (HPI Boot), the DSPBOOTADDR register is also used for communicationbetweentheHostandthebootloadercodeduringboot. The DSPBOOTADDR register is reset by any device-level global reset. For the list of device-level global resets,seeSection6.5,Reset. 31 0 DSPBOOTADDR R/W-0x00100000or0x420000000 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-5.DSPBOOTADDRRegister—0x01C40008 Table3-11.DSPBOOTADDRRegisterDescription Bit FieldName Description DSPBootAddress Afterboot,theC64x+CPUbeginsexecutionfromthis32-bitaddresslocation.Thelower10bits (bits9:0)shouldalwaysbeprogrammedto"0"astheyareignoredbytheC64x+.Thedefault valueoftheDSPBOOTADDRdependsonthebootmodeselected. 31:0 DSPBOOTADDR TheDSPBOOTADDRdefaultsto0x00100000whentheInternalBootloaderROMisused. or TheDSPBOOTADDRdefaultsto0x42000000whenEMIFACS2Spaceisused. Forthebootmodeselections,seeTable3-5,Non-FastbootModes;Table3-6,Fixed-Multiplier FastbootModes;andTable3-7,User-SelectMultiplierFastbootModes. ForNon-HostBootModes,softwarecanleavetheDSPBOOTADDRregisteratdefault. For Host Boots (HPI Boot), the DSPBOOTADDR register is also used for communication between the Host and the bootloader code during boot. For Host Boots, the DSPBOOTADDR register defaults to Internal Bootloader ROM, and the C64x+ CPU is immediately released from reset so that it can begin executing the bootloader code in this internal ROM. The bootloader code waits for the Host to boot the device. Once the Host is done booting the device, it must write a new starting address into the DSPBOOTADDR register, and follow with writing BOOTCMPLT.BC = 1 to indicate the boot is complete. As soon as the bootloader code detects BOOTCMPLT.BC = 1, it instructs the CPU to jump to this new DSPBOOTADDR address. At this point, the CPU continues the rest of the code execution starting from thenewDSPBOOTADDRlocationandthebootiscompleted. SubmitDocumentationFeedback DeviceConfiguration 77

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.5 Configurations At Reset Somedeviceconfigurationsaredeterminedatreset.Thefollowingsubsectionsgivemoredetails. 3.5.1 Device and Peripheral Configurations at Device Reset Table2-5,BOOTTerminalFunctionsliststhedeviceboot and configuration pins that are latched at device reset for configuring basic device settings for proper device operation. Table 3-12, summarizes the device bootandconfigurationpins,andthedevicefunctionsthattheyaffect. Table3-12.DefaultFunctionsAffectedbyDeviceBootandConfigurationPins DEVICEBOOTAND CONFIGURATION BOOTSELECTED PINMUXCONTROL GLOBALSETTING PERIPHERALSETTING PINS(1) BOOTMODE[3:0] BootMode PINMUX0/PINMUX1 I/OPinPower: PSC/Peripherals: Registers: Basedon Basedon Basedon BOOTMODE[3:0],the BOOTMODE[3:0],the BOOTMODE[3:0],the bootloadercodeprograms bootloadercodeprograms bootloadercodeprograms VDD3P3V_PWDNregister thePSCtoput PINMUX0andPINMUX1 topoweruptheI/Opins boot-relatedperipheral(s) registerstoselectthe requiredforboot. intheEnableState,and appropriatepinfunctions programstheperipheral(s) requiredforboot. forbootoperation. FASTBOOT Fastboot – SetsDeviceFrequency: – BasedonBOOTMODE, FASTBOOT,PLLMS,and AEMthebootloadercode programsPLLC1. AEAW[2:0]/PLLMS[2:0] IfFASTBOOT=1and PINMUX0.AEAW: SetsDeviceFrequency: – AEM=000bor101bthe AEAW[2:0]setsthe BasedonBOOTMODE, PLLMS[2:0]selectsthe defaultofthisfieldto FASTBOOT,PLLMS,and FASTBOOTPLL controltheEMIFA AEMthebootloadercode Multiplier. addressbuswidth(only programsPLLC1. applicableif PINMUX0.AEM=001b). Affectsthepinmuxingin EMIFA/VPSSSub-Block 0. AEM[2:0] TogetherwithFASTBOOT PINMUX0.AEM: SetsDeviceFrequency: PSC/EMIFA: andPLLMS[2:0], Setsthedefaultofthis BasedonBOOTMODE, TheEMIFAmodulestate determinesthe fieldtocontroltheEMIFA FASTBOOT,PLLMS,and defaultstoSwRstDisable FASTBOOTPLL PinoutMode. AEMthebootloadercode ifAEM=0;otherwise,the Multiplier. programsPLLC1. EMIFAmodulestate Affectsthepinmuxingin defaultstoEnable. EMIFA/VPSSSub-Block 0,1,and3. (1) SoftwarecanmodifyallPINMUX0andPINMUX1bitfieldsfromtheirdefaults. For proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. For discussion situations where external pullup/pulldown resistors are required, see Section3.9.1,Pullup/PulldownResistors. Note: All DM6435 configuration inputs (BOOTMODE[3:0], FASTBOOT, AEAW[2:0]/PLLMS[2:0] and AEM[2:0]) are multiplexed with other functional pins. These pins function as device boot and configuration pins only during device reset. The user must take care of any potential data contention in the system. To help avoid system data contention, the DM6435 puts these configuration pins into a high-impedance state (Hi-Z) when device reset (RESET or POR) is asserted, and continues to hold them in a high-impedance state until the internal global reset is removed; at which point, the default peripheral (either GPIO or EMIFAbasedondefaultofAEM[2:0])willnowcontrolthesepins. All of the device boot and configuration pin settings are captured in the corresponding bit fields in the BOOTCFGregister(seeSection3.4.2.1). 78 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 The following subsections provide more details on the device configurations determined at device reset: AEMandAEAW/PLLMS. 3.5.1.1 EMIFAPinoutMode(AEM[2:0]) To support different usage scenarios, the DM6435 provides intricate pin multiplexing between the EMIFA and other peripherals. The PINMUX0.AEM register bit field in the System Module determines the EMIFA Pinout Mode. The AEM[2:0] pins only select the default EMIFA Pinout Mode. It is latched at device reset de-assertion (high) into the BOOTCFG.DAEM bit field. The AEM[2:0] value also sets the default of the PINMUX0.AEM bit field. While the BOOTCFG.DAEM bit field shows the actual latched value and cannot bemodified,thePINMUX0.AEMvaluecanbechangedbysoftwaretomodifytheEMIFAPinoutMode. Note: The AEM[2:0] value does not affect the operation of the EMIFA module itself. It only affects which EMIFA pins are brought out to the device pins. For more details on the AEM settings, see Section 3.7, MultiplexedPinConfigurations. In addition, for Fastboot modes (FASTBOOT = 1), the bootloader code determines the PLL1 multiplier based on the default settings of AEM[2:0] and PLLMS[2:0]. For more details, see Section 3.4.1.1, Fastboot, and Section 3.5.1.2, EMIFA Address Width Select (AEAW) and FASTBOOT PLL Multiplier Select(PLLMS). 3.5.1.2 EMIFAAddressWidthSelect(AEAW)andFASTBOOTPLLMultiplierSelect(PLLMS) The AEAW[2:0]/PLLMS[2:0] pins serve two functional purposes (AEAW or PLLMS), depending on the FASTBOOT and AEM settings. The AEAW[2:0]/PLLMS[2:0] pins are latched at device reset de-assertion (high) and captured in the BOOTCFG.PLLMS bit field. This value also sets the default of the PINMUX0.AEAWfield. While the BOOTCFG.PLLMS field shows the actual latched value and cannot be modified, the PINMUX0.AEAWvaluecanbechangedbysoftwaretomodifytheEMIFApinout. AEAWasEMIFAAddressWidthSelect(AEAW) If AEM[2:0] = 001b [8-bit EMIFA (Async) Pinout Mode 1], the AEAW[2:0]/PLLMS[2:0] pins serve as AEAW tosetthedefaultoftheEMIFAAddressWidthSelection. WhenEMIFAisusedinthe8-bitEMIFA(Async)PinoutMode1(PINMUX0.AEM=001b),theuserhas the option to determine how many address pins are needed. The unused address pins can be used as general-purpose input/output (GPIO) pins or extra data pins for VPFE. For more details on how the AEAW settings control the exact pin out when AEM = 001b, see Section 3.7.3.11, EMIFA/VPSS Block Muxing. For other EMIFA Pinout Modes (AEM not 001b), AEAW is not applicable in determining the EMIFA addresswidth. Note: AEAW[2:0] value does not affect the operation of the EMIFA module itself. It only affects which of theEMIFAaddressbitsarebroughtouttothedevicepins. AEAWasFastBootPLLMultiplierSelect(PLLMS) If FASTBOOT = 1, and AEM[2:0] = 000b [No EMIFA] or 101b [8-bit EMIFA (NAND) Pinout Mode 5], the AEAW[2:0]/PLLMS[2:0]pinsserveasPLLMStoselectPLLmultiplierforFastbootmodes. For more information on boot modes and the FASTBOOT PLL multiplier selection, see Section 3.4.1, Boot Modes. SubmitDocumentationFeedback DeviceConfiguration 79

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.6 Configurations After Reset Thefollowingsectionsprovidedetailsonconfiguringthedeviceafterreset. Multiplexed pins are configured both at and after reset. Section 3.5.1, Device and Peripheral ConfigurationsatDeviceReset,discussesmultiplexedpincontrolatreset.Formoredetailson multiplexed pinscontrolafterreset,seeSection3.7,MultiplexedPinConfigurations. 3.6.1 Switch Central Resource (SCR) Bus Priorities Prioritization within the Switched Central Resource (SCR) is programmable for each master. The register bitfieldsanddefaultprioritylevelsforDM6435busmastersareshowninTable3-13,DM6435DefaultBus MasterPriorities.Theprioritylevelsshouldbetunedto obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registersareshowninFigure3-6and Figure 3-7. The C64x+, VPSS, and EDMA masters contain registers thatcontroltheirownpriorityvalues. Table3-13.DM6435DefaultBusMasterPriorities PriorityBitField BusMaster DefaultPriorityLevel VPSSP VPSS 0(VPSSPCRRegister) EDMATC0P EDMATC0 0(EDMACCQUEPRIRegister) EDMATC1P EDMATC1 0(EDMACCQUEPRIRegister) EDMATC2P EDMATC2 0(EDMACCQUEPRIRegister) C64X+_DMAP C64X+(DMA) 7(C64x+MDMAARBE.PRIfield) C64X+_CFGP C64X+(CFG) 1(MSTPRI0Register) EMACP EMAC 4(MSTPRI1Register) VLYNQP VLYNQ 4(MSTPRI1Register) HPIP HPI 4(MSTPRI1Register) 31 16 RESERVED R-0000000000000000 15 11 10 9 8 7 0 RESERVED C64X+_CFGP RESERVED R-00000 R/W-001 R-00000000 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-6.MSTPRI0Register—0x01C4003C 80 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-14.MSTPRI0RegisterDescription Bit FieldName Description 31:11 RESERVED Reserved.Read-only,writeshavenoeffect. C64X+_CFGmasterportpriorityinSystemInfrastructure. 000=Priority0(Highest) 100=Priority4 10:8 C64X+_CFGP 001=Priority1 101=Priority5 010=Priority2 110=Priority6 011=Priority3 111=Priority7(Lowest) 7:0 RESERVED Reserved.Read-only,writeshavenoeffect. 31 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED RSV RSV HPIP RSV VLYNQP R-00000 R/W-100 R-0 R/W-100 R-0 R/W-100 15 3 2 1 0 RESERVED EMACP R-0000000000000 R/W-100 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-7.MSTPRI1Register—0x01C40040 Table3-15.MSTPRI1RegisterDescription Bit FieldName Description 31:27 RESERVED Reserved.Read-only,writeshavenoeffect. Reserved.Forproperdeviceoperation,theusermustonlywrite"100"to 26:24 RSV thesebits. 23 RSV Reserved.Read-only,writeshavenoeffect. HPImasterportpriorityinSystemInfrastructure. 000=Priority0(Highest) 100=Priority4 22:20 HPIP 001=Priority1 101=Priority5 010=Priority2 110=Priority6 011=Priority3 111=Priority7(Lowest) 19 RSV Reserved.Read-only,writeshavenoeffect. VLYNQmasterportpriorityinSystemInfrastructure. 000=Priority0(Highest) 100=Priority4 18:16 VLYNQP 001=Priority1 101=Priority5 010=Priority2 110=Priority6 011=Priority3 111=Priority7(Lowest) 15:3 RESERVED Reserved.Read-only,writeshavenoeffect. EMACmasterportpriorityinSystemInfrastructure. 000=Priority0(Highest) 100=Priority4 2:0 EMACP 001=Priority1 101=Priority5 010=Priority2 110=Priority6 011=Priority3 111=Priority7(Lowest) SubmitDocumentationFeedback DeviceConfiguration 81

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.6.2 Peripheral Selection After Device Reset After device reset, most peripheral configurations are done within the peripheral’s registers. This section discusses some additional peripheral controls in the System Module. For information on multiplexed pin controls that determine what peripheral pins are brought out to the pins, see Section 3.7, Multiplexed Pin Configurations. 3.6.2.1 HPIControlRegister(HPICTL) The HPI Control (HPICTL) register determines the Host Burst Write Time-Out value. The user should only modify this register once during device initialization. When modifying this register, the user mustensuretheHPIFIFOsareemptyandtherearenoon-goingHPItransactions. 31 16 RESERVED R-0000000000000000 15 10 9 8 7 0 RESERVED RESERVED TIMOUT R-000000 R/W-00 R/W-10000000 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-8.HPICTLRegister—0x01C40030 Table3-16.HPICTLRegisterDescription Bit FieldName Description 31:10 RESERVED Reserved.Read-only,writeshavenoeffect. 9:8 RESERVED Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothesebits(default). HostBurstWriteTimeoutValue WhentheHPItime-outcounterreachesthevalueprogrammedhere,theHPIwriteFIFOcontentisflushed.For 7:0 TIMOUT moredetailsonthetime-outcounteranditsuseinwritebursting,seetheTMS320DM643xDMPHostPort Interface(HPI)User'sGuide(literaturenumberSPRU998). 3.6.2.2 TimerControlRegister(TIMERCTL) The Timer Control Register (TIMERCTL) provides additional control for Timer0 and Timer2. The user should only modify this register once during device initialization, when the corresponding Timer is notinuse. • Timer2Control:TheTIMERCTL.WDRSTbitdeterminesiftheWatchDogtimerevent(Timer2)can causeadevicemaxreset.Formoredetailsonthedescriptionofamaximumreset,seeSection6.5.3, MaximumReset. • Timer0Control:TheTINP0SELbitselectstheclocksourceconnectedtoTimer0'sTIN0input. 31 16 RESERVED R-0000000000000000 15 2 1 0 TINP0 WD RESERVED SEL RST R-00000000000000 R/W-0 R/W-1 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-9.TIMERCTLRegister—0x01C40084 82 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-17.TIMERCTLRegisterDescription Bit FieldName Description 31:2 RESERVED Reserved.Read-Only,writeshavenoeffect. Timer0ExternalInput(TIN0)Select 0=Timer0externalinputcomesdirectlyfromtheTINP0Lpin(default). 1 TINP0SEL 1=Timer0externalinputisTINP0Lpindividedby6.Forexample,ifTINP0L=27MHz,Timer0inputTIN0is 27MHz/6=4.5MHz. WatchDogResetEnable 0 WDRST 0=WatchDogTimerEvent(WDINTfromTimer2)doesnotcausedevicereset. 1=WatchDogTimerEvent(WDINTfromTimer2)causesadevicemaxreset(default). 3.6.2.3 EDMATCConfigurationRegister(EDMATCCFG) The EDMA Transfer Controller Configuration (EDMATCCFG) register configures the default burst size (DBS) for EDMA TC0, EDMA TC1, and EDMA TC2. For more information on the correct usage of DBS, see the TMS320DM643x DMP Enhanced Direct Memory Access (EDMA) Controller User's Guide (literature number SPRU987). The user should only modify this register once during device initializationandwhenthecorrespondingEDMATCisnotinuse. 31 16 RESERVED R-0000000000000000 15 6 5 4 3 2 1 0 RESERVED TC2DBS TC1DBS TC0DBS R-0000000000 R/W-10 R/W-01 R/W-00 LEGEND:R=Read;W=Write;-n=valueafterreset Figure3-10.EDMATCCFGRegister—0x01C40088 Table3-18.EDMATCCFGRegisterDescription Bit Field Description 31:6 RESERVED Reserved.Read-Only,writeshavenoeffect. EDMATC2DefaultBurstSize 00=16byte 01=32byte 5:4 TC2DBS 10=64byte(default) 11=reserved EDMATC2isintendedformiscellaneoustransfers. TC2FIFOsizeis128bytes,regardlessofDefaultBurstSizesetting. EDMATC1DefaultBurstSize 00=16byte 01=32byte(default) 3:2 TC1DBS 10=64byte 11=reserved EDMATC1isintendedforhighthroughputbulktransfers. TC1FIFOsizeis256bytes,regardlessofDefaultBurstSizesetting. EDMATC0DefaultBurstSize 00=16byte(default) 01=32byte 1:0 TC0DBS 10=64byte 11=reserved EDMATC0isintendedforshortbursttransferswithstringentdeadlines(e.g.,McBSP,McASP). TC0FIFOsizeis128bytes,regardlessofDefaultBurstSizesetting. SubmitDocumentationFeedback DeviceConfiguration 83

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7 Multiplexed Pin Configurations DM6435 makes extensive use of pin multiplexing to accommodate a large number of peripheral functions inthesmallestpossiblepackage,providingultimateflexibilityforendapplications. The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsible for controlling all pin multiplexing functions on the DM6435. The default setting of some of the PINMUX0 and PINMUX1 bit fields are configured by configuration pins latched at reset (see Section 3.5.1, Device and Peripheral Configurations at Device Reset). After reset, software may program the PINMUX0 and PINMUX1 registers toswitchpinfunctionalities. The following peripherals have multiplexed pins: VPSS (VPFE), EMIFA, HPI, VLYNQ, EMAC, McASP0, McBSP0,PWM0,PWM1,PWM2,Timer0,Timer1,UART0,UART1,HECC,andGPIO. ThedeviceisdividedintothefollowingPinMultiplexedBlocks(PinMuxBlocks): • EMIFA/VPSSBlock:VPSS(VPFE),EMIFA,andGPIO.Thisblockisfurthersubdividedintothese sub-blocks: – Sub-Block0:VPFE(CCDC),partofEMIFA(addressandcontrol),andGPIO – Sub-Block1:partofEMIFA(data,address,control),andGPIO – Sub-Block2:partofEMIFA(controlsignalsEM_WAIT/(RDY/BSY),EM_OE,andEM_WE) – Sub-Block3:partofEMIFA(addressEM_A[12:5]),andGPIO • HostBlock:HPI,VLYNQ,EMAC,andGPIO • SerialPortBlock:McBSP0,McASP0,andGPIO.Thisblockisfurthersub-dividedintosub-blocks. – SerialPortSub-Block0:McBSP0,partofMcASP0,andGPIO – SerialPortSub-Block1:partofMcASP0andGPIO • UART0FlowControlBlock:UART0flowcontrol,PWM0,andGPIO • UART0DataBlock:UART0dataandGPIO • Timer0Block:Timer0andMcBSP0CLKSpins • Timer1Block:Timer1andHECC,UART1data • PWM1Block:PWM1andGPIO • CLKOUTBlock:CLKOUT0,PWM2,andGPIO As shown in the list above, the McBSP0 and UART0 peripherals span multiple Pin Mux Blocks. To use these peripherals, they must be selected in all relevant Pin Mux Blocks. For more details, see Section 3.7.3, Pin Multiplexing Details, and Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks. Note: there is no actual pin multiplexing in EMIFA/VPSS Sub-Block 2. However this is still considered a "pinmuxblock"becauseitcontainspartofthepinsnecessaryforEMIFA. A high level view of the Pin Mux Blocks is shown in Figure 3-11. In each Pin Mux Block, the PINMUX0/PINMUX1defaultsettingsareunderlined. Note: some default pin functions are determined by configuration pins (AEAW[2:0] and AEM[2:0]); therefore, more than one configuration setting can serve as default based on the configuration pin settings latchedatdevicereset. 84 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 (A) Host Block (27 pins) GPIO (27) HPI (26) VLYNQ VLYNQ EMAC (15) (10) (10) GPIO (1) MDIO GPIO (17) EMAC (15) (2) MDIO GPIO (10) (2) HOSTBK=000 HOSTBK=001 HOSTBK=010 HOSTBK=011 HOSTBK=100 PWM 1 Block (1 pin) CLKOUT Block (1 pin) GPIO PWM1 GPIO CLKOUT PWM2 (1) (1) (1) (1) (1) PWM1BK=0 PWM1BK=1 CKOBK=00 CKOBK=01 CKOBK=10 UART0 Data Block (2 pins) UART0 Flow Control Block (2 pins) UART UART0 PWM0 (1) GPIO (2) GPIO (2) Data (2) FlowCtrl (2) GPIO (1) UR0DBK=0 UR0DBK=1 UR0FCBK=00 UR0FCBK=01 UR0FCBK=10 (C) Timer1 Block (2 pins) Timer0 Block (2 pins) Timer1 UART1 HECC Timer0 McBSP0 GPIO (2) (2) Data (2) (2) GPIO (2) (2) CLKS0 (1) Timer0 TINPOL(1) TIM1BK=00 TIM1BK=01 TIM1BK=10 TIM1BK=11 TIM0BK=00 TIM0BK=01 TIM0BK=11 (C) Serial Port Sub-Block 0 (6 pins) Serial Port Sub-Block 1 (6 pins) McBSP0 GPIO (6) (6) McASP0 Receive GPIO (6) McASP0 and 3 Serializers (6) Transmit and 1 Serializer (6) SPBK0=00 SPBK0=01 SPBK0=10 SPBK1=00 SPBK1=10 (A)(B) EMIFA/VPSS Block (61 pins) 8b EMIFA (Async) 8b EMIFA Pinout (NAND) Mode 1 Pinout 32KB-16MB Mode 5 per CE 8-16b 8-16b 8-16b VPFE VPFE VPFE GPIO GPIO GPIO Major Config Major Config Major Config OptionA Option B Option E AEM=000 AEM=001 AEM=101 A. DefaultsettingsforPINMUX0andPINMUX1registersareunderlined. B. EMIFA/VPSS Block: shows the Major Config Options based on the AEM settings. Actual pin functions in the EMIFA/VPSSBlockarefurtherdeterminedbyotherPINMUXfields. C. McBSP0pinsspanmultipleblocks(SerialPortSub-Block0andTimer0Block).SerialPortSub-Block0containsmost ofthepinsneededforMcBSP0operation.Timer0BlockcontainstheoptionalexternalclocksourceinputCLKS0. Figure3-11.PinMuxBlockSelection SubmitDocumentationFeedback DeviceConfiguration 85

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.1 Pin Muxing Selection At Reset Thissectionsummarizespinmuxselectionatreset. The configuration pins AEM[2:0] and AEAW[2:0] latched at device reset determine default pin muxing for thefollowingPinMuxBlocks: • EMIFA/VPSS Block: default pin mux determined by AEM[2:0] and AEAW[2:0]. After reset, software maymodifysettingsinthePINMUX0registertoaddVPFEfunctionalitiesintothisblock. – AEM[2:0]=000b,AEAW[2:0]=don'tcare:MajorConfigOptionAisselected.Thisblockdefaultsto 61GPIOpins. – AEM[2:0]=001b,AEAW[2:0]=000bto100b:MajorConfigOptionBisselected.Thisblock defaultsto8-bitEMIFA(Async)PinoutMode1,plus24-to-32GPIOpins. – AEM[2:0]=101b,AEAW[2:0]=don'tcare:MajorConfigOptionEisselected.Thisblockdefaultsto 8-bitEMIFA(NAND)Pinoutmode5,plus47GPIOpins. For a description of the PINMUX0 and PINMUX1 registers and more details on pin muxing, see Section3.7.2,PinMuxingSelectionAfterReset. 3.7.2 Pin Muxing Selection After Reset The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions in the Pin Mux Blocks. The pin control of some of the Pin Mux Blocks requires a combination of PINMUX0/PINMUX1 bit fields. For more details on the combination of the PINMUX bit fields that control eachmuxedpin,seeSection3.7.3.1,MultiplexedPinsonDM6435. This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed discussiononhowtoprogrameachPinMuxBlock,seeSection3.7.3,PinMultiplexingDetails. 3.7.2.1 PINMUX0RegisterDescription The Pin Multiplexing 0 Register (PINMUX0) controls the pin function in the EMIFA/VPSS Block. The PINMUX0 register format is shown in Figure 3-12 and the bit field descriptions are given in Table 3-19. Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6435. For more information on EMIFA/VPSS Block pin muxing, see Section 3.7.3.11, EMIFA/VPSS Block Muxing. For the pin-by-pin muxing control of the EMIFA/VPSS Block, see Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-PinMultiplexingSummary. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFLDSE CWEN CCDCSE RSV CI10SEL RSV CI32SEL RSV CI54SEL CI76SEL HVDSEL RSV RSV AEAW L SEL L R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-LLL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CS3SEL CS4SEL CS5SEL RESERVED AEM R/W-0000 R/W-00 R/W-00 R/W-00 R/W-000 R/W-LLL LEGEND:R/W=Read/Write;R=Readonly;L=pinstatelatchedatresetrisingedge;-n=valueafterreset (1)ForproperDM6435deviceoperation,alwayswriteavalueof"0"toallRESERVED/RSVbits. Figure3-12.PINMUX0Register—0x01C40000(1) 86 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-19.PINMUX0RegisterDescription Bit FieldName Description PinsControlled Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 31 RSV (default). CI[1:0]FunctionSelect. Sub-Block0 0=NoCCDCCI[1:0]. CI1(CCD9)/EM_A[19]/GP[45] 30 CI10SEL PinsfunctionasGPIOorEMIFAbasedonAEMandAEAWsettings(default). CI0(CCD8)/EM_A[20]/GP[44] 1=SelectsCCDC[1:0](asCCD8andCCD9,respectively)togetatleasta10-bit ThecombinationofPINMUX0fieldsAEM, CCDC. AEAW,andCI10SELbitscontrolthepin Tousethe10-bitCCDC,theusermustalsoconfigurePINMUX0.CCDCSEL=1. muxingofthese2pins.(1) Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 29 RSV (default). CI[3:2]FunctionSelect. Sub-Block0 0=NoCCDCCI[3:2]. CI3(CCD11)/EM_A[17]/GP[47] PinsfunctionasGPIOorEMIFAbasedonAEMandAEAWsettings(default). 28 CI32SEL CI2(CCD10)/EM_A[18]/GP[46] 1=SelectsCCDC[3:2](asCCD10andCCD11,respectively)togetatleasta 12-bitCCDC. ThecombinationofPINMUX0fieldsAEM, Tousethe12-bitCCDC,theusermustalsoconfigurePINMUX0.CCDCSEL=1 AEAW,andCI32SELbitscontrolthepin andPINMUX0.CI10SEL=1. muxingofthese2pins.(1) Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 27 RSV (default). CI[5:4]FunctionSelect. Sub-Block0 0=NoCCDCCI[5:4]. CI5(CCD13)/EM_A[15]/GP[49] PinsfunctionasGPIOorEMIFAbasedonAEMandAEAWsettings(default). 26 CI54SEL CI4(CCD12)/EM_A[16]/GP[48] 1=SelectsCCDC[5:4](asCCD12andCCD13,respectively)togetatleasta 14-bitCCDC. ThecombinationofPINMUX0fieldsAEM, Tousethe14-bitCCDC,theusermustalsoconfigurePINMUX0.CCDCSEL=1, AEAW,andCI54SELbitscontrolthepin PINMUX0.CI10SEL=1,andPINMUX0.CI32SEL=1. muxingofthese2pins.(1) CI[7:6]FunctionSelect. Sub-Block0 0=NoCCDCCI[7:6]. CI7(CCD15)/EM_A[13]/GP[51] PinsfunctionasGPIOorEMIFAbasedonAEMandAEAWsettings(default). 25 CI76SEL CI6(CCD14)/EM_A[14]/GP[50] 1=SelectsCCDC[7:6](asCCD14andCCD15,respectively)togetatleasta 16-bitCCDC. ThecombinationofPINMUX0fieldsAEM, Tousethe16-bitCCDC,theusermustalsoconfigurePINMUX0.CCDCSEL=1, AEAW,andCI76SELbitscontrolthepin PINMUX0.CI10SEL=1,PINMUX0.CI32SEL=1,andPINMUX0.CI54SEL=1. muxingofthese2pins.(1) Sub-Block0 CCDCFieldSelect. C_FIELD/EM_A[21]/GP[34] 0=NoCCDCField(C_FIELD). 24 CFLDSEL PinfunctionsasEMIFAEM_A[21]orGPIObasedonAEMsetting(default). ThecombinationofPINMUX0/1fields CFLDSELandAEMcontrolthemuxingofthis 1=CCDCField(C_FIELD). pin.(1) CCDCWriteEnableSelect. Sub-Block0 0=NoCCDCWriteEnable. PinfunctionsasEMIFAEM_R/WorGPIObasedonAEMsetting(default). C_WE/EM_R/W/GP[35] 23 CWENSEL 1=CCDCWriteEnable(C_WE). ThecombinationofPINMUX0fieldsCWENSEL PinfunctionsasCCDCWriteEnableC_WE. andAEMcontrolthemuxingofthispin.(1) ApplicableonlyforAEM=0(000b)or5(101b). Sub-Block0 CCDCHDandVDSelect. VD/GP[53] 0=NoCCDCHDandVD. 22 HVDSEL HD/GP[52] PinsfunctionasGPIO(GP[53]andGP[52])(default). ThePINMUX0fieldHVDSELalonecontrolsthe 1=CCDCHDandVD. muxingofthese2pins. Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 21 RSV (default). (1) Forthefullsetofvalidconfigurationsofthesepins,seeSection3.7.3.11.7,EMIFA/VPSSBlockPin-By-PinMultiplexingSummary. SubmitDocumentationFeedback DeviceConfiguration 87

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-19.PINMUX0RegisterDescription (continued) Bit FieldName Description PinsControlled Sub-Block0 PCLK/GP[54] CCDCSelect. YI7(CCD7)/GP[43] ThisbitfielddeterminesifCCDCissupportedornot. YI6(CCD6)/GP[42] YI5(CCD5)/GP[41] 0=CCDCnotsupported. YI4(CCD4)/GP[40] 20 CCDCSEL PinsfunctionasGPIO(GP[54]andGP[43:36])(default). YI3(CCD3)/GP[39] YI2(CCD2)/GP[38] 1=CCDCsupported. YI1(CCD1)/GP[37] PinsfunctionasCCDCPCLK,YI[7:0]. YI0(CCD0)/GP[36] ThePINMUX0fieldCCDCSELalonecontrols themuxingofthese9pins. Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 19 RSV (default). 8-bitEMIFA(Async)PinoutMode1AddressWidthSelectorFastBootPLL MultiplierSelect Thisfieldservestwopurposes: 1. IfAEM=001b,thisfieldservesasthe8-bitEMIFA(Async)PinoutMode1 AddressWidthSelect. 2. IfFASTBOOT=1andAEM=0(000b)or5(101b),thisfieldservesasthe FastbootPLLMultiplierSelect. FastbootPLLMultiplierSelect:FormoredetailsontheAEAWpinfunctionsas FastbootPLLMultiplierSelect,seeSection3.4.1,Bootmodes. EMIFAAddressWidthSelect: 000b=EMIFA(Async)pinoutsupportsonlyEM_A[12:0]addresspins. Sub-Block0 EMIFA(Async)signalsEM_A[20:13]arenotpinnedout.PINMUXbitfields CI76SEL,CI54SEL,CI32SEL,andCI10SELdeterminethefunctionofthese8 CI7(CCD15)/EM_A[13]/GP[51] pins. CI6(CCD14)/EM_A[14]/GP[50] CI5(CCD13)/EM_A[15]/GP[49] 001b=EMIFA(Async)pinoutsupportsonlyEM_A[14:0]addresspins. CI4(CCD12)/EM_A[16]/GP[48] 18:16 AEAW(1) EmMuIsFtAbe(Apsryongcr)amsigmneadlstoEM0._A[14:13]arepinnedout.PINMUX0bitfieldCI76SEL CCII32((CCCCDD1110))//EEMM__AA[[1178]]//GGPP[[4476]] EMIFA(Async)signalsEM_A[20:15]arenotpinnedout.PINMUX0bitfields CI1(CCD9)/EM_A[19]/GP[45] CI54SEL,CI32SEL,andCI10SELdeterminethefunctionofthese6pins. CI0(CCD8)/EM_A[20]/GP[44] 010b=EMIFA(Async)pinoutsupportsonlyaddresspinsEM_A[16:0]. ThecombinationofPINMUX0fieldsAEM, EMIFA(Async)signalsEM_A[16:13]arepinnedout.PINMUX0bitfieldsCI76SEL AEAW,CI10SEL,CI32SEL,CI54SEL,and andCI54SELmustbeprogrammedto0. CI76SELcontrolthemuxingofthese8pins.(2) EMIFA(Async)signalsEM_A[20:17]arenotpinnedout.PINMUX0bitfields CI32SELandCI10SELdeterminethefunctionofthese4pins. 011b=EMIFA(Async)pinoutsupportsonlyaddresspinsEM_A[18:0]. EMIFA(Async)signalsEM_A[18:13]arepinnedout.PINMUX0bitfields CI76SEL,CI54SEL,andCI32SELmustbeprogrammedto0. EMIFA(Async)signalsEM_A[20:19]arenotpinnedout.PINMUX0bitfield CI10SELdeterminesthefunctionofthese2pins. 100b=EMIFA(Async)pinoutsupportsaddresspinsEM_A[20:0]. EMIFA(Async)signalsEM_A[20:13]arepinnedout.PINMUX0bitfields CI76SEL,CI54SEL,CI32SEL,andCI10SELmustbeprogrammedto0. 101bthrough111b=Reserved. Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothesebits 15:12 RESERVED (default). ChipSelect3Select. Sub-Block1 00=GPIOpin(GP13)(default) EM_CS3/GP[13] 11:10 CS3SEL 01=EMIFAChipSelect3(EM_CS3) ThePINMUX0fieldCS3SELalonecontrolsthe 10=Reserved muxingofthispin. 11=Reserved (1) TheAEAWdefaultvalueislatchedatresetfromAEAW[2:0]configurationinputs.Thelatchedvaluesarealsoshownat BOOTCFG.PLLMS(read-only). (2) Forthefullsetofvalidconfigurationsofthesepins,seeSection3.7.3.11.7,EMIFA/VPSSBlockPin-By-PinMultiplexingSummary. 88 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-19.PINMUX0RegisterDescription (continued) Bit FieldName Description PinsControlled ChipSelect4Select. Sub-Block1 00=GPIOpin(GP32)(default) EM_CS4/GP[32] 9:8 CS4SEL 01=EMIFAChipSelect4(EM_CS4) ThePINMUX0fieldCS4SELalonecontrolsthe 10=Reserved muxingofthispin. 11=Reserved ChipSelect5Select. Sub-Block1 00=GPIOpin(GP33)(default) EM_CS5/GP[33] 7:6 CS5SEL 01=EMIFAChipSelect5(EM_CS5) ThePINMUX0fieldCS5SELalonecontrolsthe 10=Reserved muxingofthispin. 11=Reserved Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothesebits 5:3 RESERVED (default). Sub-Block0 C_WE/EM_R/W/GP[35] C_FIELD/EM_A[21]/GP[34] CI7(CCD15)/EM_A[13]/GP[51] CI6(CCD14)/EM_A[14]/GP[50] CI5(CCD13)/EM_A[15]/GP[49] CI4(CCD12)/EM_A[16]/GP[48] CI3(CCD11)/EM_A[17]/GP[47] CI2(CCD10)/EM_A[18]/GP[46] CI1(CCD9)/EM_A[19]/GP[45] CI0(CCD8)/EM_A[20]/GP[44] EMIFAPinoutModes Sub-Block1 ThisfielddoesnotaffecttheactualEMIFAoperation.Itonlydetermineswhat multiplexedpinsintheEMIFA/VPSSBlockservesasEMIFApins. EM_D[7]/GP[21] EM_D[6]/GP[20] 000b=NoEMIFAMode. EM_D[5]/GP[19] NoneofthemultiplexedpinsintheEMIFA/VPSSBlockservesasEMIFApins. EM_D[4]/GP[18] 001b=8-bitEMIFA(Async)PinoutMode1. EM_D[3]/GP[17] (Upto16M-ByteaddressreachperChipSelectSpace). EM_D[2]/GP[16] PinoutallowsuptoamaximumofthesefunctionsfromEMIFA/VPSSBlock:8-bit EM_D[1]/GP[15] EMIFA(AsyncorNAND)+16-bitCCDC(VPFE) EM_D[0]/GP[14] 2:0 AEM(1) EM_CS2/GP[12] 010b=Reserved. EM_A[3]/GP[11] EM_A[4]/GP[10]/(AEAW2/PLLMS2) 011b=Reserved. EM_A[1]/(ALE)/GP[9]/(AEAW1/PLLMS1) EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0) 100b=Reserved. EM_A[0]/GP[7]/(AEM2) 101b=8-bitEMIFA(NAND)PinoutMode5. EM_BA[0]/GP[6]/(AEM1) PinoutallowsuptoamaximumofthesefunctionsfromEMIFA/VPSSBlock:8-bit EM_BA[1]/GP[5]/(AEM0) EMIFA(NAND)+16-bitCCDC(VPFE) Sub-Block3 110bthrough111b=Reserved. EM_A[12]/GP[89] EM_A[11]/GP[90] EM_A[10]/GP[91] EM_A[9]/GP[92] EM_A[8]/GP[93] EM_A[7]/GP[94] EM_A[6]/GP[95] EM_A[5]/GP[96] Thepinmuxforthesepinsarecontrolledbya combinationofAEMandotherPINMUX0fields, includingCWENSEL,CFLDSEL,AEAW, CI76SEL,CI54SEL,CI32SEL,andCI10SEL.(2) (1) TheAEMdefaultvalueislatchedatresetfromAEM[2:0]configurationinputs.ThelatchedvaluesarealsoshownatBOOTCFG.DAEM (read-only). (2) Forthefullsetofvalidconfigurationsofthesepins,seeSection3.7.3.11.7,EMIFA/VPSSBlockPin-By-PinMultiplexingSummary. SubmitDocumentationFeedback DeviceConfiguration 89

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.2.2 PINMUX1RegisterDescription The Pin Multiplexing 1 Register (PINMUX1) controls the pin multiplexing of all Pin Mux Blocks. The PINMUX1 register format is shown in Figure 3-13 and the bit field descriptions are given in Table 3-20. Some muxed pins are controlled by more than one PINMUX bit field. For the combination of PINMUX bit fieldsthatcontroleachmuxedpin,seeSection3.7.3.1,MultiplexedPinsonDM6435. 31 26 25 24 23 22 21 20 19 18 17 16 RESERVED SPBK1 SPBK0 TIM1BK RSV TIM0BK R/W-000000 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1B CKOBK RSV UR0FCBK RSV UR0DBK RSV HOSTBK RESERVED RSV K R/W-01 R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R/W-0 R/W-000 R/W-000 R-0 LEGEND:R/W=Read/Write;R=Readonly;P=specifiedpinstate;-n=valueafterreset (1)ForproperDM6435deviceoperation,alwayswriteavalueof"0"toallRESERVED/RSVbits. Figure3-13.PINMUX1Register—0x01C40004(1) Table3-20.PINMUX1RegisterDescription Bit FieldName Description PinsControlled Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 31:26 RESERVED – (default). SerialPortSub-Block1PinSelect. SelectsthefunctionofthemultiplexedpinsintheSerialPortSub-Block1. 00=GPIOMode(default). SerialPortSub-Block1: PinsfunctionasGPIO(GP[110:105]). AXR0[0]/GP[105] ACLKX0/GP[106] 25:24 SPBK1 01=Reserved. AFSX0/GP[107] AHCLKX0/GP[108] 10=McASP0Transmitand1serializer. AMUTEIN0/GP[109] PinsfunctionasMcASP0:AXR0[0],ACLKX0,AFSX0,AHCLKX0,AMUTEIN0, AMUTE0/GP[110] andAMUTE0. 11=Reserved. SerialPortSub-Block0PinSelect. SelectsthefunctionofthemultiplexedpinsintheSerialPortSub-Block0. 00=GPIOMode(default). SerialPortSub-Block0: PinsfunctionasGPIO(GP[104:99]). ACLKR0/CLKX0/GP[99] AFSR0/DR0/GP[100] 01=McBSP0Mode. 23:22 SPBK0 AHCLKR0/CLKR0/GP[101] PinsfunctionasMcBSP0CLKX0,FSX0,DX0,CLKR0,FSR0,andDR0. AXR0[3]/FSR0/GP[102] 10=McASP0Receiveand3serializers. AXR0[2]/FSX0/GP[103] PinsfunctionasMcASP0ACLKR0,AFSR0,AHCLKR0,AXR0_3,AXR0_2,and AXR0[1]/DX0/GP[104] AXR0_1. 11=Reserved Timer1BlockPinSelect. SelectsthefunctionofthemultiplexedpinsintheTimer1Block. 00=GPIOMode(default). PinsfunctionasGPIO(GP[56:55]). Timer1Block: 01=Timer1Mode. 21:20 TIM1BK HECC_RX/TINP1L/URXD1/GP[56] PinsfunctionasTimer1TINP1LandTOUT1L. HECC_TX/TOUT1L/UTXD1/GP[55] 10=UART1DataMode. PinsfunctionasUART1datapinsURXD1andUTXD1. 11=HECCMode. PinsfunctionasHECCHECC_RXandHECC_TX. Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 19:18 RSV – (default). 90 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-20.PINMUX1RegisterDescription (continued) Bit FieldName Description PinsControlled Timer0BlockPinSelect. SelectsthefunctionofthemultiplexedpinsintheTimer0Block. 00=GPIOMode(default). PinsfunctionasGPIO(GP[98:97]). Timer0Block: 01=Timer0Mode. 17:16 TIM0BK TINP0L/GP[98] PinsfunctionasTimer0TINP0LandTOUT0L. CLKS0/TOUT0L/GP[97] 10=Reserved. 11=McBSP0ExternalClockSource+Timer0InputMode. PinsfunctionasMcBSP0externalclocksourceCLKS0,andTimer0input TINP0L. CLKOUTBlockPinSelect. SelectsthefunctionofthemultiplexedpinsintheCLKOUTBlock. 00=GPIOMode. PinfunctionsasGPIO(GP[84]). CLKOUTBlock: 15:14 CKOBK 01=CLKOUTMode(default). CLKOUT0/PWM2/GP[84] PinfunctionsasdeviceclockoutputCLKOUT0,sourcedfromPLLC1OBSCLK. 10=PWM2Mode. PinfunctionsasPWM2. 11=Reserved Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 13 RSV – (default). PWM1BlockPinSelect. SelectsthefunctionofthemultiplexedpinsinthePWM1Block. 0=GPIOMode(default). PWM1Block: 12 PWM1BK PinfunctionsasGPIO(GP[4]). GP[4]/PWM1 1=PWM1Mode. PinfunctionsasPWM1. UART0FlowControlBlockPinSelect. SelectsthefunctionofthemultiplexedpinsintheUART0FlowControlBlock. 00=GPIOMode(default). PinsfunctionasGPIO(GP[88:87]). UART0FlowControlBlock: 11:10 UR0FCBK 01=UART0FlowControlMode. UCTS0/GP[87] PinsfunctionasUART0FlowControlUCTS0andURTS0. URTS0/PWM0/GP[88] 10=PWM0+GPIOMode. PinsfunctionasPWM0andGPIO(GP[87]). 11=Reserved Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 9 RSV – (default). UART0DataBlockPinSelect. SelectsthefunctionofthemultiplexedpinsintheUART0DataBlock. UART0DataBlock: 0=GPIOMode(default). 8 UR0DBK URXD0/GP[85] PinsfunctionasGPIO(GP[86:85]). UTXD0/GP[86] 1=UART0DataMode. PinsfunctionasUART0dataURXD0andUTXD0. SubmitDocumentationFeedback DeviceConfiguration 91

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-20.PINMUX1RegisterDescription (continued) Bit FieldName Description PinsControlled Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 7 RSV – (default). HostBlock: VLYNQ_CLOCK/GP[57] HD0/VLYNQ_SCRUN/GP[58] HostBlockPinSelect. HD1/VLYNQ_RXD0/GP[59] IfEMACopertaionisdesired,EMACmustbeplacedinresetbefore HD2/VLYNQ_RXD1/GP[60] programminngPINMUX1HOSTBKtoselectEMACpins. HD3/VLYNQ_RXD2/GP[61] HD4/VLYNQ_RXD3/GP[62] HOSTBK=000:GPIOMode(default). HD5/VLYNQ_TXD0/GP[63] PinsfunctionasGPIO(GP[83:57]). HD6/VLYNQ_TXD1/GP[64] HOSTBK=001:HPI+1GPIOMode. HD7/VLYNQ_TXD2/GP[65] PinsfunctionasHPIandGPIO(GP[57]). HD8/VLYNQ_TXD3/GP[66] HD9/MCOL/GP[67] HOSTBK=010:VLYNQ+17GPIOMode. HD10/MCRS/GP[68] PinsfunctionasVLYNQ(VLYNQ_CLOCK,VLYNQ_SCRUN,VLYNQ_RXD[3:0], HD11/MTXD3/GP[69] 6:4 HOSTBK VLYNQ_TXD[3:0]),andGP[83:67]. HD12/MTXD2/GP[70] HD13/MTXD1/GP[71] HOSTBK=011:VLYNQ+MII+MDIOMode. HD14/MTXD0/GP[72] PinsfunctionasVLYNQ(VLYNQ_CLOCK,VLYNQ_SCRUN,VLYNQ_RXD[3:0], HD15/MTXCLK/GP[73] VLYNQ_TXD[3:0]),MII(TXCLK,CRS,COL,TXD[3:0],RXVD,TXEN,RXER, HHWIL/MRXDV/GP[74] RXCLK,RXD[3:0]),andMDIO(MDIO,MDC). HCNTL1/MTXEN/GP[75] HCNTL0/MRXER/GP[76] HOSTBK=100:MII+MDIO+10GPIOMode. HR/W/MRXCLK/GP[77] PinsfunctionasMII(TXCLK,CRS,COL,TXD[3:0],RXVD,TXEN,RXER, HDS2/MRXD0/GP[78] RXCLK,RXD[3:0]),MDIO(MDIO,MDC),andGP[66:57]. HDS1/MRXD1/GP[79] AllotherHOSTBKcombinationsreserved. HRDY/MRXD2/GP[80] HCS/MDCLK/GP[81] HINT/MRXD3/GP[82] HAS/MDIO/GP[83] Reserved.Forproperdeviceoperation,theusershouldonlywrite"0"tothisbit 3:1 RESERVED – (default). 0 RSV Reserved.Writeshavenoeffect. – 92 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.7.3 Pin Multiplexing Details ThissectiondiscusseshowtoprogrameachPinMuxBlocktoselectthedesiredperipheralfunctions. Thefollowingstepscanbeusedtodeterminepinmuxingsuitablefortheapplication: 1. Understandthemajorconfigurationchoicesavailableforthespecificapplication. a. DeviceMajorConfigurationChoices:Figure3-11showninSection3.7,MultiplexedPin Configurations,providesahigh-levelviewofthedevicepinmuxingandcanbeusedtodetermine thepossiblemixofperipheraloptionsforaspecificapplication. b. EMIFA/VPSSBlockMajorConfigurationChoices:TheEMIFA/VPSSblockfeaturesextensivepin multiplexingtoaccommodateavarietyofapplications.InadditiontoFigure3-11,Section3.7.3.11, EMIFA/VPSSBlockMuxing,providesmoredetailsontheMajorConfigurationchoicesforthis block. 2. SeeSection3.7.3.1,MultiplexedPinsonDM6435,forasummaryofallthemultiplexedpinsonthis deviceandthepinmuxgrouptheybelongto. 3. Refertotheindividualpinmuxsections(Section3.7.3.3,HostBlockMuxingtoSection3.7.3.11, EMIFA/VPSSBlockMuxing)forpinmuxingdetailsforaspecificpinmuxblock. a. Forperipheralsthatspanmultiplepinmuxblocks,theusermustselecttheappropriatepinsforthat peripheralinallrelevantpinmuxblocks.Formoredetails,seeSection3.7.3.2,Peripherals SpanningMultiplePinMuxBlocks. FordetailsonPINMUX0andPINMUX1registers,seeSection3.7.2. 3.7.3.1 MultiplexedPinsonDM6435 Table 3-21 summarizes all of the multiplexed pins on DM6435, the pin mux group for each pin, and the PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11, EMIFA/VPSS Block Muxing). For a description of thePINMUXregisterfields,seeSection3.7.2. Table3-21. MultiplexedPinsonDM6435 SIGNAL PINMUXDESCRIPTION ZWT ZDU NAME PINMUXGROUP CONTROLLEDBYPINMUXBITFIELDS NO. NO. PCLK/GP[54] A14 A18 EMIFA/VPSSSub-Block0 CCDCSEL VD/GP[53] A13 A17 EMIFA/VPSSSub-Block0 HVDSEL HD/GP[52] A15 A19 EMIFA/VPSSSub-Block0 HVDSEL CI7(CCD15)/EM_A[13]/GP[51] B10 A12 EMIFA/VPSSSub-Block0 AEM,AEAW,CI76SEL CI6(CCD14)/EM_A[14]/GP[50] A10 A13 EMIFA/VPSSSub-Block0 AEM,AEAW,CI76SEL CI5(CCD13)/EM_A[15]/GP[49] B11 C13 EMIFA/VPSSSub-Block0 AEM,AEAW,CI54SEL CI4(CCD12)/EM_A[16]/GP[48] C11 B13 EMIFA/VPSSSub-Block0 AEM,AEAW,CI54SEL CI3(CCD11)/EM_A[17]/GP[47] A11 B14 EMIFA/VPSSSub-Block0 AEM,AEAW,CI32SEL CI2(CCD10)/EM_A[18]/GP[46] D11 A14 EMIFA/VPSSSub-Block0 AEM,AEAW,CI32SEL CI1(CCD9)/EM_A[19]/GP[45] B12 C14 EMIFA/VPSSSub-Block0 AEM,AEAW,CI10SEL CI0(CCD8)/EM_A[20]/GP[44] C12 C15 EMIFA/VPSSSub-Block0 AEM,AEAW,CI10SEL YI7(CCD7)/GP[43] A12 A15 EMIFA/VPSSSub-Block0 CCDCSEL YI6(CCD6)/GP[42] B13 B15 EMIFA/VPSSSub-Block0 CCDCSEL YI5(CCD5)/GP[41] C13 B16 EMIFA/VPSSSub-Block0 CCDCSEL YI4(CCD4)/GP[40] D14 C18 EMIFA/VPSSSub-Block0 CCDCSEL YI3(CCD3)/GP[39] B14 A16 EMIFA/VPSSSub-Block0 CCDCSEL YI2(CCD2)/GP[38] C14 B17 EMIFA/VPSSSub-Block0 CCDCSEL YI1(CCD1)/GP[37] B15 B18 EMIFA/VPSSSub-Block0 CCDCSEL YI0(CCD0)/GP[36] C15 B19 EMIFA/VPSSSub-Block0 CCDCSEL SubmitDocumentationFeedback DeviceConfiguration 93

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-21. MultiplexedPinsonDM6435 (continued) SIGNAL PINMUXDESCRIPTION ZWT ZDU NAME PINMUXGROUP CONTROLLEDBYPINMUXBITFIELDS NO. NO. C_WE/EM_R/W/GP[35] D13 C17 EMIFA/VPSSSub-Block0 AEM,CWENSEL C_FIELD/EM_A[21]/GP[34] D12 C16 EMIFA/VPSSSub-Block0 AEM,CFLDSEL EM_CS5/GP[33] F19 J22 EMIFA/VPSSSub-Block1 CS5SEL EM_CS4/GP[32] E19 H22 EMIFA/VPSSSub-Block1 CS4SEL GP[31] D19 G22 EMIFA/VPSSSub-Block1 –(1) GP[30] G19 K22 EMIFA/VPSSSub-Block1 –(1) GP[29] H15 K21 EMIFA/VPSSSub-Block1 –(1) GP[28] H16 J21 EMIFA/VPSSSub-Block1 –(1) GP[27] H17 L19 EMIFA/VPSSSub-Block1 –(1) GP[26]/(FASTBOOT) G17 K19 EMIFA/VPSSSub-Block1 –(1) GP[25]/(BOOTMODE3) G16 H21 EMIFA/VPSSSub-Block1 –(1) GP[24]/(BOOTMODE2) G15 L20 EMIFA/VPSSSub-Block1 –(1) GP[23]/(BOOTMODE1) F15 K20 EMIFA/VPSSSub-Block1 –(1) GP[22]/(BOOTMODE0) F18 J20 EMIFA/VPSSSub-Block1 –(1) EM_D[7]/GP[21] F17 H20 EMIFA/VPSSSub-Block1 AEM EM_D[6]/GP[20] F16 F21 EMIFA/VPSSSub-Block1 AEM EM_D[5]/GP[19] E17 F22 EMIFA/VPSSSub-Block1 AEM EM_D[4]/GP[18] E18 G21 EMIFA/VPSSSub-Block1 AEM EM_D[3]/GP[17] E16 F20 EMIFA/VPSSSub-Block1 AEM EM_D[2]/GP[16] D17 E22 EMIFA/VPSSSub-Block1 AEM EM_D[1]/GP[15] D18 G20 EMIFA/VPSSSub-Block1 AEM EM_D[0]/GP[14] D16 E21 EMIFA/VPSSSub-Block1 AEM EM_CS3/GP[13] C18 D22 EMIFA/VPSSSub-Block1 CS3SEL EM_CS2/GP[12] C19 C22 EMIFA/VPSSSub-Block1 AEM EM_A[3]/GP[11] B18 D21 EMIFA/VPSSSub-Block1 AEM EM_A[4]/GP[10]/(AEAW2/PLLMS2) A17 B21 EMIFA/VPSSSub-Block1 AEM EM_A[1]/(ALE)/GP[9]/ A16 B20 EMIFA/VPSSSub-Block1 AEM (AEAW1/PLLMS1) EM_A[2]/(CLE)/GP[8]/ B16 A20 EMIFA/VPSSSub-Block1 AEM (AEAW0/PLLMS0) EM_A[0]/GP[7]/(AEM2) B17 C21 EMIFA/VPSSSub-Block1 AEM EM_BA[0]/GP[6]/(AEM1) C17 E20 EMIFA/VPSSSub-Block1 AEM EM_BA[1]/GP[5]/(AEM0) C16 C20 EMIFA/VPSSSub-Block1 AEM EM_A[12]/GP[89] D10 B12 EMIFA/VPSSSub-Block3 AEM EM_A[11]/GP[90] C10 C12 EMIFA/VPSSSub-Block3 AEM EM_A[10]/GP[91] A9 B11 EMIFA/VPSSSub-Block3 AEM EM_A[9]/GP[92] D9 C11 EMIFA/VPSSSub-Block3 AEM EM_A[8]/GP[93] B9 A11 EMIFA/VPSSSub-Block3 AEM EM_A[7]/GP[94] C9 C10 EMIFA/VPSSSub-Block3 AEM EM_A[6]/GP[95] D8 B10 EMIFA/VPSSSub-Block3 AEM EM_A[5]/GP[96] B8 A10 EMIFA/VPSSSub-Block3 AEM VLYNQ_CLOCK/GP[57] A7 A8 HostBlock HOSTBK HD0/VLYNQ_SCRUN/GP[58] C8 B9 HostBlock HOSTBK HD1/VLYNQ_RXD0/GP[59] D7 C9 HostBlock HOSTBK (1) GP[31:22]arestandalonepins.Theyarenotmuxedwithanyotherfunctions,buttheyareincludedinthistablebecausetheyare groupedintheEMIFA/VPSSSub-Block1. 94 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-21. MultiplexedPinsonDM6435 (continued) SIGNAL PINMUXDESCRIPTION ZWT ZDU NAME PINMUXGROUP CONTROLLEDBYPINMUXBITFIELDS NO. NO. HD2/VLYNQ_RXD1/GP[60] A8 A9 HostBlock HOSTBK HD3/VLYNQ_RXD2/GP[61] B7 B8 HostBlock HOSTBK HD4/VLYNQ_RXD3/GP[62] C7 C8 HostBlock HOSTBK HD5/VLYNQ_TXD0/GP[63] A6 A7 HostBlock HOSTBK HD6/VLYNQ_TXD1/GP[64] D6 C7 HostBlock HOSTBK HD7/VLYNQ_TXD2/GP[65] B6 B7 HostBlock HOSTBK HD8/VLYNQ_TXD3/GP[66] A5 A6 HostBlock HOSTBK HD9/MCOL/GP[67] C6 C6 HostBlock HOSTBK HD10/MCRS/GP[68] B5 B6 HostBlock HOSTBK HD11/MTXD3/GP[69] C5 A5 HostBlock HOSTBK HD12/MTXD2/GP[70] D5 C5 HostBlock HOSTBK HD13/MTXD1/GP[71] B4 B4 HostBlock HOSTBK HD14/MTXD0/GP[72] D4 B5 HostBlock HOSTBK HD15/MTXCLK/GP[73] A4 A4 HostBlock HOSTBK HHWIL/MRXDV/GP[74] C4 D3 HostBlock HOSTBK HCNTL1/MTXEN/GP[75] D3 C4 HostBlock HOSTBK HCNTL0/MRXER/GP[76] B3 B2 HostBlock HOSTBK HR/W/MRXCLK/GP[77] A3 A3 HostBlock HOSTBK HDS2/MRXD0/GP[78] C3 C2 HostBlock HOSTBK HDS1/MRXD1/GP[79] B2 B3 HostBlock HOSTBK HRDY/MRXD2/GP[80] D2 C3 HostBlock HOSTBK HCS/MDCLK/GP[81] C1 D1 HostBlock HOSTBK HINT/MRXD3/GP[82] C2 D2 HostBlock HOSTBK HAS/MDIO/GP[83] D1 C1 HostBlock HOSTBK GP[4]/PWM1 F3 F3 PWM1Block PWM1BK ACLKR0/CLKX0/GP[99] H1 J1 SerialPortSub-Block0 SPBK0 AFSR0/DR0/GP[100] H4 K3 SerialPortSub-Block0 SPBK0 AHCLKR0/CLKR0/GP[101] J2 K1 SerialPortSub-Block0 SPBK0 AXR0[3]/FSR0/GP[102] G4 J3 SerialPortSub-Block0 SPBK0 AXR0[2]/FSX0/GP[103] H3 J2 SerialPortSub-Block0 SPBK0 AXR0[1]/DX0/GP[104] J3 K2 SerialPortSub-Block0 SPBK0 AXR0[0]/GP[105] H2 H2 SerialPortSub-Block1 SPBK1 ACLKX0/GP[106] F1 G1 SerialPortSub-Block1 SPBK1 AFSX0/GP[107] G2 G2 SerialPortSub-Block1 SPBK1 AHCLKX0/GP[108] G1 H1 SerialPortSub-Block1 SPBK1 AMUTEIN0/GP[109] F2 G3 SerialPortSub-Block1 SPBK1 AMUTE0/GP[110] G3 H3 SerialPortSub-Block1 SPBK1 HECC_RX/TINP1L/URXD1/GP[56] L4 P3 Timer1Block TIM1BK HECC_TX/TOUT1L/UTXD1/GP[55] K4 N3 Timer1Block TIM1BK TINP0L/GP[98] K2 L2 Timer0Block TIM0BK CLKS0/TOUT0L/GP[97] J4 L3 Timer0Block TIM0BK URXD0/GP[85] L2 M2 UART0DataBlock UR0DBK UTXD0/GP[86] K3 N1 UART0DataBlock UR0DBK UCTS0/GP[87] L1 P1 UART0FlowControlBlock UR0FCBK URTS0/PWM0/GP[88] L3 M3 UART0FlowControlBlock UR0FCBK SubmitDocumentationFeedback DeviceConfiguration 95

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-21. MultiplexedPinsonDM6435 (continued) SIGNAL PINMUXDESCRIPTION ZWT ZDU NAME PINMUXGROUP CONTROLLEDBYPINMUXBITFIELDS NO. NO. CLKOUT0/PWM2/GP[84] M1 R1 CLKOUTBlock CKOBK Note: PINMUX group EMIFA/VPSS Sub-Block 2 is not shown in the above table because there is no actual pin multiplexing in that block. But this block is still considered a "pin mux block" because it contains someofthepinsnecessaryforEMIFA.Thepinsinthisblockareasfollows: • EMIFA/VPSSSub-Block2 – EM_WAIT/(RDY/BSY) – EM_OE – EM_WE 3.7.3.2 PeripheralsSpanningMultiplePinMuxBlocks Some peripherals span multiple Pin Mux Blocks. To use these peripherals, they must be selected in all of therelevantPinMuxBlocks.ThefollowingisthelistofperipheralsthatspanmultiplePinMuxBlocks: • McBSP0:SixMcBSP0pinsarelocatedintheSerialPortSub-Block0,buttheCLKS0pinismuxedin theTimer0Block.ToselectMcBSP0pins,programPINMUXregistersasfollows: – SerialPortSub-Block0:SPBK0=01 – Timer0Block:IfCLKS0pinisdesired,programTIM0BK=10or11. • UART0:ThetwoUART0datapinsarelocatedintheUART0DataBlock,butthetwoUART0flow controlpinsarelocatedintheUART0FlowControlBlock.ToselectUART0,programPINMUX registersasfollows: – UART0DataBlock:UR0BK=1 – UART0FlowControlBlock:Ifflowcontrolpinsaredesired,programUR0FCBK=01. 96 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.7.3.3 HostBlockMuxing This block of 27 pins consists of HPI, VLYNQ, EMAC, MDIO, and GPIO muxed pins. The following registerfieldselectsthepinfunctionsintheHostBlock: • PINMUX1.HOSTBK Table 3-22 summarizes the 27 pins in the Host Block, the multiplexed function on each pin, and the PINMUXconfigurationstoselectthecorrespondingfunction. SubmitDocumentationFeedback DeviceConfiguration 97

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-22.HostBlockMuxedPinsSelection MULTIPLEXEDFUNCTIONS SIGNALNAME HPI EMAC/MDIO VLYNQ GPIO FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT HOSTBK=000 or VLYNQ_CLOCK/GP[57] – – – – VLYNQ_CLOCK GP[57] HOSTBK=001 or HOSTBK=100 HD0/VLYNQ_SCRUN/GP[58] HD0 – – VLYNQ_SCRUN GP[58] HD1/VLYNQ_RXD0/GP[59] HD1 – – VLYNQ_RXD0 GP[59] HOSTBK=010 HD2/VLYNQ_RXD1/GP[60] HD2 – – VLYNQ_RXD1 or GP[60] HD3/VLYNQ_RXD2/GP[61] HD3 – – VLYNQ_RXD2 HOSTBK=011 GP[61] HOSTBK=000 HD4/VLYNQ_RXD3/GP[62] HD4 – – VLYNQ_RXD3 GP[62] or HOSTBK=100 HD5/VLYNQ_TXD0/GP[63] HD5 – – VLYNQ_TXD0 GP[63] HD6/VLYNQ_TXD1/GP[64] HD6 – – VLYNQ_TXD1 GP[64] HD7/VLYNQ_TXD2/GP[65] HD7 – – VLYNQ_TXD2 GP[65] HD8/VLYNQ_TXD3/GP[66] HD8 – – VLYNQ_TXD3 GP[66] HD9/MCOL/GP[67] HD9 MCOL – – GP[67] HD10/MCRS/GP[68] HD10 MCRS – – GP[68] HD11/MTXD3/GP[69] HD11 MTXD3 – – GP[69] HD12/MTXD2/GP[70] HD12 MTXD2 – – GP[70] HOSTBK=001 HD13/MTXD1/GP[71] HD13 MTXD1 – – GP[71] HD14/MTXD0/GP[72] HD14 MTXD0 – – GP[72] HD15/MTXCLK/GP[73] HD15 MTXCLK – – GP[73] HHWIL/MRXDV/GP[74] HHWIL MRXDV – – GP[74] HOSTBK=011 HOSTBK=000 HCNTL1/MTXEN/GP[75] HCNTL1 MTXEN or – – GP[75] or HOSTBK=100 HOSTBK=010 HCNTL0/MRXER/GP[76] HCNTL0 MRXER – – GP[76] HR/W/MRXCLK/GP[77] HR/W MRXCLK – – GP[77] HDS2/MRXD0/GP[78] HDS2 MRXD0 – – GP[78] HDS1/MRXD1/GP[79] HDS1 MRXD1 – – GP[79] HRDY/MRXD2/GP[80] HRDY MRXD2 – – GP[80] HCS/MDCLK/GP[81] HCS MDCLK – – GP[81] HINT/MRXD3/GP[82] HINT MRXD3 – – GP[82] HAS/MDIO/GP[83] HAS MDIO – – GP[83] 98 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table 3-23 provides a different view of the Host Block pin muxing, showing the Host Block function based onPINMUX1settings.TheselectionoptionsarealsoshownpictoriallyinFigure3-11. If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to selectEMACpins. Table3-23.HostBlockFunctionSelection PINMUX1 SETTING BLOCKFUNCTION RESULTINGPINFUNCTIONS HOSTBK GPIO(27) 000 (default) GPIO:GP[83:57] HPI:HHWIL,HCNTL[1:0],HR/W,HDS2,HDS1,HRDY,HCS,HINT,HAS,HD[15:0] 001 HPI+GPIO(1) GPIO:GP[57] VLYNQ:VLYNQ_CLOCK,VLYNQ_SCRUN,VLYNQ_RXD[3:0],VLYNQ_TXD[3:0] 010 VLYNQ+GPIO(17) GPIO:GP[83:67] VLYNQ:VLYNQ_CLOCK,VLYNQ_SCRUN,VLYNQ_RXD[3:0],VLYNQ_TXD[3:0] EMAC(MII):TXCLK,CRS,COL,TXD[3:0],RXDV,TXEN,RXER,RXCLK, RXD[3:0] 011 VLYNQ+EMAC(MII)+MDIO MDIO:MDC,MDIO If EMAC operation is desired, EMAC must be placed in reset before programmingPINMUX1.HOSTBKtoselectEMACpins. EMAC(MII):TXCLK,CRS,COL,TXD[3:0],RXDV,TXEN,RXER,RXCLK, RXD[3:0] MDIO:MDC,MDIO 100 EMAC(MII)+MDIO+GPIO(10) GPIO:GP[66:57] If EMAC operation is desired, EMAC must be placed in reset before programmingPINMUX1.HOSTBKtoselectEMACpins. 101to111 Reserved Reserved The VDD3P3V_PWDN.HOST field determines the power state of the Host Block pins. The Host Block pinsdefaulttopoweredup.FormoredetailsontheVDD3P3V_PWDN.HOST field, see Section 3.2, Power Considerations. SubmitDocumentationFeedback DeviceConfiguration 99

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.3.4 UART0DataBlockMuxing This block of 2 pins consists of UART0 Data and GPIO muxed pins. The PINMUX1.UR0DBK register field selectthepinfunctionsintheUART0DataBlock. Table3-24summarizesthe2 pins in the UART0 Data Block, the multiplexed function on each pin, and the PINMUXconfigurationstoselectthecorrespondingfunction. Table3-24.UART0DataBlockMuxedPinsSelection MULTIPLEXEDFUNCTIONS SIGNAL UART0 GPIO NAME FUNCTION SELECT FUNCTION SELECT URXD0/GP[85] URXD0 GP[85] UR0DBK=1 UR0DBK=0 UTXD0/GP[86] UTXD0 GP[86] As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0 operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two pinsintheUART0FlowControlBlockareoptional. Table3-25providesadifferentviewoftheUART0DataBlockpin muxing, showing the UART0 Data Block function based on PINMUX1.UR0DBK setting. The selection options are also shown pictorially in Figure3-11. Table3-25.UART0DataBlockFunctionSelection PINMUX1.UR0DBK BLOCKFUNCTION RESULTINGPINFUNCTIONS 0 GPIO(2)(default) GPIO:GP[86:85] 1 UART0Data UART0:URXD0,UTXD0 In addition, the VDD3P3V_PWDN.UR0DAT field determines the power state of the UART0 Data Block pins. The UART0 Data Block pins default to powered down and not operational. To use these pins, user must first program VDD3P3V_PWDN.UR0DAT = 0 to power up the pins. For more details on the VDD3P3V_PWDN.UR0DATfield,seeSection3.2,PowerConsiderations. TheUART0DataBlockfeaturesinternalpullupresistors,whichmatchestheUARTinactivepolarity. 3.7.3.5 UART0FlowControlBlock This block of 2 pins consists of UART0 Flow Control, PWM0, and GPIO muxed pins. The PINMUX1.UR0FCBKregisterfieldselectsthepinfunctionsintheUART0FlowControlBlock. Table 3-26 summarizes the 2 pins in the UART0 Flow Control Block, the multiplexed function on each pin, andthePINMUXconfigurationstoselectthecorrespondingfunction. Table3-26.UART0FlowControlBlockMuxedPinsSelection MULTIPLEXEDFUNCTIONS SIGNAL UART0 PWM0 GPIO NAME FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT UCTS0/ UCTS0 – – GP[87] UR0FCBK=00/10 GP[87] URTS0/ UR0FCBK=01 PWM0/ URTS0 PWM0 UR0FCBK=10 GP[88] UR0FCBK=00 GP[88] 100 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0 operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two pinsintheUART0FlowControlBlockareoptional. Table 3-27 provides a different view of the UART0 Flow Control Block pin muxing, showing the UART0 Flow Control Block function based on PINMUX1.UR0FCBK setting. The selection options are also shown pictoriallyinFigure3-11. Table3-27.UART0FlowControlBlockFunctionSelection PINMUX1.UR0FCBK BLOCKFUNCTION RESULTINGPINFUNCTIONS 00 GPIO(2)(default) GPIO:GP[88:87] 01 UART0FlowControl UART0:UCTS0,URTS0 PWM0:PWM0 10 PWM0+GPIO(1) GPIO:GP[87] 11 Reserved Reserved In addition, the VDD3P3V_PWDN.UR0FC field determines the power state of the UART0 Flow Control Block pins. The UART0 Flow Control Block pins default to powered down and not operational. To use these pins, user must first program VDD3P3V_PWDN.UR0FC = 0 to power up the pins. For more details ontheVDD3P3V_PWDN.UR0FCfield,seeSection3.2,PowerConsiderations. The UART0 Flow Control Block features internal pullup resistors, which matches the UART inactive polarity. 3.7.3.6 Timer0Block This block of 2 pins consists of Timer0, McBSP0, and GPIO muxed pins. The PINMUX1.TIM0BK register fieldselectsthepinfunctionsintheTimer0Block. Table 3-28 summarizes the 2 pins in the Timer0 Block, the multiplexed function on each pin, and the PINMUXconfigurationstoselectthecorrespondingfunction. Table3-28.Timer0BlockMuxedPinsSelection MULTIPLEXEDFUNCTIONS SIGNAL McBSP Timer0 GPIO NAME FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT TINP0L/ – – TINP0L TIM0BK=01/11 GP[98] GP[98] CLKS0/ TIM0BK=00 TOUT0L/ CLKS0 TIM0BK=11 TOUT0L TIM0BK=01 GP[97] GP[97] As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an externalclocksourcetotheMcBSP0internalsamplerategenerator. Table 3-29 provides a different view of the Timer0 Block pin muxing, showing the Timer0 Block function basedonPINMUX1.TIM0BKsetting.TheselectionoptionsarealsoshownpictoriallyinFigure3-11. SubmitDocumentationFeedback DeviceConfiguration 101

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-29.Timer0BlockFunctionSelection PINMUX1.TIM0BK BLOCKFUNCTION RESULTINGPINFUNCTIONS 00 GPIO(2)(default) GPIO:GP[98:97] 01 Timer0 Timer0:TINP0L,TOUT0L 10 Reserved – McBSP0ExternalClockSource, McBSP0:CLKS0 11 Timer0Input Timer0:TINP0L In addition, the VDD3P3V_PWDN.TIMER0 field determines the power state of the Timer0 Block pins. The Timer0 Block pins default to powered down and not operational. To use these pins, user must first program VDD3P3V_PWDN.TIMER0 = 0 to power up the pins. For more details on the VDD3P3V_PWDN.TIMER0field,seeSection3.2,PowerConsiderations. 3.7.3.7 Timer1Block This block of 2 pins consists of Timer1, HECC, UART1 Data, and GPIO muxed pins. The PINMUX1.TIM1BKregisterfieldselectsthepinfunctionsintheTimer1Block. Table 3-30 summarizes the 2 pins in the Timer1 Block, the multiplexed function on each pin, and the PINMUXconfigurationstoselectthecorrespondingfunction. Table3-30.Timer1BlockMuxedPinsSelection MULTIPLEXEDFUNCTIONS SIGNAL HECC TIMER1 UART1 GPIO NAME FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT HECC_RX/ TINP1L/ HECC_RX TINP1L URXD1 GP[56] URXD1/ GP[56] TIM1BK=11 TIM1BK=01 TIM1BK=10 TIM1BK=00 HECC_TX/ TOUT1L/ HECC_TX TOUT1L UTXD1 GP[55] UTXD1/ GP[55] UnlikeUART0,UART1onlysupportsdatapinsbutnotflowcontrolpins. Table 3-31 provides a different view of the Timer1 Block pin muxing, showing the Timer1 Block function basedonPINMUX1.TIM1BKsetting.TheselectionoptionsarealsoshownpictoriallyinFigure3-11. Table3-31.Timer1BlockFunctionSelection PINMUX1.TIM1BK BLOCKFUNCTION RESULTINGPINFUNCTIONS 00 GPIO(2)(default) GPIO:GP[56:55] 01 Timer1 Timer1:TINP1L,TOUT1L 10 UART1Data UART1:URXD1,UTXD1 11 HECC HECC:HECC_RX,HECC_TX In addition, the VDD3P3V_PWDN.TIMER1 field determines the power state of the Timer1 Block pins. The Timer1 Block pins default to powered down and not operational. To use these pins, user must first program VDD3P3V_PWDN.TIMER1 = 0 to power up the pins. For more details on the VDD3P3V_PWDN.TIMER1field,seeSection3.2,PowerConsiderations. TheTimer1Blockfeaturesinternalpullupresistors,whichmatchestheUARTandHECCinactivepolarity. 102 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.7.3.8 SerialPortBlock This block of 12 pins consists of McASP0, McBSP0, and GPIO muxed pins. The following register fields selectthepinfunctionsintheSerialPortBlock: • PINMUX1.SPBK0 • PINMUX1.SPBK1 TheSerialPortBlockisfurthersubdividedintothesesub-blocks: • SerialPortSub-Block0:McBSP0,partofMcASP0,andGPIO. • SerialPortSub-Block1:partofMcASP0andGPIO. Table 3-32 summarizes the 12 pins in the Serial Port Block, the multiplexed function on each pin, and the PINMUXconfigurationstoselectthecorrespondingfunction. Table3-32.SerialPortBlockMuxedPinsSelection MULTIPLEXEDFUNCTIONS SIGNALNAME McASP0 McBSP0 GPIO FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT SerialPortSub-block0 ACLKR0/CLKX0/GP[99] ACLKR0 CLKX0 GP[99] AFSR0/DR0/GP[100] AFSR0 DR0 GP[100] AHCLKR0/CLKR0/GP[101] AHCLKR0 CLKR0 GP[101] SPBK0=10 SPBK0=01 SPBK0=00 AXR0[3]/FSR0/GP[102] AXR0[3] FSR0 GP[102] AXR0[2]/FSX0/GP[103] AXR0[2] FSX0 GP[103] AXR0[1]/DX0/GP[104] AXR0[1] DX0 GP[104] SerialPortSub-block1 AXR0[0]/GP[105] AXR0[0] – – GP[105] ACLKX0/GP[106] ACLKX0 – – GP[106] AFSX0/GP[107] AFSX0 – – GP[107] SPBK1=10 SPBK1=00 AHCLKX0/GP[108] AHCLKX0 – – GP[108] AMUTEIN0/GP[109] AMUTEIN0 – – GP[109] AMUTE0/GP[110] AMUTE0 – – GP[110] As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an externalclocksourcetotheMcBSP0internalsamplerategenerator. SubmitDocumentationFeedback DeviceConfiguration 103

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table 3-33 and Table 3-34 provide a different view of the Serial Port Block. Table 3-33 shows the Serial PortSub-Block0functionbasedonPINMUX1.SPBK0setting. Table 3-34 shows the Serial Port Sub-Block 1 function based on PINMUX1.SPBK1 setting. These selection options are also shown pictorially in Figure3-11. Table3-33.SerialPortSub-Block0FunctionSelection PINMUX1.SPBK0 BLOCKFUNCTION RESULTINGPINFUNCTIONS 00 GPIO(6)(default) GPIO:GP[104:99] 01 McBSP0 McBSP0:CLKX0,FSX0,DX0,CLKR0,FSR0,DR0 McASP0:ACLKR0,AFSR0,AHCLKR0,AXR0[3], 10 McASP0Receive,3Serializers AXR0[2],AXR0[1] 11 Reserved Reserved Table3-34.SerialPortSub-Block1FunctionSelection PINMUX1.SPBK1 BLOCKFUNCTION RESULTINGPINFUNCTIONS 00 GPIO(6)(default) GPIO:GP[110:105] 01 Reserved – McASP0Transmitwith1Serializerand McASP0:AXR0[0],ACLKX0,AFSX0,AHCLKX0, 10 MuteControl AMUTEIN0(1),AMUTE0 11 Reserved – (1) TheinputfromtheAMUTEIN0/GP[109]pinisconnectedtoboththeMcASP0andGPIO. In addition, the VDD3P3V_PWDN.SP field determines the power state of the Serial Port Block pins. The Serial Port Block pins default to powered down and not operational. To use these pins, user must first program VDD3P3V_PWDN.SP = 0 to power up the pins. For more details on the VDD3P3V_PWDN.SP field,seeSection3.2,PowerConsiderations. To facilitate McASP0 operation, the input from the AMUTEIN0/GP[109] pin is connected to both the McASP0andtheGPIOmodule.Thereforewhenanexternal mute event occurs, in addition to notifying the McASP0,itcanalsocauseaninterruptthroughtheGPIOmodule. 104 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.7.3.9 PWM1Block This block of 1 pin consists of PWM1 and GPIO muxed pins (GP[4]/PWM1). The PINMUX1.PWM1BK registerfieldselectsthepinfunctioninthePWM1Block. Table 3-35 summarizes the 1 pin in the PWM1 Block, its multiplexed function, and the PINMUX configurationstoselectthecorrespondingfunction. Table3-35.PWM1BlockMuxedPinSelection MULTIPLEXEDFUNCTIONS SIGNAL PWM1 GPIO NAME FUNCTION SELECT FUNCTION SELECT GP[4]/PWM1 PWM1 PWM1BK=1 GP[4] PWM1BK=0 Table 3-36 provides a different view of the PWM1 Block pin muxing, showing the PWM1 Block function basedonPINMUX1.PWM1BKsetting.TheselectionoptionsarealsoshownpictoriallyinFigure3-11. Table3-36.PWM1BlockFunctionSelection PINMUX1.PWM1BK BLOCKFUNCTION RESULTINGPINFUNCTIONS 0 GPIO(1)(default) GPIO:GP[4] 1 PWM1 PWM1:PWM1 In addition, the VDD3P3V_PWDN.PWM1 field determines the power state of the PWM1 Block pin. The PWM1 Block pin defaults to powered down and not operational. To use this pin, user must first program VDD3P3V_PWDN.PWM1 = 0 to power up the pin. For more details on the VDD3P3V_PWDN.PWM1 field, seeSection3.2,PowerConsiderations. SubmitDocumentationFeedback DeviceConfiguration 105

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.3.10 CLKOUTBlock This block of 1 pin consists of CLKOUT, PWM2, and GPIO muxed pin (CLKOUT0/PWM2/GP[84]). The PINMUX1.CKOBKregisterfieldselectsthepinfunctionintheCLKOUTBlock. Table 3-37 summarizes the 1 pin in the CLKOUT Block, its multiplexed function, and the PINMUX configurationstoselectthecorrespondingfunction. Table3-37.CLKOUTBlockMultiplexedPinSelection MULTIPLEXEDFUNCTIONS SIGNAL CLKOUT0 PWM2 GPIO NAME FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT CLKOUT0/ PWM2/ CLKOUT0 CKOBK=01 PWM2 CKOBK=10 GP[84] CKOBK=00 GP[84] Table 3-38 provides a different view of the CLKOUT Block pin muxing, showing the CLKOUT Block function based on PINMUX1.CKOBK setting. The selection options are also shown pictorially in Figure3-11. Table3-38.CLKOUTBlockFunctionSelection PINMUX1.CKOBK BLOCKFUNCTION RESULTINGPINFUNCTIONS 00 GPIO(1) GPIO:GP[84] 01 CLKOUT(default) DeviceClock-Out:CLKOUT0 10 PWM2 PWM2:PWM2 11 Reserved Reserved ThisblockdefaultstoCLKOUT0pinfunction. In addition, the VDD3P3V_PWDN.CLKOUT field determines the power state of the CLKOUT Block pin. The CLKOUT Block pin defaults to powered up. For more details on the VDD3P3V_PWDN.CLKOUT field, seeSection3.2,PowerConsiderations. 106 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.7.3.11 EMIFA/VPSSBlockMuxing This block of 61 pins consists of VPSS, EMIFA, and GPIO muxed pins. The following register fields affect thepinfunctionsintheEMIFA/VPSSBlock: • AllPINMUX0registerfields:AEM,CS5SEL,CS4SEL,CS3SEL,AEAW,CCDCSEL,HVDSEL, CWENSEL,CFLDSEL,CI76SEL,CI54SEL,CI32SEL,andCI10SEL The EMIFA/VPSS Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to accommodateawidevarietyofapplications: • Sub-Block0:multiplexedbetweenVPFE,EMIFAaddress/controlpins,andGPIO. • Sub-Block1:multiplexedbetweenEMIFAdata/address/controlpins,andGPIO. • Sub-Block2:nomultiplexing.EMIFAcontrolpinsEM_WAIT/(RDY/BSY),EM_OE,EM_WE. • Sub-Block3:multiplexedbetweenEMIFAaddresspinsEM_A[12:6]andGPIO. The EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register determine the power state of the EMIFA/VPSS Block pins. The EMIFA/VPSS Block pins default to powered up. For more details on the EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register, see Section 3.2, Power Considerations. To understand pin multiplexing in the EMIFA/VPSS Block, the user should start with Section 3.7.3.11.1, EMIFA/VPSS Block Pin Selection Procedure, which outlines the procedures to select pin functions of this block. Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, provides a pin-by-pin multiplexing summary for the EMIFA/VPSS Block. For more information on the PINMUX0 and PINMUX1 registers,seeSection3.7.2,PinMuxingSelectionAfterDeviceReset. 3.7.3.11.1 EMIFA/VPSSBlockPinSelectionProcedure FollowthestepsbelowtoperformpinselectionfortheEMIFA/VPSSBlockanditssub-blocks. 1. MajorConfigurationOptions:startwithTable3-39,EMIFA/VPSSBlockMajorConfigurationChoices. Basedontheperipheralneeds,theusershouldselectfromthemajorconfigurationoptionsinthis block:MajorConfigOptionsA,B,andE. 2. Sub-Block2andSub-Block3Selection:Afterselectingthemajorconfigurationoptionfrom Table3-39,EMIFA/VPSSBlockMajorConfigurationChoices,thepinselectionforSub-Block2and Sub-Block3iscomplete. 3. Sub-Block0Selection:UseTable3-40throughTable3-42,EMIFA/VPSSSub-Block0Configuration Choices,torefineSub-Block0pinselections. a. GotothetablewiththeMajorConfigurationOptionchoseninStep1. b. EachMajorConfigurationOptionisfurtherdivideddownintomultipleMinorConfigurationOptions. SelectaMinorConfigurationOptionthatbestsuitstheapplicationneed. c. WithinthechosenMinorConfigurationOption,furtherrefinethedetailedpinconfigurationsby selectingthesettingsofPINMUX0fieldsCCDCSEL,HVDSEL,CWENSEL,CFLDSEL,CI10SEL, CI32SEL,CI54SEL,andCI76SEL. d. TheSelectionFieldscolumnsshowthesettingsneededtoprogramthePINMUX0register. 4. Sub-Block1Selection:UseTable3-43throughTable3-45,EMIFA/VPSSSub-Block1Configuration Choices,torefineSub-Block1pinselection. a. GotothetablewiththeMajorConfigurationOptionchoseninStep1. b. EachMajorConfigurationOptionisfurtherdivideddownintomultipleMinorConfigurationOptions. SelectaMinorConfigurationOptionthatbestsuitstheapplicationneed. c. WithinthechosenMinorConfigurationOption,furtherrefinethedetailedpinconfigurationsby selectingthesettingsofPINMUX0fieldsCS3SEL,CS4SEL,andCS5SEL. d. TheSelectionFieldscolumnsshowthesettingsneededtoprogramthePINMUX0register. After following the procedure in this section to determine pin functions for the EMIFA/VPSS Block, the user should refer to Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, for pin-multiplexinginformationonapin-by-pinbasis. SubmitDocumentationFeedback DeviceConfiguration 107

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.3.11.2 EMIFA/VPSSBlockMajorConfigurationChoices Table 3-39 shows the major configuration choices in the EMIFA/VPSS Block. For instructions on how to use the EMIFA/VPSS Block Major Configuration Choices table for the EMIFA/VPSS Block and Sub-Blocks,seeSection3.7.3.11.1. Table3-39.EMIFA/VPSSBlockMajorConfigurationChoices PINMUXSELECTION MAJOR FIELDS(1) RESULTINGPERIPHERALS/PINS CONFIG. OPTION AEM CCDCSEL EMIFA #GPPINS VPFEAND#GPPINS (FROMGP[33:5]) (FROMGP[54:34]) #GPPins CCDCSEL VPFE&#GPPins NoCCDC 0 21GPpins A 000 0,1 - 29GPpins 8-to-16-bitCCDC 1 0-to-12GPpins 8-bitEMIFA(ASYNC) 0 NoCCDC B 001(2) 0,1 PinoutMode1withaddresspins 9-to-13GPpins 11-to-19GPpins tCoSs.upport32KBto16MBper 1(2) 80--ttoo--1160-GbiPtCpCinDsC(2) NoCCDC 0 8-bitEMIFA(NAND) 21GPpins E 101 0,1 14-to-18GPpins PinoutMode5 8-to-16-bitCCDC 1 0-to-12GPpins (1) ForadditionalpinmuxdetailsforeachSub-Block,seeTable3-40throughTable3-42,EMIFA/VPSSSub-Block0ConfigurationChoices, andTable3-43throughTable3-45,EMIFA/VPSSSub-Block1ConfigurationChoices. (2) IfPINMUX0.AEM=001,itisnotpossibletogettheC_WEpinforVPFE. As shown in Table 3-39, the major configuration choices of the EMIFA/VPSS Block are determined by the followingPINMUXregisterfields: • PINMUX0registerfieldsAEMandCCDCSEL Based on the peripheral needs, select from the major configuration options in this block: Major ConfigurationOptionsA,B,andE. The following is an example on how to read Table 3-39. For example, the "PINMUX Selection Fields" columns indicate that Major Configuration Choice B is selected through setting PINMUX0.AEM = 1 and CCDCSEL = 0 or 1 (based on the system's VPFE requirement). The "Resulting Peripherals/Pins" columns indicatethatMajorConfigurationOptionBcansupportthefollowingcombinationofpinfunctions: • Pinsfor8-bitEMIFA(AsyncorNAND)function.Thenumberofaddresspinssupportedprovide 32KByteto16MByteaddressreachperEMIFAChipSelect(CS)space. • Pinsforupto16-bitVPFE.If8-to-16-bitVPFE(CCDCSEL=1)isselected,theusermayhave0to10 GPIOpins.ExactdetailonnumberofGPIOpinsandVPFEcontrolpinsisfurthereddeterminedby otherPINMUX0settingsdiscussedintheEMIFA/VPSSSub-Block0ConfigurationChoices. • 9-to-13GPIOpinsfromGP[33:5].FordetailsonthenumberofGPIOpins,see Section3.7.3.11.4,EMIFA/VPSSSub-Block1ConfigurationChoices. After using Table 3-39 to select the Major Configuration Option for the EMIFA/VPSS Block, proceed to selectthedetailedpinchoicesintheEMIFA/VPSSSub-Blocks. 108 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.7.3.11.3 EMIFA/VPSSSub-Block0ConfigurationChoices Table 3-40 through Table 3-42 show the configuration choices in the EMIFA/VPSS Sub-Block 0. For instructions on how to use the different configuration choices tables for the EMIFA/VPSS Block and Sub-Blocks, see Section 3.7.3.11.1. Note: italics in these tables indicate mandatory settings for a given MinorConfigurationoption. Before using Table 3-40 through Table 3-42 to configure the details of the EMIFA/VPSS Sub-Block 0, the user should first select a Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.11.2). After determining the Major Configuration Option (A, B, or E), the user can now use Table 3-40 through Table3-42torefineSub-Block0pinselections: 1. GotothetablewiththeMajorConfigurationOptionchosenfromTable3-39. 2. EachMajorConfigurationOptionisfurtherdivideddownintomultipleMinorConfigurationOptions. SelectaMinorConfigurationOptionthatbestsuitstheapplicationneed. 3. WithinthechosenMinorConfigurationOption,furtherrefinethedetailedpinconfigurationsbyselecting thesettingsofPINMUX0fieldsCCDCSEL,HVDSEL,CWENSEL,CFLDSEL,CI10SEL,CI32SEL, CI54SEL,andCI76SEL. 4. ThePINMUXSelectionFieldscolumnsshowthesettingsneededtoprogramthePINMUX0register. Table3-40.EMIFA/VPSSSub-Block0ConfigurationChoiceA(1) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM AEAW OTHERS EMIFA VPFE #GPIOPINS CfgSummary NoEMIFA NoCCDC 21GPpins CCDCSEL=0 0=GP[54,43:36] HVDSEL=0 0=GP[53:52] CWENSEL=0 0=GP[35] A1 000 000 CFLDSEL=0 0=GP[34] - - CI10SEL=0 0=GP[45:44] CI32SEL=0 0=GP[47:46] CI54SEL=0 0=GP[49:48] CI76SEL=0 0=GP[51:50] A CfgSummary NoEMIFA 8-to-16-bitCCDC 0-to-12GPpins CCDCSEL=1 1=PCLK,YI[7:0] - HVDSEL=0,1 1=VD,HD 0=GP[53:52] CWENSEL=0,1 1=C_WE 0=GP[35] A2 000 000 CFLDSEL=0,1 1=C_FIELD 0=GP[34] - CI10SEL=0,1 1=CI[1:0] 0=GP[45:44] CI31SEL=0,1 1=CI[3:2] 0=GP[47:46] CI54SEL=0,1 1=CI[5:4] 0=GP[49:48] CI76SEL=0,1 1=CI[7:6] 0=GP[51:50] (1) ItalicsindicatemandatorysettingsforagivenMinorConfigurationoption. SubmitDocumentationFeedback DeviceConfiguration 109

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-41.EMIFA/VPSSSub-Block0ConfigurationChoiceB(1) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM AEAW OTHERS EMIFA VPFE #GPIOPINS 8-bitEMIFA (Async)Pinout ConfigSummary NoCCDC 11GPpins mode1w/ EM_A[21:0] CCDCSEL=0 - 0=GP[54,43:36] HVDSEL=0 - 0=GP[53:52] B B1 001 100 CWENSEL=0 0=EM_R/W - CFLDSEL=0 0=EM_A21 - - CI10SEL=0 0=EM_A[19:20] - CI32SEL=0 0=EM_A[17:18] - CI54SEL=0 0=EM_A[15:16] - CI76SEL=0 0=EM_A[13:14] - 8-bitEMIFA (Async)Pinout ConfigSummary 8-to-16-bitCCDC 0-to-10GPpins mode1w/ EM_A[12:0]only CCDCSEL=1 - 1=PCLK,YI[7:0] - HVDSEL=0,1 - 1=VD,HD 0=GP[53:52] CWENSEL=0 0=EM_R/W - - B B2 001 000 0=EM_A21 CFLDSEL=0,1 1=C_FIELD - (notused) CI10SEL=0,1 - 1=CI[1:0] 0=GP[45:44] CI32SEL=0,1 - 1=CI[3:2] 0=GP[47:46] CI54SEL=0,1 - 1=CI[5:4] 0=GP[49:48] CI76SEL=0,1 - 1=CI[7:6] 0=GP[51:50] 8-bitEMIFA (Async)Pinout ConfigSummary 8-to-14-bitCCDC 0-to-8GPpins mode1w/ EM_A[14:0]only CCDCSEL=1 - 1=PCLK,YI[7:0] - HVDSEL=0,1 - 1=VD,HD 0=GP[53:52] CWENSEL=0 0=EM_R/W - - B B3 001 001 0=EM_A21 CFLDSEL=0,1 1=C_FIELD - (notused) CI10SEL=0,1 - 1=CI[1:0] 0=GP[45:44] CI32SEL=0,1 - 1=CI[3:2] 0=GP[47:46] CI54SEL=0,1 - 1=CI[5:4] 0=GP[49:48] CI76SEL=0 0=EM_A[13:14] - - (1) ItalicsindicatemandatorysettingsforagivenMinorConfigurationoption. 110 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-41.EMIFA/VPSSSub-Block0ConfigurationChoiceB (continued) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM AEAW OTHERS EMIFA VPFE #GPIOPINS 8-bitEMIFA (Async)Pinout ConfigSummary 8-to-12-bitCCDC 0-to-6GPpins mode1w/ EM_A[16:0]only CCDCSEL=1 - 1=PCLK,YI[7:0] - HVDSEL=0,1 - 1=VD,HD 0=GP[53:52] CWENSEL=0 0=EM_R/W - - B B4 001 010 0=EM_A21 CFLDSEL=0,1 1=C_FIELD - (notused) CI10SEL=0,1 - 1=CI[1:0] 0=GP[45:44] CI32SEL=0,1 - 1=CI[3:2] 0=GP[47:46] CI54SEL=0 0=EM_A[15:16] - - CI76SEL=0 0=EM_A[13:14] - - 8-bitEMIFA (Async)Pinout ConfigSummary 8-to-10-bitCCDC 0-to-4GPpins mode1w/ EM_A[18:0]only CCDCSEL=1 - 1=PCLK,YI[7:0] - HVDSEL=0,1 - 1=VD,HD 0=GP[53:52] CWENSEL=0 0=EM_R/W - - B B5 001 011 0=EM_A21 CFLDSEL=0,1 1=C_FIELD - (notused) CI10SEL=0,1 - 1=CI[1:0] 0=GP[45:44] CI32SEL=0 0=EM_A[17:18] - - CI54SEL=0 0=EM_A[15:16] - - CI76SEL=0 0=EM_A[13:14] - - SubmitDocumentationFeedback DeviceConfiguration 111

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-41.EMIFA/VPSSSub-Block0ConfigurationChoiceB (continued) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM AEAW OTHERS EMIFA VPFE #GPIOPINS 8-bitEMIFA (Async)Pinout ConfigSummary 8-bitCCDC 0-to-2GPpins mode1w/ EM_A[21:0] CCDCSEL=1 - 1=PCLK,YI[7:0] - HVDSEL=0,1 - 1=VD,HD 0=GP[53:52] B B6 001 100 CWENSEL=0 0=EM_R/W - - CFLDSEL=0,1 0=EM_A21 1=C_FIELD - CI10SEL=0 0=EM_A[19:20] - - CI32SEL=0 0=EM_A[17:18] - - CI54SEL=0 0=EM_A[15:16] - - CI76SEL=0 0=EM_A[13:14] - - 112 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-42.EMIFA/VPSSSub-Block0ConfigurationChoiceE(1) RESULTING MAJOR MINOR PINMUXSELECTIONFIELDS PERIPHERALS/PI CONFIG CONFIG NS OPTION OPTION AEM AEAW OTHERS EMIFA VPFE #GPIOPINS 8-bitEMIFA CfgSummary (NAND)Pinout NoCCDC 21GPpins mode5 CCDCSEL=0 0=GP[54,43:36] HVDSEL=0 0=GP[53:52] CWENSEL=0 0=GP[35] E1 101 000 CFLDSEL=0 0=GP[34] - - CI10SEL=0 0=GP[45:44] CI32SEL=0 0=GP[47:46] CI54SEL=0 0=GP[49:48] CI76SEL=0 0=GP[51:50] E 8-bitEMIFA CfgSummary (NAND)Pinout 8-to-16-bitCCDC 0-to-12GPpins mode5 CCDCSEL=1 1=PCLK,YI[7:0] - HVDSEL=0,1 1=VD,HD 0=GP[53:52] CWENSEL=0,1 1=C_WE 0=GP[35] E2 101 000 CFLDSEL=0,1 1=C_FIELD 0=GP[34] - CI10SEL=0,1 1=CI[1:0] 0=GP[45:44] CI31SEL=0,1 1=CI[3:2] 0=GP[47:46] CI54SEL=0,1 1=CI[5:4] 0=GP[49:48] CI76SEL=0,1 1=CI[7:6] 0=GP[51:50] (1) ItalicsindicatemandatorysettingsforagivenMinorConfigurationoption. As shown in Table 3-40 through Table 3-42, the configuration choices of the EMIFA/VPSS Sub-Block 0 aredeterminedbythefollowingPINMUXregisterfields: • PINMUX0registerfieldsAEM,AEAW,CCDCSEL,HVDSEL,CWENSEL,CFLDSEL,CI10SEL, CI32SEL,CI54SEL,andCI76SEL. The following is an example of how to read Table 3-40 through Table 3-42 using Sub-Block 0 Minor ConfigurationB6asanexample: • ThePINMUXSelectionFieldscolumnsindicatethatSub-Block0MinorConfigurationOptionB6is selectedthroughsetting,PINMUX0.AEM=1,PINMUX0.AEAW=4,CCDCSEL=1,HVDSEL=0or1 (basedonthesystem’sneedforVPFEcontrolsignalsVDandHD),CWENSEL=0(mandatory setting),CFLDSEL=0or1(basedonthesystem’sneedforVPFEcontrolsignalC_FIELD),CI10SEL =0(mandatory),CI32SEL=0(mandatory),CI54SEL=0(mandatory),andCI76SEL=0(mandatory). • TheResultingPeripherals/PinscolumnsshowthefunctionalpinsresultingfromthePINMUXsetting. Forexample,PINMUX0.CCDCSEL=1givestheuserthePCLKandYI[7:0]pinsfortheVPFE. PINMUX0.HVDSEL=1givestheuserVDandHDpinsforVPFE,whileHVDSEL=0givestheuser2 GPpins. SubmitDocumentationFeedback DeviceConfiguration 113

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.3.11.4 EMIFA/VPSSSub-Block1ConfigurationChoices Table 3-43 through Table 3-45 show the configuration choices in the EMIFA/VPSS Sub-Block 1. For instructions on how to use the different configuration choices tables for the EMIFA/VPSS Block and Sub-Blocks,seeSection3.7.3.11.1,EMIFA/VPSSBlockPinSelectionProcedure. Before using Table 3-43 through Table 3-45 to configure the details of the EMIFA/VPSS Sub-Block 1, the user should first select the Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.11.2, EMIFA/VPSS Block Major Configuration Choices). After determining the Major Configuration Option (A, B, orE),theusercannowuseTable3-43throughTable3-45torefinetheSub-Block1pinselections. 1. GotothetablewiththeMajorConfigurationOptionchosenfromTable3-39. 2. EachMajorConfigurationOptionisfurtherdivideddownintomultipleMinorConfigurationOptions. SelectaMinorConfigurationOptionthatbestsuitstheapplicationneed. 3. WithinthechosenMinorConfigurationOption,furtherrefinethedetailedpinconfigurationsbyselecting thesettingsofPINMUX0fieldsCS3SEL,CS4SEL,andCS5SEL. 4. ThePINMUXSelectionFieldscolumnsgivetheuserthesettingsneededtoprogramthePINMUX0 register. Table3-43.EMIFA/VPSSSub-Block1ConfigurationChoiceA(1) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM OTHERS EMIFA GPIO CfgSummary NoEMIFA 29GPpins CS3SEL=0 A A1 000 CS4SEL=0 – 0=GP[33:5] CS5SEL=0 (1) ItalicsindicatemandatorysettingsforagivenMinorConfigurationoption. Table3-44.EMIFA/VPSSSub-Block1ConfigurationChoiceB(1) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM OTHERS EMIFA GPIO 8-bitEMIFA(Async) CfgSummary 10-to-13GPpins PinoutMode1 EM_D[7:0],EM_CS2, BasicPinsYouGet 0=GP[31:22] EM_A[4:0],EM_BA[1:0] B B1 001 CS3SEL=0,1 1=EM_CS3 0=GP[13] CS4SEL=0,1 1=EM_CS4 0=GP[32] CS5SEL=0,1 1=EM_CS5 0=GP[33] (1) ItalicsindicatemandatorysettingforagivenMinorConfigurationoption. Table3-45.EMIFA/VPSSSub-Block1ConfigurationChoiceE(1) MAJOR MINOR PINMUXSELECTIONFIELDS RESULTINGPERIPHERALS/PINS CONFIG CONFIG OPTION OPTION AEM OTHERS EMIFA GPIO 8-bitEMIFA(NAND) CfgSummary 15-to-18GPpins PinoutMode5 EM_D[7:0],EM_A[2:1], 0=GP[31:22,11:10, BasicPinsYouGet EM_CS2 7:5] E E1 101 CS3SEL=0,1 1=EM_CS3 0=GP[13] CS4SEL=0,1 1=EM_CS4 0=GP[32] CS5SEL=0,1 1=EM_CS5 0=GP[33] (1) ItalicsindicatemandatorysettingforagivenMinorConfigurationoption. 114 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 The Sub-Block 1 Minor Configuration Options are independent from the Sub-Block 0 Minor Configuration Options. The user can independently select the appropriate Minor Configuration Option for each Sub-Block. As shown in Table 3-43 through Table 3-45, the configuration choices of the EMIFA/VPSS Sub-Block 1 aredeterminedbythefollowingPINMUXregisterfields: • PINMUX0registerfieldsAEM,CS3SEL,CS4SEL,andCS5SEL. The following is an example on how to read Table 3-43 through Table 3-45 using Sub-Block 1 Minor ConfigurationE1asanexample: • ThePINMUXSelectionFieldscolumnsindicatethatSub-Block1MinorConfigurationOptionE1is selectedthroughsettingPINMUX0fieldstoAEM=5,CS3SEL=0/1(basedonthedesiredpinchoice), CS4SEL=0/1(basedonthedesiredpinchoice),andCS5SEL=0/1(basedonthedesiredpin choice). • TheResultingPeripherals/PinscolumnsshowthefunctionalpinsresultingfromthePINMUXsetting. Forexample,youautomaticallygetEMIFApinsEM_D[7:0],EM_A[2:1],andEM_CS2inadditiontoat least15GPIOpinsinMinorConfigOptionE1(GP[31:22],GP[11:10],andGP[7:5]).Ifyouprogram CS3SEL=1,CS4SEL=0,andCS5SEL=0,youalsogetEM_CS3,GP[32],andGP[33]. 3.7.3.11.5 EMIFA/VPSSSub-Block2ConfigurationChoices The 3 pins in the EMIFA/VPSS Sub-Block 2 are standalone (non-multiplexed) pins. They always function as EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. No pin mux selection is necessary forthisSub-Block. 3.7.3.11.6 EMIFA/VPSSSub-Block3ConfigurationChoices The8pinsintheEMIFA/VPSSSub-Block3aremultiplexedbetween: • EMIFAAddressPinsEM_A[12:5] • GPIOpinsGP[96:89] The pin functions in the EMIFA/VPSS Sub-Block 3 are determined by the following PINMUX register fields: • PINMUX0.AEM Once the Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.11.2, EMIFA/VPSS Block Major Configuration Choices) is chosen, no further actions are necessary to refine the EMIFA/VPSS Sub-Block 3 pin selection. For instructions on configuring the EMIFA/VPSS Block, see Section 3.7.3.11.1, EMIFA/VPSSBlockPinSelectionProcedure. Table 3-46 summarizes the pin selections in the EMIFA/VPSS Sub-Block 3 based on the PINMUX selections. Table3-46.EMIFA/VPSSSub-Block3ConfigurationChoices MAJOR PINMUXSELECTIONFIELD RESULTINGPERIPHERALS/PINS CONFIG OPTION AEM EMIFA GPIO A 000 - GP[96:89] B 001 EM_A[12:5] - E 101 - GP[96:89] The following is an example on how to read Table 3-46 using Sub-Block 3 Major Configuration B as an example: • ThePINMUXSelectionFieldscolumnsindicatethatSub-Block3MajorConfigurationOptionBis selectedthroughsettingPINMUX0.AEM=001b. • TheResultingPeripherals/PinscolumnsshowthefunctionalpinsresultingfromthePINMUXsetting.In MajorConfigurationB,theusergetsEMIFAaddresspinsEM_A[12:5]fromSub-Block3. SubmitDocumentationFeedback DeviceConfiguration 115

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 3.7.3.11.7 EMIFA/VPSSBlockPin-By-PinMultiplexingSummary This section summarizes the EMIFA/VPSS Block muxing on a pin-by-pin basis. It provides an alternative view to pin muxing in the EMIFA/VPSS Block. This section should only be used after following the procedures listed in Section 3.7.3.11.1 to determine the actual EMIFA/VPSS Configuration Option for the applicationneed. Table3-47showsthepinmultiplexingcontrol for each pin in the EMIFA/VPSS Sub-Block 0. These are the fieldsinthePINMUX0andPINMUX1registersthatcontrolthemultiplexinginthissub-block: • PINMUX0:AEM,AEAW,CWENSEL,CFLDSEL,CI10SEL,CI32SEL,CI54SEL,CI76SEL,CCDCSEL, andHVDSEL Table3-48showsthepinmultiplexingcontrol for each pin in the EMIFA/VPSS Sub-Block 1. These are the fieldsinthePINMUX0registerthatcontrolthemultiplexinginthissub-block: • PINMUX0:AEM,CS5SEL,CS4SEL,andCS3SEL EMIFA/VPSS Sub-Block 2 is dedicated to EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. Thereisnopinmultiplexinginthisblock.ThesepinsalwaysfunctionasEMIFAcontrolpins. Table3-49showsthepinmultiplexingcontrol for each pin in the EMIFA/VPSS Sub-Block 3. These are the fieldsinthePINMUX0registerthatcontrolthemultiplexinginthissub-block: • PINMUX0:AEM 116 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table3-47.EMIFA/VPSSSub-Block0Pin-By-PinMuxControl MULTIPLEXEDFUNCTIONS SIGNALNAME VPFE EMIFAADDR/CTRL GPIO FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT PCLK/GP[54] PCLK CCDCSEL=1 – – GP[54] CCDCSEL=0 YI7(CCD7)/GP[43] YI7(CCD7) – – GP[43] YI6(CCD6)/GP[42] YI6(CCD6) – – GP[42] YI5(CCD5)/GP[41] YI5(CCD5) – – GP[41] YI4(CCD4)/GP[40] YI4(CCD4) – – GP[40] YI3(CCD3)/GP[39] YI3(CCD3) – – GP[39] YI2(CCD2)/GP[38] YI2(CCD2) – – GP[38] YI1(CCD1)/GP[37] YI1(CCD1) – – GP[37] YI0(CCD0)/GP[36] YI0(CCD0) – – GP[36] VD/GP[53] VD HVDSEL=1 – – GP[53] HVDSEL=0 HD/GP[52] HD – – GP[52] CI7(CCD15)/EM_A[13]/GP[51] CI7(CCD15) AEM=0/1/5, EM_A[13] AEM=1, GP[51] AEM=0/1/5, AEAW=0, AEAW=1/2/3/4, AEAW=0, CI6(CCD14)/EM_A[14]/GP[50] CI6(CCD14) CI76SEL=1 EM_A[14] CI76SEL=0 GP[50] CI76SEL=0 CI5(CCD13)/EM_A[15]/GP[49] CI5(CCD13) AEM=0/1/5, EM_A[15] AEM=1, GP[49] AEM=0/1/5, AEAW=0/1(1), AEAW=2/3/4, AEAW=0/1(1), CI4(CCD12)/EM_A[16]/GP[48] CI4(CCD12) CI54SEL=1 EM_A[16] CI54SEL=0 GP[48] CI54SEL=0 CI3(CCD11)/EM_A[17]/GP[47] CI3(CCD11) AEM=0/1/5, EM_A[17] AEM=1, GP[47] AEM=0/1/5, AEAW=0/1/2(1), AEAW=3/4, AEAW=0/1/2(1), CI2(CCD10)/EM_A[18]/GP[46] CI2(CCD10) CI32SEL=1 EM_A[18] CI32SEL=0 GP[46] CI32SEL=0 CI1(CCD9)/EM_A[19]/GP[45] CI1(CCD9) AEM=0/1/5, EM_A[19] AEM=1, GP[45] AEM=0/1/5, AEAW=0/1/2/3(1), AEAW=4, AEAW=0/1/2/3(1), CI0(CCD8)/EM_A[20]/GP[44] CI0(CCD8) CI10SEL=1 EM_A[20] CI10SEL=0 GP[44] CI10SEL=0 C_WE/EM_R/W/GP[35] CWENSEL=1, CWENSEL=0, CWENSEL=0, C_WE EM_R/W GP[35] AEM=0/5 AEM=1 AEM=0/5 C_FIELD/EM_A[21]/GP[34] CFLDSEL=1, CFLDSEL=0, CFLDSEL=0, C_FIELD EM_A[21] GP[34] AEM=0/1/5 AEM=1 AEM=0/5 (1) AEAW=1/2/3/4isonlyvalidifAEM[2:0]=1. SubmitDocumentationFeedback DeviceConfiguration 117

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table3-48.EMIFA/VPSSSub-Block1Pin-By-PinMuxControl MULTIPLEXEDFUNCTIONS SIGNAL EMIFA GPIO(1) NAME FUNCTION SELECT FUNCTION SELECT EM_CS5/GP[33] EM_CS5 CS5SEL=1 GP[33] CS5SEL=0 EM_CS4/GP[32] EM_CS4 CS4SEL=1 GP[32] CS4SEL=0 GP[31] GP[31] GP[30] GP[30] GP[29] GP[29] GP[28] GP[28] GP[27] GP[27] – – – GP[26]/(FASTBOOT) GP[26] GP[25]/(BOOTMODE3) GP[25] GP[24]/(BOOTMODE2) GP[24] GP[23]/(BOOTMODE1) GP[23] GP[22]/(BOOTMODE0) GP[22] EM_D[7]/GP[21] EM_D[7] GP[21] EM_D[6]/GP[20] EM_D[6] GP[20] EM_D[5]/GP[19] EM_D[5] GP[19] EM_D[4]/GP[18] EM_D[4] GP[18] AEM=1/5 AEM=0 EM_D[3]/GP[17] EM_D[3] GP[17] EM_D[2]/GP[16] EM_D[2] GP[16] EM_D[1]/GP[15] EM_D[1] GP[15] EM_D[0]/GP[14] EM_D[0] GP[14] EM_CS3/GP[13] EM_CS3 CS3SEL=1 GP[13] CS3SEL=0 EM_CS2/GP[12] EM_CS2 GP[12] EM_A[1]/(ALE)/ EM_A[1]/(ALE) GP[9] GP[9]/(AEAW1/PLLMS1) AEM=1/5 AEM=0 EM_A[2]/(CLE)/GP[8]/ EM_A[2]/(CLE) GP[8] (AEAW0/PLLMS0) EM_A[3]/GP[11] EM_A[3] GP[11] EM_A[4]/GP[10]/ EM_A[4] GP[10] (AEAW2/PLLMS2) AEM=1 AEM=0/5 EM_A[0]/GP[7]/(AEM2) EM_A[0] GP[7] EM_BA[0]/GP[6]/(AEM1) EM_BA[0] GP[6] EM_BA[1]/GP[5]/(AEM0) EM_BA[1] GP[5] (1) GP[31:22]arestandalonepins.Theyarenotmuxedwithanyotherfunctions.Theyareincludedinthistablebecausetheyaregrouped intheEMIFA/VPSSSub-Block1. Table3-49.EMIFA/VPSSSub-Block3Pin-By-PinMuxControl SIGNAL MULTIPLEXEDFUNCTIONS NAME EMIFA GPIO FUNCTION SELECT FUNCTION SELECT EM_A[12]/GP[89] EM_A[12] GP[89] EM_A[11]/GP[90] EM_A[11] GP[90] EM_A[10]/GP[91] EM_A[10] GP[91] EM_A[9]/GP[92] EM_A[9] GP[92] AEM=1 AEM=0/5 EM_A[8]/GP[93] EM_A[8] GP[93] EM_A[7]/GP[94] EM_A[7] GP[94] EM_A[6]/GP[95] EM_A[6] GP[95] EM_A[5]/GP[96] EM_A[5] GP[96] 118 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.8 Device Initialization Sequence After Reset Softwareshouldfollowthisinitializationsequenceaftercomingoutofdevicereset. 1. Completethebootsequenceasneeded.Formoredetailsonthebootsequence,seetheUsingthe TMS320DM643xBootloaderApplicationReport(literaturenumberSPRAAG0). 2. Ifthedeviceisnotalreadyatthedesiredoperatingfrequency,programthePLLControllers(PLLC1 andPLLC2)toconfigurethedevicefrequency.FordetailsonhowtoprogramthePLLC,seethe TMS320DM643xDMPDSPSubsystemReferenceGuide(literaturenumberSPRU978). 3. ProgramPINMUX0andPINMUX1registerstoselectdevicepinfunctions.Formoredetailson programmingthePINMUX0andPINMUX1registerstoselectdevicepinfunctions,seeSection3.7, MultiplexedPinConfigurations. Note:ifEMACoperationisdesired,theEMACmustbeplacedinresetbeforeprogramming PINMUX1.HOSTBKtoselectEMACpins. 4. ProgramtheVDD3P3V_PWDNregistertopowerupthenecessaryI/Opins.Formoredetailson programmingtheVDD3P3V_PWDNregister,seeSection3.2,PowerConsiderations.OnDM6435,the usershouldprogramVDD3P3V_PWDNbit13to1topowerdownthereservedpinsRSV17,RSV18, andRSV19. 5. Asneededbytheapplication,programthefollowingSystemModuleregisterswhentherearenoactive transactionsontherespectiveperipherals: a. HPICTL(Section3.6.2.1,HPIControlRegister):applicableforHPIonlyifadifferenthostburst writetimeoutvaluefromdefaultisdesired. b. TIMERCTL(Section3.6.2.2,TimerControlRegister):applicableforTimer0andWatchdogTimer2 only. c. EDMATCCFG(Section3.6.2.3,EDMATCConfigurationRegister):applicableforEDMAonly.The recommendationistoleavetheEDMATCCFGregisteratitsdefault. d. VPSS_CLKCTL(Section3.3.2,VPSSClocks):applicableforVPSSonly. 6. ProgramthePowerandSleepController(PSC)toenablethedesiredperipherals.Fordetailsonhow toprogramthePSC,seetheTMS320DM643xDMPDSPSubsystemReferenceGuide(literature numberSPRU978). 7. ProgramtheSwitchedCentralResource(SCR)busprioritiesforthemasterperipherals (Section3.6.1).Thismustbeconfiguredwhentherearenoactivetransactionsontherespective peripherals: a. ProgramtheMSTPRI0andMSTPRI1registersintheSystemModule.Theseregisterscanbe programmedbeforeoraftertherespectiveperipheralisenabledbythePSCinstep6. b. ProgramtheEDMACCQUEPRIregister,theC64x+MDMAARBE.PRIfield,andtheVPSSPCR register.Theseregisterscanonlybeprogrammedaftertherespectiveperipheralisenabledbythe PSCinstep6. 8. ConfiguretheC64x+Megamoduleandtheperipherals. a. FordetailsonC64x+Megamoduleconfiguration,seetheTMS320C64x+DSPMegamodule ReferenceGuide(literaturenumberSPRU871). Special considerations: Bootloader disables C64x+ cache—For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot, BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and L1DCFG.L1DMODE = 0h). If cache use is required, the application code must explicitly enable the cache. For more information on boot modes, see Section 3.4.1, Boot Modes. For more information on the bootloader, see the Using the TMS320DM643xBootloaderApplicationReport(literaturenumberSPRAAG0). SubmitDocumentationFeedback DeviceConfiguration 119

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com b. Peripheralsconfiguration:seetherespectiveperipheraluser’sguide. Special considerations: DDR2 memory controller—the Peripheral Bus Burst Priority Register (PBBPR) should be programmed to ensure good DDR2 throughput and to prevent command starvation (prevention of certain commands from being processed by the DDR2 memory controller). For more details, see the TMS320DM643x DMP DDR2 Memory Controller User’s Guide (literature number SPRU986). A hex value of 0x20 is recommended for the PBBPR PR_OLD_COUNT field to provideagoodDSPperformanceandstillallowgoodutilizationbyothermodules. 120 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 3.9 Debugging Considerations 3.9.1 Pullup/Pulldown Resistors Proper board design should ensure that input pins to the DM643x DMP device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The DM643x DMP features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwisenoted,forexternalpullup/pulldownresistors. Anexternalpullup/pulldownresistorneedstobeusedinthefollowingsituations: • Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state. • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldownresistortopullthesignaltotheoppositerail. • EMIFA Chip Select Outputs: On DM6435, the EMIFA chip select pins (EM_CS2, EM_CS3, EM_CS4, and EM_CS5) feature an internal pulldown (IPD) resistor. If these pins are connected and used as an EMIFA chip select signal, for proper device operation, an external pullup resistor must be used to ensuretheEM_CSxfunctiondefaultstoaninactive(high)state. For the boot and configuration pins (listed in Table 2-5, Boot Terminal Functions), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switchingoperatingmodes. Tipsforchoosinganexternalpullup/pulldownresistor: • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldownresistors. • Decide a target value for the net. For a pulldown resistor, this should be below the lowest V level of IL all inputs connected to the net. For a pullup resistor, this should be above the highest V level of all IH inputs on the net. A reasonable choice would be to target the V or V levels for the logic family of OL OH thelimitingdevice;which,bydefinition,havemargintotheV andV levels. IL IH • Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and externalpullup/pulldownresistorsonthenet. • For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer candrivethenettotheoppositelogiclevel(includingmargin). • Remembertoincludetoleranceswhenselectingtheresistorvalue. • Forpullupresistors,alsoremembertoincludetolerancesontheDV rail. DD For most systems, a 1-kW resistor can be used to oppose the IPU/IPD while meeting the above criteria. Usersshouldconfirmthisresistorvalueiscorrectfortheirspecificapplication. For most systems, a 20-kW resistor can be used to compliment the IPU/IPD on the boot and configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. For more detailed information on input current (I), and the low-/high-level input voltages (V and V ) for I IL IH the DM643x DMP, see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply VoltageandOperatingTemperature. SubmitDocumentationFeedback DeviceConfiguration 121

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functionstable. 122 DeviceConfiguration SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 4 System Interconnect On the DM6435 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture (see Figure 4-1). The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals and slave peripherals. Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between master and slave peripherals. Through an SCR, the DSP subsystem can send data to the DDR2 Memory Controller without affecting a data transfer between the EMAC and L2 memory. Bridges are mainly used to perform bus-width conversion as well as bus operating frequency conversion. For example, in Figure 4-1, Bridge 6 performs a frequency conversion between a bus operating at DSP/3 clock rate and a bus operating at DSP/6 clock rate.Furthermore,Bridge5performsabus-widthconversionbetweena64-bitbusanda32-bitbus. The C64x+ Megamodule, the EDMA3 transfer controllers (EDMA3TC[2:0]), and the various system peripherals can be classified into two categories: master peripherals and slave peripherals. Master peripherals are typically capable of initiating read and write transfers in the system and do not rely on the EDMA3 or on the CPU to perform transfers to and from them. The system master peripherals include the C64x+ Megamodule, the EDMA3 transfer controllers, VLYNQ, EMAC, HPI, and VPSS. Not all master peripherals may connect to all slave peripherals. The supported connections are designated by ' Y' in Table4-1. Table4-1.SystemConnectionMatrix SLAVEPERIPHERALS/MODULES MASTER DDR2 PERIPHERALS/MODULES C64x+SDMA MEMORY SCR4(1) SSCCRR72,,SSCCRR86(1,) CONTROLLER C64x+MDMA – Y – Y VPSS – Y – – VLYNQ Y Y Y Y EMAC Y Y Y Y HPI Y Y Y Y EDMA3TC's(EDMA3TC2/TC1/TC0) Y Y Y Y C64x+CFG – – Y Y (1) Alltheperipherals/modulesthatsupportaconnectiontoSCR2,SCR4,SCR6,SCR7,andSCR8haveaccesstoallperipherals/modules connectedtothoserespectiveSCRs. 4.1 System Interconnect Block Diagram Figure 4-1 displays the DM6435 system interconnect block diagram. The following is a list that helps in theinterpretationofthisdiagram: • Thedirectionofthearrowsindicateseitherabusmasterorbusslave. • Thearroworiginatesatabusmasterandterminatesatabusslave. • The direction of the arrows does not indicate the direction of data flow. Data flow is typically bi-directionalforeachofthedocumentedbuspaths. • The pattern of each arrow's line indicates the clock rate at which it is operating— i.e., either DSP/3, DSP/6,orMXI/CLKINclockrate. • AperipheralmayhavemultipleinstancesshowninFigure4-1forthefollowingreason: – Theperipheral/modulehasmasterport(s)fordatatransfers,aswellasslaveport(s)forregister access,dataaccess,and/ormemoryaccess.ExamplesoftheseperipheralsareC64x+ Megamodule,EDMA3,VPSS,VLYNQ,HPI,andEMAC. SubmitDocumentationFeedback SystemInterconnect 123

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com DSP/6 Clock Rate DSP/6 Clock Rate MXI/CLKIN Clock Rate 32 32 32 UART0 VLYNQ 32 64 DDCRo2n tMroelmleorry Bridge 8 32 (Memory/Register) UART1 EMAC 32 SCR 5 32 Bridge 2 64 32 HPI 32 HECC HPI 32 64 SDMA L624/xL+1 32 VPSS Reg 32 I2C 32 EMAC Reg 32 PWM0 32 EMAC Control SCR 2 32 Module Reg PWM1 VPSS 64 32 EMAC Control 32 SCR 6 Module RAM PWM2 EDMA3TC0 WReraitde 6644 SCR 1 64 Bridge 5 32 32 MDIO 32 Timer0 Read 64 32 32 32 GPIO Timer1 EDMA3TC1 Write 64 EDMA3TC2 WReraitde 6644 64 Bridge 4 32 32 System Reg 32 Timer2 32 32 32 PSC Bridge 6 32 64 Bridge 3 32 PLLC1 SCR 3 32 PLLC2 L2 Cache 32 MA 64 SCR 4 32 SCR 7 32 EMIFA MD EDMA3CC VLYNQ 64x+ 32 CFG 32 32 EDMA3TC0 32 SCR 8 32 McBSP0 EDMA3TC1 McASP0 EDMA3TC2 DSP/3 Clock Rate DSP/3 Clock Rate DSP/6 Clock Rate MXI/CLKIN Clock Rate Figure4-1.SystemInterconnectBlockDiagram 124 SystemInterconnect SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 5 Device Operating Conditions 5.1 Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise Noted)(1) Supplyvoltageranges: Core(CV )(2) –0.5Vto1.5V DD I/O,3.3V(DV )(2) –0.5Vto4.2V DD33 I/O,1.8V(DV ,DDR_VDDDLL,PLL ,MXV )(2) –0.5to2.5V DDR2 PWR18 DD Inputvoltageranges: V I/O,3.3-Vpins –0.5Vto4.2V I V I/O,1.8V –0.5Vto2.5V I Outputvoltageranges: V I/O,3.3-Vpins –0.5Vto4.2V O V I/O,1.8V –0.5Vto2.5V O OperatingJunctiontemperature Commercial 0Cto90C ranges,T: J Automotive –40Cto125C (QorSsuffix) Storagetemperaturerange,T (default) –65Cto150C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttoV SS. SubmitDocumentationFeedback DeviceOperatingConditions 125

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 5.2 Recommended Operating Conditions(1) MIN NOM MAX UNIT (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4 1.14 1.2 1.26 V CVDD Supplyvoltage,Core(CVDD)(2) devices) (-7/-6/-5/-4/-L/-Q5devices) 1.0 1.05 1.1 V Supplyvoltage,I/O,3.3V(DVDD33) 2.97 3.3 3.63 V DVDD SMuXpVpDlyD(v3o))ltage,I/O,1.8V(DVDDR2,DDR_VDDDLL,PLLPWR18, 1.71 1.8 1.89 V VSS Supplyground(VSS,DDR_VSSDLL,MXVSS(4)) 0 0 0 V DDR_VREF DDR2referencevoltage(5) 0.49DVDDR2 0.5DVDDR2 0.51DVDDR2 V DDR_ZP DDR2impedancecontrol,connectedvia200W resistortoVSS VSS V DDR_ZN DDR2impedancecontrol,connectedvia200W resistortoDVDDR2 DVDDR2 V High-levelinputvoltage,3.3V(exceptI2Cpins) 2 V VIH High-levelinputvoltage,MXI/CLKIN 0.65MXV V High-levelinputvoltage,I2C 0.7DVDD33 Low-levelinputvoltage,3.3V(exceptI2Cpins) 0.8 V VIL Low-levelinputvoltage,MXI/CLKIN 0.35MXV V Low-levelinputvoltage,I2C 0 0.3DVDD33 V OperatingJunction Commercial 0 90 C TJ temperature(6)(7) Automotive(QorSsuffix) –40 125 C Commercial 0 70 C TA OperatingAmbientTemperature(7) Automotive(QorSsuffix) -40 85 C -7devices 700 MHz -Q6devices 660 MHz DSPOperatingFrequency (SYSCLK1), -6/-Ldevices 600 MHz CVDD=1.2V -5/-Q5devices 500 MHz FSYSCLK1(2) -4/-Q4devices 400 MHz -7devices 560 MHz DSPOperatingFrequency -6/-Ldevices 450 MHz (SYSCLK1), CVDD=1.05V -5/-Q5devices 400 MHz -4devices 350 MHz (1) Theactualvoltagemustbedeterminedatdevicepower-up,andnotbechangeddynamicallyduringrun-time. (2) Appliesto"tapeandreel"partnumbercounterpartsaswell.Formoreinformation,seeSection2.8,DeviceandDevelopment-Support ToolNomenclature. (3) Oscillator1.8Vpowersupply(MXV )canbeconnectedtothesame1.8VpowersupplyasDV . DD DDR2 (4) Oscillatorground(MXV )mustbekeptseparatefromothergroundsandconnecteddirectlytothecrystalloadcapacitorground. SS (5) DDR_VREFisexpectedtoequal0.5DV ofthetransmittingdeviceandtotrackvariationsintheDV . DDR2 DDR2 (6) Intheabsenceofaheatsinkordirectthermalattachmentonthetopofthedevice,usethefollowingformulatodeterminethedevice junctiontemperature:T =T +(PowerxPsi ).PowerandT canbemeasuredbytheuser.Section7.1,ThermalDataforZWTand J C JT C Section7.1.1,ThermalDataforZDUprovidethejunction-to-packagetop(PSI )valuebasedonairflowinthesystem.Inthepresence JT ofaheatsinkordirectthermalattachmentonthetopofthedevice,additionalcalculationsandconsiderationsmustbetakeninto account.Formoredetailedinformationonthermalconsiderations,measurements,andcalculations,seetheThermalConsiderationsfor TMS320DM64xx,TMS320DM64x,andTMS320C6000DevicesApplicationReport(literaturenumberSPRAAL9). (7) ApplicationsmustmeetboththeOperatingJunctionTemperatureandOperatingAmbientTemperaturerequirements.Formoredetailed informationonthermalconsiderations,measurements,andcalculations,seetheThermalConsiderationsforTMS320DM64xx, TMS320DM64x,andTMS320C6000DevicesApplicationReport(literaturenumberSPRAAL9). 126 DeviceOperatingConditions SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER TESTCONDITIONS(1) MIN TYP MAX UNIT High-leveloutputvoltage(3.3VI/Oexcept VOH I2Cpins) DVDD33=MIN,IOH=MAX 2.4 V Low-leveloutputvoltage(3.3VI/Oexcept I2Cpins) DVDD33=MIN,IOL=MAX 0.4 V VOL Low-leveloutputvoltage(3.3VI/OI2C pins) IO=3mA 0 0.4 V Inputcurrent[DC](exceptI2Ccapable VI=VSStoDVDD33withinternalpullupresistor(3) 50 100 250 µA II(2) pins) VI=VSStoDVDD33withinternalpulldownresistor(3) –250 –100 –50 µA Inputcurrent[DC](I2C) VI=VSStoDVDD33 – 10 µA CLK_OUT0/PWM2/GPIO[84]and -8 mA VLYNQ_CLOCK/GP[57] IOH High-leveloutputcurrent[DC] DDR2 –13.4 mA Allotherperipherals -4 mA CLK_OUT0/PWM2/GPIO[84]and 8 mA VLYNQ_CLOCK/GP[57] IOL Low-leveloutputcurrent[DC] DDR2 13.4 mA Allotherperipherals 4 mA IOZ(4) I/OOff-stateoutputcurrent VVOO==DDVVDDDD3333oorrVVSSSS;;iinntteerrnnaallppuulllldeinsaabblleedd – 100 50 µAA CVDD=1.2V,DSPclock=700MHz 597 mA CVDD=1.2V,DSPclock=660MHz 560 mA CVDD=1.2V,DSPclock=600MHz 524 mA ICDD Core(CVDD,VDDA_1P1V)supplycurrent(5) CVDD=1.2V,DSPclock=500MHz 460 mA CVDD=1.2V,DSPclock=400MHz 392 mA CVDD=1.05V,DSPclock=560MHz 442 mA CVDD=1.05V,DSPclock=450MHz 372 mA CVDD=1.05V,DSPclock=400MHz 341 mA DVDD=3.3V,CVDD=1.2V,DSPclock=700MHz 13 mA DVDD=3.3V,CVDD=1.2V,DSPclock=660MHz 13 mA DVDD=3.3V,CVDD=1.2V,DSPclock=600MHz 13 mA IDDD 3.3VI/O(DVDD33)supplycurrent(5) DVDD=3.3V,CVDD=1.2V,DSPclock=500MHz 13 mA DVDD=3.3V,CVDD=1.2V,DSPclock=400MHz 13 mA DVDD=3.3V,CVDD=1.05V,DSPclock=560MHz 13 mA DVDD=3.3V,CVDD=1.05V,DSPclock=450MHz 13 mA DVDD=3.3V,CV=1.05V,DSPclock=400MHz 13 mA (1) FortestconditionsshownasMIN,MAX,orNOM,usetheappropriatevaluespecifiedintherecommendedoperatingconditionstable. (2) I appliestoinput-onlypinsandbi-directionalpins.Forinput-onlypins,I indicatestheinputleakagecurrent.Forbi-directionalpins,I I I I indicatestheinputleakagecurrentandoff-state(Hi-Z)outputleakagecurrent. (3) Appliesonlytopinswithaninternalpullup(IPU)orpulldown(IPD)resistor. (4) I appliestooutput-onlypins,indicatingoff-state(Hi-Z)outputleakagecurrent. OZ (5) Measuredunderthefollowingconditions:60%DSPCPUutilizationdoingtypicalactivity(peripheralconfigurations,otherhousekeeping activities);DDR2MemoryControllerat50%utilization(135MHz),50%writes,32bits,50%bitswitching;2MHzMcBSP0at100% utilizationand50%switching;Timer0at100%utilization.Atroomtemperature(25C)fortypicalprocessZWTdevices.Theactual currentdrawvariesacrossmanufacturingprocessesandishighlyapplication-dependent.DM643xDMPdevicesareofferedintwobasic options:lower-poweroptionandhigh-performanceoption.Low-powerdevicesofferlowerpowerconsumptionacrosstemperatureand voltagewhencomparedwithhigh-performancedevices.However,high-performancedevicesofferhigheroperatingspeeds.Formore detailsoncoreandI/Oactivity,aswellasinformationrelevanttoboardpowersupplydesign,seetheTMS320DM643xPower ConsumptionSummaryApplicationReport(literaturenumberSPRAAO6). SubmitDocumentationFeedback DeviceOperatingConditions 127

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com ElectricalCharacteristicsOverRecommendedRangesofSupplyVoltageandOperatingTemperature (UnlessOtherwiseNoted)(continued) PARAMETER TESTCONDITIONS(1) MIN TYP MAX UNIT DVDD=1.8V,CVDD=1.2V,DSPclock=700MHz 94 mA DVDD=1.8V,CVDD=1.2V,DSPclock=660MHz 94 mA DVDD=1.8V,CVDD=1.2V,DSPclock=600MHz 93 mA 1.8VI/O(DVDDR2,DDR_VDDDLL, DVDD=1.8V,CVDD=1.2V,DSPclock=500MHz 92 mA IDDD PLLVPRW18,VDDA_1P8V,MXVDD)supply current(5) DVDD=1.8V,CVDD=1.2V,DSPclock=400MHz 91 mA DVDD=1.8V,CVDD=1.05V,DSPclock=560MHz 74 mA DVDD=1.8V,CVDD=1.05V,DSPclock=450MHz 73 mA DVDD=1.8V,CVDD=1.05V,DSPclock=400MHz 72 mA CI Inputcapacitance 5 pF Co Outputcapacitance 5 pF 128 DeviceOperatingConditions SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6 Peripheral Information and Electrical Specifications 6.1 Parameter Information Tester Pin Electronics Data Sheet Timing Reference Point 42 W 3.5 nH Output Transmission Line Under Test Z0 = 50 W (see Note) Device Pin 4.0 pF 1.85 pF (see Note) NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure6-1.TestLoadCircuitforACTimingMeasurements Theloadcapacitancevaluestatedis only for characterization and measurement of AC timing signals. This loadcapacitancevaluedoesnotindicatethemaximumloadthedeviceiscapableofdriving. 6.1.1 3.3-V Signal Transition Levels AllinputandoutputtimingparametersarereferencedtoV forboth"0"and"1"logiclevels.For 3.3 V I/O, ref V =1.5V.For1.8VI/O,V =0.9V. ref ref V ref Figure6-2.InputandOutputVoltageReferenceLevelsforACTimingMeasurements All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, IL IH V MAXandV MINforoutputclocks. OL OH Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure6-3.RiseandFallTransitionTimeVoltageReferenceLevels 6.1.2 3.3-V Signal Transition Rates Alltimingsaretestedwithaninputedgerateof4voltspernanosecond(4V/ns). 6.1.3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjustedbyincreasing/decreasingsuchdelays. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 129

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed,externallogichardwaresuchasbuffersmaybeusedtocompensateanytimingdifferences. For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the TMS320DM643xDMPDMSoCApplicationReport(literaturenumberSPRAAL6). 6.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between V and V (or between V and V ) in a monotonic IH IL IL IH manner. 6.3 Power Supplies For more information regarding TI's power management products and suggested devices to power TI DSPs,visitwww.ti.com/dsppower. 6.3.1 Power-Supply Sequencing The DM6435 includes one core supply (CV ), and two I/O supplies—DV and DV . To ensure DD DD33 DDR2 proper device operation, a specific power-up sequence must be followed. Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable features.FormoreinformationonTIpowersuppliesandtheirfeatures,visitwww.ti.com/dsppower. Hereisasummaryofthepowersequencingrequirements: • The power ramp order must be DV before DV , and DV before CV —meaning during DD33 DDR2 DDR2 DD power up, the voltage at the DV rail should never exceed the voltage at the DV rail. Similarly, DDR2 DD33 thevoltageattheCV railshouldneverexceedthevoltageattheDV rail. DD DDR2 • From the time that power ramp begins, all power supplies (DV , DV , CV ) must be stable DD33 DDR2 DD within 200 ms. The term "stable" means reaching the recommended operating condition (see Section5.2,RecommendedOperatingConditionstable). 6.3.2 Power-Supply Design Considerations Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the DM6435 device, the PC board should include separate power planes for core, I/O, and ground;allbypassedwithhigh-qualitylow-ESL/ESRcapacitors. 6.3.3 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum distancetobeeffective.Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitancevalue. Largercapsforeachsupplycanbeplacedfurtheraway for bulk decoupling. Large bulk caps (on the order of 100 m F) should be furthest away, but still as close as possible. Large caps for each supply should be placedoutsideoftheBGAfootprint. As with the selection of any component, verification of capacitor availability over the product's production lifetimeshouldbeconsidered. For more details on capacitor usage and placement, see the Implementing DDR2 PCB Layout on the TMS320DM643xDMPDMSoCApplicationReport(literaturenumberSPRAAL6). 130 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.3.4 DM6435 Power and Clock Domains The DM6435 includes one single power domain — the "Always On" power domain. The "Always On" power domain is always on when the chip is on. The "Always On" domain is powered by the CV pins of DD theDM6435.AllDM6435modulesliewithinthe"AlwaysOn"power domain. Table 6-1 provides a listing of theDM6435clockdomains. One primary reference clock is required for the DM6435 device. The can be either a crystal input or driven by external oscillators. A 27-MHz crystal is recommended for the system PLLs, which generate the internal clocks for the digital media processor, coprocessors, peripherals (including imaging peripherals), andtheEDMA3.ForfurtherdescriptionoftheDM6435clockdomains,seeTable6-3andFigure6-4. Table6-1.DM6435PowerandClockDomains PowerDomain ClockDomain Peripheral/Module AlwaysOn CLKIN UART0 AlwaysOn CLKIN UART1 AlwaysOn CLKIN HECC AlwaysOn CLKIN I2C AlwaysOn CLKIN Timer0 AlwaysOn CLKIN Timer1 AlwaysOn CLKIN Timer2 AlwaysOn CLKIN PWM0 AlwaysOn CLKIN PWM1 AlwaysOn CLKIN PWM2 AlwaysOn CLKDIV3 DDR2 AlwaysOn CLKDIV3 VPSS AlwaysOn CLKDIV3 EDMA AlwaysOn CLKDIV3 SCR AlwaysOn CLKDIV6 GPSC AlwaysOn CLKDIV6 LPSCs AlwaysOn CLKDIV6 PLLC1 AlwaysOn CLKDIV6 PLLC2 AlwaysOn CLKDIV6 IcePick AlwaysOn CLKDIV6 EMIFA AlwaysOn CLKDIV6 HPI AlwaysOn CLKDIV6 VLYNQ AlwaysOn CLKDIV6 EMAC AlwaysOn CLKDIV6 McASP0 AlwaysOn CLKDIV6 McBSP0 AlwaysOn CLKDIV6 GPIO AlwaysOn CLKDIV1 C64x+CPU Table6-2.DM6435ClockDomains DOMAINCLOCK FIXEDRATIOvs. EXAMPLE SUBSYSTEM CLOCKDOMAIN SOURCE SYSCLK1FREQUENCY FREQUENCY(MHz) Peripherals(CLKINDomain) CLKIN PLLC1AUXCLK(1) – 27MHz DSPSubsystem CLKDIV1 PLLC1SYSCLK1 1:1 594MHz EDMA3 CLKDIV3 PLLC1SYSCLK2 1:3 198MHz VPSS CLKDIV3 PLLC1SYSCLK2 1:3 198MHz Peripherals(CLKDIV3Domain) CLKDIV3 PLLC1SYSCLK2 1:3 198MHz (1) PLLC1AUXCLKrunsatexactlythesamefrequencyasthedeviceclocksourcefromtheMXI/CLKINpin. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 131

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-2.DM6435ClockDomains (continued) DOMAINCLOCK FIXEDRATIOvs. EXAMPLE SUBSYSTEM CLOCKDOMAIN SOURCE SYSCLK1FREQUENCY FREQUENCY(MHz) Peripherals(CLKDIV6Domain) CLKDIV6 PLLC1SYSCLK3 1:6 99MHz The CLKDIV1:CLKDIV3:CLKDIV6 ratio must be strictly followed by programming the PLL Controller 1 (PLLC1)PLLDIV1,PLLDIV2,andPLLDIV3registersappropriately(seeTable6-3). Table6-3.PLLC1ProgrammingforCLKDIV1,CLKDIV3,CLKDIV6Domains CLKDIV1DOMAIN CLKDIV3DOMAIN CLKDIV6DOMAIN (SYSCLK1) (SYSCLK2) (SYSCLK3) PLL1 PLL1 PLL1 PLLDIV1.RATIO PLLDIV2.RATIO PLLDIV3.RATIO Divide-Down Divide-Down Divide-Down DIV1 /1 0 /3 2 /6 5 DIV2 /2 1 /6 5 /12 11 DIV3 /3 2 /9 8 /18 17 HECC UARTs (x2) MXI/CLKIN AUXCLK I2C (27 MHz) PWMs (x3) OBSCLK OSCDIV1 (/1) (CLKOUT0 Pin) Timers (x3) SYSCLK1 PLLDIV1 (/1) DSP Subsystem SYSCLK3 PLLDIV3 (/6) HPI SYSCLK2 PLLDIV2 (/3) SCR VLYNQ PLL Controller 1 EDMA EMAC EMIFA VPFE PCLK McASP0 PLLDIV1 (/2) DDR2 PHY McBSP0 BPDIV DDR2 VTP GPIO PLL Controller 2 DDR2 Mem Ctlr Figure6-4.PLL1andPLL2ClockDomainBlockDiagram For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-5 and Figure 6-6, respectively. 132 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 CLKMODE PLLEN PLLOUT CLKIN 1 PLL 1 PLLDIV1 (/1) SYSCLK1 (CLKDIV1 Domain) OSCIN 0 PLLDIV2 (/3) SYSCLK2 0 (CLKDIV3 Domain) PLLM PLLDIV3 (/6) SYSCLK3 (CLKDIV6 Domain) AUXCLK (CLKIN Domain) OSCDIV1 OBSCLK (CLKOUT0 Pin) Figure6-5.PLL1StructureBlockDiagram CLKMODE PLLEN PLLOUT CLKIN 1 PLL 1 PLL2_SYSCLK1 OSCIN 0 PLLDIV1 (/2) (DDR2 PHY) 0 PLLM PLL2_SYSCLKBP BPDIV (DDR2 VTP) Figure6-6.PLL2StructureBlockDiagram SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 133

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.3.5 Power and Sleep Controller (PSC) The Power and Sleep Controller (PSC) controls power by turning off unused power domains or by gating off clocks to individual peripherals/modules. The DM6435 device only utilizes the clock gating feature of thePSCforpowersavings.ThePSCconsistsofaGlobalPSC(GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The LPSCs for DM6435 are shown in Table 6-4. The PSC Register memory map is given in Table 6-5. For more details on the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literaturenumberSPRU978). Table6-4.DM6435LPSCAssignments LPSC Peripheral/Module LPSC Peripheral/Module LPSC Peripheral/Module Number Number Number 0 VPSSDMA 14 EMIFA 28 TIMER1 1 VPSSMMR 15 Reserved 29 Reserved 2 EDMACC 16 McBSP0 30 Reserved 3 EDMATC0 17 Reserved 31 Reserved 4 EDMATC1 18 I2C 32 Reserved 5 EDMATC2 19 UART0 33 Reserved 6 EMACMemoryController 20 UART1 34 Reserved 7 MDIO 21 Reserved 35 Reserved 8 EMAC 22 HECC 36 Reserved 9 McASP0 23 PWM0 37 Reserved 10 Reserved 24 PWM1 38 Reserved 11 VLYNQ 25 PWM2 39 C64x+CPU 12 HPI 26 GPIO 40 Reserved 13 DDR2MemoryController 27 TIMER0 Table6-5.PSCRegisterMemoryMap REGISTER HEXADDRESSRANGE DESCRIPTION ACRONYM 0x01C41000 PID PeripheralRevisionandClassInformationRegister 0x01C41004-0x01C4100F - Reserved 0x01C41010 GBLCTL GlobalControlRegister 0x01C41014 - Reserved 0x01C41018 INTEVAL InterruptEvaluationRegister 0x01C4101C-0x01C4103F - Reserved 0x01C41040 MERRPR0 ModuleErrorPending0(mod0-31)Register 0x01C41044 MERRPR1 ModuleErrorPending1(mod32-63)Register 0x01C41048-0x01C4104F - Reserved 0x01C41050 MERRCR0 ModuleErrorClear0(mod0-31)Register 0x01C41054 MERRCR1 ModuleErrorClear1(mod32-63)Register 0x01C41058-0x01C4105F - Reserved 0x01C41060 PERRPR PowerErrorPendingRegister 0x01C41064-0x01C41067 - Reserved 0x01C41068 PERRCR PowerErrorClearRegister 0x01C4106C-0x01C4111F - Reserved 0x01C41120 PTCMD PowerDomainTransitionCommandRegister 0x01C41124-0x01C41127 - Reserved 134 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-5.PSCRegisterMemoryMap (continued) REGISTER HEXADDRESSRANGE DESCRIPTION ACRONYM 0x01C41128 PTSTAT PowerDomainTransitionStatusRegister 0x01C4112C-0x01C411FF - Reserved 0x01C41200 PDSTAT0 PowerDomainStatus0Register(AlwaysOn) 0x01C41204-0x01C412FF - Reserved 0x01C41300 PDCTL0 PowerDomainControl0Register(AlwaysOn) 0x01C41304-0x1C4150F - Reserved 0x01C41510 MCKOUT0 ModuleClockOutputStatus(mod0-31)Register 0x01C41514 MCKOUT1 ModuleClockOutputStatus(mod32-63)Register 0x01C41518-0x01C415FF - Reserved 0x01C41600-0x01C417FF - Reserved 0x01C41800 MDSTAT0 ModuleStatus0Register(VPSSDMA) 0x01C41804 MDSTAT1 ModuleStatus1Register(VPSSMMR) 0x01C41808 MDSTAT2 ModuleStatus2Register(EDMACC) 0x01C4180C MDSTAT3 ModuleStatus3Register(EDMATC0) 0x01C41810 MDSTAT4 ModuleStatus4Register(EDMATC1) 0x01C41814 MDSTAT5 ModuleStatus5Register(EMACTC2) 0x01C41818 MDSTAT6 ModuleStatus6Register(EMACMemoryController) 0x01C4181C MDSTAT7 ModuleStatus7Register(MDIO) 0x01C41820 MDSTAT8 ModuleStatus8Register(EMAC) 0x01C41824 MDSTAT9 ModuleStatus9Register(McASP0) 0x01C41828 - Reserved 0x01C4182C MDSTAT11 ModuleStatus11Register(VLYNQ) 0x01C41830 MDSTAT12 ModuleStatus12Register(HPI) 0x01C41834 MDSTAT13 ModuleStatus13Register(DDR2) 0x01C41838 MDSTAT14 ModuleStatus14Register(EMIFA) 0x01C4183C - Reserved 0x01C41840 MDSTAT16 ModuleStatus16Register(McBSP0) 0x01C41844 - Reserved 0x01C41848 MDSTAT18 ModuleStatus18Register(I2C) 0x01C4184C MDSTAT19 ModuleStatus19Register(UART0) 0x01C41850 MDSTAT20 ModuleStatus20Register(UART1) 0x01C41854 - Reserved 0x01C41858 MDSTAT22 ModuleStatus22Register(HECC) 0x01C4185C MDSTAT23 ModuleStatus23Register(PWM0) 0x01C41860 MDSTAT24 ModuleStatus24Register(PWM1) 0x01C41864 MDSTAT25 ModuleStatus25Register(PWM2) 0x01C41868 MDSTAT26 ModuleStatus26Register(GPIO) 0x01C4186C MDSTAT27 ModuleStatus27Register(TIMER0) 0x01C41870 MDSTAT28 ModuleStatus28Register(TIMER1) 0x01C41874-0x01C4189B - Reserved 0x01C4189C MDSTAT39 ModuleStatus39Register(C64x+CPU) 0x01C418A0 - Reserved 0x01C418A4-0x01C419FF - Reserved 0x01C41A00 MDCTL0 ModuleControl0Register(VPSSDMA) 0x01C41A04 MDCTL1 ModuleControl1Register(VPSSMMR) 0x01C41A08 MDCTL2 ModuleControl2Register(EDMACC) SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 135

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-5.PSCRegisterMemoryMap (continued) REGISTER HEXADDRESSRANGE DESCRIPTION ACRONYM 0x01C41A0C MDCTL3 ModuleControl3Register(EDMATC0) 0x01C41A10 MDCTL4 ModuleControl4Register(EDMATC1) 0x01C41A14 MDCTL5 ModuleControl5Register(EMACTC2) 0x01C41A18 MDCTL6 ModuleControl6Register(EMACMemoryController) 0x01C41A1C MDCTL7 ModuleControl7Register(MDIO) 0x01C41A20 MDCTL8 ModuleControl8Register(EMAC) 0x01C41A24 MDCTL9 ModuleControl9Register(McASP0) 0x01C41A28 - Reserved 0x01C41A2C MDCTL11 ModuleControl11Register(VLYNQ) 0x01C41A30 MDCTL12 ModuleControl12Register(HPI) 0x01C41A34 MDCTL13 ModuleControl13Register(DDR2) 0x01C41A38 MDCTL14 ModuleControl14Register(EMIFA) 0x01C41A3C - Reserved 0x01C41A40 MDCTL16 ModuleControl16Register(McBSP0) 0x01C41A44 - Reserved 0x01C41A48 MDCTL18 ModuleControl18Register(I2C) 0x01C41A4C MDCTL19 ModuleControl19Register(UART0) 0x01C41A50 MDCTL20 ModuleControl20Register(UART1) 0x01C41A54 - Reserved 0x01C41A58 MDCTL22 ModuleControl22Register(HECC) 0x01C41A5C MDCTL23 ModuleControl23Register(PWM0) 0x01C41A60 MDCTL24 ModuleControl24Register(PWM1) 0x01C41A64 MDCTL25 ModuleControl25Register(PWM2) 0x01C41A68 MDCTL26 ModuleControl26Register(GPIO) 0x01C41A6C MDCTL27 ModuleControl27Register(TIMER0) 0x01C41A70 MDCTL28 ModuleControl28Register(TIMER1) 0x01C41A74-0x01C41A9B - Reserved 0x01C41A9C MDCTL39 ModuleControl39Register(C64x+CPU) 0x01C41AA0 - Reserved 0x01C41AA4-0x01C41FFF - Reserved 136 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.4 Enhanced Direct Memory Access (EDMA3) Controller The EDMA controller handles all data transfers between memories and the device slave peripherals on the DM6435 device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmeddatatransfers,andhostaccesses.Thesearesummarizedasfollows: • Transferto/fromon-chipmemories – DSPL1Dmemory – DSPL2memory • Transferto/fromexternalstorage – DDR2SDRAM – NANDflash – AsynchronousEMIF(EMIFA) • Transferto/fromperipherals/hosts – VLYNQ – HPI – McBSP0 – McASP0 – PWM – UART0/1 – HECC The EDMA supports two addressing modes: constant addressing and increment addressing. On the DM6435, constant addressing mode is not supported by any peripheral or internal memory. For more information on these two addressing modes, see the TMS320DM643x DMP Enhanced Direct Memory Access(EDMA3)ControllerUser’sGuide(literaturenumberSPRU987). 6.4.1 EDMA3 Channel Synchronization Events The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 6-6 lists the source of EDMA synchronization events associated with each of the programmable EDMA channels. For the DM6435 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM643x DMP Enhanced Direct MemoryAccess(EDMA3)ControllerUser’sGuide(literaturenumberSPRU987). Table6-6.DM6435EDMAChannelSynchronizationEvents(1) EDMA EVENTNAME EVENTDESCRIPTION CHANNEL 0-1 – Reserved 2 XEVT0 McBSP0TransmitEvent 3 REVT0 McBSP0ReceiveEvent 4 – Reserved 5 – Reserved 6 HISTEVT VPSSHistogramEvent 7 H3AEVT VPSSH3AEvent 8 PRVUEVT VPSSPreviewerEvent 9 RSZEVT VPSSResizerEvent 10 AXEVTE0 McASP0TransmitEventEven (1) Inadditiontotheeventsshowninthistable,eachofthe64channelscanalsobesynchronizedwiththetransfercompletionoralternate transfercompletionevents.FormoredetailedinformationonEDMAevent-transferchaining,seetheDocumentSupportsectionforthe EnhancedDirectMemoryAccess(EDMA)ControllerReferenceGuide. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 137

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-6.DM6435EDMAChannelSynchronizationEvents (continued) EDMA EVENTNAME EVENTDESCRIPTION CHANNEL 11 AXEVTO0 McASP0TransmitEventOdd 12 AXEVT0 McASP0TransmitEvent 13 AREVTE0 McASP0ReceiveEventEven 14 AREVTO0 McASP0ReceiveEventOdd 15 AREVT0 McASP0ReceiveEvent 16-21 – Reserved 22 URXEVT0 UART0ReceiveEvent 23 UTXEVT0 UART0TransmitEvent 24 URXEVT1 UART1ReceiveEvent 25 UTXEVT1 UART1TransmitEvent 26 – Reserved 27 – Reserved 28 ICREVT I2CReceiveEvent 29 ICXEVT I2CTransmitEvent 30-31 – Reserved 32 GPINT0 GPIO0Interrupt 33 GPINT1 GPIO1Interrupt 34 GPINT2 GPIO2Interrupt 35 GPINT3 GPIO3Interrupt 36 GPINT4 GPIO4Interrupt 37 GPINT5 GPIO5Interrupt 38 GPINT6 GPIO6Interrupt 39 GPINT7 GPIO7Interrupt 40 GPBNKINT0 GPIOBank0Interrupt 41 GPBNKINT1 GPIOBank1Interrupt 42 GPBNKINT2 GPIOBank2Interrupt 43 GPBNKINT3 GPIOBank3Interrupt 44 GPBNKINT4 GPIOBank4Interrupt 45 GPBNKINT5 GPIOBank5Interrupt 46 GPBNKINT6 GPIOBank6Interrupt 47 – Reserved 48 TEVTL0 Timer0EventLowInterrupt 49 TEVTH0 Timer0EventHighInterrupt 50 TEVTL1 Timer1EventLowInterrupt 51 TEVTH1 Timer1EvemtHighInterrupt 52 PWM0 PWM0Event 53 PWM1 PWM1Event 54 PWM2 PWM2Event 55-63 – Reserved 138 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.4.2 EDMA Peripheral Register Description(s) Table6-7liststheEDMAregisters,theircorrespondingacronyms,andDM6435devicememorylocations. Table6-7.DM6435EDMARegisters HEXADDRESS ACRONYM REGISTERNAME ChannelControllerRegisters 0x01C00000-0x01C00003 Reserved 0x01C00004 CCCFG EDMA3CCConfigurationRegister 0x01C00008-0x01C001FF Reserved GlobalRegisters 0x01C00200 QCHMAP0 QDMAChannel0MappingtoPaRAMRegister 0x01C00204 QCHMAP1 QDMAChannel1MappingtoPaRAMRegister 0x01C00208 QCHMAP2 QDMAChannel2MappingtoPaRAMRegister 0x01C0020C QCHMAP3 QDMAChannel3MappingtoPaRAMRegister 0x01C00210 QCHMAP4 QDMAChannel4MappingtoPaRAMRegister 0x01C00214 QCHMAP5 QDMAChannel5MappingtoPaRAMRegister 0x01C00218 QCHMAP6 QDMAChannel6MappingtoPaRAMRegister 0x01C0021C QCHMAP7 QDMAChannel7MappingtoPaRAMRegister 0x01C00240 DMAQNUM0 DMAQueueNumberRegister0(Channels00to07) 0x01C00244 DMAQNUM1 DMAQueueNumberRegister1(Channels08to15) 0x01C00248 DMAQNUM2 DMAQueueNumberRegister2(Channels16to23) 0x01C0024C DMAQNUM3 DMAQueueNumberRegister3(Channels24to31) 0x01C00250 DMAQNUM4 DMAQueueNumberRegister4(Channels32to39) 0x01C00254 DMAQNUM5 DMAQueueNumberRegister5(Channels40to47) 0x01C00258 DMAQNUM6 DMAQueueNumberRegister6(Channels48to55) 0x01C0025C DMAQNUM7 DMAQueueNumberRegister7(Channels56to63) 0x01C00260 QDMAQNUM CCQDMAQueueNumber 0x01C00264-0x01C00283 – Reserved 0x01C00284 QUEPRI QueuePriorityRegister 0x01C00288-0x01C002FF – Reserved 0x01C00300 EMR EventMissedRegister 0x01C00304 EMRH EventMissedRegisterHigh 0x01C00308 EMCR EventMissedClearRegister 0x01C0030C EMCRH EventMissedClearRegisterHigh 0x01C00310 QEMR QDMAEventMissedRegister 0x01C00314 QEMCR QDMAEventMissedClearRegister 0x01C00318 CCERR EDMA3CCErrorRegister 0x01C0031C CCERRCLR EDMA3CCErrorClearRegister 0x01C00320 EEVAL ErrorEvaluateRegister 0x01C00340 DRAE0 DMARegionAccessEnableRegisterforRegion0 0x01C00344 DRAEH0 DMARegionAccessEnableRegisterHighforRegion0 0x01C00348 DRAE1 DMARegionAccessEnableRegisterforRegion1 0x01C0034C DRAEH1 DMARegionAccessEnableRegisterHighforRegion1 0x01C00350 – Reserved 0x01C00354 – Reserved 0x01C00358 – Reserved 0x01C0035C – Reserved 0x01C00360-0x01C0037C – Reserved 0x01C00380 QRAE0 QDMARegionAccessEnableRegisterforRegion0 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 139

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C00384 QRAE1 QDMARegionAccessEnableRegisterforRegion1 0x01C00388 – Reserved 0x01C0038C – Reserved 0x01C00390-0x01C0039C – Reserved 0x01C00400 Q0E0 EventQ0Entry0Register 0x01C00404 Q0E1 EventQ0Entry1Register 0x01C00408 Q0E2 EventQ0Entry2Register 0x01C0040C Q0E3 EventQ0Entry3Register 0x01C00410 Q0E4 EventQ0Entry4Register 0x01C00414 Q0E5 EventQ0Entry5Register 0x01C00418 Q0E6 EventQ0Entry6Register 0x01C0041C Q0E7 EventQ0Entry7Register 0x01C00420 Q0E8 EventQ0Entry8Register 0x01C00424 Q0E9 EventQ0Entry9Register 0x01C00428 Q0E10 EventQ0Entry10Register 0x01C0042C Q0E11 EventQ0Entry11Register 0x01C00430 Q0E12 EventQ0Entry12Register 0x01C00434 Q0E13 EventQ0Entry13Register 0x01C00438 Q0E14 EventQ0Entry14Register 0x01C0043C Q0E15 EventQ0Entry15Register 0x01C00440 Q1E0 EventQ1Entry0Register 0x01C00444 Q1E1 EventQ1Entry1Register 0x01C00448 Q1E2 EventQ1Entry2Register 0x01C0044C Q1E3 EventQ1Entry3Register 0x01C00450 Q1E4 EventQ1Entry4Register 0x01C00454 Q1E5 EventQ1Entry5Register 0x01C00458 Q1E6 EventQ1Entry6Register 0x01C0045C Q1E7 EventQ1Entry7Register 0x01C00460 Q1E8 EventQ1Entry8Register 0x01C00464 Q1E9 EventQ1Entry9Register 0x01C00468 Q1E10 EventQ1Entry10Register 0x01C0046C Q1E11 EventQ1Entry11Register 0x01C00470 Q1E12 EventQ1Entry12Register 0x01C00474 Q1E13 EventQ1Entry13Register 0x01C00478 Q1E14 EventQ1Entry14Register 0x01C0047C Q1E15 EventQ1Entry15Register 0x01C00480 Q2E0 EventQ2Entry0Register 0x01C00484 Q2E1 EventQ2Entry1Register 0x01C00488 Q2E2 EventQ2Entry2Register 0x01C0048C Q2E3 EventQ2Entry3Register 0x01C00490 Q2E4 EventQ2Entry4Register 0x01C00494 Q2E5 EventQ2Entry5Register 0x01C00498 Q2E6 EventQ2Entry6Register 0x01C0049C Q2E7 EventQ2Entry7Register 0x01C004A0 Q2E8 EventQ2Entry8Register 0x01C004A4 Q2E9 EventQ2Entry9Register 0x01C004A8 Q2E10 EventQ2Entry10Register 140 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C004AC Q2E11 EventQ2Entry11Register 0x01C004B0 Q2E12 EventQ2Entry12Register 0x01C004B4 Q2E13 EventQ2Entry13Register 0x01C004B8 Q2E14 EventQ2Entry14Register 0x01C004BC Q2E15 EventQ2Entry15Register 0x01C004C0-0x01C005FF Reserved 0x01C00600 QSTAT0 Queue0StatusRegister 0x01C00604 QSTAT1 Queue1StatusRegister 0x01C00608 QSTAT2 Queue2StatusRegister 0x01C0060C-0x01C0061F Reserved 0x01C00620 QWMTHRA QueueWatermarkThresholdARegisterforQ[2:0] 0x01C00624 – Reserved 0x01C00640 CCSTAT EDMA3CCStatusRegister 0x01C00644-0x01C00FFF Reserved GlobalChannelRegisters 0x01C01000 ER EventRegister 0x01C01004 ERH EventRegisterHigh 0x01C01008 ECR EventClearRegister 0x01C0100C ECRH EventClearRegisterHigh 0x01C01010 ESR EventSetRegister 0x01C01014 ESRH EventSetRegisterHigh 0x01C01018 CER ChainedEventRegister 0x01C0101C CERH ChainedEventRegisterHigh 0x01C01020 EER EventEnableRegister 0x01C01024 EERH EventEnableRegisterHigh 0x01C01028 EECR EventEnableClearRegister 0x01C0102C EECRH EventEnableClearRegisterHigh 0x01C01030 EESR EventEnableSetRegister 0x01C01034 EESRH EventEnableSetRegisterHigh 0x01C01038 SER SecondaryEventRegister 0x01C0103C SERH SecondaryEventRegisterHigh 0x01C01040 SECR SecondaryEventClearRegister 0x01C01044 SECRH SecondaryEventClearRegisterHigh 0x01C01048-0x01C0104F Reserved 0x01C01050 IER InterruptEnableRegister 0x01C01054 IERH InterruptEnableRegisterHigh 0x01C01058 IECR InterruptEnableClearRegister 0x01C0105C IECRH InterruptEnableClearRegisterHigh 0x01C01060 IESR InterruptEnableSetRegister 0x01C01064 IESRH InterruptEnableSetRegisterHigh 0x01C01068 IPR InterruptPendingRegister 0x01C0106C IPRH InterruptPendingRegisterHigh 0x01C01070 ICR InterruptClearRegister 0x01C01074 ICRH InterruptClearRegisterHigh 0x01C01078 IEVAL InterruptEvaluateRegister 0x01C01080 QER QDMAEventRegister 0x01C01084 QEER QDMAEventEnableRegister SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 141

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C01088 QEECR QDMAEventEnableClearRegister 0x01C0108C QEESR QDMAEventEnableSetRegister 0x01C01090 QSER QDMASecondaryEventRegister 0x01C01094 QSECR QDMASecondaryEventClearRegister 0x01C01098-0x01C01FFF Reserved ShadowRegion0ChannelRegisters 0x01C02000 ER EventRegister 0x01C02004 ERH EventRegisterHigh 0x01C02008 ECR EventClearRegister 0x01C0200C ECRH EventClearRegisterHigh 0x01C02010 ESR EventSetRegister 0x01C02014 ESRH EventSetRegisterHigh 0x01C02018 CER ChainedEventRegister 0x01C0201C CERH ChainedEventRegisterHigh 0x01C02020 EER EventEnableRegister 0x01C02024 EERH EventEnableRegisterHigh 0x01C02028 EECR EventEnableClearRegister 0x01C0202C EECRH EventEnableClearRegisterHigh 0x01C02030 EESR EventEnableSetRegister 0x01C02034 EESRH EventEnableSetRegisterHigh 0x01C02038 SER SecondaryEventRegister 0x01C0203C SERH SecondaryEventRegisterHigh 0x01C02040 SECR SecondaryEventClearRegister 0x01C02044 SECRH SecondaryEventClearRegisterHigh 0x01C02048-0x01C0204C - Reserved 0x01C02050 IER InterruptEnableRegister 0x01C02054 IERH InterruptEnableRegisterHigh 0x01C02058 IECR InterruptEnableClearRegister 0x01C0205C IECRH InterruptEnableClearRegisterHigh 0x01C02060 IESR InterruptEnableSetRegister 0x01C02064 IESRH InterruptEnableSetRegisterHigh 0x01C02068 IPR InterruptPendingRegister 0x01C0206C IPRH InterruptPendingRegisterHigh 0x01C02070 ICR InterruptClearRegister 0x01C02074 ICRH InterruptClearRegisterHigh 0x01C02078 IEVAL InterruptEvaluateRegister 0x01C0207C - Reserved 0x01C02080 QER QDMAEventRegister 0x01C02084 QEER QDMAEventEnableRegister 0x01C02088 QEECR QDMAEventEnableClearRegister 0x01C0208C QEESR QDMAEventEnableSetRegister 0x01C02090 QSER QDMASecondaryEventRegister 0x01C02094 QSECR QDMASecondaryEventClearRegister 0x01C02098-0x01C021FC - Reserved ShadowRegion1ChannelRegisters 0x01C02200 ER EventRegister 0x01C02204 ERH EventRegisterHigh 142 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C02208 ECR EventClearRegister 0x01C0220C ECRH EventClearRegisterHigh 0x01C02210 ESR EventSetRegister 0x01C02214 ESRH EventSetRegisterHigh 0x01C02218 CER ChainedEventRegister 0x01C0221C CERH ChainedEventRegisterHigh 0x01C02220 EER EventEnableRegister 0x01C02224 EERH EventEnableRegisterHigh 0x01C02228 EECR EventEnableClearRegister 0x01C0222C EECRH EventEnableClearRegisterHigh 0x01C02230 EESR EventEnableSetRegister 0x01C02234 EESRH EventEnableSetRegisterHigh 0x01C02238 SER SecondaryEventRegister 0x01C0223C SERH SecondaryEventRegisterHigh 0x01C02240 SECR SecondaryEventClearRegister 0x01C02244 SECRH SecondaryEventClearRegisterHigh 0x01C02248-0x01C0224C - Reserved 0x01C02250 IER InterruptEnableRegister 0x01C02254 IERH InterruptEnableRegisterHigh 0x01C02258 IECR InterruptEnableClearRegister 0x01C0225C IECRH InterruptEnableClearRegisterHigh 0x01C02260 IESR InterruptEnableSetRegister 0x01C02264 IESRH InterruptEnableSetRegisterHigh 0x01C02268 IPR InterruptPendingRegister 0x01C0226C IPRH InterruptPendingRegisterHigh 0x01C02270 ICR InterruptClearRegister 0x01C02274 ICRH InterruptClearRegisterHigh 0x01C02278 IEVAL InterruptEvaluateRegister 0x01C0227C - Reserved 0x01C02280 QER QDMAEventRegister 0x01C02284 QEER QDMAEventEnableRegister 0x01C02288 QEECR QDMAEventEnableClearRegister 0x01C0228C QEESR QDMAEventEnableSetRegister 0x01C02290 QSER QDMASecondaryEventRegister 0x01C02294 QSECR QDMASecondaryEventClearRegister 0x01C02298-0x01C023FC - Reserved 0x01C02400-0x01C025FC - Reserved 0x01C02600-0x01C027FC - Reserved 0x01C02800-0x01C029FC - Reserved 0x01C02A00-0x01C02BFC - Reserved 0x01C02C00-0x01C02DFC - Reserved 0x01C02E00-0x01C02FFC - Reserved 0x01C02FFD-0x01C03FFF - Reserved 0x01C04000-0x01C04FFF - ParameterSetRAM(seeTable6-8) 0x01C05000-0x01C07FFF - Reserved 0x01C08000-0x01C0FFFF - Reserved TransferController0Registers SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 143

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C10000 - Reserved 0x01C10004 TCCFG EDMA3TC0ConfigurationRegister 0x01C10008-0x01C100FF - Reserved 0x01C10100 TCSTAT EDMA3TC0ChannelStatusRegister 0x01C10104-0x01C10110 - Reserved 0x01C10114-0x01C1011F - Reserved 0x01C10120 ERRSTAT EDMA3TC0ErrorStatusRegister 0x01C10124 ERREN EDMA3TC0ErrorEnableRegister 0x01C10128 ERRCLR EDMA3TC0ErrorClearRegister 0x01C1012C ERRDET EDMA3TC0ErrorDetailsRegister 0x01C10130 ERRCMD EDMA3TC0ErrorInterruptCommandRegister 0x01C10134-0x01C1013F - Reserved 0x01C10140 RDRATE EDMA3TC0ReadCommandRateRegister 0x01C10144-0x01C101FF - Reserved 0x01C10200-0x01C1023F - Reserved 0x01C10240 SAOPT EDMA3TC0SourceActiveOptionsRegister 0x01C10244 SASRC EDMA3TC0SourceActiveSourceAddressRegister 0x01C10248 SACNT EDMA3TC0SourceActiveCountRegister 0x01C1024C SADST EDMA3TC0SourceActiveDestinationAddressRegister 0x01C10250 SABIDX EDMA3TC0ActiveB-IndexRegister 0x01C10254 SAMPPRXY EDMA3TC0SourceActiveMemoryProtectionProxyRegister 0x01C10258 SACNTRLD EDMA3TC0SourceActiveCountReloadRegister 0x01C1025C SASRCBREF EDMA3TC0SourceActiveSourceAddressB-ReferenceRegister 0x01C10260 SADSTBREF EDMA3TC0SourceActiveDestinationAddressB-ReferenceRegister 0x01C10264-0x01C1027F - Reserved 0x01C10280 DFCNTRLD EDMA3TC0DestinationFIFOSetCountReloadRegister 0x01C10284 DFSRCBREF EDMA3TC0DestinationFIFOSetSourceAddressB-ReferenceRegister EDMA3TC0DestinationFIFOSetDestinationAddressB-Reference 0x01C10288 DFDSTBREF Register 0x01C1028C-0x01C102FF - Reserved 0x01C10300 DFOPT0 EDMA3TC0DestinationFIFOOptionsRegister0 0x01C10304 DFSRC0 EDMA3TC0DestinationFIFOSourceAddressRegister0 0x01C10308 DFCNT0 EDMA3TC0DestinationFIFOCountRegister0 0x01C1030C DFDST0 EDMA3TC0DestinationFIFODestinationAddressRegister0 0x01C10310 DFBIDX0 EDMA3TC0DestinationFIFOB-IndexRegister0 0x01C10314 DFMPPRXY0 EDMA3TC0DestinationFIFOMemoryProtectionProxyRegister0 0x01C10318-0x01C1033F - Reserved 0x01C10340 DFOPT1 EDMA3TC0DestinationFIFOOptionsRegister1 0x01C10344 DFSRC1 EDMA3TC0DestinationFIFOSourceAddressRegister1 0x01C10348 DFCNT1 EDMA3TC0DestinationFIFOCountRegister1 0x01C1034C DFDST1 EDMA3TC0DestinationFIFODestinationAddressRegister1 0x01C10350 DFBIDX1 EDMA3TC0DestinationFIFOB-IndexRegister1 0x01C10354 DFMPPRXY1 EDMA3TC0DestinationFIFOMemoryProtectionProxyRegister1 0x01C10358-0x01C1037F - Reserved 0x01C10380 DFOPT2 EDMA3TC0DestinationFIFOOptionsRegister2 0x01C10384 DFSRC2 EDMA3TC0DestinationFIFOSourceAddressRegister2 0x01C10388 DFCNT2 EDMA3TC0DestinationFIFOCountRegister2 144 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C1038C DFDST2 EDMA3TC0DestinationFIFODestinationAddressRegister2 0x01C10390 DFBIDX2 EDMA3TC0DestinationFIFOB-IndexRegister2 0x01C10394 DFMPPRXY2 EDMA3TC0DestinationFIFOMemoryProtectionProxyRegister2 0x01C10398-0x01C103BF - Reserved 0x01C103C0 DFOPT3 EDMA3TC0DestinationFIFOOptionsRegister3 0x01C103C4 DFSRC3 EDMA3TC0DestinationFIFOSourceAddressRegister3 0x01C103C8 DFCNT3 EDMA3TC0DestinationFIFOCountRegister3 0x01C103CC DFDST3 EDMA3TC0DestinationFIFODestinationAddressRegister3 0x01C103D0 DFBIDX3 EDMA3TC0DestinationFIFOB-IndexRegister3 0x01C103D4 DFMPPRXY3 EDMA3TC0DestinationFIFOMemoryProtectionProxyRegister3 0x01C103D8-0x01C103FF - Reserved TransferController1Registers 0x01C10400 - Reserved 0x01C10404 TCCFG EDMA3TC1ConfigurationRegister 0x01C10408-0x01C104FF - Reserved 0x01C10500 TCSTAT EDMA3TC1ChannelStatusRegister 0x01C10504-0x01C10510 - Reserved 0x01C10514-0x01C1051F - Reserved 0x01C10520 ERRSTAT EDMA3TC1ErrorStatusRegister 0x01C10524 ERREN EDMA3TC1ErrorEnableRegister 0x01C10528 ERRCLR EDMA3TC1ErrorClearRegister 0x01C1052C ERRDET EDMA3TC1ErrorDetailsRegister 0x01C10530 ERRCMD EDMA3TC1ErrorInterruptCommandRegister 0x01C10534-0x01C1053F - Reserved 0x01C10540 RDRATE EDMA3TC1ReadCommandRateRegister 0x01C10544-0x01C105FF - Reserved 0x01C10600-0x01C1063F - Reserved 0x01C10640 SAOPT EDMA3TC1SourceActiveOptionsRegister 0x01C10644 SASRC EDMA3TC1SourceActiveSourceAddressRegister 0x01C10648 SACNT EDMA3TC1SourceActiveCountRegister 0x01C1064C SADST EDMA3TC1SourceActiveDestinationAddressRegister 0x01C10650 SABIDX EDMA3TC1ActiveB-IndexRegister 0x01C10654 SAMPPRXY EDMA3TC1SourceActiveMemoryProtectionProxyRegister 0x01C10658 SACNTRLD EDMA3TC1SourceActiveCountReloadRegister 0x01C1065C SASRCBREF EDMA3TC1SourceActiveSourceAddressB-ReferenceRegister 0x01C10660 SADSTBREF EDMA3TC1SourceActiveDestinationAddressB-ReferenceRegister 0x01C10664-0x01C1067F - Reserved 0x01C10680 DFCNTRLD EDMA3TC1DestinationFIFOSetCountReloadRegister 0x01C10684 DFSRCBREF EDMA3TC1DestinationFIFOSetSourceAddressB-ReferenceRegister EDMA3TC1DestinationFIFOSetDestinationAddressB-Reference 0x01C10688 DFDSTBREF Register 0x01C1068C-0x01C106FF - Reserved 0x01C10700 DFOPT0 EDMA3TC1DestinationFIFOOptionsRegister0 0x01C10704 DFSRC0 EDMA3TC1DestinationFIFOSourceAddressRegister0 0x01C10708 DFCNT0 EDMA3TC1DestinationFIFOCountRegister0 0x01C1070C DFDST0 EDMA3TC1DestinationFIFODestinationAddressRegister0 0x01C10710 DFBIDX0 EDMA3TC1DestinationFIFOB-IndexRegister0 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 145

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C10714 DFMPPRXY0 EDMA3TC1DestinationFIFOMemoryProtectionProxyRegister0 0x01C10718-0x01C1073F - Reserved 0x01C10740 DFOPT1 EDMA3TC1DestinationFIFOOptionsRegister1 0x01C10744 DFSRC1 EDMA3TC1DestinationFIFOSourceAddressRegister1 0x01C10748 DFCNT1 EDMA3TC1DestinationFIFOCountRegister1 0x01C1074C DFDST1 EDMA3TC1DestinationFIFODestinationAddressRegister1 0x01C10750 DFBIDX1 EDMA3TC1DestinationFIFOB-IndexRegister1 0x01C10754 DFMPPRXY1 EDMA3TC1DestinationFIFOMemoryProtectionProxyRegister1 0x01C10758-0x01C1077F - Reserved 0x01C10780 DFOPT2 EDMA3TC1DestinationFIFOOptionsRegister2 0x01C10784 DFSRC2 EDMA3TC1DestinationFIFOSourceAddressRegister2 0x01C10788 DFCNT2 EDMA3TC1DestinationFIFOCountRegister2 0x01C1078C DFDST2 EDMA3TC1DestinationFIFODestinationAddressRegister2 0x01C10790 DFBIDX2 EDMA3TC1DestinationFIFOB-IndexRegister2 0x01C10794 DFMPPRXY2 EDMA3TC1DestinationFIFOMemoryProtectionProxyRegister2 0x01C10798-0x01C107BF - Reserved 0x01C107C0 DFOPT3 EDMA3TC1DestinationFIFOOptionsRegister3 0x01C107C4 DFSRC3 EDMA3TC1DestinationFIFOSourceAddressRegister3 0x01C107C8 DFCNT3 EDMA3TC1DestinationFIFOCountRegister3 0x01C107CC DFDST3 EDMA3TC1DestinationFIFODestinationAddressRegister3 0x01C107D0 DFBIDX3 EDMA3TC1DestinationFIFOB-IndexRegister3 0x01C107D4 DFMPPRXY3 EDMA3TC1DestinationFIFOMemoryProtectionProxyRegister3 0x01C107D8-0x01C107FF - Reserved TransferController2Registers 0x01C10800 - Reserved 0x01C10804 TCCFG EDMA3TC2ConfigurationRegister 0x01C10808-0x01C108FF - Reserved 0x01C10900 TCSTAT EDMA3TC2ChannelStatusRegister 0x01C10904-0x01C10910 - Reserved 0x01C10914-0x01C1091F - Reserved 0x01C10920 ERRSTAT EDMA3TC2ErrorStatusRegister 0x01C10924 ERREN EDMA3TC2ErrorEnableRegister 0x01C10928 ERRCLR EDMA3TC2ErrorClearRegister 0x01C1092C ERRDET EDMA3TC2ErrorDetailsRegister 0x01C10930 ERRCMD EDMA3TC2ErrorInterruptCommandRegister 0x01C10934-0x01C1093F - Reserved 0x01C10940 RDRATE EDMA3TC2ReadCommandRateRegister 0x01C10944-0x01C109FF - Reserved 0x01C10A00-0x01C10A3F - Reserved 0x01C10A40 SAOPT EDMA3TC2SourceActiveOptionsRegister 0x01C10A44 SASRC EDMA3TC2SourceActiveSourceAddressRegister 0x01C10A48 SACNT EDMA3TC2SourceActiveCountRegister 0x01C10A4C SADST EDMA3TC2SourceActiveDestinationAddressRegister 0x01C10A50 SABIDX EDMA3TC2ActiveB-IndexRegister 0x01C10A54 SAMPPRXY EDMA3TC2SourceActiveMemoryProtectionProxyRegister 0x01C10A58 SACNTRLD EDMA3TC2SourceActiveCountReloadRegister 0x01C10A5C SASRCBREF EDMA3TC2SourceActiveSourceAddressB-ReferenceRegister 146 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-7.DM6435EDMARegisters (continued) HEXADDRESS ACRONYM REGISTERNAME 0x01C10A60 SADSTBREF EDMA3TC2SourceActiveDestinationAddressB-ReferenceRegister 0x01C10A64-0x01C10A7F - Reserved 0x01C10A80 DFCNTRLD EDMA3TC2DestinationFIFOSetCountReloadRegister 0x01C10A84 DFSRCBREF EDMA3TC2DestinationFIFOSetSourceAddressB-ReferenceRegister EDMA3TC2DestinationFIFOSetDestinationAddressB-Reference 0x01C10A88 DFDSTBREF Register 0x01C10A8C-0x01C10AFF - Reserved 0x01C10B00 DFOPT0 EDMA3TC2DestinationFIFOOptionsRegister0 0x01C10B04 DFSRC0 EDMA3TC2DestinationFIFOSourceAddressRegister0 0x01C10B08 DFCNT0 EDMA3TC2DestinationFIFOCountRegister0 0x01C10B0C DFDST0 EDMA3TC2DestinationFIFODestinationAddressRegister0 0x01C10B10 DFBIDX0 EDMA3TC2DestinationFIFOB-IndexRegister0 0x01C10B14 DFMPPRXY0 EDMA3TC2DestinationFIFOMemoryProtectionProxyRegister0 0x01C10B18-0x01C10B3F - Reserved 0x01C10B40 DFOPT1 EDMA3TC2DestinationFIFOOptionsRegister1 0x01C10B44 DFSRC1 EDMA3TC2DestinationFIFOSourceAddressRegister1 0x01C10B48 DFCNT1 EDMA3TC2DestinationFIFOCountRegister1 0x01C10B4C DFDST1 EDMA3TC2DestinationFIFODestinationAddressRegister1 0x01C10B50 DFBIDX1 EDMA3TC2DestinationFIFOB-IndexRegister1 0x01C10B54 DFMPPRXY1 EDMA3TC2DestinationFIFOMemoryProtectionProxyRegister1 0x01C10B58-0x01C10B7F - Reserved 0x01C10B80 DFOPT2 EDMA3TC2DestinationFIFOOptionsRegister2 0x01C10B84 DFSRC2 EDMA3TC2DestinationFIFOSourceAddressRegister2 0x01C10B88 DFCNT2 EDMA3TC2DestinationFIFOCountRegister2 0x01C10B8C DFDST2 EDMA3TC2DestinationFIFODestinationAddressRegister2 0x01C10B90 DFBIDX2 EDMA3TC2DestinationFIFOB-IndexRegister2 0x01C10B94 DFMPPRXY2 EDMA3TC2DestinationFIFOMemoryProtectionProxyRegister2 0x01C10B98-0x01C10BBF - Reserved 0x01C10BC0 DFOPT3 EDMA3TC2DestinationFIFOOptionsRegister3 0x01C10BC4 DFSRC3 EDMA3TC2DestinationFIFOSourceAddressRegister3 0x01C10BC8 DFCNT3 EDMA3TC2DestinationFIFOCountRegister3 0x01C10BCC DFDST3 EDMA3TC2DestinationFIFODestinationAddressRegister3 0x01C10BD0 DFBIDX3 EDMA3TC2DestinationFIFOB-IndexRegister3 0x01C10BD4 DFMPPRXY3 EDMA3TC2DestinationFIFOMemoryProtectionProxyRegister3 0x01C10BD8-0x01C10BFF - Reserved Table 6-8 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-9 shows the parametersetentryregisterswithrelativememoryaddresslocationswithineachoftheparametersets. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 147

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-8.EDMAParameterSetRAM HEXADDRESSRANGE DESCRIPTION 0x01C04000-0x01C0401F ParametersSet0(832-bitwords) 0x01C04020-0x01C0403F ParametersSet1(832-bitwords) 0x01C04040-0x01C0405F ParametersSet2(832-bitwords) 0x01C04060-0x01C0407F ParametersSet3(832-bitwords) 0x01C04080-0x01C0409F ParametersSet4(832-bitwords) 0x01C040A0-0x01C040BF ParametersSet5(832-bitwords) ... ... 0x01C04FC0-0x01C04FDF ParametersSet126(832-bitwords) 0x01C04FE0-0x01C04FFF ParametersSet127(832-bitwords) Table6-9.ParameterSetEntries HEXOFFSETADDRESS ACRONYM PARAMETERENTRY WITHINTHEPARAMETERSET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT ACount,BCount 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceBIndex,DestinationBIndex 0x0014 LINK_BCNTRLD LinkAddress,BCountReload 0x0018 SRC_DST_CIDX SourceCIndex,DestinationCIndex 0x001C CCNT CCount 148 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.5 Reset Theresetcontrollerdetectsthedifferenttypeofresetssupported on the DM6435 device and manages the distributionofthoseresetsthroughoutthedevice. The DM6435 device has several types of device-level global resets - power-on reset, warm reset, and max reset. Table 6-10 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. See Section 6.5.9, Reset Electrical Data/Timing, for more information on the effects of each resetonthePLLcontrollersandtheirclocks. Table6-10.Device-LevelGlobalResetTypes TYPE INITIATOR EFFECT(s) PORpin Globalchipreset(Coldreset).ActivatesthePORsignalonchip, whichresetstheentirechipincludingtheemulationlogic. Power-onReset Thepower-onreset(POR)pinmustbedrivenlowduringpower (POR) rampofthedevice. Devicebootandconfigurationpinarelatched. Resetseverythingexceptfortheemulationlogic.Emulatorstays WarmReset RESETpin aliveduringWarmReset. Devicebootandconfigurationpinarelatched. SameasaWarmReset,excepttheDM6435devicebootand MaxReset Emulator,WDTimer(Timer2) configurationpinsarenotre-latched. In addition to device-level global resets, the PSC provides the capability to cause local resets to peripheralsand/ortheCPU. 6.5.1 Power-on Reset (POR Pin) Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the emulationlogic.Power-onResetisalsoreferredtoasacoldresetsincethedeviceusually goes through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies havereachedtheirnormaloperatingconditions. If an external 27-MHz oscillator is used on the MXI/CLKIN pin, the source clock should also be running at the correct frequency prior to de-asserting the POR pin. Note:Adevicepower-upcycleisnotrequiredtoinitiateaPower-onReset. ThefollowingsequencemustbefollowedduringaPower-onReset. 1. WaitforthepowersuppliestoreachnormaloperatingconditionswhilekeepingthePORpinasserted (drivenlow). 2. WaitfortheinputclocksourcetobestablewhilekeepingthePORpinasserted(low). 3. Oncethepowersuppliesandtheinputclocksourcearestable,thePORpinmustremainasserted (low)foraminimumof12MXIcycles. WithinthelowperiodofthePORpin,thefollowinghappens: – Theresetsignalsflowtotheentirechip(includingtheemulationlogic),resettingthemoduleson chip. – ThePLLControllerclocksstartatthefrequencyoftheMXIclock.Theclocksarepropagated throughoutthechiptoresetthechipsynchronously.Bydefault,bothPLL1andPLL2areinreset andunlocked.ThePLLControllersdefaulttoPLLBypassMode. – TheRESETOUTpinstaysasserted(low),indicatingthedeviceisinreset. 4. ThePORpinmaynowbedeasserted(drivenhigh). When the POR pin is deasserted (high), the configuration pin values are latched and the PLL Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are stillinPLLBypassMode.Otherdeviceinitializationalsobegins. 5. Afterdeviceinitializationiscomplete,thePLLControllerspausethesystemclocksfor10cycles.Atthe endofthese10cycles,theRESETOUTpinisdeasserted(drivenhigh). Atthispoint: SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 149

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com – TheI/Opinsarecontrolledbythedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0andPINMUX1registers). – TheclockandresetofeachperipheralisdeterminedbythedefaultsettingsofthePowerandSleep Controller(PSC). – ThePLLControllersareoperatinginPLLBypassMode. – TheC64x+beginsexecutingfromDSPBOOTADDR(determinedbybootmodeselection). After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the UsingtheTMS320DM643xBootloaderApplicationReport(literaturenumberSPRAAG0). After the boot sequence, follow the software initialization sequence described in Section 3.8, Device InitializationSequenceAfterReset. 6.5.1.1 UsageofPORversusRESETPins PORandRESETareindependentresets. If the device needs to go through a power-up cycle, POR (not RESET) must be used to fully reset the device. In functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation for functional end-system is to use the POR pin for full device reset. If RESET pin is not needed, it can be pulledinactive(high)viaanexternalpullupresistor. In a debug system, it is typically desirable to allow the reset of the device without crashing an emulation session. In this case, the user can use the POR pin to achieve full device reset and use the RESET pin to achieveadebugreset—whichresetstheentiredeviceexceptemulationlogic. 6.5.1.2 LatchingBootandConfigurationPins Internal to the chip, the two device reset pins RESET and POR are logically AND’d together only for the purpose of latching device boot and configuration pins. The values on all device and boot configuration pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from low-to-high. 6.5.2 Warm Reset (RESET Pin) A Warm Reset is activated by driving the RESET pin active low. This resets everything in the device excepttheemulationlogic.Anemulatorsessionwillstayaliveduringwarmreset. For more information on POR vs. RESET usage, see Section 6.5.1.1, Usage of POR versus RESET Pins andSection6.5.1.2,LatchingBootandConfigurationPins. ThefollowingsequencemustbefollowedduringaWarmReset: 1. Powersuppliesandinputclocksourceshouldalreadybestable. 2. TheRESETpinmustbeasserted(low)foraminimumof12MXIcycles. WithinthelowperiodoftheRESETpin,thefollowinghappens: – Theresetsignalsflowtotheentirechipresettingallthemodulesonchip,excepttheemulation logic. – ThePLLControllersareresetthereby,switchingbacktoPLLBypassModeandresettingalltheir registerstodefaultvalues.BothPLL1andPLL2areplacedinresetandloselock. – TheRESETOUTpinbecomesasserted(low),indicatingthedeviceisinreset. 3. TheRESETpinmaynowbedeasserted(drivenhigh). When the RESET pin is deasserted (high), the configuration pin values are latched and the PLL Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are stillinPLLBypassMode.Otherdeviceinitializationalsobegins. 4. Afterdeviceinitializationiscomplete,thePLLControllerspausethesystemclocksfor10cycles.Atthe endofthese10cycles,theRESETOUTpinisdeasserted(drivenhigh). 150 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Atthispoint: – TheI/Opinsarecontrolledbythedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0andPINMUX1registers). – TheclockandresetofeachperipheralisdeterminedbythedefaultsettingsofthePowerandSleep Controller(PSC). – ThePLLControllersareoperatinginPLLBypassMode. – TheC64x+beginsexecutingfromDSPBOOTADDR(determinedbybootmodeselection). After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the UsingtheTMS320DM643xBootloaderApplicationReport(literaturenumberSPRAAG0)). After the boot sequence, follow the software initialization sequence described in Section 3.8, Device InitializationSequenceAfterReset. 6.5.3 Maximum Reset A Maximum (Max) Reset is initiated by the emulator or the watchdog timer (Timer 2). The effects are the same as a warm reset, except the device boot and configuration pins are not re-latched. The emulator initiates a maximum reset via the ICEPICK module. This ICEPICK initiated reset is non-maskable. When thewatchdogtimercounterreacheszero,thiswillalsoinitiateamaximumresettorecoverfroma runaway condition.ThewatchdogtimeoutresetconditionismaskediftheTIMERCTL.WDRSTbitisclearedto"0". To invoke the maximum reset via the ICEPICK module, the user can perform the following from the Code ComposerStudio™IDEmenu:Debugfi AdvancedResetsfi SystemReset ThisistheMaxResetsequence: 1. MaxResetisinitiatedbytheemulatororthewatchdogtimer. Duringthistime,thefollowinghappens: – Theresetsignalsflowtotheentirechipresettingallthemodulesonchipexcepttheemulation logic. – ThePLLControllersareresetthereby,switchingbacktoPLLBypassModeandresettingalltheir registerstodefaultvalues.BothPLL1andPLL2areplacedinresetandloselock. – TheRESETOUTpinbecomesasserted(low),indicatingthedeviceisinreset. 2. Afterdeviceinitializationiscomplete,thePLLControllerspausethesystemclocksfor10cycles.Atthe endofthese10cycles,theRESETOUTpinisdeasserted(drivenhigh). Atthispoint: – TheI/Opinsarecontrolledbythedefaultperipherals(defaultperipheralsaredeterminedby PINMUX0andPINMUX1registers). – TheclockandresetofeachperipheralisdeterminedbythedefaultsettingsofthePowerandSleep Controller(PSC). – ThePLLControllersareoperatinginPLLBypassMode. – TheC64x+beginsexecutingfromDSPBOOTADDR(determinedbybootmodeselection). After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched with a Max Reset, the previous values (as shown in the BOOTCFG register) are used to select the boot mode. For more details on the boot sequence, see the Using the TMS320DM643x Bootloader Application Report(literaturenumberSPRAAG0). After the boot sequence, follow the software initialization sequence described in Section 3.8, Device InitializationSequenceAfterReset. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 151

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.5.4 CPU Local Reset The C64x+ DSP CPU has an internal reset input that allows a host (HPI) to control it. This reset is configuredthrougharegisterbit(MDCTL[39].LRST)inthePowerSleepController(PSC)module. When in C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be accessible. For procedures on asserting and de-asserting CPU local reset by the host, see the TMS320DM643xDMPDSPSubsystemReferenceGuide(literaturenumberSPRU978). For information on peripheral selection at the rising edge of POR or RESET, see Section 3, Device Configurationsofthisdatamanual. 6.5.5 Peripheral Local Reset The user can configure the local reset and clock state of a peripheral through programming the PSC. Table 6-4, DM6435 LPSC Assignments identifies the LPSC numbers and the peripherals capable of being locally reset by the PSC. For more detailed information on the programming of these peripherals by the PSC,seetheTMS320DM643xDMPDSPSubsystemReferenceGuide(literaturenumberSPRU978). 6.5.6 Reset Priority If any of the above reset sources occur simultaneously, the PLLC only processes the highest priority reset request.Theresetrequestprioritiesareasfollows(hightolow): • Power-onReset • MaximumReset • WarmReset • CPUReset 6.5.7 Reset Controller Register The Reset Type Status (RSTYPE) register (01C4 00E4) is the only register for the reset controller. This register falls in the same memory range as the PLL1 controller registers (see Table 6-18 for the PLL1 Controller Registers (including Reset Controller)). For more details on the RSTYPE register, see the TMS320DM643xDMPDSPSubsystemReferenceGuide(literaturenumberSPRU978). 6.5.8 Pin Behaviors at Reset During normal operations, pins are controlled by the respective peripheral selected in the PINMUX0 or PINMUX1register.Duringdevicelevelglobalreset,thepinbehavesasfollows: MultiplexedBootandConfigurationPins These pins are forced 3-stated when RESETOUT is asserted (low). This is to ensure the proper boot and configuration values can be latched on these multiplexed pins. This is particularly useful in the case where the boot and configuration values are driven by an external control device. After RESETOUT is deasserted(high),thesepinsarecontrolledbytheirrespectivedefaultperipheral. • BootandConfigurationPinsGroup:GP[28],GP[27],GP[26]/(FASTBOOT),GP[25]/(BOOTMODE3), GP[24]/(BOOTMODE2),GP[23]/(BOOTMODE1),GP[22]/(BOOTMODE0), EM_A[4]/GP[10]/(AEAW2/PLLMS2),EM_A[1]/(ALE)/GP[9]/(AEAW1/PLLMS1), EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0),EM_A[0]/GP[7]/(AEM2),EM_BA[0]/GP[6]/(AEM1),and EM_BA[1]/GP[5]/(AEM0). For information on whether external pullup/pulldown resistors should be used on the boot and configurationpins,seeSection3.9.1,Pullup/PulldownResistors. 152 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 DefaultPowerDownPins As discussed in Section 3.2, Power Considerations, the VDD3P3V_PWDN register controls power to the 3.3-V pins. The VDD3P3V_PWDN register defaults to powering down some 3.3-V pins to save power. For more details on the VDD3P3V_PWDN register and which 3.3-V pins default to powerup or powerdown, Section 3.2, Power Considerations. The pins that default to powerdown, are both reset to powerdown and high-impedance. They remain in that state until configured otherwise by VDD3P3_PWDN and PINMUX0/PINMUX1programming. • DefaultPowerDownPinGroup:GP[4]/PWM1,ACLKR0/CLKX0/GP[99],AFSR0/DR0/GP[100], AHCLKR0/CLKR0/GP[101],AXR0[3]/FSR0/GP[102],AXR0[2]/FSX0/GP[103],AXR0[1]/DX0/GP[104], AXR0/GP[105],ACLKX0/GP[106],AFSX0/GP[107],AHCLKX0/GP[108],AMUTEIN0/GP[109], AMUTE0/GP[110],HECC_TX/TOUT1L/UTXD1/GP[55],HECC_RX/TINP1L/URXD1/GP[56], CLKS0/TOUT0L/GP[97],TINP0L/GP[98],URXD0/GP[85],UTXD0/GP[86],UCTS0/GP[87],and URTS0/PWM0/GP[88]. AllOtherPins During RESETOUT assertion (low), all other pins are controlled by the default peripheral. The default peripheralisdeterminedbythedefaultsettingsofthePINMUX0orPINMUX1registers. Some of the PINMUX0/PINMUX1 settings are determined by configuration pins latched at reset. To determine the reset behavior of these pins, see Section 3.7, Multiplexed Pin Configurations and read the restofthethissubsectiontounderstandhowthatdefaultperipheralcontrolsthepin. The reset behaviors for all these other pins are categorized as follows (also see Figure 6-7 and Figure 6-8 inSection6.5.9,ResetElectricalData/Timing): • Z+/LowGroup(ZLonger-to-LowGroup):Thesepinsare3-statedwhendevice-levelglobalreset source(e.g.,POR,RESET,orMaxReset)isasserted.Thesepinsremain3-statedthroughout RESETOUTassertion.WhenRESETOUTisdeasserted,thesepinsdrivealogiclow. • Z+/HighGroup(ZLonger-to-HighGroup):Thesepinsare3-statedwhendevice-levelglobalreset source(e.g.,POR,RESET,orMaxReset)isasserted.Thesepinsremain3-statedthroughout RESETOUTassertion.WhenRESETOUTisdeasserted,thesepinsdrivealogichigh. • Z+/InvalidGroup(ZLonger-to-InvalidGroup):Thesepinsare3-statedwhendevice-levelglobal resetsource(e.g.,POR,RESET,orMaxReset)isasserted.Thesepinsremain3-statedthroughout RESETOUTassertion.WhenRESETOUTisdeasserted,thesepinsdriveaninvalidvalueuntil configuredotherwisebytheirrespectiveperipheral(aftertheperipheralisenabledbythePSC). • ZGroup:Thesepinsare3-statedbydefault,andthesepinsremain3-statedthroughoutRESETOUT assertion.WhenRESETOUTisdeasserted,thesepinsremain3-stateduntilconfiguredotherwiseby theirrespectiveperipheral(aftertheperipheralisenabledbythePSC). • LowGroup:Thesepinsarelowbydefault,andremainlowuntilconfiguredotherwisebytheir respectiveperipheral(aftertheperipheralisenabledbythePSC). • HighGroup:Thesepinsarehighbydefault,andremainhighuntilconfiguredotherwisebytheir respectiveperipheral(aftertheperipheralisenabledbythePSC). • Z/LowGroup(Z-to-LowGroup):Thesepinsare3-statedwhendevice-levelglobalresetsource(e.g., POR,RESET,orMaxReset)isasserted.Whentheresetsourceisdeasserted,thesepinsdrivea logiclow. • Z/HighGroup(Z-to-HighGroup):Thesepinsare3-statedwhendevice-levelglobalresetsource (e.g.,POR,RESET,orMaxReset)isasserted.Whenresetsourceisdeasserted,thesepinsdrivea logichigh. • ClockGroup:Theseclockpinsaretogglingbydefault.TheypausedmomentarilybeforeRESETOUT isdeasserted(high).TheonlypinintheClockGroupisCLKOUT0. Thisisalistofpossibledefaultperipheralsandhowtheycontrolthepinsduringreset: • GPIO:AllGPIOpinsbehaveaccordingtoZGroup. Note:ThefollowingEMIFAlistonlyincludespinsthatcandefaulttofunctionasEMIFAsignals. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 153

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com • EMIFA:TheseEMIFAsignalsaremultiplexedwithbootandconfigurationpins:EM_A[4],EM_A[2:0], EM_BA[0],EM_BA[1];therefore,theyareforced3-statedthroughoutRESETOUT. – Z+/LowGroup:EM_A[4],EM_A[2:0] – Z+/HighGroup:EM_BA[0],EM_BA[1],EM_OE,EM_WE – Z+/InvalidGroup:EM_D[7:0] – Z/LowGroup:EM_A[21:5],EM_A[3],EM_R/W – Z/HighGroup:EM_CS2 – ZGroup:EM_WAIT/(RDY/BSY) • DDR2MemoryController: – ClockGroup:DDR_CLK,DDR_CLK – DDR2ZGroup:DDR_DQM[3:0],DDR_DQS[3:0],DDR_D[31:0] – DDR2LowGroup:DDR_CKE,DDR_BA[2:0],DDR_A[12:0] – DDR2HighGroup:DDR_CS,DDR_WE,DDR_RAS,DDR_CAS • I2C:AllI2CpinsbehaveaccordingtoZGroup. • JTAG:TDO,EMU0,andEMU1pinsbehaveaccordingtoZGroup.TCK,TDI,TMS,andTRSTare input-onlypins. • Clock:CLKOUT0 For more information on the pin behaviors during device-level global reset, see Figure 6-7 and Figure 6-8 inSection6.5.9,ResetElectricalData/Timing. 6.5.9 Reset Electrical Data/Timing Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD) resistorshouldnotbereliedupon;TIrecommendstheuseofanexternalpullup/pulldownresistor. Table6-11.TimingRequirementsforReset(seeFigure6-7andFigure6-8) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Pulseduration,PORloworRESETlow 12C(1) ns w(RESET) 4 tsu(CONFIG) Shiegthu(p2)time,bootandconfigurationpinsvalidbeforePORhighorRESET 12C(1) ns Holdtime,bootandconfigurationpinsvalidafterPORhighorRESET 5 th(CONFIG) high(2) 0 ns (1) C=1/MXIclockfrequencyinns.Thedeviceclocksourcemustbestableandatavalidfrequencypriortomeetingthet w(RESET) requirement. (2) Forthelistofbootandconfigurationpins,seeTable2-5,BootTerminalFunctions. Table6-12.SwitchingCharacteristicsOverRecommendedOperatingConditionsDuringReset(1) (seeFigure6-8) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 2 t Delaytime,PORhighorRESEThightoRESETOUThigh 1900C ns d(RSTH-RSTOUTH) 3 t Pulseduration,SYSCLKspaused(low)beforeRESETOUThigh 10C 10C ns w(PAUSE) 6 t Delaytime,PORloworRESETlowtopinsinvalid 20 ns d(RSTL-IV) 7 t Delaytime,PORhighorRESEThightopinsvalid 20 ns d(RSTH-V) 8 t Delaytime,RESETOUThightopinsvalid 0 ns d(RSTOUTH-V) 9 t Delaytime,RESETOUThightopinsinvalid 12C ns d(RSTOUTH-IV) (1) C=1/CLKIN1clockfrequencyinns. 154 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Figure 6-7 shows the Power-Up Timing. Figure 6-8 shows the Warm Reset (RESET) Timing. Max Reset Timing is identical to Warm Reset Timing, except the boot and configuration pins are not relatched and theBOOTCFGregisterretainsitspreviousvaluelatchedbeforetheMaxResetwasinitiated. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 155

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Power Supplies Power Supplies Stable Ramping Clock Source Stable MXI(A) CLKOUT0 1 POR RESET 2 RESETOUT 3 SYSCLKREFCLK (PLLC1) SYSCLK1 SYSCLK2 SYSCLK3 4 5 8 Boot and Config Driven or Hi-Z Configuration Pins Hi-Z 8 Z+/Low Group (Z longer-to-low) Hi-Z 8 Z+/High Group (Z longer-to-low) Hi-Z 9 Z+/Invalid Group Invalid (Z longer-to-Invalid) Hi-Z Z Group 7 Z/Low Group (Z-to-low) 7 Z/High Group (Z-to-high) 7 DDR2 Z Group 7 DDR2 Low Group 7 DDR2 High Group A. PowersuppliesandMXImustbestablebeforethestartoft . W(RESET). B. Pinresetbehaviordependsonwhichperipheraldefaultstocontrollingthemultiplexedpin.Formoredetailsonwhat pingroup(e.g.,ZGroup,Z/LowGroup,Z/HighGroup,etc.)eachpinbelongsto,seeSection6.5.8,PinBehaviorsat Reset. Figure6-7.Power-UpTiming(B) 156 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Power Supplies Stable MXI CLKOUT0 POR 1 RESET 2 RESETOUT 3 SYSCLKREFCLK PLL1 Clock (PLLC1) SYSCLK1 Div1 Clock SYSCLK2 Div3 Clock SYSCLK3 Div6 Clock 6 4 5 8 Boot and Driven or Hi-Z Config Driven or Hi-Z Configuration Pins 8 Z+/Low Group (Z longer-to-low) 8 Z+/High Group (Z longer-to-high) 9 Z+/Invalid Group Invalid (Z longer-to-invalid) Z Group Driven or Hi-Z 6 7 Z/Low Group Driven or Hi-Z (Z-to-low) 6 7 Z/High Group Driven or Hi-Z (Z-to-high) 6 DDR2 Z Group 6 DDR2 Low Group 6 DDR2 High Group A. Pinresetbehaviordependsonwhichperipheraldefaultstocontrollingthemultiplexedpin.Formoredetailsonwhat pingroup(e.g.,ZGroup,Z/LowGroup,Z/HighGroup,etc.)eachpinbelongsto,seeSection6.5.8,PinBehaviorsat Reset. Figure6-8.WarmReset(RESET)Timing(A) SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 157

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.6 External Clock Input From MXI/CLKIN Pin TheDM6435deviceincludestwooptionstoprovideanexternalclockinput: • Useanon-chiposcillatorwithexternalcrystal. • Useanexternal1.8-VLVCMOS-compatibleclockinput. The optimal external clock input frequency is 27 MHz. Section 6.6.1 provides more details on Option 1, using an on-chip oscillator with external crystal. Section 6.6.2 provides details on Option 2, using an external1.8-VLVCMOS-compatibleclockinput. 6.6.1 Clock Input Option 1—Crystal Inthisoption,acrystalisusedastheexternalclockinputtotheDM6435. The 27-MHz oscillator provides the reference clock for all DM6435 subsystems and peripherals. The on-chip oscillator requires an external 27-MHz crystal connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 6-9. The external crystal load capacitors must be connected only to the 27-MHz oscillator ground pin (MXV ). Do not connect to board ground (V ). The MXV pin SS SS DD canbeconnectedtothesame1.8VpowersupplyasDV . DDR2 MXI/CLKIN MXO MXV MXV SS DD Crystal 27 MHz C1 C2 1.8 V Figure6-9.27-MHzSystemOscillator The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF). C in the equation is the load specified by the crystal manufacturer. All discrete L components used to implement the oscillator circuit should be placed as close as possible to the associatedoscillatorpins(MXIandMXO)andtotheMXV pin. SS C C C (cid:2) 1 2 L (C (cid:1)C ) 1 2 Table6-13. InputRequirementsforCrystal PARAMETER MIN TYP MAX UNIT Start-uptime(frompowerupuntiloscillatingatstablefrequencyof27 4 ms MHz) Oscillatonfrequency 27 MHz ESR 60 W FrequencyStability(1) – 50 ppm (1) Forvideoandaudioapplications,stabilityoftheinputclockisveryimportant.Theusershouldselectcrystalswithlowenoughppmto ensuregoodvideoandaudioqualityforthespecificapplication. 158 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.6.2 Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input Inthisoption,a1.8-VLVCMOS-CompatibleClockInputisusedastheexternalclockinputtotheDM6435. The external connections are shown in Figure 6-10. The MXI/CLKIN pin is connected to the 1.8-V LVCMOS-Compatible clock source. The MXO pin is left unconnected. The MXV pin is connected to SS boardground(V ).TheMXV pincanbeconnectedtothesame1.8-VpowersupplyasDV . SS DD DDR2 MXI/CLKIN MXO MXV MXV SS DD NC 1.8 V Figure6-10.1.8-VLVCMOS-CompatibleClockInput The clock source must meet the MXI/CLKIN timing requirements in Section 6.7.4, Clock PLL Electrical Data/Timing(InputandOutputClocks). SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 159

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.7 Clock PLLs TherearetwoindependentlycontrolledPLLsonDM6435.PLL1generatesthefrequenciesrequiredfor the DSP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the DDR2 interface.TherecommendedreferenceclockforbothPLLsisthe27-MHzcrystalinput. 6.7.1 PLL1 and PLL2 Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLL ). An PWR18 external EMI filter circuit must be added to PLL , as shown in Figure 6-11. The 1.8-V supply of the PWR18 EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O power-supply pins (DV ).TIrecommendsEMIfiltermanufacturerMurata,partnumberNFM18CC222R1C3. DDDR2 All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown in Figure 6-11. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1,C2,andtheEMIFilter). DM643x PLL1 +1.8 V PLLPWR18 C1 C2 EMI Filter 0.1 (cid:1)F 0.01 (cid:1)F PLL2 Figure6-11.PLL1andPLL2ExternalConnection The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, seeSection6.7.4,ClockPLLElectricalData/Timing(InputandOutputClocks). There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios might not be supported). For these constraints(ranges),seeTable6-14throughTable6-16. Table6-14.PLL1andPLL2MultiplierRanges PLLMULTIPLIER(PLLM) MIN MAX PLL1Multiplier x14 x30 PLL2Multiplier x14 x32 160 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-15.PLLC1ClockFrequencyRanges CLOCKSIGNALNAME MIN MAX UNIT MXI/CLKIN(1) 20 30 MHz PLLOUT -7devices 300 700 MHz CVDD=1.2V -6/-5/-4/-L/-Q6/-Q5/-Q4devices 300 600 MHz PLLOUT -7devices 300 520 MHz CVDD=1.05V -6/-5/-4/-L/-Q5devices 300 520 MHz -7devices 700 MHz -Q6devices 660 MHz SYSCLK1(2)(CLKDIV1Domain) -6/-Ldevices 600 MHz CV =1.2V DD -5/-Q5devices 500 MHz -4/-Q4devices 400 MHz -7devices 520 MHz SYSCLK1(2)(CLKDIV1Domain), -6/-Ldevices 450 MHz CVDD=1.05V -5/-Q5devices 400 MHz -4devices 350 MHz (1) MXI/CLKINinputclockisusedforbothPLLControllers(PLLC1andPLLC2). (2) Appliesto"tapeandreel"partnumbercounterpartsaswell.Formoreinformation,seeSection2.8, DeviceandDevelopment-SupportToolNomenclature. Table6-16.PLLC2ClockFrequencyRanges CLOCKSIGNALNAME MIN MAX UNIT MXI/CLKIN(1) 20 30 MHz At1.2-VCV 300 900 MHz DD PLLOUT At1.05-VCV 300 666 MHz DD PLL2_SYSCLK1(toDDR2PHY) 333 MHz (1) MXI/CLKINinputclockisusedforbothPLLControllers(PLLC1andPLLC2). BothPLL1andPLL2havestabilization,lock,andresettimingrequirementsthatmustbefollowed. The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0 transition). The PLL should not be operated until this stabilization time has expired. This stabilization step must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the PLLCTL.PLLPWRDNbitresetstoa"1".ForthePLLstabliziationtimevalue,seeTable6-17. The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0) beforebringingthePLLoutofreset(writingPLLRST=1).ForthePLLresettimevalue,seeTable6-17. The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the PLLlocktimevalue,seeTable6-17. Table6-17.PLL1andPLL2Stabilization,Lock,andResetTimes PLLSTABILIZATION/LOCK/RESET MIN TYP MAX UNIT TIME PLLStabilizationTime 150 m s PLLLockTime 2000C(1) ns PLLResetTime 128C(1) ns (1) C=CLKINcycletimeinns.Forexample,whenMXI/CLKINfrequencyis27MHz,useC=37.037ns. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 161

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com For details on the PLL initialization software sequence, see theTMS320DM643x DMP DSP Subsystem ReferenceGuide(literaturenumberSPRU978). For more information on the clock domains and their clock ratio restrictions, see Section 6.3.4, DM6435 PowerandClockDomains. 6.7.2 PLL Controller Register Description(s) A summary of the PLL controller registers is shown in Table 6-18. For more details, see the TMS320DM643xDMPDSPSubsystemReferenceGuide(literaturenumberSPRU978). Table6-18.PLLandResetControllerRegistersMemoryMap HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION ControllerRegisters 0x01C40800 PID PeripheralIDRegister 0x01C408E4 RSTYPE ResetTypeRegister 0x01C40900 PLLCTL PLLController1PLLControlRegister 0x01C40910 PLLM PLLController1PLLMultiplierControlRegister 0x01C40918 PLLDIV1 PLLController1Divider1Register(SYSCLK1) 0x01C4091C PLLDIV2 PLLController1Divider2Register(SYSCLK2) 0x01C40920 PLLDIV3 PLLController1Divider3Register(SYSCLK3) 0x01C40924 OSCDIV1 PLLController1OscillatorDivider1Register(OBSCLK)[CLKOUT0pin] 0x01C40928 – Reserved 0x01C4092C – Reserved 0x01C40938 PLLCMD PLLController1CommandRegister 0x01C4093C PLLSTAT PLLController1StatusRegister(ShowsPLLC1Status) PLLController1ClockAlignControlRegister 0x01C40940 ALNCTL (IndicatesWhichSYSCLKsNeedtobeAlignedforProperDeviceOperation) PLLController1PLLDIVDividerRatioChangeStatusRegister 0x01C40944 DCHANGE (IndicatesifSYSCLKDivideRatiohasBeenModified) 0x01C40948 CKEN PLLController1ClockEnableControlRegister 0x01C4094C CKSTAT PLLController1ClockStatusRegister(ForAllClocksExceptSYSCLKx) 0x01C40950 SYSTAT PLLController1SYSCLKStatusRegister(IndicatesSYSCLKon/offStatus) 0x01C40960 – Reserved 0x01C40964 – Reserved PLL2ControllerRegisters 0x01C40C00 PID PeripheralIDRegister 0x01C40D00 PLLCTL PLLController2PLLControlRegister 0x01C40D10 PLLM PLLController2PLLMultiplierControlRegister 0x01C40D18 PLLDIV1 PLLController2Divider1Register(SYSCLK1) 0x01C40D1C – Reserved 0x01C40D20-0x01C40D2C – Reserved 0x01C40D2C BPDIV PLLController2BypassDividerRegister(SYSCLKBP) 0x01C40D38 PLLCMD PLLController2CommandRegister 0x01C40D3C PLLSTAT PLLController2StatusRegister(ShowsPLLC2Status) PLLController2ClockAlignControlRegister 0x01C40D40 ALNCTL (IndicatesWhichSYSCLKsNeedtobeAlignedforProperDeviceOperation) PLLController2PLLDIVDividerRatioChangeStatusRegister 0x01C40D44 DCHANGE (IndicatesifSYSCLKDivideRatiohasBeenModified) 0x01C40D48 – Reserved 0x01C40D4C CKSTAT PLLController2ClockStatusRegister(ForAllClocksExceptSYSCLKx) 0x01C40D50 SYSTAT PLLController2SYSCLKStatusRegister(IndicatesSYSCLKon/offStatus) 162 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-18.PLLandResetControllerRegistersMemoryMap (continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C40D54-0x01C40FFF – Reserved 6.7.3 Clock PLL Considerations with External Clock Sources If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power both the DM6435 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 6.7.4, Clock PLL Electrical Data/Timing(InputandOutputClocks). Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature and Section 6.7.4, Clock PLL ElectricalData/Timing(InputandOutputClocks). SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 163

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.7.4 Clock PLL Electrical Data/Timing (Input and Output Clocks) Table6-19.TimingRequirementsforMXI/CLKIN (1)(2)(3)(4)(seeFigure6-12) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,MXI/CLKIN 33.3 50 ns c(MXI) 2 t Pulseduration,MXI/CLKINhigh 0.45C 0.55C ns w(MXIH) 3 t Pulseduration,MXI/CLKINlow 0.45C 0.55C ns w(MXIL) 4 t Transitiontime,MXI/CLKIN 0.05C ns t(MXI) 5 t Periodjitter,MXI/CLKIN 0.02C ns J(MXI) FrequencyStability – 50 ppm (1) TheMXI/CLKINfrequencyandPLLmultiplyfactorshouldbechosensuchthattheresultingclockfrequencyiswithinthespecificrange forCPUoperatingfrequency.Forexample,fora-6speeddevicewitha27MHzCLKINfrequency,thePLLmultiplyfactorshouldbe £ 22. (2) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. IL IH (3) FormoredetailsonthePLLmultiplierfactors,seetheTMS320DM63xDMPDSPSubsystemReferenceGuide(literaturenumber SPRU978). (4) C=CLKINcycletimeinns.Forexample,whenMXI/CLKINfrequencyis27MHz,useC=37.037ns. 5 1 4 2 MXI/CLKIN 3 4 Figure6-12.MXI/CLKINTiming Table6-20.SwitchingCharacteristicsOverRecommendedOperatingConditionsforCLKOUT0(1)(2) (seeFigure6-13) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,CLKOUT0 33.3 50 ns C 2 t Pulseduration,CLKOUT0high 0.45P 0.55P ns w(CLKOUT0H) 3 t Pulseduration,CLKOUT0low 0.45P 0.55P ns w(CLKOUT0L) 4 t Transitiontime,CLKOUT0 0.05P ns t(CLKOUT0) (1) ThereferencepointsfortheriseandfalltransitionsaremeasuredatV MAXandV MIN. OL OH (2) P=1/CLKOUT0clockfrequencyinnanoseconds(ns).Forexample,whenCLKOUT0frequencyis27MHz,useP=37.04ns. 2 1 4 CLK_OUT0 (Divide-by-1) 3 4 Figure6-13.CLKOUT0Timing 164 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.8 Interrupts The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-21. Also, the interrupt controller controls the generation of the CPU exception and emulation interrupts. The NMI input to the C64x+ DSP interrupt controller is not connected internally; therefore, the NMI interrupt is not available. Table6-22summarizestheC64x+ interrupt controller registers and memory locations. For more details on DSP interrupt controller, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature numberSPRU978). Table6-21.DM6435DSPSystemEventMapping DSP DSP SYSTEM ACRONYM SOURCE INTERRUPT ACRONYM SOURCE EVENT NUMBER NUMBER 0 EVT0 C64x+IntCtl0 64 GPIO0 GPIO 1 EVT1 C64x+IntCtl1 65 GPIO1 GPIO 2 EVT2 C64x+IntCtl2 66 GPIO2 GPIO 3 EVT3 C64x+IntCtl3 67 GPIO3 GPIO 4 TINTL0 Timer0–TINT12 68 GPIO4 GPIO 5 TINTH0 Timer0–TINT34 69 GPIO5 GPIO 6 TINTL1 Timer1–TINT12 70 GPIO6 GPIO 7 TINTH1 Timer1–TINT34 71 GPIO7 GPIO 8 WDINT Timer2–TINT12 72 GPIOBNK0 GPIO 9 EMU_DTDMA C64x+EMC 73 GPIOBNK1 GPIO 10 Reserved 74 GPIOBNK2 GPIO 11 EMU_RTDXRX C64x+RTDX 75 GPIOBNK3 GPIO 12 EMU_RTDXTX C64x+RTDX 76 GPIOBNK4 GPIO 13 IDMAINT0 C64x+EMC0 77 GPIOBNK5 GPIO 14 IDMAINT1 C64x+EMC1 78 GPIOBNK6 GPIO 15 Reserved 79 Reserved 16 Reserved 80 PWM0 PWM0 17 Reserved 81 PWM1 PWM1 18 Reserved 82 PWM2 PWM2 19 Reserved 83 IICINT0 I2C 20 Reserved 84 UARTINT0 UART0 21 Reserved 85 UARTINT1 UART1 22 Reserved 86 Reserved 23 Reserved 87 Reserved 24 VDINT0 VPSS–CCDC0 88 Reserved 25 VDINT1 VPSS–CCDC1 89 Reserved 26 VDINT2 VPSS–CCDC2 90 Reserved 27 HISTINT VPSS–Histogram 91 Reserved 28 H3AINT VPSS–AE/AWB/AF 92 Reserved 29 PRVUINT VPSS–Previewer 93 Reserved 30 RSZINT VPSS–Resizer 94 Reserved 31 Reserved 95 Reserved C64x+InterruptControllerDroppedCPU 32 Reserved 96 INTERR InterruptEvent 33 Reserved 97 EMC_IDMAERR C64x+EMCInvalidIDMAParameters 34 EDMA3CC_INTG EDMACCGlobalInterupt 98 Reserved 35 EDMA3CC_INT0 EDMACCInterruptRegion0 99 Reserved 36 EDMA3CC_INT1 EDMACCInterruptRegion1 100 Reserved 37 EDMA3CC_ERRINT EDMACCError 101 Reserved 38 EDMA3TC_ERRINT0 EDMATC0Error 102 Reserved 39 EDMA3TC_ERRINT1 EDMATC1Error 103 Reserved 40 EDMA3TC_ERRINT2 EDMATC2Error 104 Reserved 41 PSCINT PSCALLINT 105 Reserved 42 Reserved 106 Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 165

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-21.DM6435DSPSystemEventMapping (continued) DSP DSP SYSTEM ACRONYM SOURCE INTERRUPT ACRONYM SOURCE EVENT NUMBER NUMBER 43 EMACINT EMACMemoryController 107 Reserved 44 Reserved 108 Reserved 45 Reserved 109 Reserved 46 Reserved 110 Reserved 47 HPIINT HPI 111 Reserved 48 MBXINT0 McBSP0Transmit 112 Reserved 49 MBRINT0 McBSP0Receive 113 PMC_ED C64x+PMC 50 Reserved 114 Reserved 51 Reserved 115 Reserved 52 Reserved 116 UMCED1 C64x+UMC1 53 DDRINT DDR2MemoryController 117 UMCED2 C64x+UMC2 54 EMIFAINT EMIFA 118 PDCINT C64x+PDC 55 VLQINT VLYNQ 119 SYSCMPA C64x+SYS 56 Reserved 120 PMCCMPA C64x+PMC 57 HECC0INT HECCInterrupt0 121 PMCDMPA C64x+PMC 58 HECC1INT HECCInterrupt1 122 DMCCMPA C64x+DMC 59 AXINT0 McASP0Transmit 123 DMCDMPA C64x+DMC 60 ARINT0 McASP0Receive 124 UMCCMPA C64x+UMC 61 Reserved 125 UMCDMPA C64x+UMC 62 Reserved 126 EMCCMPA C64x+EMC 63 Reserved 127 EMCBUSERR C64x+EMC 166 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-22.C64x+InterruptControllerRegisters HEXADDRESS ACRONYM REGISTERDESCRIPTION 0x01800000 EVTFLAG0 Eventflagregister0 0x01800004 EVTFLAG1 Eventflagregister1 0x01800008 EVTFLAG2 Eventflagregister2 0x0180000C EVTFLAG3 Eventflagregister3 0x01800020 EVTSET0 Eventsetregister0 0x01800024 EVTSET1 Eventsetregister1 0x01800028 EVTSET2 Eventsetregister2 0x0180002C EVTSET3 Eventsetregister3 0x01800040 EVTCLR0 Eventclearregister0 0x01800044 EVTCLR1 Eventclearregister1 0x01800048 EVTCLR2 Eventclearregister2 0x0180004C EVTCLR3 Eventclearregister3 0x01800080 EVTMASK0 Eventmaskregister0 0x01800084 EVTMASK1 Eventmaskregister1 0x01800088 EVTMASK2 Eventmaskregister2 0x0180008C EVTMASK3 Eventmaskregister3 0x018000A0 MEVTFLAG0 Maskedeventflagregister0 0x018000A4 MEVTFLAG1 Maskedeventflagregister1 0x018000A8 MEVTFLAG2 Maskedeventflagregister2 0x018000AC MEVTFLAG3 Maskedeventflagregister3 0x018000C0 EXPMASK0 Exceptionmaskregister0 0x018000C4 EXPMASK1 Exceptionmaskregister1 0x018000C8 EXPMASK2 Exceptionmaskregister2 0x018000CC EXPMASK3 Exceptionmaskregister3 0x018000E0 MEXPFLAG0 Maskedexceptionflagregister0 0x018000E4 MEXPFLAG1 Maskedexceptionflagregister1 0x018000E8 MEXPFLAG2 Maskedexceptionflagregister2 0x018000EC MEXPFLAG3 Maskedexceptionflagregister3 0x01800104 INTMUX1 Interruptmuxregister1 0x01800108 INTMUX2 Interruptmuxregister2 0x0180010C INTMUX3 Interruptmuxregister3 0x01800180 INTXSTAT Interruptexceptionstatus 0x01800184 INTXCLR Interruptexceptionclear 0x01800188 INTDMASK Droppedinterruptmaskregister SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 167

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.9 External Memory Interface (EMIF) DM6435supportsseveralmemoryandexternaldeviceinterfaces,including: • AsynchronousEMIF(EMIFA)forinterfacingtoNORFlash,SRAM,etc. • NANDFlash 6.9.1 Asynchronous EMIF (EMIFA) TheDM6435AsynchronousEMIF (EMIFA) provides an 8-bit data bus, an address bus width up to 24-bits, and 4 chip selects, along with memory control signals. These signals are multiplexed between these peripherals: • EMIFAandNANDinterfaces • VPFE(CCDC) • GPIO 6.9.2 NAND (NAND, SmartMedia, xD) The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided and each are individually configurable to provide either EMIFA or NAND support. The NAND featuressupportedareasfollows. • NANDflashonupto4asynchronouschipselects. • 8-bitdatabuswidth • Programmablecycletimings. • PerformsECCcalculation. • NANDModealsosupportsSmartMediaandxDmemorycards • BootROMsupportsbootingoftheDM6435fromNANDflashlocatedatCS2 The memory map for EMIFA and NAND registers is shown in Table 6-23. For more details on the EMIFA and NAND interfaces, see Section 2.9, Documentation Support for the link to the TMS320DM643x DMP Peripherals Overview Reference Guide (literature number SPRU983) for the TMS320DM643x AsynchronousExternalMemoryInterface(EMIF)User'sGuide(literaturenumberSPRU984). 168 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-23.EMIFA/NANDRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01E00000 RCSR RevisionCodeandStatusRegister 0x01E00004 AWCCR AsynchronousWaitCycleConfigurationRegister 0x01E00008-0x01E0000F - Reserved 0x01E00010 A1CR Asynchronous1ConfigurationRegister(CS2Space) 0x01E00014 A2CR Asynchronous2ConfigurationRegister(CS3Space) 0x01E00018 A3CR Asynchronous3ConfigurationRegister(CS4Space) 0x01E0001C A4CR Asynchronous4ConfigurationRegister(CS5Space) 0x01E00020-0x01E0003F - Reserved 0x01E00040 EIRR EMIFInterruptRawRegister 0x01E00044 EIMR EMIFInterruptMaskRegister 0x01E00048 EIMSR EMIFInterruptMaskSetRegister 0x01E0004C EIMCR EMIFInterruptMaskClearRegister 0x01E00050-0x01E0005F - Reserved 0x01E00060 NANDFCR NANDFlashControlRegister 0x01E00064 NANDFSR NANDFlashStatusRegister 0x01E00070 NANDF1ECC NANDFlash1ECCRegister(CS2Space) 0x01E00074 NANDF2ECC NANDFlash2ECCRegister(CS3Space) 0x01E00078 NANDF3ECC NANDFlash3ECCRegister(CS4Space) 0x01E0007C NANDF4ECC NANDFlash4ECCRegister(CS5Space) 0x01E00080-0x01E00FFF - Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 169

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.9.3 EMIFA Electrical Data/Timing Table6-24.TimingRequirementsforAsynchronousMemoryCyclesforEMIFAModule(1) (seeFigure6-14andFigure6-15) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN NOM MAX READSandWRITES 2 t Pulseduration,EM_WAITassertionanddeassertion 2E ns w(EM_WAIT) READS 12 t Setuptime,EM_D[7:0]validbeforeEM_OEhigh 5 ns su(EMDV-EMOEH) 13 t Holdtime,EM_D[7:0]validafterEM_OEhigh 0 ns h(EMOEH-EMDIV) 14 tsu(EMWAIT- Setuptime,EM_WAITassertedbeforeEM_OEhigh(2) 4E+5 ns EMOEH) WRITES 28 tsu(EMWAIT- Setuptime,EM_WAITassertedbeforeEM_WEhigh(2) 4E+5 ns EMWEH) (1) E=SYSCLK3periodinnsforEMIFA.Forexample,whenrunningtheDSPCPUat600MHz,useE=10ns. (2) SetupbeforeendofSTROBEphase(ifnoextendedwaitstatesareinserted)bywhichEM_WAITmustbeassertedtoaddextended waitstates.Figure6-16andFigure6-17describeEMIFtransactionsthatincludeextendedwaitstatesinsertedduringtheSTROBE phase.However,cyclesinsertedaspartofthisextendedwaitperiodshouldnotbecounted;the4Erequirementistothestartofwhere theHOLDphasewouldbeginiftherewerenoextendedwaitcycles. 170 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-25.SwitchingCharacteristicsOverRecommendedOperatingConditionsforAsynchronous MemoryCyclesforEMIFAModule(1)(2)(seeFigure6-14andFigure6-15) -7/-6/-5/-4 NO PARAMETER -L/-Q6/-Q5/-Q4 UNIT . MIN NOM MAX READSandWRITES 1 t Turnaroundtime (TA+1)*E ns d(TURNAROUND) READS (RS+RST+RH+ 3 tc(EMRCYCLE) EMIFreadcycletime TA+4)*E(3) ns Outputsetuptime,EM_CS[5:2]lowto (RS+1)*E-4 (RS+1)*E+4 ns EM_OElow(SS=0) 4 t su(EMCSL-EMOEL) Outputsetuptime,EM_CS[5:2]lowto -4 4 ns EM_OElow(SS=1) Outputholdtime,EM_OEhighto (RH+1)*E-4 (RH+1)*E+4 ns EM_CS[5:2]high(SS=0) 5 t h(EMOEH-EMCSH) Outputholdtime,EM_OEhighto -4 4 ns EM_CS[5:2]high(SS=1) Outputsetuptime,EM_BA[1:0]validto 6 t (RS+1)*E-4 (RS+1)*E+4 ns su(EMBAV-EMOEL) EM_OElow Outputholdtime,EM_OEhighto 7 t (RH+1)*E-4 (RH+1)*E+4 ns h(EMOEH-EMBAIV) EM_BA[1:0]invalid Outputsetuptime,EM_A[21:0]validto 8 t (RS+1)*E-4 (RS+1)*E+4 ns su(EMBAV-EMOEL) EM_OElow Outputholdtime,EM_OEhighto 9 t (RH+1)*E-4 (RH+1)*E+4 ns h(EMOEH-EMBAIV) EM_A[21:0]invalid 10 t EM_OEactivelowwidth (RST+1)*E(3) ns w(EMOEL) DelaytimefromEM_WAITdeasserted 11 t 4E+4 ns d(EMWAITH-EMOEH) toEM_OEhigh WRITES (WS+WST+WH+ 15 tc(EMWCYCLE) EMIFwritecycletime TA+4)*E(3) ns Outputsetuptime,EM_CS[5:2]lowto (WS+1)*E-4 (WS+1)*E+4 ns EM_WElow(SS=0) 16 t su(EMCSL-EMWEL) Outputsetuptime,EM_CS[5:2]lowto -4 4 ns EM_WElow(SS=1) Outputholdtime,EM_WEhighto (WH+1)*E-4 (WH+1)*E+4 ns EM_CS[5:2]high(SS=0) 17 t h(EMWEH-EMCSH) Outputholdtime,EM_WEhighto -4 4 ns EM_CS[5:2]high(SS=1) Outputsetuptime,EM_R/Wvalidto 18 t (WS+1)*E-4 (WS+1)*E+4 ns su(EMRNW-EMWEL) EM_WElow Outputholdtime,EM_WEhighto 19 t (WH+1)*E-4 (WH+1)*E+4 ns h(EMWEH-EMRNW) EM_R/Winvalid Outputsetuptime,EM_BA[1:0]validto 20 t (WS+1)*E-4 (WS+1)*E+4 ns su(EMBAV-EMWEL) EM_WElow Outputholdtime,EM_WEhighto 21 t (WH+1)*E-4 (WH+1)*E+4 ns h(EMWEH-EMBAIV) EM_BA[1:0]invalid Outputsetuptime,EM_A[21:0]validto 22 t (WS+1)*E-4 (WS+1)*E+4 ns su(EMAV-EMWEL) EM_WElow Outputholdtime,EM_WEhighto 23 t (WH+1)*E-4 (WH+1)*E+4 ns h(EMWEH-EMAIV) EM_A[21:0]invalid (1) RS=Readsetup,RST=ReadSTrobe,RH=ReadHold,WS=WriteSetup,WST=WriteSTrobe,WH=WriteHold,TA=Turn Around,EW=ExtendWaitmode,SS=SelectStrobemode.TheseparametersareprogrammedviatheAsynchronousnConfiguration andAsynchronousWaitCycleConfigurationRegisters. (2) E=SYSCLK3periodinnsforEMIFA.Forexample,whenrunningtheDSPCPUat600MHz,useE=10ns. (3) WhenEW=1,theEMIFwillextendthestrobeperiodupto4,096additionalcycleswhentheEM_WAITpinisassertedbytheexternal device. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 171

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-25.SwitchingCharacteristicsOverRecommendedOperatingConditionsforAsynchronous MemoryCyclesforEMIFAModule(seeFigure6-14andFigure6-15) (continued) -7/-6/-5/-4 NO PARAMETER -L/-Q6/-Q5/-Q4 UNIT . MIN NOM MAX 24 t EM_WEactivelowwidth (WST+1)*E(3) ns w(EMWEL) DelaytimefromEM_WAITdeasserted 25 t 4E+4 ns d(EMWAITH-EMWEH) toEM_WEhigh Outputsetuptime,EM_D[7:0]validto 26 t (WS+1)*E-4 (WS+1)*E+4 ns su(EMDV-EMWEL) EM_WElow Outputholdtime,EM_WEhighto 27 t (WH+1)*E-4 (WH+1)*E+4 ns h(EMWEH-EMDIV) EM_D[7:0]invalid 3 1 EM_CS[5:2] EM_R/W EM_BA[1:0] EM_A[21:0] 4 5 8 9 6 7 10 EM_OE 13 12 EM_D[7:0] EM_WE Figure6-14.AsynchronousMemoryReadTimingforEMIF 172 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 15 1 EM_CS[5:2] EM_R/W EM_BA[1:0] EM_A[21:0] 16 17 18 19 20 21 24 22 23 EM_WE 27 26 EM_D[7:0] EM_OE Figure6-15.AsynchronousMemoryWriteTimingforEMIF EM_CS[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_BA[1:0] EM_A[21:0] EM_D[7:0] 14 11 EM_OE 2 2 EM_WAIT Asserted Deasserted Figure6-16.EM_WAITReadTimingRequirements SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 173

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com EM_CS[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_BA[1:0] EM_A[21:0] EM_D[7:0] 28 25 EM_WE 2 2 EM_WAIT Asserted Deasserted Figure6-17.EM_WAITWriteTimingRequirements 6.9.4 DDR2 Memory Controller The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM devices. For details on the DDR2 Memory Controller, see Section 2.9, Document Support for the link to the TMS320DM643x DMP Peripherals Overview Reference Guide (literature number SPRU983) for the TMS320C642x/DM643xDMPDDR2MemoryControllerUser'sGuide(literaturenumberSPRU986). DDR2 SDRAM plays a key role in a DaVinci-based system. Such a system is expected to require a significantamountofhigh-speedexternalmemoryfor: • Bufferingofinputimagedatafromsensorsorvideosources • Intermediatebufferingforprocessing/resizingofimagedataintheVPFE • Intermediate buffering for large raw Bayer data image files while performing image processing functions • Bufferingforintermediatedatawhileperformingvideoencodeanddecodefunctions • StorageofexecutablecodefortheDSP AmemorymapoftheDDR2MemoryControllerregistersisshowninTable6-26. Table6-26.DDR2MemoryControllerRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C4004C DDRVTPER DDR2VTPEnableRegister 0x01C42038 DDRVTPR DDR2VTPRegister 0x20000000-0x20000003 - Reserved 0x20000004 SDRSTAT SDRAMStatusRegister 0x20000008 SDBCR SDRAMBankConfigurationRegister 0x2000000C SDRCR SDRAMRefreshControlRegister 0x20000010 SDTIMR SDRAMTimingRegister 0x20000014 SDTIMR2 SDRAMTimingRegister2 0x20000020 PBBPR PeripheralBusBurstPriorityRegister 0x20000024-0x200000BF - Reserved 0x200000C0 IRR InterruptRawRegister 0x200000C4 IMR InterruptMaskedRegister 0x200000C8 IMSR InterruptMaskSetRegister 0x200000CC IMCR InterruptMaskClearRegister 174 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-26.DDR2MemoryControllerRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x200000D0-0x200000E3 - Reserved 0x200000E4 DDRPHYCR DDRPHYControlRegister 0x200000E8-0x200000EF - Reserved 0x200000F0 VTPIOCR DDRVTPIOControlRegister 0x200000F4-0x20007FFF - Reserved 6.9.4.1 DDR2MemoryControllerElectricalData/Timing The Implementing DDR2 PCB Layout on the TMS320DM643x DMP DMSoC Application Report (literature number SPRAAL6) specifies a complete DDR2 interface solution for the DM6435 as well as a list of compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2interfacetimingsinthissolutionaremet. TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout ontheTMS320DM643xDMPDMSoCApplicationReport(literaturenumberSPRAAL6). Table6-27.SwitchingCharacteristicsOverRecommendedOperatingConditionsforDDR2Memory Controller(1)(2)(seeFigure6-18) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,DDR_CLK 6 8 ns c(DDR_CLK) (1) DDR_CLKcycletime=2xPLL2_SYSCLK1cycletime. (2) ThePLL2ControllermustbeprogrammedsuchthattheresultingDDR_CLKclockfrequencyiswithinthespecifiedrange. 1 DDR_CLK Figure6-18.DDR2MemoryControllerClockTiming SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 175

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.10 Video Processing Sub-System (VPSS) Overview The DM6435 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.); the DM6435 VPSS doesnotsupportaVideoProcessingBackEnd(VPBE)outputinterface. TheVPSSregistermemorymappingisshowninTable6-28. Table6-28.VPSSRegisterDescriptions HEXADDRESSRANGE REGISTERACRONYM Description 0x01C73400 PID PeripheralRevisionandClassInformation 0x01C73404 PCR VPSSControlRegister 0x01C73408 - Reserved 0x01C73508 SDR_REG_EXP SDRAMNonReal-TimeReadRequestExpand 0x01C7350C- - Reserved 0x01C73FFF 6.10.1 Video Processing Front-End (VPFE) The Video Processing Front-End (VPFE) consists of the CCD Controller (CCDC), Preview Engine, Resizer, Hardware 3A (H3A) Statistic Generator, and Histogram blocks. Together, these modules provide DM6435withapowerfulandflexiblefront-endinterface.Thesemodulesarebrieflydescribedbelow: • TheCCDCprovidesaninterfacetoimagesensorsanddigitalvideosources. • ThePreviewEngineisaparameterizedhardwiredimageprocessingblockwhichisusedforconverting RAWcolordatafromaBayerpatterntoYUV4:2:2. • TheResizermodulere-sizestheinputimagedatatothedesireddisplayorvideoencodingresolution. • TheH3AmoduleprovidescontrolloopsforAutoFocus(AF),AutoWhiteBalance(AWB)andAuto Exposure(AE). • TheHistogrammodulebinsinputcolorpixels,dependingontheamplitude,andprovidesstatistics requiredtoimplementvarious3A(AE/AF/AWB)algorithmsandtunethefinalimage/videooutput. TheVPFEregistermemorymappingisshowninTable6-29. Table6-29.VPFERegisterAddressRangeDescriptions HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C70400–0x01C707FF CCDC VPFE–CCDController 0x01C70800–0x01C70BFF PREV VPFE–PreviewEngine/ImageSignalProcessor 0x01C70C00–0x01C709FF RESZ VPFE–Resizer 0x01C71000–0x01C713FF HIST VPFE–Histogram 0x01C71400–0x01C717FF H3A VPFE–Hardware3A(Auto-Focus/WB/Exposure) 0x01C73400–0x01C73FFF VPSS VPSSSharedBufferLogicRegisters 6.10.1.1 CCDController(CCDC) The CCDC receives raw image/video data from sensors (CMOS or CCD) or YUV video data in numerous formatsfromvideodecoderdevices.ThefollowingfeaturesaresupportedbytheCCDCmodule. • ConventionalBayerpatternformat. • GeneratesHD/VDtimingsignalsandfieldIDtoanexternaltiminggeneratororcansynchronizetoan externaltiminggenerator. • Interfacetoprogressiveandinterlacedsensors. • REC656/CCIR-656standard(YCbCr4:2:2format,either8-or16-bit). • YCbCr4:2:2format,either8-or16-bitwithdiscreteHandVSYNCsignals. • Upto16-bitinput. 176 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 • Opticalblackclampingsignalgeneration. • Shuttersignalcontrol. • Digitalclampingandblacklevelcompensation. • 10-bitto8-bitA-lawcompression. • Low-passfilterpriortowritingtoSDRAM.Ifthisfilterisenabled,2pixelseachintheleftandright edgesofeachlinearecroppedfromtheoutput. • Outputrangefrom16-bitsto8-bitswide(8-bitswideallowsfor50%savinginstoragearea). • Downsamplingviaprogrammablecullingpatterns. • ControloutputtotheDDR2viaanexternalwriteenablesignal. • Upto16Kpixels(imagesize)inboththehorizontalandverticaldirection. TheCCDCregistermemorymappingisshowninTable6-30. Table6-30.CCDCRegisterDescriptions HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C70400 PID PeripheralRevisionandClassInformation 0x01C70404 PCR PeripheralControlRegister 0x01C70408 SYN_MODE SYNCandModeSetRegister 0x01C7040C HD_VD_WID HDandVDSignalWidth 0x01C70410 PIX_LINES NumberofPixelsinaHorizontalLineandNumberofLinesinaFrame 0x01C70414 HORZ_INFO HorizontalPixelInformation 0x01C70418 VERT_START VerticalLine-SettingsfortheStartingPixel 0x01C7041C VERT_LINES NumberofVerticalLines 0x01C70420 CULLING CullingInformationinHorizontalandVerticalDirections 0x01C70424 HSIZE_OFF HorizontalSize 0x01C70428 SDOFST SDRAM/DDRAMLineOffset 0x01C7042C SDR_ADDR SDRAMAddress 0x01C70430 CLAMP OpticalBlackClampingSettings 0x01C70434 DCSUB DCClamp 0x01C70438 COLPTN CCDColorPattern 0x01C7043C BLKCMP BlackCompensation 0x01C70440 - Reserved 0x01C70444 - Reserved 0x01C70448 VDINT VDInterruptTiming 0x01C7044C ALAW A-LawSetting 0x01C70450 REC656IF REC656Interface 0x01C70454 CCDCFG CCDConfiguration 0x01C70458 FMTCFG DataReformatter/VideoPortConfiguration 0x01C7045C FMT_HORZ DataReformatter/VideoInputInterfaceHorizontalInformation 0x01C70460 FMT_VERT DataReformatter/VideoInputInterfaceVerticalInformation 0x01C70464 FMT_ADDR0 AddressPointer0Setup 0x01C70468 FMT_ADDR1 AddressPointer1Setup 0x01C7046C FMT_ADDR2 AddressPointer2Setup 0x01C70470 FMT_ADDR3 AddressPointer3Setup 0x01C70474 FMT_ADDR4 AddressPointer4Setup 0x01C70478 FMT_ADDR5 AddressPointer5Setup 0x01C7047C FMT_ADDR6 AddressPointer6Setup 0x01C70480 FMT_ADDR7 AddressPointer7Setup 0x01C70484 PRGEVEN_0 ProgramEntries0-7forEvenLine SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 177

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-30.CCDCRegisterDescriptions (continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C70488 RRGEVEN_1 ProgramEntries8-15forEvenLine 0x01C7048C PRGGODD_0 ProgramEntries0-7forOddLine 0x01C70490 PRGGODD_1 ProgramEntries8-15forOddLine 0x01C70494 VP_OUT VideoPortOutputSettings 6.10.1.2 PreviewEngine The preview engine transforms raw unprocessed image/video data from a sensor (CMOS or CCD) into YCbCr 4:2:2 data. The output of the preview engine is used for both video compression and external display devices such as a NTSC/PAL analog encoder or a digital LCD. The following features are supportedbythepreviewengine. • AcceptsconventionalBayerpatternformats. • Inputimage/videodatafromeithertheCCD/CMOScontrollerortheDDR2memory. • Outputwidthupto1280pixelswide. • Automatic/mandatorycroppingofpixels/lineswhenedgeprocessingisperformed.Ifallthe correspondingmodulesareenabled,atotalof14pixelsperline(7leftmostand7rightmost)and8 lines(4topmostand4bottommost)willnotbeoutput. • Simplehorizontalaveraging(byfactorsof2,4,or8)tohandleinputwidthsthataregreaterthan1280 (plusthecroppednumber)pixelswide. • DarkframecapturetoDDR2. • Darkframesubtractionforeveryinputrawdataframe,fetchedfromDDR2,pixel-by-pixeltoimprove videoquality. • Lensshadingcompensation.Eachinputpixelismultipliedwithacorresponding8-bitgainvalueand theresultisrightshiftedbyaprogrammableparameter(0-7bits). • A-lawdecompressiontotransformnon-linear8-bitdatato10-bitlineardata.Thisfeatureallowsdatain DDR2tobe8-bits,whichsaves50%oftheareaiftheinputtothepreviewengineisfromtheDDR2. • Horizontalmedianfilterforreducingtemperatureinducednoiseinpixels. • Programmablenoisefilterthatoperatesona3x3gridofthesamecolor(effectively,thisisafiveline storagerequirement). • Digitalgainandwhitebalance(colorseparategainforwhitebalance). • ProgrammableCFAinterpolationthatoperatesona5x5grid. • ConventionalBayerpatternRGBandcomplementarycolorsensors. • Supportforanimagethatisdownsampledby2xinthehorizontaldirection(withandwithoutphase correction).Inthiscase,theimageis2/3populatedinsteadoftheconventional1/3colors. • Supportforanimagethatisdownsampledby2xinboththehorizontalandverticaldirection.Inthis case,theimageisfullypopulatedinsteadoftheconventional1/3colors. • ProgrammableRGB-to-RGBblendingmatrix(9coefficientsforthe3x3matrix). • Fullyprogrammablegammacorrection(1024entriesforeachcolorheldinanon-chipRAM). • Programmablecolorconversion(RGBtoYUV)coefficients(9coefficientsforthe3x3matrix). • Luminanceenhancement(non-linear)andchrominancesuppression&offset. ThePreviewEngineregistermemorymappingisshowninTable6-31. Table6-31.PreviewEngineRegisterDescriptions HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C70800 PID PeripheralRevisionandClassInformation 0x01C70804 PCR PeripheralControlRegister 0x01C70808 HORZ_INFO HorizontalInformation/Setup 178 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-31.PreviewEngineRegisterDescriptions (continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C7080C VERT_INFO VerticalInformation/Setup 0x01C70810 RSDR_ADDR ReadAddressFromSDRAM 0x01C70814 RADR_OFFSET LineOffsetfortheReadData 0x01C70818 DSDR_ADDR DarkFrameAddressFromSDRAM 0x01C7081C DRKF_OFFSET LineOffsetfortheDarkFrameData 0x01C70820 WSDR_ADDR WriteAddresstotheSDRAM 0x01C70824 WADD_OFFSET LineOffsetfortheWriteData 0x01C70828 AVE InputFormatter/Averager 0x01C7082C HMED HorizontalMedianFilter 0x01C70830 NF NoiseFilter 0x01C70834 WB_DGAIN WhiteBalanceDigitalGain 0x01C70838 WBGAIN WhiteBalanceCoefficients 0x01C7083C WBSEL WhiteBalanceCoefficientsSelection 0x01C70840 CFA CFARegister 0x01C70844 BLKADJOFF BlackAdjustmentOffset 0x01C70848 RGB_MAT1 RGB2RGBBlendingMatrixCoefficients 0x01C7084C RGB_MAT2 RGB2RGBBlendingMatrixCoefficients 0x01C70850 RGB_MAT3 RGB2RGBBlendingMatrixCoefficients 0x01C70854 RGB_MAT4 RGB2RGBBlendingMatrixCoefficients 0x01C70858 RGB_MAT5 RGB2RGBBlendingMatrixCoefficients 0x01C7085C RGB_OFF1 RGB2RGBBlendingMatrixOffsets 0x01C70860 RGB_OFF2 RGB2RGBBlendingMatrixOffsets 0x01C70864 CSC0 ColorSpaceConversionCoefficients 0x01C70868 CSC1 ColorSpaceConversionCoefficients 0x01C7086C CSC2 ColorSpaceConversionCoefficients 0x01C70870 CSC_OFFSET ColorSpaceConversionOffsets 0x01C70874 CNT_BRT ContrastandBrightnessSettings 0x01C70878 CSUP ChrominanceSuppressionSettings 0x01C7087C SETUP_YC Maximum/MinimumYandCSettings 0x01C70880 SET_TBL_ADDRESS SetupTableAddresses 0x01C70884 SET_TBL_DATA SetupTableData 6.10.1.3 Resizer The resizer module can accept input image/video data from either the preview engine or DDR2. The outputoftheresizermoduleissenttoDDR2.Thefollowingfeaturesaresupportedbytheresizermodule. • Anoutputwidthupto1280horizontalpixels. • InputfromexternalDDR2. • Upto4xupsampling(digitalzoom). • Bi-cubicinterpolation(4-taphorizontal,4-tapvertical)canbeimplementedwiththeprogrammablefilter coefficients. • 8phasesoffiltercoefficients. • Optionalbi-linearinterpolationforthechrominancecomponents. • Upto1/4xdownsampling • 4-taphorizontaland4-tapverticalfiltercoefficients(with8-phases)for1xto1/2xdownsampling • 1/2xto1/4xdownsampling,for7-tapmodewith4-phases. • ResizingeitherYUV4:2:2packeddata(16-bits)orcolorseparatedata(8-bitdatawithinDDR)thatis contiguous. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 179

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com • Separate/independentresizingfactorforthehorizontalandverticaldirections. • Upsamplinganddownsamplingratiosthatareavailableare:256/N,withNrangingfrom64to1024. • Programmableluminancesharpeningafterthehorizontalresizingandbeforetheverticalresizingstep. TheResizerregistermemorymappingisshowninTable6-32. Table6-32.ResizerRegisterDescriptions HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C70C00 PID PeripheralRevisionandClassInformation 0x01C70C04 PCR PeripheralControlRegister 0x01C70C08 RSZ_CNT ResizerControlBits 0x01C70C0C OUT_SIZE OutputWidthandHeightAfterResizing 0x01C70C10 IN_START InputStartingInformation 0x01C70C14 IN_SIZE InputWidthandHeightBeforeResizing 0x01C70C18 SDR_INADD InputSDRAMAddress 0x01C70C1C SDR_INOFF SDRAMOffsetfortheInputLine 0x01C70C20 SDR_OUTADD OutputSDRAMAddress 0x01C70C24 SDR_OUTOFF SDRAMOffsetfortheOutputLine 0x01C70C28 HFILT10 HorizontalFilterCoefficients1and0 0x01C70C2C HFILT32 HorizontalFilterCoefficients3and2 0x01C70C30 HFILT54 HorizontalFilterCoefficients5and4 0x01C70C34 HFILT76 HorizontalFilterCoefficients7and6 0x01C70C38 HFILT98 HorizontalFilterCoefficients9and8 0x01C70C3C HFILT1110 HorizontalFilterCoefficients11and10 0x01C70C40 HFILT1312 HorizontalFilterCoefficients13and12 0x01C70C44 HFILT1514 HorizontalFilterCoefficients15and14 0x01C70C48 HFILT1716 HorizontalFilterCoefficients17and16 0x01C70C4C HFILT1918 HorizontalFilterCoefficients19and18 0x01C70C50 HFILT2120 HorizontalFilterCoefficients21and20 0x01C70C54 HFILT2322 HorizontalFilterCoefficients23and22 0x01C70C58 HFILT2524 HorizontalFilterCoefficients25and24 0x01C70C5C HFILT2726 HorizontalFilterCoefficients27and26 0x01C70C60 HFILT2928 HorizontalFilterCoefficients29and28 0x01C70C64 HFILT3130 HorizontalFilterCoefficients31and30 0x01C70C68 VFILT10 VerticalFilterCoefficients1and0 0x01C70C6C VFILT32 VerticalFilterCoefficients3and2 0x01C70C70 VFILT54 VerticalFilterCoefficients5and4 0x01C70C74 VFILT76 VerticalFilterCoefficients7and6 0x01C70C78 VFILT98 VerticalFilterCoefficients9and8 0x01C70C7C VFILT1110 VerticalFilterCoefficients11and10 0x01C70C80 VFILT1312 VerticalFilterCoefficients13and12 0x01C70C84 VFILT1514 VerticalFilterCoefficients15and14 0x01C70C88 VFILT1716 VerticalFilterCoefficients17and16 0x01C70C8C VFILT1918 VerticalFilterCoefficients19and18 0x01C70C90 VFILT2120 VerticalFilterCoefficients21and20 0x01C70C94 VFILT2322 VerticalFilterCoefficients23and22 0x01C70C98 VFILT2524 VerticalFilterCoefficients25and24 0x01C70C9C VFILT2726 VerticalFilterCoefficients27and26 0x01C70CA0 VFILT2928 VerticalFilterCoefficients29and28 0x01C70CA4 VFILT3130 VerticalFilterCoefficients31and30 180 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-32.ResizerRegisterDescriptions (continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C70CA8 YENH LuminanceEnhancer 6.10.1.4 Hardware3A(H3A) The Hardware 3A (H3A) module provides control loops for Auto Focus, Auto White Balance and Auto Exposure.Thereare2maincomponentsoftheH3Amodule: • AutoFocus(AF)Engine • AutoExposure(AE)&AutoWhiteBalance(AWB)Engine The AF engine extracts and filters the red, green, and blue data from the input image/video data and provides either the accumulation or peaks of the data in a specified region. The specified region is a two dimensionalblockofdataandisreferredtoasa“paxel”forthecaseofAF. The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a “window”. The number, dimensions, and starting position of the AF paxels and the AE/AWB windows are separately programmable. TheH3AregistermemorymappingisshowninTable6-33. Table6-33.H3ARegisterDescriptions HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C71400 PID PeripheralRevisionandClassInformation 0x01C71404 PCR PeripheralControlRegister 0x01C71408 AFPAX1 SetupfortheAFEnginePaxelConfiguration 0x01C7140C AFPAX2 SetupfortheAFEnginePaxelConfiguration 0x01C71410 AFPAXSTART StartPositionforAFEnginePaxels 0x01C71414 AFIIRSH StartPositionforIIRSH 0x01C71418 AFBUFST SDRAM/DDRAMStartAddressforAFEngine 0x01C7141C AFCOEF010 IIRFilterCoefficientDataforSET0 0x01C71420 AFCOEF032 IIRFilterCoefficientDataforSET0 0x01C71424 AFCOEFF054 IIRFilterCoefficientDataforSET0 0x01C71428 AFCOEFF076 IIRFilterCoefficientDataforSET0 0x01C7142C AFCOEFF098 IIRFilterCoefficientDataforSET0 0x01C71430 AFCOEFF0010 IIRFilterCoefficientDataforSET0 0x01C71434 AFCOEF110 IIRFilterCoefficientDataforSET1 0x01C71438 AFCOEF132 IIRFilterCoefficientDataforSET1 0x01C7143C AFCOEFF154 IIRFilterCoefficientDataforSET1 0x01C71440 AFCOEFF176 IIRFilterCoefficientDataforSET1 0x01C71444 AFCOEFF198 IIRFilterCoefficientDataforSET1 0x01C71448 AFCOEFF1010 IIRFilterCoefficientDataforSET1 0x01C7144C AEWWIN1 ConfigurationforAE/AWBWindows 0x01C71450 AEWINSTART StartPositionforAE/AWBWindows 0x01C71454 AEWINBLK StartPositionandHeightforBlackLineofAE/AWBWindows 0x01C71458 AEWSUBWIN ConfigurationforSubsampleDatainAE/AWBWindow 0x01C7145C AEWBUFST SDRAM/DDRAMStartAddressforAE/AWBEngine 6.10.1.4.1 AutoFocus(AF)Engine ThefollowingfeaturesaresupportedbytheAutoFocus(AF)Engine. • PeakModeinaPaxel(aPaxelisdefinedasatwodimensionalblockofpixels). • AccumulatethemaximumFocusValueofeachlineinaPaxel SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 181

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com • Accumulation/SumMode(insteadofPeakmode). • AccumulateFocusValueinaPaxel. • Upto36Paxelsinthehorizontaldirectionandupto128Paxelsintheverticaldirection. • ProgrammablewidthandheightforthePaxel.Allpaxelsintheframewillbeofsamesize. • Programmablered,green,andbluepositionwithina2x2matrix. • Separatehorizontalstartforpaxelandfiltering. • Programmableverticallineincrementswithinapaxel. • ParallelIIRfiltersconfiguredinadual-biquadconfigurationwithindividualcoefficients(2filterswith11 coefficientseach).Thefiltersareintendedtocomputethesharpness/peaksintheframetofocuson. 6.10.1.4.2 AutoExposure(AE)andAutoWhiteBalance(AWB)Engine ThefollowingfeaturesaresupportedbytheAutoExposure(AE)andAutoWhiteBalance(AWB)Engine. • Accumulateclippedpixelsalongwithallnon-saturatedpixels. • Upto36horizontalwindows. • Upto128verticalwindows. • Programmablewidthandheightforthewindows.Allwindowsintheframewillbeofsamesize. • Separateverticalstartcoordinateandheightforablackrowofpaxelsthatisdifferentthanthe remainingcolorpaxels. • ProgrammableHorizontalSamplingPointsinawindow. • ProgrammableVerticalSamplingPointsinawindow. 6.10.1.5 Histogram The histogram module accepts raw image/video data and bins the pixels on a value (and color separate) basis. The value of the pixel itself is not stored, but each bin contains the number of pixels that are within the appropriate set range. The source of the raw data for the histogram is typically a CCD/CMOS sensor (via the CCDC module) or optionally from DDR2. The following features are supported by the histogram module. • Uptofourregions/areas. • Separatehorizontal/verticalstartandendpositionforeachregion. • Pixelsfromoverlappingregionsareaccumulatedintothehighestpriorityregion.Thepriorityis:region0 >region1>region2>region3. • InterfacetoconventionalBayerpattern.Eachregioncanaccumulateeither3or4colors. • 32,64,128,or256binspercolorperregion. • 32,64,or128binspercolorfor2regions. • 32or64binspercolorfor3or4regions. • AutomaticclearofhistogramRAMafteranARMread. • Saturationofthepixelcountifthecountexceedsthemaximumvalue(eachmemorylocationis20-bit wide). • Downshiftrangingfrom0to7bits(maximumbinrange128). • Thelastbin(highestrangeofvalues)willaccumulateanyvaluethatishigherthanthelowerbound. TheHistogramregistermemorymappingisshowninTable6-34. Table6-34.HistogramRegisterDescriptions HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C71000 PID PeripheralRevisionandClassInformationRegister 0x01C71004 PCR PeripheralControlRegister 0x01C71008 HIST_CNT HistogramControlBitsRegister 0x01C7100C WB_GAIN White/ChannelBalanceSettingsRegister 182 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-34.HistogramRegisterDescriptions (continued) HEXADDRESSRANGE REGISTERACRONYM DESCRIPTION 0x01C71010 R0_HORZ Region0HorizontalInformationRegister 0x01C71014 R0_VERT Region0VerticalInformationRegister 0x01C71018 R1_HORZ Region1HorizontalInformationRegister 0x01C7101C R1_VERT Region1VerticalInformationRegister 0x01C71020 R2_HORZ Region2HorizontalInformationRegister 0x01C71024 R2_VERT Region2VerticalInformationRegister 0x01C71028 R3_HORZ Region3HorizontalInformationRegister 0x01C7102C R3_VERT Region3VerticalInformationRegister 0x01C71030 HIST_ADDR HistogramAddressforDatatobeReadRegister 0x01C71034 HIST_DATA HistogramDataThatisReadFromtheMemoryRegister 0x01C71038 RADD ReadAddressFromDDR2MemoryRegister 0x01C7103C RADD_OFF ReadAddressOffsetforEachLineintheDDR2MemoryRegister 0x01C71040 H_V_INFO Horizontal/VerticalInformationRegister(Horizontal/VerticalNumberof PixelsWhenDataisReadFromDDR2MemoryInformationRegister) SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 183

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.10.1.6 VPFEElectricalData/Timing Table6-35.TimingRequirementsforVPFEPCLKMaster/SlaveMode(1)(seeFigure6-19) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,PCLK 10.204 ns c(PCLK) 2 t Pulseduration,PCLKhigh 0.4P ns w(PCLKH) 3 t Pulseduration,PCLKlow 0.4P ns w(PCLKL) 4 t Transitiontime,PCLK 7 ns t(PCLK) (1) P=PCLKperiodinns. 2 3 1 PCLK 4 4 Figure6-19.VPFEPCLKTiming Table6-36.TimingRequirementsforVPFE(CCD)SlaveMode(1)(seeFigure6-20) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 5 t Setuptime,CCDvalidbeforePCLKedge 4.5 ns su(CCDV-PCLK) 6 t Holdtime,CCDvalidafterPCLKedge 1 ns h(PCLK-CCDV) 7 t Setuptime,HDvalidbeforePCLKedge 4.5 ns su(HDV-PCLK) 8 t Holdtime,HDvalidafterPCLKedge 1 ns h(PCLK-HDV) 9 t Setuptime,VDvalidbeforePCLKedge 4.5 ns su(VDV-PCLK) 10 t Holdtime,VDvalidafterPCLKedge 1 ns h(PCLK-VDV) 11 t Setuptime,C_WEvalidbeforePCLKedge 4.5 ns su(C_WEV-PCLK) 12 t Holdtime,C_WEvalidafterPCLKedge 1 ns h(PCLK-C_WEV) 13 t Setuptime,C_FIELDvalidbeforePCLKedge 4.5 ns su(C_FIELDV-PCLK) 14 t Holdtime,C_FIELDvalidafterPCLKedge 1 ns h(PCLK-C_FIELDV) (1) TheVPFEmaybeconfiguredtooperateineitherpositiveornegativeedgeclockingmode.Wheninpositiveedgeclockingmodethe risingedgeofPCLKisreferenced.WheninnegativeedgeclockingmodethefallingedgeofPCLKisreferenced. 184 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 8, 10 7, 9 HD/VD 11, 13 12, 14 C_WE/C_FIELD 5 6 CCD[15:0] Figure6-20.VPFE(CCD)SlaveModeInputDataTiming Table6-37.TimingRequirementsforVPFE(CCD)MasterMode(1)(seeFigure6-21) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 15 t Setuptime,CCDvalidbeforePCLKedge 4.5 ns su(CCDV-PCLK) 16 t Holdtime,CCDvalidafterPCLKedge 1 ns h(PCLK-CCDV) 23 t Setuptime,C_WEvalidbeforePCLKedge 4.5 ns su(CWEV-PCLK) 24 t Holdtime,C_WEvalidafterPCLKedge 1 ns h(PCLK-CWEV) (1) TheVPFEmaybeconfiguredtooperateineitherpositiveornegativeedgeclockingmode.Wheninpositiveedgeclockingmodethe risingedgeofPCLKisreferenced.WheninnegativeedgeclockingmodethefallingedgeofPCLKisreferenced. PCLK (Positive Edge Clocking) PCLK (Positive Edge Clocking) 15 16 CCD[15:0] 23 24 C_WE/C_FIELD Figure6-21.VPFE(CCD)MasterModeInputDataTiming SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 185

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-38.SwitchingCharacteristicsOverRecommendedOperatingConditionsforVPFE(CCD)Master Mode(1)(seeFigure6-22) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 18 t Delaytime,PCLKedgetoHDvalid 2 9.5 ns d(PCLK-HDV) 20 t Delaytime,PCLKedgetoVDvalid 2 9.5 ns d(PCLK-VDV) 22 t Delaytime,PCLKedgetoC_FIELDvalid 2 9.5 ns d(PCLK-C_FIELDV) (1) TheVPFEmaybeconfiguredtooperateineitherpositiveornegativeedgeclockingmode.Wheninpositiveedgeclockingmodethe risingedgeofPCLKisreferenced.WheninnegativeedgeclockingmodethefallingedgeofPCLKisreferenced. PCLK 18 HD 20 VD 22 C_FIELD Figure6-22.VPFE(CCD)MasterModeControlOutputDataTiming 186 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.11 Universal Asynchronous Receiver/Transmitter (UART) DM6435has2UARTperipherals.EachUARThasthefollowingfeatures: • 16-bytestoragespaceforboththetransmitterandreceiverFIFOs • 1,4,8,or14byteselectablereceiverFIFOtriggerlevelforautoflowcontrolandDMA • DMAsignalingcapabilityforbothreceivedandtransmitteddata • Programmableauto-rtsandauto-ctsforautoflowcontrol • Frequencypre-scalevaluesfrom1to65,535togenerateappropriatebaudrates • Prioritizedinterrupts • Programmableserialdataformats – 5,6,7,or8-bitcharacters – Even,odd,ornoparitybitgenerationanddetection – 1,1.5,or2stopbitgeneration • Falsestartbitdetection • Linebreakgenerationanddetection • Internaldiagnosticcapabilities – Loopbackcontrolsforcommunicationslinkfaultisolation – Break,parity,overrun,andframingerrorsimulation • Modemcontrolfunctions(CTS,RTS)onUART0only. TheUART0/1registersarelistedinTable6-39andTable6-40. 6.11.1 UART Peripheral Register Description(s) Table6-39.UART0RegisterDescriptions HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C20000 RBR UART0ReceiverBufferRegister(ReadOnly) 0x01C20000 THR UART0TransmitterHoldingRegister(WriteOnly) 0x01C20004 IER UART0InterruptEnableRegister 0x01C20008 IIR UART0InterruptIdentificationRegister(ReadOnly) 0x01C20008 FCR UART0FIFOControlRegister(WriteOnly) 0x01C2000C LCR UART0LineControlRegister 0x01C20010 MCR UART0ModemControlRegister 0x01C20014 LSR UART0LineStatusRegister 0x01C20018 - Reserved 0x01C2001C - Reserved 0x01C20020 DLL UART0DivisorLatch(LSB) 0x01C20024 DLH UART0DivisorLatch(MSB) 0x01C20028 PID1 PeripheralIdentificationRegister1 0x01C2002C PID2 PeripheralIdentificationRegister2 0x01C20030 PWREMU_MGMT UART0PowerandEmulationManagementRegister 0x01C20034-0x01C203FF - Reserved Table6-40.UART1RegisterDescriptions HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C20400 RBR UART1ReceiverBufferRegister(ReadOnly) 0x01C20400 THR UART1TransmitterHoldingRegister(WriteOnly) 0x01C20404 IER UART1InterruptEnableRegister SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 187

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-40.UART1RegisterDescriptions (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C20408 IIR UART1InterruptIdentificationRegister(ReadOnly) 0x01C20408 FCR UART1FIFOControlRegister(WriteOnly) 0x01C2040C LCR UART1LineControlRegister 0x01C20410 MCR UART1ModemControlRegister 0x01C20414 LSR UART1LineStatusRegister 0x01C20418 - Reserved 0x01C2041C - Reserved 0x01C20420 DLL UART1DivisorLatch(LSB) 0x01C20424 DLH UART1DivisorLatch(MSB) 0x01C20428 PID1 PeripheralIdentificationRegister1 0x01C2042C PID2 PeripheralIdentificationRegister2 0x01C20430 PWREMU_MGMT UART1PowerandEmulationManagementRegister 0x01C20434-0x01C207FF - Reserved 188 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.11.2 UART Electrical Data/Timing Table6-41.TimingRequirementsforUARTxReceive(1)(seeFigure6-23) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 4 t Pulseduration,receivedatabit(URXDx)[15/30/100pF] 0.96U 1.05U ns w(URXDB) 5 t Pulseduration,receivestartbit[15/30/100pF] 0.96U 1.05U ns w(URXSB) (1) U=UARTbaudtime=1/programmedbaudrate. Table6-42.SwitchingCharacteristicsOverRecommendedOperatingConditionsforUARTxTransmit(1) (seeFigure6-23) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 f Maximumprogrammablebaudrate 128 kHz (baud) 2 t Pulseduration,transmitdatabit(UTXDx)[15/30/100pF] U-2 U+2 ns w(UTXDB) 3 t Pulseduration,transmitstartbit[15/30/100pF] U-2 U+2 ns w(UTXSB) (1) U=UARTbaudtime=1/programmedbaudrate. 3 2 Start UTXDx Bit Data Bits 5 4 Start URXDx Bit Data Bits Figure6-23.UARTTransmit/ReceiveTiming SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 189

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.12 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between DM6435 and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP throughtheI2Cmodule.TheI2CportdoesnotsupportCBUScompatibledevices. TheI2Cportsupports: • CompatiblewithPhilipsI2CSpecificationRevision2.1(January2000) • FastModeupto400Kbps(nofail-safeI/Obuffers) • NoiseFiltertoRemoveNoise50nsorless • Seven-andTen-BitDeviceAddressingModes • Master(Transmit/Receive)andSlave(Transmit/Receive)Functionality • Events:DMA,Interrupt,orPolling • Slew-RateLimitedOpen-DrainOutputBuffers I2C Module Clock Prescale Peripheral Clock (DSP/18) ICPSC Control Bit Clock Own SCL Generator ICOAR Address Noise I2C Clock Filter ICCLKH Slave ICSAR Address ICCLKL ICMDR Mode Data Transmit ICCNT Count Transmit ICXSR Extended Shift ICEMDR Mode Transmit ICDXR Buffer SDA Noise Interrupt/DMA I2C Data Filter Interrupt Receive ICIMR Mask/Status Receive ICDRR Buffer ICSTR ISnttaetrursupt Receive Interrupt ICRSR Shift ICIVR Vector Shading denotes control/status registers. Figure6-24.I2CModuleBlockDiagram For more detailed information on the I2C peripheral, see Section 2.9, Documentation Support section of this document for the TMS320DM643x DMP Peripherals Overview Reference Guide (literature number SPRU983). 190 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.12.1 I2C Peripheral Register Description(s) Table6-43.I2CRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x1C21000 ICOAR I2COwnAddressRegister 0x1C21004 ICIMR I2CInterruptMaskRegister 0x1C21008 ICSTR I2CInterruptStatusRegister 0x1C2100C ICCLKL I2CClockDividerLowRegister 0x1C21010 ICCLKH I2CClockDividerHighRegister 0x1C21014 ICCNT I2CDataCountRegister 0x1C21018 ICDRR I2CDataReceiveRegister 0x1C2101C ICSAR I2CSlaveAddressRegister 0x1C21020 ICDXR I2CDataTransmitRegister 0x1C21024 ICMDR I2CModeRegister 0x1C21028 ICIVR I2CInterruptVectorRegister 0x1C2102C ICEMDR I2CExtendedModeRegister 0x1C21030 ICPSC I2CPrescalerRegister 0x1C21034 ICPID1 I2CPeripheralIdentificationRegister1 0x1C21038 ICPID2 I2CPeripheralIdentificationRegister2 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 191

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.12.2 I2C Electrical Data/Timing 6.12.2.1 Inter-IntegratedCircuits(I2C)Timing Table6-44.TimingRequirementsforI2CTimings(1)(seeFigure6-25) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. STANDARD UNIT FASTMODE MODE MIN MAX MIN MAX 1 t Cycletime,SCL 10 2.5 µs c(SCL) Setuptime,SCLhighbeforeSDAlow(forarepeatedSTART 2 t 4.7 0.6 µs su(SCLH-SDAL) condition) Holdtime,SCLlowafterSDAlow(foraSTARTandarepeated 3 t 4 0.6 µs h(SCLL-SDAL) STARTcondition) 4 t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) 5 t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) 6 t Setuptime,SDAvalidbeforeSCLhigh 250 100(2) ns su(SDAV-SCLH) 7 t Holdtime,SDAvalidafterSCLlow 0(3) 0(3) 0.9(4) µs h(SDA-SCLL) Pulseduration,SDAhighbetweenSTOPandSTART 8 t 4.7 1.3 µs w(SDAH) conditions 9 t Risetime,SDA 1000 20+0.1C (5) 300 ns r(SDA) b 10 t Risetime,SCL 1000 20+0.1C (5) 300 ns r(SCL) b 11 t Falltime,SDA 300 20+0.1C (5) 300 ns f(SDA) b 12 t Falltime,SCL 300 20+0.1C (5) 300 ns f(SCL) b 13 t Setuptime,SCLhighbeforeSDAhigh(forSTOPcondition) 4 0.6 µs su(SCLH-SDAH) 14 t Pulseduration,spike(mustbesuppressed) 0 50 ns w(SP) 15 C (5) Capacitiveloadforeachbusline 400 400 pF b (1) TheI2CpinsSDAandSCLdonotfeaturefail-safeI/Obuffers.Thesepinscouldpotentiallydrawcurrentwhenthedeviceispowered down. (2) AFast-modeI2C-bus™devicecanbeusedinaStandard-modeI2C-bussystem,buttherequirementt ‡ 250nsmustthenbe su(SDA-SCLH) met.ThiswillautomaticallybethecaseifthedevicedoesnotstretchtheLOWperiodoftheSCLsignal.Ifsuchadevicedoesstretch theLOWperiodoftheSCLsignal,itmustoutputthenextdatabittotheSDAlinet max+t =1000+250=1250ns r su(SDA-SCLH) (accordingtotheStandard-modeI2C-BusSpecification)beforetheSCLlineisreleased. (3) Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignal(referredtotheV oftheSCLsignal)tobridgethe IHmin undefinedregionofthefallingedgeofSCL. (4) Themaximumt hasonlytobemetifthedevicedoesnotstretchthelowperiod[t ]oftheSCLsignal. h(SDA-SCLL) w(SCLL) (5) C =totalcapacitanceofonebuslineinpF.IfmixedwithHS-modedevices,fasterfall-timesareallowed. b 11 9 SDA 8 6 14 4 13 10 5 SCL 1 12 3 7 2 3 Stop Start Repeated Stop Start Figure6-25.I2CReceiveTimings 192 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-45.SwitchingCharacteristicsforI2CTimings(1)(seeFigure6-26) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER STANDARD UNIT FASTMODE MODE MIN MAX MIN MAX 16 t Cycletime,SCL 10 2.5 µs c(SCL) Delaytime,SCLhightoSDAlow(forarepeatedSTART 17 t 4.7 0.6 µs d(SCLH-SDAL) condition) Delaytime,SDAlowtoSCLlow(foraSTARTandarepeated 18 t 4 0.6 µs d(SDAL-SCLL) STARTcondition) 19 t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) 20 t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) 21 t Delaytime,SDAvalidtoSCLhigh 250 100 ns d(SDAV-SCLH) 22 t Validtime,SDAvalidafterSCLlow 0 0 0.9 µs v(SCLL-SDAV) Pulseduration,SDAhighbetweenSTOPandSTART 23 t 4.7 1.3 µs w(SDAH) conditions 24 t Risetime,SDA 1000 20+0.1C (1) 300 ns r(SDA) b 25 t Risetime,SCL 1000 20+0.1C (1) 300 ns r(SCL) b 26 t Falltime,SDA 300 20+0.1C (1) 300 ns f(SDA) b 27 t Falltime,SCL 300 20+0.1C (1) 300 ns f(SCL) b 28 t Delaytime,SCLhightoSDAhigh(forSTOPcondition) 4 0.6 µs d(SCLH-SDAH) 29 C CapacitanceforeachI2Cpin 10 10 pF p (1) C =totalcapacitanceofonebuslineinpF.IfmixedwithHS-modedevices,fasterfall-timesareallowed. b 26 24 SDA 23 21 19 28 25 20 SCL 16 27 18 22 17 18 Stop Start Repeated Stop Start Figure6-26.I2CTransmitTimings SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 193

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.13 Host-Port Interface (HPI) Peripheral 6.13.1 HPI Device-Specific Information TheDM6435deviceincludesauser-configurable16-bitHost-portinterface(HPI16). Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the DM6435. The DM6435 HPI does not support the HAS feature. For proper device operation, the HAS pin must be pulledupviaanexternalresistor. 6.13.2 HPI Peripheral Register Description(s) Table6-46.HPIControlRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS 01C67800 PID PeripheralIdentificationRegister TheCPUhasread/write 01C67804 PWREMU_MGMT HPIpowerandemulationmanagementregister accesstothe PWREMU_MGMTregister. 01C67808-01C67824 - Reserved 01C67828 - Reserved 01C6782C - Reserved TheHostandtheCPUboth 01C67830 HPIC HPIcontrolregister haveread/writeaccesstothe HPICregister. 01C67834 (HPHIAPWIA)(1) H(WPrIitaed)dressregister TachceeHssostoththaesHrePaIdA/wrerigteisters. HPIA HPIaddressregister TheCPUhasonlyread 01C67838 (HPIAR)(1) (Read) accesstotheHPIAregisters. 01C6780C-01C67FFF - Reserved (1) Therearetwo32-bitHPIAregisters:HPIARforreadoperationsandHPIAWforwriteoperations.TheHPIcanbeconfiguredsuchthat HPIARandHPIAWactasasingle32-bitHPIA(single-HPIAmode)orastwoseparate32-bitHPIAs(dual-HPIAmode)fromthe perspectiveoftheHost.TheCPUcanaccessHPIAWandHPIARindependently.FormoredetailsabouttheHPIAregistersandtheir modes,seetheTMS320C643xDMPHostPortInterface(HPI)User'sGuide(literaturenumberSPRU998). 194 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.13.3 HPI Electrical Data/Timing Table6-47.TimingRequirementsforHost-PortInterfaceCycles(1)(2)(seeFigure6-27andFigure6-28) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Setuptime,selectsignals(3)validbeforeHSTROBElow 5 ns su(SELV-HSTBL) 2 t Holdtime,selectsignals(3)validafterHSTROBElow 2 ns h(HSTBL-SELV) 3 t Pulseduration,HSTROBEactivelow 15 ns w(HSTBL) 4 t Pulseduration,HSTROBEinactivehighbetweenconsecutiveaccesses 2M ns w(HSTBH) 11 t Setuptime,hostdatavalidbeforeHSTROBEhigh 5 ns su(HDV-HSTBH) 12 t Holdtime,hostdatavalidafterHSTROBEhigh 0 ns h(HSTBH-HDV) Holdtime,HSTROBEhighafterHRDYlow.HSTROBEshouldnotbe 13 t inactivateduntilHRDYisactive(low);otherwise,HPIwriteswillnot 0 ns h(HRDYL-HSTBL) completeproperly. (1) HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. (2) M=SYSCLK3period=(CPUclockfrequency)/6inns.Forexample,whenrunningpartsat600MHz,use10ns. (3) Selectsignalsinclude:HCNTL[1:0],HR/WandHHWIL. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 195

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-48. SwitchingCharacteristicsforHost-PortInterfaceCycles(1)(2)(3) (seeFigure6-27andFigure6-28) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX ForHPIWrite,HRDYcangohigh(not ready)fortheseHPIWriteconditions; otherwise,HRDYstayslow(ready): Case1:Back-to-backHPIAwrites(can beeitherfirstorsecondhalf-word) Case2:HPIAwritefollowinga PREFETCHcommand(canbeeither firstorsecondhalf-word) Case3:HPIDwritewhenFIFOisfull orflushing(canbeeitherfirstor secondhalf-word) Case4:HPIAwriteandWriteFIFOnot empty ForHPIRead,HRDYcangohigh(not ready)fortheseHPIReadconditions: Delaytime,HSTROBElowto Case1:HPIDread(with 5 td(HSTBL-HRDYV) HRDYvalid auto-increment)anddatanotinRead 12 ns FIFO(canonlyhappentofirst half-wordofHPIDaccess) Case2:Firsthalf-wordaccessofHPID Readwithoutauto-increment ForHPIRead,HRDYstayslow(ready) fortheseHPIReadconditions: Case1:HPIDreadwithauto-increment anddataisalreadyinReadFIFO (appliestoeitherhalf-wordofHPID access) Case2:HPIDreadwithout auto-incrementanddataisalreadyin ReadFIFO(alwaysappliestosecond half-wordofHPIDaccess) Case3:HPICorHPIAread(appliesto eitherhalf-wordaccess) 6 t Enabletime,HDdrivenfromHSTROBElow 2 ns en(HSTBL-HD) 7 t Delaytime,HRDYlowtoHDvalid 0 ns d(HRDYL-HDV) 8 t Outputholdtime,HDvalidafterHSTROBEhigh 1.5 ns oh(HSTBH-HDV) 14 t Disabletime,HDhigh-impedancefromHSTROBEhigh 12 ns dis(HSTBH-HDV) ForHPIRead.Appliestoconditions wheredataisalreadyresidingin HPID/FIFO: Case1:HPICorHPIAread Delaytime,HSTROBElowto 15 t Case2:Firsthalf-wordofHPIDread 15 ns d(HSTBL-HDV) HDvalid withauto-incrementanddatais alreadyinReadFIFO Case3:Secondhalf-wordofHPID readwithorwithoutauto-increment ForHPIWrite,HRDYcangohigh(not ready)fortheseHPIWriteconditions; otherwise,HRDYstayslow(ready): Case1:HPIDwritewhenWriteFIFOis Delaytime,HSTROBEhighto full(canhappentoeitherhalf-word) 18 t 12 ns d(HSTBH-HRDYV) HRDYvalid Case2:HPIAwrite(canhappento eitherhalf-word) Case3:HPIDwritewithout auto-increment(onlyhappensto secondhalf-word) (1) M=SYSCLK3period=(CPUclockfrequency)/6inns.Forexample,whenrunningpartsat600MHz,use10ns. (2) HSTROBEreferstothefollowinglogicaloperationonHCS,HDS1,andHDS2:[NOT(HDS1XORHDS2)]ORHCS. (3) Bydesign,wheneverHCSisdriveninactive(high),HPIwilldriveHRDYactive(low). 196 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 HCS HAS(D) 2 2 1 1 HCNTL[1:0] 2 2 1 1 HR/W 2 2 1 1 HHWIL 4 3 3 HSTROBE(A)(C) 15 15 14 14 6 8 6 8 HD[15:0] (output) 5 13 1st Half-Word 2nd Half-Word 7 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User’s Guide (literature number SPRU998). C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D For proper HPI operation, HAS must be pulled up via an external resistor. Figure6-27.HPI16ReadTiming(HASNotUsed,TiedHigh) SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 197

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com HCS HAS(D) 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 HSTROBE(A)(C) 11 11 12 12 HD[15:0] (input) 1st Half-Word 2nd Half-Word 18 5 18 13 13 5 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320DM643x Host Port Interface (HPI) User’s Guide (literature number SPRU998). C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D For proper HPI operation, HAS must be pulled up via an external resistor. Figure6-28.HPI16WriteTiming(HASNotUsed,TiedHigh) 198 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.14 Multichannel Buffered Serial Port (McBSP) TheMcBSPprovidesthesefunctions: • Full-duplexcommunication • Double-buffereddataregisters,whichallowacontinuousdatastream • Independentframingandclockingforreceiveandtransmit • Directinterfacetoindustry-standardcodecs,analoginterfacechips(AICs),andotherserially connectedanalog-to-digital(A/D)anddigital-to-analog(D/A)devices • Externalshiftclockoraninternal,programmablefrequencyshiftclockfordatatransfer If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must alwaysbesettoavalueof1orgreater. For more detailed information on the McBSP peripheral, see the TMS320DM643x DMP Multichannel BufferedSerialPort(McBSP)User'sGuide(literaturenumberSPRU943). 6.14.1 McBSP Peripheral Register Description(s) Table6-49.McBSP0Registers HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS TheCPUandEDMA3 controllercanonlyread 01D00000 DRR0 McBSP0DataReceiveRegister thisregister;theycannot writetoit. 01D00004 DXR0 McBSP0DataTransmitRegister 01D00008 SPCR0 McBSP0SerialPortControlRegister 01D0000C RCR0 McBSP0ReceiveControlRegister 01D00010 XCR0 McBSP0TransmitControlRegister 01D00014 SRGR0 McBSP0SampleRateGeneratorregister 01D00018 MCR0 McBSP0MultichannelControlRegister McBSP0EnhancedReceiveChannelEnableRegister 01D0001C RCERE00 0PartitionA/B McBSP0EnhancedTransmitChannelEnableRegister 01D00020 XCERE00 0PartitionA/B 01D00024 PCR0 McBSP0PinControlRegister McBSP0EnhancedReceiveChannelEnableRegister 01D00028 RCERE10 1PartitionC/D McBSP0EnhancedTransmitChannelEnableRegister 01D0002C XCERE10 1PartitionC/D McBSP0EnhancedReceiveChannelEnableRegister 01D00030 RCERE20 2PartitionE/F McBSP0EnhancedTransmitChannelEnableRegister 01D00034 XCERE20 2PartitionE/F McBSP0EnhancedReceiveChannelEnableRegister 01D00038 RCERE30 3PartitionG/H McBSP0EnhancedTransmitChannelEnableRegister 01D0003C XCERE30 3PartitionG/H 01D00040-01D007FF - Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 199

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.14.2 McBSP Electrical Data/Timing 6.14.2.1 MultichannelBufferedSerialPort(McBSP)Timing Table6-50.TimingRequirementsforMcBSP(1)(seeFigure6-29) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 2 t Cycletime,CLKR/X CLKR/Xext 2P(2)(3) ns c(CKRX) 3 t Pulseduration,CLKR/XhighorCLKR/Xlow CLKR/Xext P-1(4) ns w(CKRX) CLKRint 14 5 t Setuptime,externalFSRhighbeforeCLKRlow ns su(FRH-CKRL) CLKRext 4 CLKRint 6 6 t Holdtime,externalFSRhighafterCLKRlow ns h(CKRL-FRH) CLKRext 4 CLKRint 14 7 t Setuptime,DRvalidbeforeCLKRlow ns su(DRV-CKRL) CLKRext 4 CLKRint 3 8 t Holdtime,DRvalidafterCLKRlow ns h(CKRL-DRV) CLKRext 3.5 CLKXint 14 10 t Setuptime,externalFSXhighbeforeCLKXlow ns su(FXH-CKXL) CLKXext 4 CLKXint 6 11 t Holdtime,externalFSXhighafterCLKXlow ns h(CKXL-FXH) CLKXext 3 (1) CLKRP=CLKXP=FSRP=FSXP=0.Ifpolarityofanyofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (3) Usewhichevervalueisgreater.MinimumCLKR/Xcycletimesmustbemet,evenwhenCLKR/Xisgeneratedbyaninternalclock source.TheminimumCLKR/Xcycletimesarebasedoninternallogicspeed;themaximumusablespeedmaybelowerduetoEDMA limitationsandACtimingrequirements. (4) ThisparameterappliestothemaximumMcBSPfrequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle. 200 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-51.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcBSP(1)(2) (seeFigure6-29) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX Delaytime,CLKShightoCLKR/XhighforinternalCLKR/X 1 t 3 10 ns d(CKSH-CKRXH) generatedfromCLKSinput 2 t Cycletime,CLKR/X CLKR/Xint 2P(3)(4)(5) ns c(CKRX) 3 t Pulseduration,CLKR/XhighorCLKR/Xlow CLKR/Xint C-2(6) C+2(6) ns w(CKRX) 4 t Delaytime,CLKRhightointernalFSRvalid CLKRint -4 5.5 ns d(CKRH-FRV) CLKXint -4 5.5 9 t Delaytime,CLKXhightointernalFSXvalid ns d(CKXH-FXV) CLKXext 2.5 14.5 Disabletime,DXhighimpedancefollowing CLKXint -5.5 7.5 12 t ns dis(CKXH-DXHZ) lastdatabitfromCLKXhigh CLKXext -2.1 16 CLKXint -4+D1(7) 5.5+D2(7) 13 t Delaytime,CLKXhightoDXvalid ns d(CKXH-DXV) CLKXext 2.5+D1(7) 14.5+D2(7) Delaytime,FSXhightoDXvalid FSXint -4(8) 5(8) 14 td(FXH-DXV) ONLYapplieswhenindata FSXext 1(8) 14.5(8) ns delay0(XDATDLY=00b)mode (1) CLKRP=CLKXP=FSRP=FSXP=0.Ifpolarityofanyofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimumdelaytimesalsorepresentminimumoutputholdtimes. (3) MinimumCLKR/Xcycletimesmustbemet,evenwhenCLKR/Xisgeneratedbyaninternalclocksource.MinimumCLKR/Xcycletimes arebasedoninternallogicspeed;themaximumusablespeedmaybelowerduetoEDMAlimitationsandACtimingrequirements. (4) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (5) Usewhichevervalueisgreater. (6) C=HorL S=samplerategeneratorinputclock=PifCLKSM=1(P=SYSCLK3period) S=samplerategeneratorinputclock=P_clksifCLKSM=0(P_clks=CLKSperiod) H=CLKXhighpulsewidth=(CLKGDV/2+1)*SifCLKGDViseven H=(CLKGDV+1)/2*SifCLKGDVisodd L=CLKXlowpulsewidth=(CLKGDV/2)*SifCLKGDViseven L=(CLKGDV+1)/2*SifCLKGDVisodd CLKGDVshouldbesetappropriatelytoensuretheMcBSPbitratedoesnotexceedthemaximumlimit(see(4)above). (7) ExtradelayfromCLKXhightoDXvalidappliesonlytothefirstdatabitofadevice,ifandonlyifDXENA=1inSPCR. ifDXENA=0,thenD1=D2=0 ifDXENA=1,thenD1=6P,D2=12P (8) ExtradelayfromFSXhightoDXvalidappliesonlytothefirstdatabitofadevice,ifandonlyifDXENA=1inSPCR. ifDXENA=0,thenD1=D2=0 ifDXENA=1,thenD1=6P,D2=12P SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 201

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 8 DR Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 13(A) 14 12 13(A) DX Bit 0 Bit(n-1) (n-2) (n-3) A. ParameterNo.13appliestothefirstdatabitonlywhenXDATDLY„ 0. Figure6-29.McBSPTiming(B) Table6-52.TimingRequirementsforFSRWhenGSYNC=1(seeFigure6-30) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Setuptime,FSRhighbeforeCLKShigh 4 ns su(FRH-CKSH) 2 t Holdtime,FSRhighafterCLKShigh 4 ns h(CKSH-FRH) CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure6-30.FSRTimingWhenGSYNC=1 202 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-53.TimingRequirementsforMcBSPasSPIMasterorSlave:CLKSTP=10b,CLKXP=0(1)(2) (seeFigure6-31) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MASTER SLAVE MIN MAX MIN MAX 4 t Setuptime,DRvalidbeforeCLKXlow 14 2-3P ns su(DRV-CKXL) 5 t Holdtime,DRvalidafterCLKXlow 4 5+6P ns h(CKXL-DRV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. Table6-54.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcBSPasSPI MasterorSlave:CLKSTP=10b,CLKXP=0(1)(2)(seeFigure6-31) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER MASTER(3) SLAVE UNIT MIN MAX MIN MAX 1 t Holdtime,FSXlowafterCLKXlow(4) T-4 T+5.5 ns h(CKXL-FXL) 2 t Delaytime,FSXlowtoCLKXhigh(5) L-4 L+4 ns d(FXL-CKXH) 3 t Delaytime,CLKXhightoDXvalid -4 5.5 3P+2.8 5P+17 ns d(CKXH-DXV) Disabletime,DXhighimpedancefollowing 6 t L-6 L+7.5 ns dis(CKXL-DXHZ) lastdatabitfromCLKXlow Disabletime,DXhighimpedancefollowing 7 t P+3 3P+17 ns dis(FXH-DXHZ) lastdatabitfromFSXhigh 8 t Delaytime,FSXlowtoDXvalid 2P+1.8 4P+17 ns d(FXL-DXV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. (3) S=Samplerategeneratorinputclock=2PifCLKSM=1(P=SYSCLK3period) S=Samplerategeneratorinputclock=2P_clksifCLKSM=0(P_clks=CLKSperiod) T=CLKXperiod=(1+CLKGDV)*S H=CLKXhighpulsewidth=(CLKGDV/2+1)*SifCLKGDViseven H=(CLKGDV+1)/2*SifCLKGDVisodd L=CLKXlowpulsewidth=(CLKGDV/2)*SifCLKGDViseven L=(CLKGDV+1)/2*SifCLKGDVisodd (4) FSRP=FSXP=1.AsaSPIMaster,FSXisinvertedtoprovideactive-lowslave-enableoutput.AsaSlave,theactive-lowsignalinput onFSXandFSRisinvertedbeforebeingusedinternally. CLKXM=FSXM=1,CLKRM=FSRM=0forMasterMcBSP CLKXM=CLKRM=FSXM=FSRM=0forSlaveMcBSP (5) FSXshouldbelowbeforetherisingedgeofclocktoenableSlavedevicesandthenbeginaSPItransferattherisingedgeoftheMaster clock(CLKX). CLKX 1 2 FSX 7 8 6 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure6-31.McBSPTimingasSPIMasterorSlave:CLKSTP=10b,CLKXP=0 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 203

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-55.TimingRequirementsforMcBSPasSPIMasterorSlave:CLKSTP=11b,CLKXP=0(1)(2) (seeFigure6-32) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MASTER SLAVE MIN MAX MIN MAX 4 t Setuptime,DRvalidbeforeCLKXhigh 14 2-3P ns su(DRV-CKXH) 5 t Holdtime,DRvalidafterCLKXhigh 4 5+6P ns h(CKXH-DRV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. 204 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-56.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcBSPasSPI MasterorSlave:CLKSTP=11b,CLKXP=0(1)(2)(seeFigure6-32) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER MASTER(3) SLAVE UNIT MIN MAX MIN MAX 1 t Holdtime,FSXlowafterCLKXlow(4) L-4 L+5.5 ns h(CKXL-FXL) 2 t Delaytime,FSXlowtoCLKXhigh(5) T-4 T+4 ns d(FXL-CKXH) 3 t Delaytime,CLKXlowtoDXvalid -4 5.5 3P+2.8 5P+17 ns d(CKXL-DXV) Disabletime,DXhighimpedancefollowing 6 t -6 7.5 3P+2 5P+17 ns dis(CKXL-DXHZ) lastdatabitfromCLKXlow 7 t Delaytime,FSXlowtoDXvalid H-4 H+5.5 2P+2 4P+17 ns d(FXL-DXV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. (3) S=Samplerategeneratorinputclock=2PifCLKSM=1(P=SYSCLK3period) S=Samplerategeneratorinputclock=2P_clksifCLKSM=0(P_clks=CLKSperiod) T=CLKXperiod=(1+CLKGDV)*S H=CLKXhighpulsewidth=(CLKGDV/2+1)*SifCLKGDViseven H=(CLKGDV+1)/2*SifCLKGDVisodd L=CLKXlowpulsewidth=(CLKGDV/2)*SifCLKGDViseven L=(CLKGDV+1)/2*SifCLKGDVisodd (4) FSRP=FSXP=1.AsaSPIMaster,FSXisinvertedtoprovideactive-lowslave-enableoutput.AsaSlave,theactive-lowsignalinput onFSXandFSRisinvertedbeforebeingusedinternally. CLKXM=FSXM=1,CLKRM=FSRM=0forMasterMcBSP CLKXM=CLKRM=FSXM=FSRM=0forSlaveMcBSP (5) FSXshouldbelowbeforetherisingedgeofclocktoenableSlavedevicesandthenbeginaSPItransferattherisingedgeoftheMaster clock(CLKX). CLKX 1 2 FSX 6 7 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure6-32.McBSPTimingasSPIMasterorSlave:CLKSTP=11b,CLKXP=0 Table6-57.TimingRequirementsforMcBSPasSPIMasterorSlave:CLKSTP=10b,CLKXP=1(1)(2) (seeFigure6-33) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MASTER SLAVE MIN MAX MIN MAX 4 t Setuptime,DRvalidbeforeCLKXhigh 14 2-3P ns su(DRV-CKXH) 5 t Holdtime,DRvalidafterCLKXhigh 4 5+6P ns h(CKXH-DRV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 205

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-58.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcBSPasSPI MasterorSlave:CLKSTP=10b,CLKXP=1(1)(2)(seeFigure6-33) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER MASTER(3) SLAVE UNIT MIN MAX MIN MAX 1 t Holdtime,FSXlowafterCLKXhigh(4) T-4 T+5.5 ns h(CKXH-FXL) 2 t Delaytime,FSXlowtoCLKXlow(5) H-4 H+4 ns d(FXL-CKXL) 3 t Delaytime,CLKXlowtoDXvalid -4 5.5 3P+2.8 5P+17 ns d(CKXL-DXV) Disabletime,DXhighimpedancefollowing 6 t H-6 H+7.5 ns dis(CKXH-DXHZ) lastdatabitfromCLKXhigh Disabletime,DXhighimpedancefollowing 7 t P+3 3P+17 ns dis(FXH-DXHZ) lastdatabitfromFSXhigh 8 t Delaytime,FSXlowtoDXvalid 2P+2 4P+17 ns d(FXL-DXV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. (3) S=Samplerategeneratorinputclock=2PifCLKSM=1(P=SYSCLK3period) S=Samplerategeneratorinputclock=2P_clksifCLKSM=0(P_clks=CLKSperiod) T=CLKXperiod=(1+CLKGDV)*S H=CLKXhighpulsewidth=(CLKGDV/2+1)*SifCLKGDViseven H=(CLKGDV+1)/2*SifCLKGDVisodd L=CLKXlowpulsewidth=(CLKGDV/2)*SifCLKGDViseven L=(CLKGDV+1)/2*SifCLKGDVisodd (4) FSRP=FSXP=1.AsaSPIMaster,FSXisinvertedtoprovideactive-lowslave-enableoutput.AsaSlave,theactive-lowsignalinput onFSXandFSRisinvertedbeforebeingusedinternally. CLKXM=FSXM=1,CLKRM=FSRM=0forMasterMcBSP CLKXM=CLKRM=FSXM=FSRM=0forSlaveMcBSP (5) FSXshouldbelowbeforetherisingedgeofclocktoenableSlavedevicesandthenbeginaSPItransferattherisingedgeoftheMaster clock(CLKX). CLKX 1 2 FSX 7 6 8 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure6-33.McBSPTimingasSPIMasterorSlave:CLKSTP=10b,CLKXP=1 Table6-59.TimingRequirementsforMcBSPasSPIMasterorSlave:CLKSTP=11b,CLKXP=1(1)(2) (seeFigure6-34) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MASTER SLAVE MIN MAX MIN MAX 4 t Setuptime,DRvalidbeforeCLKXhigh 14 2-3P ns su(DRV-CKXH) 5 t Holdtime,DRvalidafterCLKXhigh 4 5+6P ns h(CKXH-DRV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. 206 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-60.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcBSPasSPI MasterorSlave:CLKSTP=11b,CLKXP=1(1)(2)(seeFigure6-34) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER MASTER(3) SLAVE UNIT MIN MAX MIN MAX 1 t Holdtime,FSXlowafterCLKXhigh(4) H-4 H+5.5 ns h(CKXH-FXL) 2 t Delaytime,FSXlowtoCLKXlow(5) T-4 T+4 ns d(FXL-CKXL) 3 t Delaytime,CLKXhightoDXvalid -4 5.5 3P+2.8 5P+17 ns d(CKXH-DXV) Disabletime,DXhighimpedancefollowing 6 t -6 7.5 3P+2 5P+17 ns dis(CKXH-DXHZ) lastdatabitfromCLKXhigh 7 t Delaytime,FSXlowtoDXvalid L-4 L+5.5 2P+2 4P+17 ns d(FXL-DXV) (1) P=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useP=10ns. (2) ForallSPISlavemodes,therateoftheinternalclockCLKGmustbeatleast8timesfasterthanthatoftheSPIdatarate.Usershould programsamplerategeneratortoachievemaximumCLKGbysettingCLKSM=CLKGDV=1. (3) S=Samplerategeneratorinputclock=2PifCLKSM=1(P=SYSCLK3period) S=Samplerategeneratorinputclock=2P_clksifCLKSM=0(P_clks=CLKSperiod) T=CLKXperiod=(1+CLKGDV)*S H=CLKXhighpulsewidth=(CLKGDV/2+1)*SifCLKGDViseven H=(CLKGDV+1)/2*SifCLKGDVisodd L=CLKXlowpulsewidth=(CLKGDV/2)*SifCLKGDViseven L=(CLKGDV+1)/2*SifCLKGDVisodd (4) FSRP=FSXP=1.AsaSPIMaster,FSXisinvertedtoprovideactive-lowslave-enableoutput.AsaSlave,theactive-lowsignalinput onFSXandFSRisinvertedbeforebeingusedinternally. CLKXM=FSXM=1,CLKRM=FSRM=0forMasterMcBSP CLKXM=CLKRM=FSXM=FSRM=0forSlaveMcBSP (5) FSXshouldbelowbeforetherisingedgeofclocktoenableSlavedevicesandthenbeginaSPItransferattherisingedgeoftheMaster clock(CLKX). CLKX 1 2 FSX 6 7 3 DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure6-34.McBSPTimingasSPIMasterorSlave:CLKSTP=11b,CLKXP=1 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 207

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.15 Multichannel Audio Serial Port (McASP0) Peripheral The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound(I2S)protocols,andintercomponentdigitalaudiointerfacetransmission(DIT). 6.15.1 McASP0 Device-Specific Information The DM6435 device includes one multichannel audio serial port (McASP) interface peripheral (McASP0). TheMcASP0isaserialportoptimizedfortheneedsofmultichannelaudioapplications. The McASP0 consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a poolof16shiftregistersthatmaybeconfiguredtooperateaseithertransmitdataorreceivedata. The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronousserialformat. The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the sameformat.However,thetransmitandreceiveformatsneednotbethesame. Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audiodata(forexample,passingcontrolinformationbetweentwoDSPs). The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, aswellaserrormanagement. For more detailed information on and the functionality of the McASP0 peripheral, see the TMS320DM643x DMPMultichannelAudioSerialPort(McASP)User'sGuide(literaturenumberSPRU980). 208 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.15.1.1 McASPBlockDiagram Figure 6-35 illustrates the major blocks along with external signals of the TMS320DM6435 McASP0 peripheral;andshowsthe4serialdata[AXR]pins. McASP0 Transmit DIT Frame Sync AFSX0 RAM Generator Transmit Clock Check Transmit AHCLKX0 Clock (High- Generator ACLKX0 Frequency) Error AMUTE0 Detect AMUTEIN0 Receive Receive Clock Check Clock AHCLKR0 (High- Generator ACLKR0 Frequency) mit s an Transmit Receive rT Data Frame Sync AFSR0 S Formatter Generator M D O PI G X/ R Serializer 0 AXR0[0] X/ E T Serializer 1 AXR0[1] L AB Serializer 2 AXR0[2] M M Serializer 3 AXR0[3] A R G O R P Y L L A U D VI DI N ve I ei c Re Receive GPIO A Data Control M Formatter D Figure6-35.McASP0Configuration SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 209

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.15.1.2 McASP0PeripheralRegisterDescription(s) Table6-61.McASP0ControlRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 01D01000 PID PeripheralIdentificationregister[Registervalue:0x00100101] 01D01004 – Reserved 01D01008 – Reserved 01D0100C – Reserved 01D01010 PFUNC Pinfunctionregister 01D01014 PDIR Pindirectionregister 01D01018 – Reserved 01D0101C – Reserved 01D01020 – Reserved 01D01024–01D01040 – Reserved 01D01044 GBLCTL Globalcontrolregister 01D01048 AMUTE Mutecontrolregister 01D0104C DLBCTL DigitalLoop-backcontrolregister 01D01050 DITCTL DITmodecontrolregister 01D01054–01D0105C – Reserved AliasofGBLCTLcontainingonlyReceiverResetbits,allowstransmittobereset 01D01060 RGBLCTL independentlyfromreceive. 01D01064 RMASK ReceiverformatUNITbitmaskregister 01D01068 RFMT Receivebitstreamformatregister 01D0106C AFSRCTL Receiveframesynccontrolregister 01D01070 ACLKRCTL Receiveclockcontrolregister 01D01074 AHCLKRCTL High-frequencyreceiveclockcontrolregister 01D01078 RTDM ReceiveTDMslot0–31register 01D0107C RINTCTL Receiverinterruptcontrolregister 01D01080 RSTAT Statusregister–Receiver 01D01084 RSLOT CurrentreceiveTDMslotregister 01D01088 RCLKCHK Receiverclockcheckcontrolregister 01D0108C–01D0109C – Reserved AliasofGBLCTLcontainingonlyTransmitterResetbits,allowstransmittobereset 01D010A0 XGBLCTL independentlyfromreceive. 01D010A4 XMASK TransmitformatUNITbitmaskregister 01D010A8 XFMT Transmitbitstreamformatregister 01D010AC AFSXCTL Transmitframesynccontrolregister 01D010B0 ACLKXCTL Transmitclockcontrolregister 01D010B4 AHCLKXCTL High-frequencyTransmitclockcontrolregister 01D010B8 XTDM TransmitTDMslot0–31register 01D010BC XINTCTL Transmitinterruptcontrolregister 01D010C0 XSTAT Statusregister–Transmitter 01D010C4 XSLOT CurrenttransmitTDMslot 01D010C8 XCLKCHK Transmitclockcheckcontrolregister 210 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-61.McASP0ControlRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 01D010CC–01D010FC – Reserved 01D01100 DITCSRA0 Left(evenTDMslot)channelstatusregisterfile 01D01104 DITCSRA1 Left(evenTDMslot)channelstatusregisterfile 01D01108 DITCSRA2 Left(evenTDMslot)channelstatusregisterfile 01D0110C DITCSRA3 Left(evenTDMslot)channelstatusregisterfile 01D01110 DITCSRA4 Left(evenTDMslot)channelstatusregisterfile 01D01114 DITCSRA5 Left(evenTDMslot)channelstatusregisterfile 01D01118 DITCSRB0 Right(oddTDMslot)channelstatusregisterfile 01D0111C DITCSRB1 Right(oddTDMslot)channelstatusregisterfile 01D01120 DITCSRB2 Right(oddTDMslot)channelstatusregisterfile 01D01124 DITCSRB3 Right(oddTDMslot)channelstatusregisterfile 01D01128 DITCSRB4 Right(oddTDMslot)channelstatusregisterfile 01D0112C DITCSRB5 Right(oddTDMslot)channelstatusregisterfile 01D01130 DITUDRA0 Left(evenTDMslot)userdataregisterfile 01D01134 DITUDRA1 Left(evenTDMslot)userdataregisterfile 01D01138 DITUDRA2 Left(evenTDMslot)userdataregisterfile 01D0113C DITUDRA3 Left(evenTDMslot)userdataregisterfile 01D01140 DITUDRA4 Left(evenTDMslot)userdataregisterfile 01D01144 DITUDRA5 Left(evenTDMslot)userdataregisterfile 01D01148 DITUDRB0 Right(oddTDMslot)userdataregisterfile 01D0114C DITUDRB1 Right(oddTDMslot)userdataregisterfile 01D01150 DITUDRB2 Right(oddTDMslot)userdataregisterfile 01D01154 DITUDRB3 Right(oddTDMslot)userdataregisterfile 01D01158 DITUDRB4 Right(oddTDMslot)userdataregisterfile 01D0115C DITUDRB5 Right(oddTDMslot)userdataregisterfile 01D01160–01D0117C – Reserved 01D01180 SRCTL0 Serializer0controlregister 01D01184 SRCTL1 Serializer1controlregister 01D01188 SRCTL2 Serializer2controlregister 01D0118C SRCTL3 Serializer3controlregister 01D01190–01D011FC – Reserved 01D01200 XBUF0 TransmitBufferforSerializer0 01D01204 XBUF1 TransmitBufferforSerializer1 01D01208 XBUF2 TransmitBufferforSerializer2 01D0120C XBUF3 TransmitBufferforSerializer3 01D01210–01D0127C – Reserved 01D01280 RBUF0 ReceiveBufferforSerializer0 01D01284 RBUF1 ReceiveBufferforSerializer1 01D01288 RBUF2 ReceiveBufferforSerializer2 01D0128C RBUF3 ReceiveBufferforSerializer3 01D01290–01D013FF – Reserved Table6-62.McASP0DataRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS (UsedwhenRSELorXSEL McASP0receivebuffersorMcASP0transmitbuffersvia bits=0[thesebitsarelocated 01D01400–01D017FF RBUF/XBUF thePeripheralDataBus. intheRFMTorXFMTregisters, respectively].) SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 211

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.15.1.3 McASP0ElectricalData/Timing 6.15.1.3.1 MultichannelAudioSerialPort(McASP)Timing Table6-63.TimingRequirementsforMcASP(seeFigure6-36andFigure6-37)(1) -7/-6/-5/-4 -L/-Q6/-Q5/- NO. Q4 UNIT MIN MAX 1 t Cycletime,AHCLKR/X 25 ns c(AHCKRX) 2 t Pulseduration,AHCLKR/Xhighorlow 10 ns w(AHCKRX) 3 t Cycletime,ACLKR/X ACLKR/Xext 25 ns c(CKRX) 4 t Pulseduration,ACLKR/Xhighorlow ACLKR/Xext 10 ns w(CKRX) ACLKR/Xint 11 ns 5 t Setuptime,AFSR/XinputvalidbeforeACLKR/Xlatchesdata su(FRX-CKRX) ACLKR/Xext 3 ns ACLKR/Xint 0 ns 6 t Holdtime,AFSR/XinputvalidafterACLKR/Xlatchesdata ACLKR/Xextinput 4 ns h(CKRX-FRX) ACLKR/Xextoutput 6 ns ACLKR/Xint 11 ns 7 t Setuptime,AXRinputvalidbeforeACLKR/Xlatchesdata su(AXR-CKRX) ACLKR/Xext 3 ns ACLKR/Xint 3 ns 8 t Holdtime,AXRinputvalidafterACLKR/Xlatchesdata ACLKR/Xextinput 4 ns h(CKRX-AXR) ACLKR/Xextoutput 6 ns (1) ACLKXinternal:ACLKXCTL.CLKXM=1,PDIR.ACLKX=1 ACLKXexternalinput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=0 ACLKXexternaloutput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=1 ACLKRinternal:ACLKRCTL.CLKRM=1,PDIR.ACLKR=1 ACLKRexternalinput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=0 ACLKRexternaloutput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=1 212 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-64.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMcASP(1)(2) (seeFigure6-36andFigure6-37)(3) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 9 t Cycletime,AHCLKR/X 25 ns c(AHCKRX) 10 t Pulseduration,AHCLKR/Xhighorlow AH-2.5 ns w(AHCKRX) ACLKR/X 11 t Cycletime,ACLKR/X 25 ns c(CKRX) int ACLKR/X 12 t Pulseduration,ACLKR/Xhighorlow A-2.5 ns w(CKRX) int ACLKR/X -2.25 5.5 ns int ACLKR/X 13 t Delaytime,ACLKR/XtransmitedgetoAFSX/Routputvalid 0 12.5 ns d(CKRX-FRX) extinput ACLKR/X 0 14 ns extoutput ACLKXint -2.25 5.5 ns ACLKX 0 12.5 ns 14 t Delaytime,ACLKXtransmitedgetoAXRoutputvalid extinput d(CKX-AXRV) ACLKX 0 14 ns extoutput ACLKR/X -4.5 8 ns Disabletime,AXRhighimpedancefollowinglastdatabitfrom int 15 t dis(CKRX-AXRHZ) ACLKR/Xtransmitedge ACLKR/X -4.5 12.5 ns ext (1) A=(ACLKR/Xperiod)/2inns.Forexample,whenACLKR/Xperiodis25ns,useA=12.5ns. (2) AH=(AHCLKR/Xperiod)/2inns.Forexample,whenAHCLKR/Xperiodis25ns,useAH=12.5ns. (3) ACLKXinternal:ACLKXCTL.CLKXM=1,PDIR.ACLKX=1 ACLKXexternalinput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=0 ACLKXexternaloutput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=1 ACLKRinternal:ACLKRCTL.CLKRM=1,PDIR.ACLKR=1 ACLKRexternalinput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=0 ACLKRexternaloutput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=1 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 213

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30A31 B0 B1 B30B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiverisconfiguredforfallingedge(toshiftdatain). B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiverisconfiguredforrisingedge(toshiftdatain). Figure6-36.McASPInputTimings 214 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (CLKRP = CLKXP = 1)(A) ACLKR/X (CLKRP = CLKXP = 0)(B) 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A1 A30A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiverisconfiguredforrisingedge(toshiftdatain). B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiverisconfiguredforfallingedge(toshiftdatain). Figure6-37.McASPOutputTimings SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 215

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.16 High-End Controller Area Network Controller (HECC) The DM6435 device has a High-End Controller Area Network Controllers (HECC). The HECC uses established protocol to communicate serially with other controllers in harsh environments. The HECC is fullycompliantwiththeControllerAreaNetwork(CAN)protocol,version2.0B. KeyfeaturesoftheHECCincludethefollowing: • CAN,version2.0Bcompliant • 32RX/TXmessageobjects • 32receiveidentifiermasks • Programmablewake-uponbusactivity • Programmableinterruptscheme • Automaticreplytoaremoterequest • Automaticre-transmissionincaseoferrororlossofarbitration • Protectionagainstreceptionofanewmessage • 32-bittimestamp • Localnetworktimecounter • Programmablepriorityregisterforeachmessage • Programmabletransmissionandreceptiontime-out • HECC/SCCmodeofoperation • Standard-ExtendedIdentifier • Self-testmode For more details on the HECC, see the TMS320DM643x High-End CAN Controller (HECC) User's Guide (literaturenumberSPRU981). 6.16.1 HECC Device-Specific Information Software must not access "Reserved" locations of the HECC. Access to HECC "Reserved" locations may hangthedevice. 216 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.16.2 HECC Peripheral Register Description(s) Table 6-65 through Table 6-68 show the High-End CAN Controller (HECC) registers. For more detailed information, see the TMS320DM643x DMP High-End CAN Controller User’s Guide (literature number SPRU981). Table6-65.HECCControlandStatusRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 01C23000 CANME MailboxEnableRegister 01C23004 CANMD MailboxDirectionRegister 01C23008 CANTRS TransmissionRequestSetRegister 01C2300C CANTRR TransmissionRequestResetRegister 01C23010 CANTA TransmissionAcknowledgeRegister 01C23014 CANAA AbortAcknowledgeRegister 01C23018 CANRMP ReceiveMessagePendingRegister 01C2301C CANRML ReceiveMessageLostRegister 01C23020 CANRFP RemoteFramePendingRegister 01C23024 CANGAM GlobalAcceptanceMaskRegister(SCCModeOnly) 01C23028 CANMC MasterControlRegister 01C2302C CANBTC Bit-TimingConfigurationRegister 01C23030 CANES ErrorandStatusRegister 01C23034 CANTEC TransmitErrorCounterRegister 01C23038 CANREC ReceiveErrorCounterRegister 01C2303C CANGIF0 GlobalInterruptFlag0Register 01C23040 CANGIM GlobalInterruptMaskRegister 01C23044 CANGIF1 GlobalInterruptFlag1Register 01C23048 CANMIM MailboxInterruptMaskRegister 01C2304C CANMIL MailboxInterruptLevelRegister 01C23050 CANOPC OverwriteProtectionControlRegister 01C23054 CANTIOC TransmitI/OControlRegister 01C23058 CANRIOC ReceiveI/OControlRegister 01C2305C CANLNT LocalNetworkTimeRegister(HECCModeOnly) 01C23060 CANTOC Time-OutControlRegister(HECCModeOnly) 01C23064 CANTOS Time-OutStatusRegister(HECCModeOnly) 01C23068–01C2306C – Reserved 01C23070 CANETC ErrorTestControlRegister 01C23074–01C2307C – Reserved 01C23080 SCCLAM0 SCCLocalAcceptanceMaskRegister0(SCCModeOnly) 01C23084–01C23088 – Reserved 01C2308C SSCLAM3 SCCLocalAcceptanceMaskRegister3(SCCModeOnly) 01C23090–01C24FFF – Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 217

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-66.HECCMessageObjectRegisters(1) HEXADDRESSRANGE ACRONYM REGISTERNAME HECCLocalAcceptanceMaskRegisters 01C25000 LAM0 HECCLocalAcceptanceMaskRegisterforMailbox0 01C25004 LAM1 HECCLocalAcceptanceMaskRegisterforMailbox1 01C25008 LAM2 HECCLocalAcceptanceMaskRegisterforMailbox2 01C2500C LAM3 HECCLocalAcceptanceMaskRegisterforMailbox3 01C25010 LAM4 HECCLocalAcceptanceMaskRegisterforMailbox4 01C25014 LAM5 HECCLocalAcceptanceMaskRegisterforMailbox5 01C25018 LAM6 HECCLocalAcceptanceMaskRegisterforMailbox6 01C2501C LAM7 HECCLocalAcceptanceMaskRegisterforMailbox7 01C25020 LAM8 HECCLocalAcceptanceMaskRegisterforMailbox8 01C25024 LAM9 HECCLocalAcceptanceMaskRegisterforMailbox9 01C25028 LAM10 HECCLocalAcceptanceMaskRegisterforMailbox10 01C2502C LAM11 HECCLocalAcceptanceMaskRegisterforMailbox11 01C25030 LAM12 HECCLocalAcceptanceMaskRegisterforMailbox12 01C25034 LAM13 HECCLocalAcceptanceMaskRegisterforMailbox13 01C25038 LAM14 HECCLocalAcceptanceMaskRegisterforMailbox14 01C2503C LAM15 HECCLocalAcceptanceMaskRegisterforMailbox15 01C25040 LAM16 HECCLocalAcceptanceMaskRegisterforMailbox16 01C25044 LAM17 HECCLocalAcceptanceMaskRegisterforMailbox17 01C25048 LAM18 HECCLocalAcceptanceMaskRegisterforMailbox18 01C2504C LAM19 HECCLocalAcceptanceMaskRegisterforMailbox19 01C25050 LAM20 HECCLocalAcceptanceMaskRegisterforMailbox20 01C25054 LAM21 HECCLocalAcceptanceMaskRegisterforMailbox21 01C25058 LAM22 HECCLocalAcceptanceMaskRegisterforMailbox22 01C2505C LAM23 HECCLocalAcceptanceMaskRegisterforMailbox23 01C25060 LAM24 HECCLocalAcceptanceMaskRegisterforMailbox24 01C25064 LAM25 HECCLocalAcceptanceMaskRegisterforMailbox25 01C25068 LAM26 HECCLocalAcceptanceMaskRegisterforMailbox26 01C2506C LAM27 HECCLocalAcceptanceMaskRegisterforMailbox27 01C25070 LAM28 HECCLocalAcceptanceMaskRegisterforMailbox28 01C25074 LAM29 HECCLocalAcceptanceMaskRegisterforMailbox29 01C25078 LAM30 HECCLocalAcceptanceMaskRegisterforMailbox30 01C2507C LAM31 HECCLocalAcceptanceMaskRegisterforMailbox31 MessageObjectTime-StampRegisters 01C25080 MOTS0 MessageObjectTime-StampRegisterforMailbox0 01C25084 MOTS1 MessageObjectTime-StampRegisterforMailbox1 01C25088 MOTS2 MessageObjectTime-StampRegisterforMailbox2 01C2508C MOTS3 MessageObjectTime-StampRegisterforMailbox3 01C25090 MOTS4 MessageObjectTime-StampRegisterforMailbox4 01C25094 MOTS5 MessageObjectTime-StampRegisterforMailbox5 01C25098 MOTS6 MessageObjectTime-StampRegisterforMailbox6 01C2509C MOTS7 MessageObjectTime-StampRegisterforMailbox7 01C250A0 MOTS8 MessageObjectTime-StampRegisterforMailbox8 01C250A4 MOTS9 MessageObjectTime-StampRegisterforMailbox9 01C250A8 MOTS10 MessageObjectTime-StampRegisterforMailbox10 01C250AC MOTS11 MessageObjectTime-StampRegisterforMailbox11 (1) AllregistersinthistableapplytoHECCmodeonly,theydonotapplytoSCCmode. 218 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-66.HECCMessageObjectRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 01C250B0 MOTS12 MessageObjectTime-StampRegisterforMailbox12 01C250B4 MOTS13 MessageObjectTime-StampRegisterforMailbox13 01C250B8 MOTS14 MessageObjectTime-StampRegisterforMailbox14 01C250BC MOTS15 MessageObjectTime-StampRegisterforMailbox15 01C250C0 MOTS16 MessageObjectTime-StampRegisterforMailbox16 01C250C4 MOTS17 MessageObjectTime-StampRegisterforMailbox17 01C250C8 MOTS18 MessageObjectTime-StampRegisterforMailbox18 01C250CC MOTS19 MessageObjectTime-StampRegisterforMailbox19 01C250D0 MOTS20 MessageObjectTime-StampRegisterforMailbox20 01C250D4 MOTS21 MessageObjectTime-StampRegisterforMailbox21 01C250D8 MOTS22 MessageObjectTime-StampRegisterforMailbox22 01C250DC MOTS23 MessageObjectTime-StampRegisterforMailbox23 01C250E0 MOTS24 MessageObjectTime-StampRegisterforMailbox24 01C250E4 MOTS25 MessageObjectTime-StampRegisterforMailbox25 01C250E8 MOTS26 MessageObjectTime-StampRegisterforMailbox26 01C250EC MOTS27 MessageObjectTime-StampRegisterforMailbox27 01C250F0 MOTS28 MessageObjectTime-StampRegisterforMailbox28 01C250F4 MOTS29 MessageObjectTime-StampRegisterforMailbox29 01C250F8 MOTS30 MessageObjectTime-StampRegisterforMailbox30 01C250FC MOTS31 MessageObjectTime-StampRegisterforMailbox31 MessageObjectTime-OutRegisters 01C25100 MOTO0 MessageObjectTime-OutRegisterforMailbox0 01C25104 MOTO1 MessageObjectTime-OutRegisterforMailbox1 01C25108 MOTO2 MessageObjectTime-OutRegisterforMailbox2 01C2510C MOTO3 MessageObjectTime-OutRegisterforMailbox3 01C25110 MOTO4 MessageObjectTime-OutRegisterforMailbox4 01C25114 MOTO5 MessageObjectTime-OutRegisterforMailbox5 01C25118 MOTO6 MessageObjectTime-OutRegisterforMailbox6 01C2511C MOTO7 MessageObjectTime-OutRegisterforMailbox7 01C25120 MOTO8 MessageObjectTime-OutRegisterforMailbox8 01C25124 MOTO9 MessageObjectTime-OutRegisterforMailbox9 01C25128 MOTO10 MessageObjectTime-OutRegisterforMailbox10 01C2512C MOTO11 MessageObjectTime-OutRegisterforMailbox11 01C25130 MOTO12 MessageObjectTime-OutRegisterforMailbox12 01C25134 MOTO13 MessageObjectTime-OutRegisterforMailbox13 01C25138 MOTO14 MessageObjectTime-OutRegisterforMailbox14 01C2513C MOTO15 MessageObjectTime-OutRegisterforMailbox15 01C25140 MOTO16 MessageObjectTime-OutRegisterforMailbox16 01C25144 MOTO17 MessageObjectTime-OutRegisterforMailbox17 01C25148 MOTO18 MessageObjectTime-OutRegisterforMailbox18 01C2514C MOTO19 MessageObjectTime-OutRegisterforMailbox19 01C25150 MOTO20 MessageObjectTime-OutRegisterforMailbox20 01C25154 MOTO21 MessageObjectTime-OutRegisterforMailbox21 01C25158 MOTO22 MessageObjectTime-OutRegisterforMailbox22 01C2515C MOTO23 MessageObjectTime-OutRegisterforMailbox23 01C25160 MOTO24 MessageObjectTime-OutRegisterforMailbox24 01C25164 MOTO25 MessageObjectTime-OutRegisterforMailbox25 SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 219

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-66.HECCMessageObjectRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 01C25168 MOTO26 MessageObjectTime-OutRegisterforMailbox26 01C2516C MOTO27 MessageObjectTime-OutRegisterforMailbox27 01C25170 MOTO28 MessageObjectTime-OutRegisterforMailbox28 01C25174 MOTO29 MessageObjectTime-OutRegisterforMailbox29 01C25178 MOTO30 MessageObjectTime-OutRegisterforMailbox30 01C2517C MOTO31 MessageObjectTime-OutRegisterforMailbox31 Table6-67.HECCMessageMailboxRAM(1)(2) HEXADDRESSRANGE DESCRIPTION 01C24000–01C2400F Mailbox0(432-bitRegisters) 01C24010–01C2401F Mailbox1(432-bitRegisters) 01C24020–01C2402F Mailbox2(432-bitRegisters) 01C24030–01C2403F Mailbox3(432-bitRegisters) 01C24040–01C2404F Mailbox4(432-bitRegisters) ... ... 01C241E0–01C241EF Mailbox30(432-bitRegisters) 01C241F0–01C241FF Mailbox31(432-bitRegisters) (1) ThistablesummarizestheaddressrangesfortheMessageMailboxes0to31.ForthecontentswithineachMessageMailboxRAM,see Table6-68,MessageMailboxnRAMEntries. (2) ForSCCmode,onlyMailboxes0to15aresupported. Table6-68.HECCMessageMailboxnRAMEntries(1) HEXADDRESS ACRONYM(2) MAILBOXREGISTERNAME OFFSET(withinRAM) 0 MIDn MessageIdentifierRegisterforMailboxn 4 MCFn MessageControlFieldRegisterforMailboxn 8 MDLn MessageDataLow-WordRegisterforMailboxn C MDHn MessageDataHigh-WordRegisterforMailboxn (1) ForthehexaddressrangeofMailboxn,seeTable6-67,MessageMailboxRAM.Forexample,MessageMailbox0occupieshex addressrange0x01C24000–0x01C2400F. (2) Thesuffix"n"indicatestheMessageMailboxnumber.Forexample,MessageMailbox0hasthefollowingMessageMailboxRegisters: MID0,MCF0,MDL0,andMDH0. 220 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.16.3 HECC Electrical Data/Timing Table6-69.TimingRequirementsforHECCReceive(1)(seeFigure6-38) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 f Maximumprogrammablebaudrate 1 Mbps (baud) 2 t Pulseduration,receivedatabit H-2 H+2 ns w(HECC_RX) (1) H=HECCbaudtime=1/programmedbaudrate. Table6-70.SwitchingCharacteristicsOverRecommendedOperatingConditionsforHECCTransmit(1) (seeFigure6-38) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 3 f Maximumprogrammablebaudrate 1 Mbps (baud) 4 t Pulseduration,transmitdatabit H-2 H+2 ns w(HECC_TX) (1) H=HECCbaudtime=1/programmedbaudrate. 2 HECCx_RX 4 HECCx_TX Figure6-38.HECCTransmit/ReceiveTiming SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 221

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.17 Ethernet Media Access Controller (EMAC) The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6435 and the network. The DM6435 EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100 Mbps) in either half- or full-duplex mode. The EMAC module also supports hardware flow control and qualityofservice(QOS)support. The EMAC controls the flow of packet data from the DM6435 device to the PHY. The MDIO module controlsPHYconfigurationandstatusmonitoring. The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE 802.3standardhasalsobeenadoptedbyISO/IECandre-designatedasISO/IEC8802-3:2000(E). Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame willbedetectedasanerrorbythenetwork. Both the EMAC and the MDIO modules interface to the DM6435 device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplexandcontrolinterrupts. For the DM6435 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide (literature number SPRU941) which describes the DM6435 EMAC peripheral in detail, see Section 2.9, Documentation Support section . For a list of supported registers and register fields, see Table 6-71 [Ethernet MAC (EMAC) Control Registers] and Table 6-72 [EMAC Statistics Registers]inthisdatamanual. 6.17.1 EMAC Peripheral Register Description(s) Table6-71.EthernetMAC(EMAC)ControlRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 01C80000 TXIDVER TransmitIdentificationandVersionRegister 01C80004 TXCONTROL TransmitControlRegister 01C80008 TXTEARDOWN TransmitTeardownRegister 01C80010 RXIDVER ReceiveIdentificationandVersionRegister 01C80014 RXCONTROL ReceiveControlRegister 01C80018 RXTEARDOWN ReceiveTeardownRegister 01C80080 TXINTSTATRAW TransmitInterruptStatus(Unmasked)Register 01C80084 TXINTSTATMASKED TransmitInterruptStatus(Masked)Register 01C80088 TXINTMASKSET TransmitInterruptMaskSetRegister 01C8008C TXINTMASKCLEAR TransmitInterruptMaskClearRegister 01C80090 MACINVECTOR MACInputVectorRegister 01C800A0 RXINTSTATRAW ReceiveInterruptStatus(Unmasked)Register 01C800A4 RXINTSTATMASKED ReceiveInterruptStatus(Masked)Register 01C800A8 RXINTMASKSET ReceiveInterruptMaskSetRegister 01C800AC RXINTMASKCLEAR ReceiveInterruptMaskClearRegister 01C800B0 MACINTSTATRAW MACInterruptStatus(Unmasked)Register 01C800B4 MACINTSTATMASKED MACInterruptStatus(Masked)Register 01C800B8 MACINTMASKSET MACInterruptMaskSetRegister 01C800BC MACINTMASKCLEAR MACInterruptMaskClearRegister 01C80100 RXMBPENABLE ReceiveMulticast/Broadcast/PromiscuousChannelEnableRegister 01C80104 RXUNICASTSET ReceiveUnicastEnableSetRegister 222 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-71.EthernetMAC(EMAC)ControlRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 01C80108 RXUNICASTCLEAR ReceiveUnicastClearRegister 01C8010C RXMAXLEN ReceiveMaximumLengthRegister 01C80110 RXBUFFEROFFSET ReceiveBufferOffsetRegister 01C80114 RXFILTERLOWTHRESH ReceiveFilterLowPriorityFrameThresholdRegister 01C80120 RX0FLOWTHRESH ReceiveChannel0FlowControlThresholdRegister 01C80124 RX1FLOWTHRESH ReceiveChannel1FlowControlThresholdRegister 01C80128 RX2FLOWTHRESH ReceiveChannel2FlowControlThresholdRegister 01C8012C RX3FLOWTHRESH ReceiveChannel3FlowControlThresholdRegister 01C80130 RX4FLOWTHRESH ReceiveChannel4FlowControlThresholdRegister 01C80134 RX5FLOWTHRESH ReceiveChannel5FlowControlThresholdRegister 01C80138 RX6FLOWTHRESH ReceiveChannel6FlowControlThresholdRegister 01C8013C RX7FLOWTHRESH ReceiveChannel7FlowControlThresholdRegister 01C80140 RX0FREEBUFFER ReceiveChannel0FreeBufferCountRegister 01C80144 RX1FREEBUFFER ReceiveChannel1FreeBufferCountRegister 01C80148 RX2FREEBUFFER ReceiveChannel2FreeBufferCountRegister 01C8014C RX3FREEBUFFER ReceiveChannel3FreeBufferCountRegister 01C80150 RX4FREEBUFFER ReceiveChannel4FreeBufferCountRegister 01C80154 RX5FREEBUFFER ReceiveChannel5FreeBufferCountRegister 01C80158 RX6FREEBUFFER ReceiveChannel6FreeBufferCountRegister 01C8015C RX7FREEBUFFER ReceiveChannel7FreeBufferCountRegister 01C80160 MACCONTROL MACControlRegister 01C80164 MACSTATUS MACStatusRegister 01C80168 EMCONTROL EmulationControlRegister 01C8016C FIFOCONTROL FIFOControlRegister(TransmitandReceive) 01C80170 MACCONFIG MACConfigurationRegister 01C80174 SOFTRESET SoftResetRegister 01C801D0 MACSRCADDRLO MACSourceAddressLowBytesRegister(Lower32-bits) 01C801D4 MACSRCADDRHI MACSourceAddressHighBytesRegister(Upper16-bits) 01C801D8 MACHASH1 MACHashAddressRegister1 01C801DC MACHASH2 MACHashAddressRegister2 01C801E0 BOFFTEST BackOffTestRegister 01C801E4 TPACETEST TransmitPacingAlgorithmTestRegister 01C801E8 RXPAUSE ReceivePauseTimerRegister 01C801EC TXPAUSE TransmitPauseTimerRegister 01C80200-01C802FC (seeTable6-72) EMACStatisticsRegisters 01C80500 MACADDRLO MACAddressLowBytesRegister 01C80504 MACADDRHI MACAddressHighBytesRegister 01C80508 MACINDEX MACIndexRegister 01C80600 TX0HDP TransmitChannel0DMAHeadDescriptorPointerRegister 01C80604 TX1HDP TransmitChannel1DMAHeadDescriptorPointerRegister 01C80608 TX2HDP TransmitChannel2DMAHeadDescriptorPointerRegister 01C8060C TX3HDP TransmitChannel3DMAHeadDescriptorPointerRegister 01C80610 TX4HDP TransmitChannel4DMAHeadDescriptorPointerRegister 01C80614 TX5HDP TransmitChannel5DMAHeadDescriptorPointerRegister 01C80618 TX6HDP TransmitChannel6DMAHeadDescriptorPointerRegister 01C8061C TX7HDP TransmitChannel7DMAHeadDescriptorPointerRegister 01C80620 RX0HDP ReceiveChannel0DMAHeadDescriptorPointerRegister SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 223

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-71.EthernetMAC(EMAC)ControlRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 01C80624 RX1HDP ReceiveChannel1DMAHeadDescriptorPointerRegister 01C80628 RX2HDP ReceiveChannel2DMAHeadDescriptorPointerRegister 01C8062C RX3HDP ReceiveChannel3DMAHeadDescriptorPointerRegister 01C80630 RX4HDP ReceiveChannel4DMAHeadDescriptorPointerRegister 01C80634 RX5HDP ReceiveChannel5DMAHeadDescriptorPointerRegister 01C80638 RX6HDP ReceiveChannel6DMAHeadDescriptorPointerRegister 01C8063C RX7HDP ReceiveChannel7DMAHeadDescriptorPointerRegister TransmitChannel0CompletionPointer(InterruptAcknowledge) 01C80640 TX0CP Register TransmitChannel1CompletionPointer(InterruptAcknowledge) 01C80644 TX1CP Register TransmitChannel2CompletionPointer(InterruptAcknowledge) 01C80648 TX2CP Register TransmitChannel3CompletionPointer(InterruptAcknowledge) 01C8064C TX3CP Register TransmitChannel4CompletionPointer(InterruptAcknowledge) 01C80650 TX4CP Register TransmitChannel5CompletionPointer(InterruptAcknowledge) 01C80654 TX5CP Register TransmitChannel6CompletionPointer(InterruptAcknowledge) 01C80658 TX6CP Register TransmitChannel7CompletionPointer(InterruptAcknowledge) 01C8065C TX7CP Register ReceiveChannel0CompletionPointer(InterruptAcknowledge) 01C80660 RX0CP Register ReceiveChannel1CompletionPointer(InterruptAcknowledge) 01C80664 RX1CP Register ReceiveChannel2CompletionPointer(InterruptAcknowledge) 01C80668 RX2CP Register ReceiveChannel3CompletionPointer(InterruptAcknowledge) 01C8066C RX3CP Register ReceiveChannel4CompletionPointer(InterruptAcknowledge) 01C80670 RX4CP Register ReceiveChannel5CompletionPointer(InterruptAcknowledge) 01C80674 RX5CP Register ReceiveChannel6CompletionPointer(InterruptAcknowledge) 01C80678 RX6CP Register ReceiveChannel7CompletionPointer(InterruptAcknowledge) 01C8067C RX7CP Register 224 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-72.EMACStatisticsRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 01C80200 RXGOODFRAMES GoodReceiveFramesRegister BroadcastReceiveFramesRegister 01C80204 RXBCASTFRAMES (Totalnumberofgoodbroadcastframesreceived) MulticastReceiveFramesRegister 01C80208 RXMCASTFRAMES (Totalnumberofgoodmulticastframesreceived) 01C8020C RXPAUSEFRAMES PauseReceiveFramesRegister ReceiveCRCErrorsRegister(Totalnumberofframesreceivedwith 01C80210 RXCRCERRORS CRCerrors) ReceiveAlignment/CodeErrorsRegister 01C80214 RXALIGNCODEERRORS (Totalnumberofframesreceivedwithalignment/codeerrors) ReceiveOversizedFramesRegister 01C80218 RXOVERSIZED (Totalnumberofoversizedframesreceived) ReceiveJabberFramesRegister 01C8021C RXJABBER (Totalnumberofjabberframesreceived) ReceiveUndersizedFramesRegister 01C80220 RXUNDERSIZED (Totalnumberofundersizedframesreceived) 01C80224 RXFRAGMENTS ReceiveFrameFragmentsRegister 01C80228 RXFILTERED FilteredReceiveFramesRegister 01C8022C RXQOSFILTERED ReceivedQOSFilteredFramesRegister ReceiveOctetFramesRegister 01C80230 RXOCTETS (Totalnumberofreceivedbytesingoodframes) GoodTransmitFramesRegister 01C80234 TXGOODFRAMES (Totalnumberofgoodframestransmitted) 01C80238 TXBCASTFRAMES BroadcastTransmitFramesRegister 01C8023C TXMCASTFRAMES MulticastTransmitFramesRegister 01C80240 TXPAUSEFRAMES PauseTransmitFramesRegister 01C80244 TXDEFERRED DeferredTransmitFramesRegister 01C80248 TXCOLLISION TransmitCollisionFramesRegister 01C8024C TXSINGLECOLL TransmitSingleCollisionFramesRegister 01C80250 TXMULTICOLL TransmitMultipleCollisionFramesRegister 01C80254 TXEXCESSIVECOLL TransmitExcessiveCollisionFramesRegister 01C80258 TXLATECOLL TransmitLateCollisionFramesRegister 01C8025C TXUNDERRUN TransmitUnderrunErrorRegister 01C80260 TXCARRIERSENSE TransmitCarrierSenseErrorsRegister 01C80264 TXOCTETS TransmitOctetFramesRegister 01C80268 FRAME64 TransmitandReceive64OctetFramesRegister 01C8026C FRAME65T127 TransmitandReceive65to127OctetFramesRegister 01C80270 FRAME128T255 TransmitandReceive128to255OctetFramesRegister 01C80274 FRAME256T511 TransmitandReceive256to511OctetFramesRegister 01C80278 FRAME512T1023 TransmitandReceive512to1023OctetFramesRegister 01C8027C FRAME1024TUP TransmitandReceive1024to1518OctetFramesRegister 01C80280 NETOCTETS NetworkOctetFramesRegister 01C80284 RXSOFOVERRUNS ReceiveFIFOorDMAStartofFrameOverrunsRegister 01C80288 RXMOFOVERRUNS ReceiveFIFOorDMAMiddleofFrameOverrunsRegister ReceiveDMAStartofFrameandMiddleofFrameOverruns 01C8028C RXDMAOVERRUNS Register SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 225

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-73.EMACControlModuleRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C81004 EWCTL Interruptcontrolregister 0x01C81008 EWINTTCNT Interrupttimercount Table6-74.EMACControlModuleRAM HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C82000-0x01C83FFF EMACControlModuleDescriptorMemory 226 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.17.2 EMAC Electrical Data/Timing Table6-75.TimingRequirementsforMRCLK(seeFigure6-39) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT 10Mbps 100Mbps MIN MAX MIN MAX 1 t Cycletime,MRCLK 400 40 ns c(MRCLK) 2 t Pulseduration,MRCLKhigh 140 14 ns w(MRCLKH) 3 t Pulseduration,MRCLKlow 140 14 ns w(MRCLKL) 1 2 3 MRCLK Figure6-39.MRCLKTiming(EMAC-Receive) Table6-76.TimingRequirementsforMTCLK(seeFigure6-39) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT 10Mbps 100Mbps MIN MAX MIN MAX 1 t Cycletime,MTCLK 400 40 ns c(MTCLK) 2 t Pulseduration,MTCLKhigh 140 14 ns w(MTCLKH) 3 t Pulseduration,MTCLKlow 140 14 ns w(MTCLKL) 1 2 3 MTCLK Figure6-40.MTCLKTiming(EMAC-Transmit) Table6-77.TimingRequirementsforEMACMIIReceive10/100Mbit/s(1)(seeFigure6-41) -7/-6/-5/-4 -L/-Q6/-Q5/- NO. Q4 UNIT MIN MAX 1 t Setuptime,receiveselectedsignalsvalidbeforeMRCLKhigh 8 ns su(MRXD-MRCLKH) 2 t Holdtime,receiveselectedsignalsvalidafterMRCLKhigh 8 ns h(MRCLKH-MRXD) (1) Receiveselectedsignalsinclude:MRXD3-MRXD0,MRXDV,andMRXER. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 227

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 1 2 MRCLK (Input) MRXD3−MRXD0, MRXDV, MRXER (Inputs) Figure6-41.EMACReceiveInterfaceTiming Table6-78.SwitchingCharacteristicsOverRecommendedOperatingConditionsforEMACMIITransmit 10/100Mbit/s(1)(seeFigure6-42) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Delaytime,MTCLKhightotransmitselectedsignalsvalid 2 25 ns d(MTCLKH-MTXD) (1) Transmitselectedsignalsinclude:MTXD3-MTXD0,andMTXEN. 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) Figure6-42.EMACTransmitInterfaceTiming 228 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.18 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerateallPHYdevicesinthesystem. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenancefromthecoreprocessor.OnlyonePHYmaybeconnectedatanygiventime. For more detailed information on the MDIO peripheral, see the Documentation Support section for the Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module Reference Guide. For a list of supported registers and register fields, see Table 6-79 [MDIO Registers] in this data manual. 6.18.1 Peripheral Register Description(s) Table6-79.MDIORegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C84000 – Reserved 0x01C84004 CONTROL MDIOControlRegister 0x01C84008 ALIVE MDIOPHYAliveStatusRegister 0x01C8400C LINK MDIOPHYLinkStatusRegister 0x01C84010 LINKINTRAW MDIOLinkStatusChangeInterrupt(Unmasked)Register 0x01C84014 LINKINTMASKED MDIOLinkStatusChangeInterrupt(Masked)Register 0x01C84018 – Reserved 0x01C84020 USERINTRAW MDIOUserCommandCompleteInterrupt(Unmasked)Register 0x01C84024 USERINTMASKED MDIOUserCommandCompleteInterrupt(Masked)Register 0x01C84028 USERINTMASKSET MDIOUserCommandCompleteInterruptMaskSetRegister 0x01C8402C USERINTMASKCLEAR MDIOUserCommandCompleteInterruptMaskClearRegister 0x01C84030-0x01C8407C – Reserved 0x01C84080 USERACCESS0 MDIOUserAccessRegister0 0x01C84084 USERPHYSEL0 MDIOUserPHYSelectRegister0 0x01C84088 USERACCESS1 MDIOUserAccessRegister1 0x01C8408C USERPHYSEL1 MDIOUserPHYSelectRegister1 0x01C84090-0x01C847FF – Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 229

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.18.2 Management Data Input/Output (MDIO) Electrical Data/Timing Table6-80.TimingRequirementsforMDIOInput(seeFigure6-43andFigure6-44) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,MDCLK 400 ns c(MDCLK) 2 t Pulseduration,MDCLKhigh/low 180 ns w(MDCLK) 3 t Transitiontime,MDCLK 5 ns t(MDCLK) 4 t Setuptime,MDIOdatainputvalidbeforeMDCLKhigh 10 ns su(MDIO-MDCLKH) 5 t Holdtime,MDIOdatainputvalidafterMDCLKhigh 10 ns h(MDCLKH-MDIO) 1 3 3 MDCLK 4 5 MDIO (input) Figure6-43.MDIOInputTiming Table6-81.SwitchingCharacteristicsOverRecommendedOperatingConditionsforMDIOOutput (seeFigure6-44) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 7 t Delaytime,MDCLKlowtoMDIOdataoutputvalid 100 ns d(MDCLKL-MDIO) 1 MDCLK 7 MDIO (output) Figure6-44.MDIOOutputTiming 6.19 Timers TheDM6435devicehas364-bitgeneral-purposetimerswhichhavethefollowingfeatures: • 64-bitcount-upcounter • Timermodes: – 64-bitgeneral-purposetimermode(Timer0and1) – Dual32-bitgeneral-purposetimermode(Timer0and1) – Watchdogtimermode(Timer2) • 2possibleclocksources: 230 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 – Internalclock – ExternalclockinputviatimerinputpinTINPL(Timer0and1only) • 2operationmodes: – One-timeoperation(timerrunsforoneperiodthenstops) – Continuousoperation(timerautomaticallyresetsaftereachperiod) • GeneratesinterruptstotheDSP • GeneratessynceventtoEDMA • Causesdeviceglobalresetuponwatchdogtimertimeout(Timer2only) For more detailed information, see Section 2.9, Documentation Support for the TMS320DM643x DMP 64-BitTimerUser'sGuide(literaturenumberSPRU989). 6.19.1 Timer Peripheral Register Description(s) Table6-82.Timer0Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x01C21400 - Reserved 0x01C21404 EMUMGT_CLKSPD Timer0EmulationManagement/ClockSpeedRegister 0x01C21410 TIM12 Timer0CounterRegister12 0x01C21414 TIM34 Timer0CounterRegister34 0x01C21418 PRD12 Timer0PeriodRegister12 0x01C2141C PRD34 Timer0PeriodRegister34 0x01C21420 TCR Timer0ControlRegister 0x01C21424 TGCR Timer0GlobalControlRegister 0x01C21428-0x01C217FF - Reserved Table6-83.Timer1Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x01C21800 - Reserved 0x01C21804 EMUMGT_CLKSPD Timer1EmulationManagement/ClockSpeedRegister 0x01C21810 TIM12 Timer1CounterRegister12 0x01C21814 TIM34 Timer1CounterRegister34 0x01C21818 PRD12 Timer1PeriodRegister12 0x01C2181C PRD34 Timer1PeriodRegister34 0x01C21820 TCR Timer1ControlRegister 0x01C21824 TGCR Timer1GlobalControlRegister 0x01C21828-0x01C21BFF - Reserved Table6-84.Timer2(Watchdog)Registers HEXADDRESSRANGE ACRONYM DESCRIPTION 0x01C21C00 - Reserved 0x01C21C04 EMUMGT_CLKSPD Timer2EmulationManagement/ClockSpeedRegister 0x01C21C10 TIM12 Timer2CounterRegister12 0x01C21C14 TIM34 Timer2CounterRegister34 0x01C21C18 PRD12 Timer2PeriodRegister12 0x01C21C1C PRD34 Timer2PeriodRegister34 0x01C21C20 TCR Timer2ControlRegister 0x01C21C24 TGCR Timer2GlobalControlRegister 0x01C21C28 WDTCR Timer2WatchdogTimerControlRegister SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 231

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-84.Timer2(Watchdog)Registers (continued) HEXADDRESSRANGE ACRONYM DESCRIPTION 0x01C21C2C-0x01C21FFF - Reserved 6.19.2 Timer Electrical Data/Timing Table6-85.TimingRequirementsforTimerInput(1)(2)(3)(seeFigure6-45) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX TINP0L,ifTIMERCTL.TINP0SEL=0 2P ns [default] 1 t Pulseduration,TINPxLhigh w(TINPH) TINP0L,ifTIMERCTL.TINP0SEL=1 0.33P ns TINP1L 2P ns TINP0L,ifTIMERCTL.TINP0SEL=0 2P ns [default] 2 t Pulseduration,TINPxLlow w(TINPL) TINP0L,ifTIMERCTL.TINP0SEL=1 0.33P ns TINP1L 2P ns (1) P=MXI/CLKINcycletimeinns.Forexample,whenMXI/CLKINfrequencyis27MHz,useP=37.037ns. (2) TheTIMERCTL.TINP0SELfieldintheSystemModuledeterminesiftheTINP0LinputdirectlygoestoTimer0 (TIMERCTL.TINP0SEL=0),oriftheTINP0Linputisfirstdivideddownby6beforegoingtoTimer0(TIMERCTL.TINP0SEL=1). (3) TINP1LinputgoesdirectlytoTimer1. Table6-86.SwitchingCharacteristicsOverRecommendedOperatingConditionsforTimerOutput(1)(see Figure6-45) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 3 t Pulseduration,TOUTxLhigh P ns w(TOUTH) 4 t Pulseduration,TOUTxLlow P ns w(TOUTL) (1) P=MXI/CLKINcycletimeinns.Forexample,whenMXI/CLKINfrequencyis27MHz,useP=37.037ns. 1 2 TINPxL 3 4 TOUTxL Figure6-45.TimerTiming 232 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.20 Pulse Width Modulator (PWM) The3DM6435PulseWidthModulator(PWM)peripheralssupportthefollowingfeatures: • Periodcounter • First-phasedurationcounter • Repeatcountforone-shotoperation • Configurabletooperateineitherone-shotorcontinuousmode • Bufferedperiodandfirst-phasedurationregisters • One-shotoperationtriggerablebyhardwareeventswithprogrammableedgetransitions.(low-to-highor high-to-low). • One-shotoperationgeneratesN+1periodsofwaveform,Nbeingtherepeatcountregistervalue • Emulationsupport TheregistermemorymapsforPWM0/1/2areshowninTable6-87,Table6-88,andTable6-89. Table6-87.PWM0RegisterMemoryMap HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C22000 Reserved 0x01C22004 PCR PWM0PeripheralControlRegister 0x01C22008 CFG PWM0ConfigurationRegister 0x01C2200C START PWM0StartRegister 0x01C22010 RPT PWM0RepeatCountRegister 0x01C22014 PER PWM0PeriodRegister 0x01C22018 PH1D PWM0First-PhaseDurationRegister 0x01C2201C-0x01C223FF - Reserved Table6-88.PWM1RegisterMemoryMap HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C22400 Reserved 0x01C22404 PCR PWM1PeripheralControlRegister 0x01C22408 CFG PWM1ConfigurationRegister 0x01C2240C START PWM1StartRegister 0x01C22410 RPT PWM1RepeatCountRegister 0x01C22414 PER PWM1PeriodRegister 0x01C22418 PH1D PWM1First-PhaseDurationRegister 0x01C2241C-0x01C227FF - Reserved Table6-89.PWM2RegisterMemoryMap HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C22800 Reserved 0x01C22804 PCR PWM2PeripheralControlRegister 0x01C22808 CFG PWM2ConfigurationRegister 0x01C2280C START PWM2StartRegister 0x01C22810 RPT PWM2RepeatCountRegister 0x01C22814 PER PWM2PeriodRegister 0x01C22818 PH1D PWM2First-PhaseDurationRegister 0x01C2281C-0x01C22BFF - Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 233

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.20.1 PWM0/1/2 Electrical Data/Timing Table6-90.SwitchingCharacteristicsOverRecommendedOperatingConditionsforPWM0/1/2Outputs (seeFigure6-46andFigure6-47) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Pulseduration,PWMxhigh 37 ns w(PWMH) 2 t Pulseduration,PWMxlow 37 ns w(PWML) 3 t Transitiontime,PWMx 5 ns t(PWM) 4 t Delaytime,CCDC(VD)triggereventtoPWMxvalid 2 10 ns d(CCDC-PWMV) 1 2 PWM0/1/2 3 3 Figure6-46.PWMOutputTiming VD(CCDC) 4 PWM0 INVALID VALID 4 PWM1 INVALID VALID 4 PWM2 INVALID VALID Figure6-47.PWMOutputDelayTiming 234 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.21 VLYNQ The DM6435 VLYNQ peripheral provides a high speed serial communications interface with the following features. • LowPinCount • ScalablePerformance/Support • SimplePacketBasedTransferProtocolforMemoryMappedAccess – WriteRequest/DataPacket – ReadRequestPacket – ReadResponseDataPacket – InterruptRequestPacket • SupportsbothSymmetricandAsymmetricOperation – TxpinsonfirstdeviceconnecttoRxpinsonseconddeviceandviceversa – Datapinwidthsareautomaticallydetectedafterreset – Requestpackets,responsepackets,andflowcontrolinformationareallmultiplexedandsent acrossthesamephysicalpins – SupportsbothHost/PeripheralandPeertoPeercommunication • SimpleBlockCodePacketFormatting(8b/10b) • InBandFlowControl – Noextrapinsneeded – Allowsreceivertomomentarilythrottlebacktransmitterwhenoverflowisabouttooccur – Usesbuiltinspecialcodecapabilityofblockcodetoseamlesslyinterleaveflowcontrolinformation withuserdata – Allowssystemdesignertobalancecostofdatabufferingversusperformance • Multipleoutstandingtransactions • Automaticpacketformattingoptimizations • Internalloop-backmode 6.21.1 VLYNQ Peripheral Register Description(s) Table6-91.VLYNQRegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01E01000 - Reserved 0x01E01004 CTRL VLYNQLocalControlRegister 0x01E01008 STAT VLYNQLocalStatusRegister 0x01E0100C INTPRI VLYNQLocalInterruptPriorityVectorStatus/ClearRegister 0x01E01010 INTSTATCLR VLYNQLocalUnmaskedInterruptStatus/ClearRegister 0x01E01014 INTPENDSET VLYNQLocalInterruptPending/SetRegister 0x01E01018 INTPTR VLYNQLocalInterruptPointerRegister 0x01E0101C XAM VLYNQLocalTransmitAddressMapRegister 0x01E01020 RAMS1 VLYNQLocalReceiveAddressMapSize1Register 0x01E01024 RAMO1 VLYNQLocalReceiveAddressMapOffset1Register 0x01E01028 RAMS2 VLYNQLocalReceiveAddressMapSize2Register 0x01E0102C RAMO2 VLYNQLocalReceiveAddressMapOffset2Register 0x01E01030 RAMS3 VLYNQLocalReceiveAddressMapSize3Register 0x01E01034 RAMO3 VLYNQLocalReceiveAddressMapOffset3Register 0x01E01038 RAMS4 VLYNQLocalReceiveAddressMapSize4Register 0x01E0103C RAMO4 VLYNQLocalReceiveAddressMapOffset4Register SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 235

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-91.VLYNQRegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01E01040 CHIPVER VLYNQLocalChipVersionRegister 0x01E01044 AUTNGO VLYNQLocalAutoNegotiationRegister 0x01E01048 - Reserved 0x01E0104C - Reserved 0x01E01050-0x01E0105C - Reserved 0x01E01060 - Reserved 01E010C000064 - Reserved 0x01E01068-0x01E0107C - Reservedforfutureuse 0x01E01080 RREVID VLYNQRemoteRevisionRegister 0x01E01084 RCTRL VLYNQRemoteControlRegister 0x01E01088 RSTAT VLYNQRemoteStatusRegister 0x01E0108C RINTPRI VLYNQRemoteInterruptPriorityVectorStatus/ClearRegister 0x01E01090 RINTSTATCLR VLYNQRemoteUnmaskedInterruptStatus/ClearRegister 0x01E01094 RINTPENDSET VLYNQRemoteInterruptPending/SetRegister 0x01E01098 RINTPTR VLYNQRemoteInterruptPointerRegister 0x01E0109C RXAM VLYNQRemoteTransmitAddressMapRegister 0x01E010A0 RRAMS1 VLYNQRemoteReceiveAddressMapSize1Register 0x01E010A4 RRAMO1 VLYNQRemoteReceiveAddressMapOffset1Register 0x01E010A8 RRAMS2 VLYNQRemoteReceiveAddressMapSize2Register 0x01E010AC RRAMO2 VLYNQRemoteReceiveAddressMapOffset2Register 0x01E010B0 RRAMS3 VLYNQRemoteReceiveAddressMapSize3Register 0x01E010B4 RRAMO3 VLYNQRemoteReceiveAddressMapOffset3Register 0x01E010B8 RRAMS4 VLYNQRemoteReceiveAddressMapSize4Register 0x01E010BC RRAMO4 VLYNQRemoteReceiveAddressMapOffset4Register VLYNQRemoteChipVersionRegister(valuesonthedevice_idand 0x01E010C0 RCHIPVER device_revpinsofremoteVLYNQ) 0x01E010C4 RAUTNGO VLYNQRemoteAutoNegotiationRegister 0x01E010C8 RMANNGO VLYNQRemoteManualNegotiationRegister 0x01E010CC RNGOSTAT VLYNQRemoteNegotiationStatusRegister 0x01E010D0-0x01E010DC - Reserved VLYNQRemoteInterruptVectors3-0(sourcedfromvlynq_int_i[3:0]portof 0x01E010E0 RINTVEC0 remoteVLYNQ) VLYNQRemoteInterruptVectors7-4(sourcedfromvlynq_int_i[7:4]portof 0x01E010E4 RINTVEC1 remoteVLYNQ) 0x01E010E8-0x01E010FC - Reservedforfutureuse 0x01E01100-0x01E01FFF - Reserved 236 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.21.2 VLYNQ Electrical Data/Timing Table6-92.TimingRequirementsforVLYNQ_CLKInput(seeFigure6-48) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,VLYNQ_CLK 10 ns c(VCLK) 2 t Pulseduration,VLYNQ_CLKhigh 3 ns w(VCLKH) 3 t Pulseduration,VLYNQ_CLKlow 3 ns w(VCLKL) Table6-93.SwitchingCharacteristicsOverRecommendedOperatingConditionsforVLYNQ_CLKOutput (seeFigure6-48) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,VLYNQ_CLK 10 ns c(VCLK) 2 t Pulseduration,VLYNQ_CLKhigh 4 ns w(VCLKH) 3 t Pulseduration,VLYNQ_CLKlow 4 ns w(VCLKL) 1 2 VLYNQ_CLK 3 Figure6-48.VLYNQ_CLKTimingforVLYNQ Table6-94.SwitchingCharacteristicsOverRecommendedOperatingConditionsforTransmitDataforthe VLYNQModule(seeFigure6-49) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX t 1 d(VCLKH- Delaytime,VLYNQ_CLKhightoVLYNQ_TXD[3:0]invalid 2.25 ns TXDI) t 2 d(VCLKH- Delaytime,VLYNQ_CLKhightoVLYNQ_TXD[3:0]valid 12 ns TXDV) SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 237

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com Table6-95.TimingRequirementsforReceiveDatafortheVLYNQModule(1)(seeFigure6-49) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX Setuptime,VLYNQ_RXD[3:0]validbefore RTMdisabled,RTMsample=3 1.75 ns 3 t su(RXDV-VCLKH) VLYNQ_CLKhigh RTMenabled (1) ns Holdtime,VLYNQ_RXD[3:0]validafter RTMdisabled,RTMsample=3 3 ns 4 t h(VCLKH-RXDV) VLYNQ_CLKhigh RTMenabled (1) ns (1) TheVLYNQreceivetimingmanager(RTM)isaserialreceivelogicdesignedtoeliminatesetupandholdviolationsthatcouldoccurin traditionalinputsignals.RTMlogicautomaticallyselectsthesetupandholdtimingfromoneofeightdataflops(seeTable6-96).When RTMlogicisdisabled,thesetupandholdtimingfromthedefaultdataflop(3)isused. Table6-96.RTMRXDataFlopHold/SetupTiming Constraints(TypicalValues) RXDataFlop HOLD(Y) SETUP(X) 0 1.3 0.9 1 1.4 0.7 2 1.5 -0.4 3 1.6 -0.6 4 1.8 -0.8 5 2.0 -1.0 6 2.2 -1.1 7 2.4 -1.2 1 VLYNQ_CLK 2 VLYNQ_TXD[3:0] Data 4 3 VLYNQ_RXD[3:0] Data Figure6-49.VLYNQTransmit/ReceiveTiming 238 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.22 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. Whenconfiguredas an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. TheGPIOpinsaregroupedintobanksof16pinsperbank(i.e.,bank0consistsofGP[0:15]). TheDM6435GPIOperipheralsupportsthefollowing: • Upto1113.3-VGPIOpins,GP[0:110] • Interrupts: – Upto8uniqueGP[0:7]interruptsfromBank0 – 7GPIObank(aggregated)interruptsignalsfromeachofthe7banksofGPIOs – Interruptscanbetriggeredbyrisingand/orfallingedge,specifiedforeachinterruptcapableGPIO signal • DMAevents: – Upto8uniqueGPIODMAeventsfromBank0 – 7GPIObank(aggregated)DMAeventsignalsfromeachofthe7banksofGPIOs • Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to antherprocessduringGPIOprogramming). • SeparateInput/Outputregisters • Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can betoggledbydirectwritetotheoutputregister(s). • Output register, when read, reflects output drive status. This, in addition to the input register reflecting pinstatusandopen-drainI/Ocell,allowswiredlogicbeimplemented. The memory map for the GPIO registers is shown in Table 6-97. For more detailed information on GPIOs, see the TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (literature number SPRU988). SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 239

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.22.1 GPIO Peripheral Register Description(s) Table6-97.GPIORegisters HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C67000 PID PeripheralIdentificationRegister 0x01C67004 - Reserved 0x01C67008 BINTEN GPIOinterruptper-bankenable GPIOBanks0and1 0x01C6700C - Reserved 0x01C67010 DIR01 GPIOBanks0and1DirectionRegister(GP[0:31]) 0x01C67014 OUT_DATA01 GPIOBanks0and1OutputDataRegister(GP[0:31]) 0x01C67018 SET_DATA01 GPIOBanks0and1SetDataRegister(GP[0:31]) 0x01C6701C CLR_DATA01 GPIOBanks0and1Cleardataforbanks0and1(GP[0:31]) 0x01C67020 IN_DATA01 GPIOBanks0and1InputDataRegister(GP[0:31]) 0x01C67024 SET_RIS_TRIG01 GPIOBanks0and1SetRisingEdgeInterruptRegister(GP[0:31]) 0x01C67028 CLR_RIS_TRIG01 GPIOBanks0and1ClearRisingEdgeInterruptRegister(GP[0:31]) 0x01C6702C SET_FAL_TRIG01 GPIOBanks0and1SetFallingEdgeInterruptRegister(GP[0:31]) 0x01C67030 CLR_FAL_TRIG01 GPIOBanks0and1ClearFallingEdgeInterruptRegister(GP[0:31]) 0x01C67034 INSTAT01 GPIOBanks0and1InterruptStatusRegister(GP[0:31]) GPIOBanks2and3 0x01C67038 DIR23 GPIOBanks2and3DirectionRegister(GP[32:63]) 0x01C6703C OUT_DATA23 GPIOBanks2and3OutputDataRegister(GP[32:63]) 0x01C67040 SET_DATA23 GPIOBanks2and3SetDataRegister(GP[32:63]) 0x01C67044 CLR_DATA23 GPIOBanks2and3ClearDataRegister(GP[32:63]) 0x01C67048 IN_DATA23 GPIOBanks2and3InputDataRegister(GP[32:63]) 0x01C6704C SET_RIS_TRIG23 GPIOBanks2and3SetRisingEdgeInterruptRegister(GP[32:63]) 0x01C67050 CLR_RIS_TRIG23 GPIOBanks2and3ClearRisingEdgeInterruptRegister(GP[32:63]) 0x01C67054 SET_FAL_TRIG23 GPIOBanks2and3SetFallingEdgeInterruptRegister(GP[32:63]) 0x01C67058 CLR_FAL_TRIG23 GPIOBanks2and3ClearFallingEdgeInterruptRegister(GP[32:63]) 0x01C6705C INSTAT23 GPIOBanks2and3InterruptStatusRegister(GP[32:63]) GPIOBank4and5 0x01C67060 DIR45 GPIOBank4and5DirectionRegister(GP[64:95]) 0x01C67064 OUT_DATA45 GPIOBank4and5OutputDataRegister(GP[64:95]) 0x01C67068 SET_DATA45 GPIOBank4and5SetDataRegister(GP[64:95]) 0x01C6706C CLR_DATA45 GPIOBank4and5ClearDataRegister(GP[64:95]) 0x01C67070 IN_DATA45 GPIOBank4and5InputDataRegister(GP[64:95]) 0x01C67074 SET_RIS_TRIG45 GPIOBank4and5SetRisingEdgeInterruptRegister(GP[64:95]) 0x01C67078 CLR_RIS_TRIG45 GPIOBank4and5ClearRisingEdgeInterruptRegister(GP[64:95]) 0x01C6707C SET_FAL_TRIG45 GPIOBank4and5SetFallingEdgeInterruptRegister(GP[64:95]) 0x01C67080 CLR_FAL_TRIG45 GPIOBank4and5ClearFallingEdgeInterruptRegister(GP[64:95]) 0x01C67084 INSTAT45 GPIOBank4and5InterruptStatusRegister(GP[64:95]) GPIOBank6 0x01C67088 DIR6 GPIOBank6DirectionRegister(GP[96:110]) 0x01C6708C OUT_DATA6 GPIOBank6OutputDataRegister(GP[96:110]) 0x01C67090 SET_DATA6 GPIOBank6SetDataRegister(GP[96:110]) 0x01C67094 CLR_DATA6 GPIOBank6ClearDataRegister(GP[96:110]) 0x01C67098 IN_DATA6 GPIOBank6InputDataRegister(GP[96:110]) 0x01C6709C SET_RIS_TRIG6 GPIOBank6SetRisingEdgeInterruptRegister(GP[96:110]) 0x01C670A0 CLR_RIS_TRIG6 GPIOBank6ClearRisingEdgeInterruptRegister(GP[96:110]) 240 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 Table6-97.GPIORegisters (continued) HEXADDRESSRANGE ACRONYM REGISTERNAME 0x01C670A4 SET_FAL_TRIG6 GPIOBank6SetFallingEdgeInterruptRegister(GP[96:110]) 0x01C670A8 CLR_FAL_TRIG6 GPIOBank6ClearFallingEdgeInterruptRegister(GP[96:110]) 0x01C670AC INSTAT6 GPIOBank6InterruptStatusRegister(GP[96:110]) 0x01C670B0-0x01C67FFF - Reserved SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 241

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.22.2 GPIO Peripheral Input/Output Electrical Data/Timing Table6-98.TimingRequirementsforGPIOInputs(1)(seeFigure6-50) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Pulseduration,GP[x]inputhigh 2C(2) ns w(GPIH) 2 t Pulseduration,GP[x]inputlow 2C(2) ns w(GPIL) (1) ThepulsewidthgivenissufficienttogenerateaCPUinterruptoranEDMAevent.However,ifauserwantstohaveDM6435recognize theGP[x]inputchangesthroughsoftwarepollingoftheGPIOregister,theGP[x]inputdurationmustbeextendedtoallowDM6435 enoughtimetoaccesstheGPIOregisterthroughtheinternalbus. (2) C=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useC=10ns. Table6-99.SwitchingCharacteristicsOverRecommendedOperatingConditionsforGPIOOutputs (seeFigure6-50) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 3 t Pulseduration,GP[x]outputhigh 2C(1)(2) ns w(GPOH) 4 t Pulseduration,GP[x]outputlow 2C(1)(2) ns w(GPOL) (1) Thisparametervalueshouldnotbeusedasamaximumperformancespecification.Actualperformanceofback-to-backaccessesofthe GPIOisdependentuponinternalbusactivity. (2) C=SYSCLK3periodinns.Forexample,whenrunningpartsat600MHz,useC=10ns. 2 1 GP[x] Input 4 3 GP[x] Output Figure6-50.GPIOPortTiming 242 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 6.23 IEEE 1149.1 JTAG TheJTAG(3)interfaceisusedforBSDLtestingandemulationoftheDM6435device. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK;otherwise,theboundaryscanlogicmaynotrespondasexpectedafterTRSTisasserted. For maximum reliability, DM6435 includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properlyinitialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllersmaynotdriveTRSThighbutexpecttheuseofapullupresistoronTRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally driveTRSThighbeforeattemptinganyemulationorboundaryscanoperations. 6.23.1 JTAG ID (JTAGID) Register Description(s) (3) IEEEStandard1149.1-1990Standard-Test-AccessPortandBoundaryScanArchitecture. Table6-100.JTAGID(JTAGID)Register HEXADDRESSRANGE ACRONYM REGISTERNAME COMMENTS Read-only.Provides32-bit 0x01C40028 JTAGID JTAGIdentificationRegister JTAGIDofthedevice. The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the DM6435 device, the JTAG ID register resides at address location 0x01C4 0028. For the actual register bit namesandtheirassociatedbitfielddescriptions,seeFigure6-51andTable6-101. 31-28 27-12 11-1 0 VARIANT(4-Bit) PARTNUMBER(16-Bit) MANUFACTURER(11-Bit) LSB R-n R-1011011100100001 R-00000010111 R-1 LEGEND:R=Read,W=Write,n=valueatreset Figure6-51.JTAGID(JTAGID)Register—0x01C40028 Table6-101.JTAGID(JTAGID)RegisterSelectionBitDescriptions BIT NAME DESCRIPTION 31:28 VARIANT Variant(4-Bit)value.Areadfromthisfieldalwaysreturns0b0000. 27:12 PARTNUMBER PartNumber(16-Bit)value.DM6435value:1011011100100001. 11-1 MANUFACTURER Manufacturer(11-Bit)value.DM6435value:00000010111. 0 LSB LSB.Thisbitisreadasa"1"forDM6435. SubmitDocumentationFeedback PeripheralInformationandElectricalSpecifications 243

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 6.23.2 JTAG Electrical Data/Timing Table6-102.TimingRequirementsforJTAGTestPort(seeFigure6-52) -7/-6/-5/-4 NO. -L/-Q6/-Q5/-Q4 UNIT MIN MAX 1 t Cycletime,TCK 33 ns c(TCK) 3 t Setuptime,TDI/TMS/TRSTvalidbeforeTCKhigh 2.5 ns su(TDIV-TCKH) 4 t Holdtime,TDI/TMS/TRSTvalidafterTCKhigh 16.5 ns h(TCKH-TDIV) Table6-103.SwitchingCharacteristicsOverRecommendedOperatingConditionsforJTAGTestPort (seeFigure6-52) -7/-6/-5/-4 NO. PARAMETER -L/-Q6/-Q5/-Q4 UNIT MIN MAX 2 t Delaytime,TCKlowtoTDOvalid 0 14 ns d(TCKL-TDOV) 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure6-52.JTAGTest-PortTiming 244 PeripheralInformationandElectricalSpecifications SubmitDocumentationFeedback

TMS320DM6435 Digital Media Processor www.ti.com SPRS344C–NOVEMBER2006–REVISEDJUNE2008 7 Mechanical Data The following table(s) show the thermal resistance characteristics for the PBGA–ZWT and ZDU mechanical package(s). For more details, see the Thermal Considerations for TMS320DM64xx, TMS320DM64x,andTMS320C6000DevicesApplicationReport(literaturenumberSPRAAL9). 7.1 Thermal Data for ZWT Table7-1.ThermalResistanceCharacteristics(PBGAPackage)[ZWT] NO. (cid:176) C/W(1) AIRFLOW(m/s)(2) 1 RΘ Junction-to-case 5.4 N/A JC 2 RΘ Junction-to-board 16.0 N/A JB 3 26.6 0.00 4 RΘ Junction-to-freeair 21.9 1.0 JA 5 20.4 2.00 7 0.0 0.00 8 Psi Junction-to-packagetop 0.1 1.0 JT 9 0.2 2.00 11 15.9 0.00 12 Psi Junction-to-board 15.8 1.0 JB 13 15.3 2.00 (1) Thejunction-to-casemeasurementwasconductedinaJEDECdefined1S0Psystem.OthermeasurementswereconductedinaJEDEC defined1S2Psystemandwillchangebasedonenvironmentaswellasapplication. Formoreinformation,seethesethreeEIA/JEDECstandards: • EIA/JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentConditions-NaturalConvection(StillAir) • EIA/JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages . (2) m/s=meterspersecond SubmitDocumentationFeedback MechanicalData 245

TMS320DM6435 Digital Media Processor SPRS344C–NOVEMBER2006–REVISEDJUNE2008 www.ti.com 7.1.1 Thermal Data for ZDU Table7-2.ThermalResistanceCharacteristics(PBGAPackage)[ZDU] NO. (cid:176) C/W(1) AIRFLOW(m/s)(2) 1 RΘ Junction-to-case 7.7 N/A JC 2 RΘ Junction-to-board 10.5 N/A JB 3 19.7 0.00 4 RΘ Junction-to-freeair 15.5 1.0 JA 5 14.3 2.00 7 4.9 0.00 8 Psi Junction-to-packagetop 5.1 1.0 JT 9 5.2 2.00 11 10.4 0.00 12 Psi Junction-to-board 9.8 1.0 JB 13 9.6 2.00 (1) Thejunction-to-casemeasurementwasconductedinaJEDECdefined1S0Psystem.OthermeasurementswereconductedinaJEDEC defined1S2Psystemandwillchangebasedonenvironmentaswellasapplication. Formoreinformation,seethesethreeEIA/JEDECstandards: • EIA/JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentConditions-NaturalConvection(StillAir) • EIA/JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages (2) m/s=meterspersecond 7.1.2 Packaging Information The following packaging information and addendum reflect the most current data available for the designateddevice(s).Thisdataissubjecttochangewithoutnoticeandwithoutrevisionofthisdocument. 246 MechanicalData SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320DM6435EZWT6 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR L2 (RoHS) DM6435EZWT TMS320 TMS320DM6435ZDU6 ACTIVE BGA ZDU 376 60 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 DM6435ZDU6 & no Sb/Br) TMS320DM6435ZDU7 ACTIVE BGA ZDU 376 60 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 L2 & no Sb/Br) DM6435ZDU TMS320 7 TMS320DM6435ZDUQ6 ACTIVE BGA ZDU 376 60 Green (RoHS SNAGCU Level-3-260C-168 HR L1 & no Sb/Br) DM6435ZDUQ TMS320 6 TMS320DM6435ZWT4 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR 0 to 90 L2 (RoHS) DM6435ZWT TMS320 4 TMS320DM6435ZWT5 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR 0 to 0 L2 (RoHS) DM6435ZWT TMS320 5 TMS320DM6435ZWT5CX ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR 0 to 0 L2 (RoHS) DM6435ZWT TMS320 5 TMS320DM6435ZWT6 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR 0 to 90 L2 (RoHS) DM6435ZWT TMS320 TMS320DM6435ZWT6CX ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR 0 to 90 L2 (RoHS) DM6435ZWT TMS320 TMS320DM6435ZWT7 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR L2 (RoHS) DM6435ZWT TMS320 7 TMS320DM6435ZWTL ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR L2 (RoHS) DM6435ZWTL Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TMS320 TMS320DM6435ZWTQ5 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR -40 to 125 L1 (RoHS) DM6435ZWTQ TMS320 5 TMS320DM6435ZWTQ6 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR L1 (RoHS) DM6435ZWTQ TMS320 6 TNETV6435INZWTQ5 ACTIVE NFBGA ZWT 361 90 Pb-Free SNAGCU Level-3-260C-168 HR -40 to 125 L1 (RoHS) DM6435ZWTQ TMS320 5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2019 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

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